arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <121>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <1068>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp@408000000 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp@600000000 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp@816000000 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp@1008000000 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp@1200000000 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp@1416000000 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp@408000000 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@600000000 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp@816000000 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp@1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 261         };
 262
 263         arm-pmu {
 264                 compatible = "arm,armv8-pmuv3";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 266         };
 267
 268         xin24m: xin24m {
 269                 compatible = "fixed-clock";
 270                 #clock-cells = <0>;
 271                 clock-frequency = <24000000>;
 272                 clock-output-names = "xin24m";
 273         };
 274
 275         amba {
 276                 compatible = "arm,amba-bus";
 277                 #address-cells = <2>;
 278                 #size-cells = <2>;
 279                 ranges;
 280
 281                 dmac_bus: dma-controller@ff6d0000 {
 282                         compatible = "arm,pl330", "arm,primecell";
 283                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 284                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 286                         #dma-cells = <1>;
 287                         clocks = <&cru ACLK_DMAC0_PERILP>;
 288                         clock-names = "apb_pclk";
 289                         peripherals-req-type-burst;
 290                 };
 291
 292                 dmac_peri: dma-controller@ff6e0000 {
 293                         compatible = "arm,pl330", "arm,primecell";
 294                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 295                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 297                         #dma-cells = <1>;
 298                         clocks = <&cru ACLK_DMAC1_PERILP>;
 299                         clock-names = "apb_pclk";
 300                         peripherals-req-type-burst;
 301                 };
 302         };
 303
 304         gmac: eth@fe300000 {
 305                 compatible = "rockchip,rk3399-gmac";
 306                 reg = <0x0 0xfe300000 0x0 0x10000>;
 307                 rockchip,grf = <&grf>;
 308                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 309                 interrupt-names = "macirq";
 310                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 311                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 312                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 313                          <&cru PCLK_GMAC>;
 314                 clock-names = "stmmaceth", "mac_clk_rx",
 315                               "mac_clk_tx", "clk_mac_ref",
 316                               "clk_mac_refout", "aclk_mac",
 317                               "pclk_mac";
 318                 resets = <&cru SRST_A_GMAC>;
 319                 reset-names = "stmmaceth";
 320                 status = "disabled";
 321         };
 322
 323         emmc_phy: phy {
 324                 compatible = "rockchip,rk3399-emmc-phy";
 325                 reg-offset = <0xf780>;
 326                 #phy-cells = <0>;
 327                 rockchip,grf = <&grf>;
 328                 ctrl-base = <0xfe330000>;
 329                 status = "disabled";
 330         };
 331
 332         sdio0: dwmmc@fe310000 {
 333                 compatible = "rockchip,rk3399-dw-mshc",
 334                              "rockchip,rk3288-dw-mshc";
 335                 reg = <0x0 0xfe310000 0x0 0x4000>;
 336                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 337                 clock-freq-min-max = <400000 150000000>;
 338                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 339                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 340                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 341                 fifo-depth = <0x100>;
 342                 status = "disabled";
 343         };
 344
 345         sdmmc: dwmmc@fe320000 {
 346                 compatible = "rockchip,rk3399-dw-mshc",
 347                              "rockchip,rk3288-dw-mshc";
 348                 reg = <0x0 0xfe320000 0x0 0x4000>;
 349                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 350                 clock-freq-min-max = <400000 150000000>;
 351                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 352                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 353                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 354                 fifo-depth = <0x100>;
 355                 status = "disabled";
 356         };
 357
 358         sdhci: sdhci@fe330000 {
 359                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 360                 reg = <0x0 0xfe330000 0x0 0x10000>;
 361                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 362                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 363                 clock-names = "clk_xin", "clk_ahb";
 364                 assigned-clocks = <&cru SCLK_EMMC>;
 365                 assigned-clock-parents = <&cru PLL_CPLL>;
 366                 assigned-clock-rates = <200000000>;
 367                 phys = <&emmc_phy>;
 368                 phy-names = "phy_arasan";
 369                 status = "disabled";
 370         };
 371
 372         usb_host0_ehci: usb@fe380000 {
 373                 compatible = "generic-ehci";
 374                 reg = <0x0 0xfe380000 0x0 0x20000>;
 375                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 376                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 377                 clock-names = "hclk_host0", "hclk_host0_arb";
 378                 phys = <&u2phy0_host>;
 379                 phy-names = "usb";
 380                 status = "disabled";
 381         };
 382
 383         usb_host0_ohci: usb@fe3a0000 {
 384                 compatible = "generic-ohci";
 385                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 386                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 387                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 388                 clock-names = "hclk_host0", "hclk_host0_arb";
 389                 status = "disabled";
 390         };
 391
 392         usb_host1_ehci: usb@fe3c0000 {
 393                 compatible = "generic-ehci";
 394                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 395                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 397                 clock-names = "hclk_host1", "hclk_host1_arb";
 398                 phys = <&u2phy1_host>;
 399                 phy-names = "usb";
 400                 status = "disabled";
 401         };
 402
 403         usb_host1_ohci: usb@fe3e0000 {
 404                 compatible = "generic-ohci";
 405                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 406                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 407                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 408                 clock-names = "hclk_host1", "hclk_host1_arb";
 409                 status = "disabled";
 410         };
 411
 412         usbdrd3_0: usb@fe800000 {
 413                 compatible = "rockchip,dwc3";
 414                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 415                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 416                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 417                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 418                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 419                               "aclk_usb3", "aclk_usb3_grf";
 420                 #address-cells = <2>;
 421                 #size-cells = <2>;
 422                 ranges;
 423                 status = "disabled";
 424                 usbdrd_dwc3_0: dwc3@fe800000 {
 425                         compatible = "snps,dwc3";
 426                         reg = <0x0 0xfe800000 0x0 0x100000>;
 427                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 428                         dr_mode = "otg";
 429                         snps,dis_enblslpm_quirk;
 430                         snps,phyif_utmi_16_bits;
 431                         snps,dis_u2_freeclk_exists_quirk;
 432                         snps,dis_del_phy_power_chg_quirk;
 433                         snps,xhci_slow_suspend_quirk;
 434                         status = "disabled";
 435                 };
 436         };
 437
 438         usbdrd3_1: usb@fe900000 {
 439                 compatible = "rockchip,dwc3";
 440                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 441                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 442                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 443                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 444                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 445                               "aclk_usb3", "aclk_usb3_grf";
 446                 #address-cells = <2>;
 447                 #size-cells = <2>;
 448                 ranges;
 449                 status = "disabled";
 450                 usbdrd_dwc3_1: dwc3@fe900000 {
 451                         compatible = "snps,dwc3";
 452                         reg = <0x0 0xfe900000 0x0 0x100000>;
 453                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 454                         dr_mode = "otg";
 455                         snps,dis_enblslpm_quirk;
 456                         snps,phyif_utmi_16_bits;
 457                         snps,dis_u2_freeclk_exists_quirk;
 458                         snps,dis_del_phy_power_chg_quirk;
 459                         snps,xhci_slow_suspend_quirk;
 460                         status = "disabled";
 461                 };
 462         };
 463
 464         gic: interrupt-controller@fee00000 {
 465                 compatible = "arm,gic-v3";
 466                 #interrupt-cells = <3>;
 467                 #address-cells = <2>;
 468                 #size-cells = <2>;
 469                 ranges;
 470                 interrupt-controller;
 471
 472                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 473                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 474                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 475                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 476                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 477                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 478                 its: interrupt-controller@fee20000 {
 479                         compatible = "arm,gic-v3-its";
 480                         msi-controller;
 481                         reg = <0x0 0xfee20000 0x0 0x20000>;
 482                 };
 483         };
 484
 485         saradc: saradc@ff100000 {
 486                 compatible = "rockchip,rk3399-saradc";
 487                 reg = <0x0 0xff100000 0x0 0x100>;
 488                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 489                 #io-channel-cells = <1>;
 490                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 491                 clock-names = "saradc", "apb_pclk";
 492                 status = "disabled";
 493         };
 494
 495         i2c0: i2c@ff3c0000 {
 496                 compatible = "rockchip,rk3399-i2c";
 497                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 498                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 499                 clock-names = "i2c", "pclk";
 500                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&i2c0_xfer>;
 503                 #address-cells = <1>;
 504                 #size-cells = <0>;
 505                 status = "disabled";
 506         };
 507
 508         i2c1: i2c@ff110000 {
 509                 compatible = "rockchip,rk3399-i2c";
 510                 reg = <0x0 0xff110000 0x0 0x1000>;
 511                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 512                 clock-names = "i2c", "pclk";
 513                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&i2c1_xfer>;
 516                 #address-cells = <1>;
 517                 #size-cells = <0>;
 518                 status = "disabled";
 519         };
 520
 521         i2c2: i2c@ff120000 {
 522                 compatible = "rockchip,rk3399-i2c";
 523                 reg = <0x0 0xff120000 0x0 0x1000>;
 524                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 525                 clock-names = "i2c", "pclk";
 526                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&i2c2_xfer>;
 529                 #address-cells = <1>;
 530                 #size-cells = <0>;
 531                 status = "disabled";
 532         };
 533
 534         i2c3: i2c@ff130000 {
 535                 compatible = "rockchip,rk3399-i2c";
 536                 reg = <0x0 0xff130000 0x0 0x1000>;
 537                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 538                 clock-names = "i2c", "pclk";
 539                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&i2c3_xfer>;
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 status = "disabled";
 545         };
 546
 547         i2c5: i2c@ff140000 {
 548                 compatible = "rockchip,rk3399-i2c";
 549                 reg = <0x0 0xff140000 0x0 0x1000>;
 550                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 551                 clock-names = "i2c", "pclk";
 552                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 553                 pinctrl-names = "default";
 554                 pinctrl-0 = <&i2c5_xfer>;
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557                 status = "disabled";
 558         };
 559
 560         i2c6: i2c@ff150000 {
 561                 compatible = "rockchip,rk3399-i2c";
 562                 reg = <0x0 0xff150000 0x0 0x1000>;
 563                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 564                 clock-names = "i2c", "pclk";
 565                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&i2c6_xfer>;
 568                 #address-cells = <1>;
 569                 #size-cells = <0>;
 570                 status = "disabled";
 571         };
 572
 573         i2c7: i2c@ff160000 {
 574                 compatible = "rockchip,rk3399-i2c";
 575                 reg = <0x0 0xff160000 0x0 0x1000>;
 576                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 577                 clock-names = "i2c", "pclk";
 578                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&i2c7_xfer>;
 581                 #address-cells = <1>;
 582                 #size-cells = <0>;
 583                 status = "disabled";
 584         };
 585
 586         uart0: serial@ff180000 {
 587                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 588                 reg = <0x0 0xff180000 0x0 0x100>;
 589                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 590                 clock-names = "baudclk", "apb_pclk";
 591                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 592                 reg-shift = <2>;
 593                 reg-io-width = <4>;
 594                 pinctrl-names = "default";
 595                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 596                 status = "disabled";
 597         };
 598
 599         uart1: serial@ff190000 {
 600                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 601                 reg = <0x0 0xff190000 0x0 0x100>;
 602                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 603                 clock-names = "baudclk", "apb_pclk";
 604                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 605                 reg-shift = <2>;
 606                 reg-io-width = <4>;
 607                 pinctrl-names = "default";
 608                 pinctrl-0 = <&uart1_xfer>;
 609                 status = "disabled";
 610         };
 611
 612         uart2: serial@ff1a0000 {
 613                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 614                 reg = <0x0 0xff1a0000 0x0 0x100>;
 615                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 616                 clock-names = "baudclk", "apb_pclk";
 617                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 618                 reg-shift = <2>;
 619                 reg-io-width = <4>;
 620                 pinctrl-names = "default";
 621                 pinctrl-0 = <&uart2c_xfer>;
 622                 status = "disabled";
 623         };
 624
 625         uart3: serial@ff1b0000 {
 626                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 627                 reg = <0x0 0xff1b0000 0x0 0x100>;
 628                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 629                 clock-names = "baudclk", "apb_pclk";
 630                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 631                 reg-shift = <2>;
 632                 reg-io-width = <4>;
 633                 pinctrl-names = "default";
 634                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 635                 status = "disabled";
 636         };
 637
 638         spi0: spi@ff1c0000 {
 639                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 640                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 641                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 642                 clock-names = "spiclk", "apb_pclk";
 643                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 644                 pinctrl-names = "default";
 645                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 646                 #address-cells = <1>;
 647                 #size-cells = <0>;
 648                 status = "disabled";
 649         };
 650
 651         spi1: spi@ff1d0000 {
 652                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 653                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 654                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 655                 clock-names = "spiclk", "apb_pclk";
 656                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 657                 pinctrl-names = "default";
 658                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 659                 #address-cells = <1>;
 660                 #size-cells = <0>;
 661                 status = "disabled";
 662         };
 663
 664         spi2: spi@ff1e0000 {
 665                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 666                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 667                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 668                 clock-names = "spiclk", "apb_pclk";
 669                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 670                 pinctrl-names = "default";
 671                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 672                 #address-cells = <1>;
 673                 #size-cells = <0>;
 674                 status = "disabled";
 675         };
 676
 677         spi4: spi@ff1f0000 {
 678                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 679                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 680                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 681                 clock-names = "spiclk", "apb_pclk";
 682                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 683                 pinctrl-names = "default";
 684                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 685                 #address-cells = <1>;
 686                 #size-cells = <0>;
 687                 status = "disabled";
 688         };
 689
 690         spi5: spi@ff200000 {
 691                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 692                 reg = <0x0 0xff200000 0x0 0x1000>;
 693                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 694                 clock-names = "spiclk", "apb_pclk";
 695                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 696                 pinctrl-names = "default";
 697                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 698                 #address-cells = <1>;
 699                 #size-cells = <0>;
 700                 status = "disabled";
 701         };
 702
 703         thermal-zones {
 704                 soc_thermal: soc-thermal {
 705                         polling-delay-passive = <20>; /* milliseconds */
 706                         polling-delay = <1000>; /* milliseconds */
 707                         sustainable-power = <1600>; /* milliwatts */
 708
 709                         thermal-sensors = <&tsadc 0>;
 710
 711                         trips {
 712                                 threshold: trip-point@0 {
 713                                         temperature = <70000>; /* millicelsius */
 714                                         hysteresis = <2000>; /* millicelsius */
 715                                         type = "passive";
 716                                 };
 717                                 target: trip-point@1 {
 718                                         temperature = <85000>; /* millicelsius */
 719                                         hysteresis = <2000>; /* millicelsius */
 720                                         type = "passive";
 721                                 };
 722                                 soc_crit: soc-crit {
 723                                         temperature = <95000>; /* millicelsius */
 724                                         hysteresis = <2000>; /* millicelsius */
 725                                         type = "critical";
 726                                 };
 727                         };
 728
 729                         cooling-maps {
 730                                 map0 {
 731                                         trip = <&target>;
 732                                         cooling-device =
 733                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 734                                         contribution = <10240>;
 735                                 };
 736                                 map1 {
 737                                         trip = <&target>;
 738                                         cooling-device =
 739                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 740                                         contribution = <1024>;
 741                                 };
 742                                 map2 {
 743                                         trip = <&target>;
 744                                         cooling-device =
 745                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 746                                         contribution = <10240>;
 747                                 };
 748                         };
 749                 };
 750
 751                 gpu_thermal: gpu-thermal {
 752                         polling-delay-passive = <100>; /* milliseconds */
 753                         polling-delay = <1000>; /* milliseconds */
 754
 755                         thermal-sensors = <&tsadc 1>;
 756                 };
 757         };
 758
 759         tsadc: tsadc@ff260000 {
 760                 compatible = "rockchip,rk3399-tsadc";
 761                 reg = <0x0 0xff260000 0x0 0x100>;
 762                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 763                 rockchip,grf = <&grf>;
 764                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 765                 clock-names = "tsadc", "apb_pclk";
 766                 assigned-clocks = <&cru SCLK_TSADC>;
 767                 assigned-clock-rates = <750000>;
 768                 resets = <&cru SRST_TSADC>;
 769                 reset-names = "tsadc-apb";
 770                 pinctrl-names = "init", "default", "sleep";
 771                 pinctrl-0 = <&otp_gpio>;
 772                 pinctrl-1 = <&otp_out>;
 773                 pinctrl-2 = <&otp_gpio>;
 774                 #thermal-sensor-cells = <1>;
 775                 rockchip,hw-tshut-temp = <95000>;
 776                 status = "disabled";
 777         };
 778
 779         qos_hdcp: qos@ffa90000 {
 780                 compatible = "syscon";
 781                 reg = <0x0 0xffa90000 0x0 0x20>;
 782         };
 783
 784         qos_iep: qos@ffa98000 {
 785                 compatible = "syscon";
 786                 reg = <0x0 0xffa98000 0x0 0x20>;
 787         };
 788
 789         qos_isp0_m0: qos@ffaa0000 {
 790                 compatible = "syscon";
 791                 reg = <0x0 0xffaa0000 0x0 0x20>;
 792         };
 793
 794         qos_isp0_m1: qos@ffaa0080 {
 795                 compatible = "syscon";
 796                 reg = <0x0 0xffaa0080 0x0 0x20>;
 797         };
 798
 799         qos_isp1_m0: qos@ffaa8000 {
 800                 compatible = "syscon";
 801                 reg = <0x0 0xffaa8000 0x0 0x20>;
 802         };
 803
 804         qos_isp1_m1: qos@ffaa8080 {
 805                 compatible = "syscon";
 806                 reg = <0x0 0xffaa8080 0x0 0x20>;
 807         };
 808
 809         qos_rga_r: qos@ffab0000 {
 810                 compatible = "syscon";
 811                 reg = <0x0 0xffab0000 0x0 0x20>;
 812         };
 813
 814         qos_rga_w: qos@ffab0080 {
 815                 compatible = "syscon";
 816                 reg = <0x0 0xffab0080 0x0 0x20>;
 817         };
 818
 819         qos_video_m0: qos@ffab8000 {
 820                 compatible = "syscon";
 821                 reg = <0x0 0xffab8000 0x0 0x20>;
 822         };
 823
 824         qos_video_m1_r: qos@ffac0000 {
 825                 compatible = "syscon";
 826                 reg = <0x0 0xffac0000 0x0 0x20>;
 827         };
 828
 829         qos_video_m1_w: qos@ffac0080 {
 830                 compatible = "syscon";
 831                 reg = <0x0 0xffac0080 0x0 0x20>;
 832         };
 833
 834         qos_vop_big_r: qos@ffac8000 {
 835                 compatible = "syscon";
 836                 reg = <0x0 0xffac8000 0x0 0x20>;
 837         };
 838
 839         qos_vop_big_w: qos@ffac8080 {
 840                 compatible = "syscon";
 841                 reg = <0x0 0xffac8080 0x0 0x20>;
 842         };
 843
 844         qos_vop_little: qos@ffad0000 {
 845                 compatible = "syscon";
 846                 reg = <0x0 0xffad0000 0x0 0x20>;
 847         };
 848
 849         qos_gpu: qos@ffae0000 {
 850                 compatible = "syscon";
 851                 reg = <0x0 0xffae0000 0x0 0x20>;
 852         };
 853
 854         pmu: power-management@ff310000 {
 855                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 856                 reg = <0x0 0xff310000 0x0 0x1000>;
 857
 858                 /*
 859                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 860                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 861                  * Some of the power domains are grouped together for every
 862                  * voltage domain.
 863                  * The detail contents as below.
 864                  */
 865                 power: power-controller {
 866                         compatible = "rockchip,rk3399-power-controller";
 867                         #power-domain-cells = <1>;
 868                         #address-cells = <1>;
 869                         #size-cells = <0>;
 870
 871                         /* These power domains are grouped by VD_CENTER */
 872                         pd_iep@RK3399_PD_IEP {
 873                                 reg = <RK3399_PD_IEP>;
 874                                 clocks = <&cru ACLK_IEP>,
 875                                          <&cru HCLK_IEP>;
 876                                 pm_qos = <&qos_iep>;
 877                         };
 878                         pd_rga@RK3399_PD_RGA {
 879                                 reg = <RK3399_PD_RGA>;
 880                                 clocks = <&cru ACLK_RGA>,
 881                                          <&cru HCLK_RGA>;
 882                                 pm_qos = <&qos_rga_r>,
 883                                          <&qos_rga_w>;
 884                         };
 885                         pd_vcodec@RK3399_PD_VCODEC {
 886                                 reg = <RK3399_PD_VCODEC>;
 887                                 clocks = <&cru ACLK_VCODEC>,
 888                                          <&cru HCLK_VCODEC>;
 889                                 pm_qos = <&qos_video_m0>;
 890                         };
 891                         pd_vdu@RK3399_PD_VDU {
 892                                 reg = <RK3399_PD_VDU>;
 893                                 clocks = <&cru ACLK_VDU>,
 894                                          <&cru HCLK_VDU>;
 895                                 pm_qos = <&qos_video_m1_r>,
 896                                          <&qos_video_m1_w>;
 897                         };
 898
 899                         /* These power domains are grouped by VD_GPU */
 900                         pd_gpu@RK3399_PD_GPU {
 901                                 reg = <RK3399_PD_GPU>;
 902                                 clocks = <&cru ACLK_GPU>;
 903                                 pm_qos = <&qos_gpu>;
 904                         };
 905
 906                         /* These power domains are grouped by VD_LOGIC */
 907                         pd_vio@RK3399_PD_VIO {
 908                                 reg = <RK3399_PD_VIO>;
 909                                 #address-cells = <1>;
 910                                 #size-cells = <0>;
 911
 912                                 pd_hdcp@RK3399_PD_HDCP {
 913                                         reg = <RK3399_PD_HDCP>;
 914                                         clocks = <&cru ACLK_HDCP>,
 915                                                  <&cru HCLK_HDCP>,
 916                                                  <&cru PCLK_HDCP>;
 917                                         pm_qos = <&qos_hdcp>;
 918                                 };
 919                                 pd_isp0@RK3399_PD_ISP0 {
 920                                         reg = <RK3399_PD_ISP0>;
 921                                         clocks = <&cru ACLK_ISP0>,
 922                                                  <&cru HCLK_ISP0>;
 923                                         pm_qos = <&qos_isp0_m0>,
 924                                                  <&qos_isp0_m1>;
 925                                 };
 926                                 pd_isp1@RK3399_PD_ISP1 {
 927                                         reg = <RK3399_PD_ISP1>;
 928                                         clocks = <&cru ACLK_ISP1>,
 929                                                  <&cru HCLK_ISP1>;
 930                                         pm_qos = <&qos_isp1_m0>,
 931                                                  <&qos_isp1_m1>;
 932                                 };
 933                                 pd_vo@RK3399_PD_VO {
 934                                         reg = <RK3399_PD_VO>;
 935                                         #address-cells = <1>;
 936                                         #size-cells = <0>;
 937
 938                                         pd_vopb@RK3399_PD_VOPB {
 939                                                 reg = <RK3399_PD_VOPB>;
 940                                                 clocks = <&cru ACLK_VOP0>,
 941                                                          <&cru HCLK_VOP0>;
 942                                                 pm_qos = <&qos_vop_big_r>,
 943                                                          <&qos_vop_big_w>;
 944                                         };
 945                                         pd_vopl@RK3399_PD_VOPL {
 946                                                 reg = <RK3399_PD_VOPL>;
 947                                                 clocks = <&cru ACLK_VOP1>,
 948                                                          <&cru HCLK_VOP1>;
 949                                                 pm_qos = <&qos_vop_little>;
 950                                         };
 951                                 };
 952                         };
 953                 };
 954         };
 955
 956         pmugrf: syscon@ff320000 {
 957                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 958                 reg = <0x0 0xff320000 0x0 0x1000>;
 959
 960                 reboot-mode {
 961                         compatible = "syscon-reboot-mode";
 962                         offset = <0x300>;
 963                         mode-normal = <BOOT_NORMAL>;
 964                         mode-recovery = <BOOT_RECOVERY>;
 965                         mode-bootloader = <BOOT_FASTBOOT>;
 966                         mode-loader = <BOOT_LOADER>;
 967                 };
 968         };
 969
 970         spi3: spi@ff350000 {
 971                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 972                 reg = <0x0 0xff350000 0x0 0x1000>;
 973                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 974                 clock-names = "spiclk", "apb_pclk";
 975                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 976                 pinctrl-names = "default";
 977                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 978                 #address-cells = <1>;
 979                 #size-cells = <0>;
 980                 status = "disabled";
 981         };
 982
 983         uart4: serial@ff370000 {
 984                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 985                 reg = <0x0 0xff370000 0x0 0x100>;
 986                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 987                 clock-names = "baudclk", "apb_pclk";
 988                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 989                 reg-shift = <2>;
 990                 reg-io-width = <4>;
 991                 pinctrl-names = "default";
 992                 pinctrl-0 = <&uart4_xfer>;
 993                 status = "disabled";
 994         };
 995
 996         i2c4: i2c@ff3d0000 {
 997                 compatible = "rockchip,rk3399-i2c";
 998                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 999                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1000                 clock-names = "i2c", "pclk";
1001                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1002                 pinctrl-names = "default";
1003                 pinctrl-0 = <&i2c4_xfer>;
1004                 #address-cells = <1>;
1005                 #size-cells = <0>;
1006                 status = "disabled";
1007         };
1008
1009         i2c8: i2c@ff3e0000 {
1010                 compatible = "rockchip,rk3399-i2c";
1011                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1012                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1013                 clock-names = "i2c", "pclk";
1014                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1015                 pinctrl-names = "default";
1016                 pinctrl-0 = <&i2c8_xfer>;
1017                 #address-cells = <1>;
1018                 #size-cells = <0>;
1019                 status = "disabled";
1020         };
1021
1022         pcie0: pcie@f8000000 {
1023                 compatible = "rockchip,rk3399-pcie";
1024                 #address-cells = <3>;
1025                 #size-cells = <2>;
1026                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1027                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1028                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1029                               "hclk_pcie", "clk_pciephy_ref";
1030                 bus-range = <0x0 0x1>;
1031                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1032                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1033                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1034                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1035                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1036                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1037                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1038                       < 0x0 0xfd000000 0x0 0x1000000 >;
1039                 reg-name = "axi-base", "apb-base";
1040                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1041                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1042                          <&cru SRST_PCIE_PIPE>;
1043                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1044                               "mgmt-sticky-rst", "pipe-rst";
1045                 rockchip,grf = <&grf>;
1046                 pcie-conf = <0xe220>;
1047                 pcie-status = <0xe2a4>;
1048                 pcie-laneoff = <0xe214>;
1049                 msi-parent = <&its>;
1050                 #interrupt-cells = <1>;
1051                 interrupt-map-mask = <0 0 0 7>;
1052                 interrupt-map = <0 0 0 1 &pcie0 1>,
1053                                 <0 0 0 2 &pcie0 2>,
1054                                 <0 0 0 3 &pcie0 3>,
1055                                 <0 0 0 4 &pcie0 4>;
1056                 status = "disabled";
1057                 pcie_intc: interrupt-controller {
1058                         interrupt-controller;
1059                         #address-cells = <0>;
1060                         #interrupt-cells = <1>;
1061                 };
1062         };
1063
1064         pwm0: pwm@ff420000 {
1065                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1066                 reg = <0x0 0xff420000 0x0 0x10>;
1067                 #pwm-cells = <3>;
1068                 pinctrl-names = "default";
1069                 pinctrl-0 = <&pwm0_pin>;
1070                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1071                 clock-names = "pwm";
1072                 status = "disabled";
1073         };
1074
1075         pwm1: pwm@ff420010 {
1076                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1077                 reg = <0x0 0xff420010 0x0 0x10>;
1078                 #pwm-cells = <3>;
1079                 pinctrl-names = "default";
1080                 pinctrl-0 = <&pwm1_pin>;
1081                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1082                 clock-names = "pwm";
1083                 status = "disabled";
1084         };
1085
1086         pwm2: pwm@ff420020 {
1087                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1088                 reg = <0x0 0xff420020 0x0 0x10>;
1089                 #pwm-cells = <3>;
1090                 pinctrl-names = "default";
1091                 pinctrl-0 = <&pwm2_pin>;
1092                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1093                 clock-names = "pwm";
1094                 status = "disabled";
1095         };
1096
1097         pwm3: pwm@ff420030 {
1098                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1099                 reg = <0x0 0xff420030 0x0 0x10>;
1100                 #pwm-cells = <3>;
1101                 pinctrl-names = "default";
1102                 pinctrl-0 = <&pwm3a_pin>;
1103                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1104                 clock-names = "pwm";
1105                 status = "disabled";
1106         };
1107
1108         rga: rga@ff680000 {
1109                 compatible = "rockchip,rk3399-rga";
1110                 reg = <0x0 0xff680000 0x0 0x10000>;
1111                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1112                 interrupt-names = "rga";
1113                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1114                 clock-names = "aclk", "hclk", "sclk";
1115                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1116                 reset-names = "core", "axi", "ahb";
1117                 status = "disabled";
1118         };
1119
1120         pmucru: pmu-clock-controller@ff750000 {
1121                 compatible = "rockchip,rk3399-pmucru";
1122                 reg = <0x0 0xff750000 0x0 0x1000>;
1123                 #clock-cells = <1>;
1124                 #reset-cells = <1>;
1125                 assigned-clocks = <&pmucru PLL_PPLL>;
1126                 assigned-clock-rates = <676000000>;
1127         };
1128
1129         cru: clock-controller@ff760000 {
1130                 compatible = "rockchip,rk3399-cru";
1131                 reg = <0x0 0xff760000 0x0 0x1000>;
1132                 #clock-cells = <1>;
1133                 #reset-cells = <1>;
1134                 assigned-clocks =
1135                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1136                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1137                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1138                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1139                         <&cru PLL_NPLL>,
1140                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1141                         <&cru PCLK_PERIHP>,
1142                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1143                         <&cru PCLK_PERILP0>,
1144                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1145                 assigned-clock-rates =
1146                          <400000000>,  <200000000>,
1147                          <400000000>,  <200000000>,
1148                          <816000000>, <816000000>,
1149                          <594000000>,  <800000000>,
1150                         <1000000000>,
1151                          <150000000>,   <75000000>,
1152                           <37500000>,
1153                          <100000000>,  <100000000>,
1154                           <50000000>,
1155                          <100000000>,   <50000000>;
1156         };
1157
1158         grf: syscon@ff770000 {
1159                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1160                 reg = <0x0 0xff770000 0x0 0x10000>;
1161                 #address-cells = <1>;
1162                 #size-cells = <1>;
1163
1164                 u2phy0: usb2-phy@e450 {
1165                         compatible = "rockchip,rk3399-usb2phy";
1166                         reg = <0xe450 0x10>;
1167                         clocks = <&cru SCLK_USB2PHY0_REF>;
1168                         clock-names = "phyclk";
1169                         #clock-cells = <0>;
1170                         clock-output-names = "clk_usbphy0_480m";
1171                         status = "disabled";
1172
1173                         u2phy0_otg: otg-port {
1174                                 #phy-cells = <0>;
1175                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1176                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1177                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1178                                 interrupt-names = "otg-bvalid", "otg-id",
1179                                                   "linestate";
1180                                 status = "disabled";
1181                         };
1182
1183                         u2phy0_host: host-port {
1184                                 #phy-cells = <0>;
1185                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1186                                 interrupt-names = "linestate";
1187                                 status = "disabled";
1188                         };
1189                 };
1190
1191                 u2phy1: usb2-phy@e460 {
1192                         compatible = "rockchip,rk3399-usb2phy";
1193                         reg = <0xe460 0x10>;
1194                         clocks = <&cru SCLK_USB2PHY1_REF>;
1195                         clock-names = "phyclk";
1196                         #clock-cells = <0>;
1197                         clock-output-names = "clk_usbphy1_480m";
1198                         status = "disabled";
1199
1200                         u2phy1_host: host-port {
1201                                 #phy-cells = <0>;
1202                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1203                                 interrupt-names = "linestate";
1204                                 status = "disabled";
1205                         };
1206                 };
1207         };
1208
1209         tcphy0: phy@ff7c0000 {
1210                 compatible = "rockchip,rk3399-typec-phy";
1211                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1212                 rockchip,grf = <&grf>;
1213                 #phy-cells = <0>;
1214                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1215                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1216                 clock-names = "tcpdcore", "tcpdphy-ref";
1217                 resets = <&cru SRST_UPHY0>,
1218                          <&cru SRST_UPHY0_PIPE_L00>,
1219                          <&cru SRST_P_UPHY0_TCPHY>;
1220                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1221                 rockchip,typec-conn-dir = <0xe580 0 16>;
1222                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1223                 rockchip,external-psm = <0xe588 14 30>;
1224                 rockchip,pipe-status = <0xe5c0 0 0>;
1225                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1226                 status = "disabled";
1227         };
1228
1229         tcphy1: phy@ff800000 {
1230                 compatible = "rockchip,rk3399-typec-phy";
1231                 reg = <0x0 0xff800000 0x0 0x40000>;
1232                 rockchip,grf = <&grf>;
1233                 #phy-cells = <0>;
1234                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1235                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1236                 clock-names = "tcpdcore", "tcpdphy-ref";
1237                 resets = <&cru SRST_UPHY1>,
1238                          <&cru SRST_UPHY1_PIPE_L00>,
1239                          <&cru SRST_P_UPHY1_TCPHY>;
1240                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1241                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1242                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1243                 rockchip,external-psm = <0xe594 14 30>;
1244                 rockchip,pipe-status = <0xe5c0 16 16>;
1245                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1246                 status = "disabled";
1247         };
1248
1249         watchdog@ff840000 {
1250                 compatible = "snps,dw-wdt";
1251                 reg = <0x0 0xff840000 0x0 0x100>;
1252                 clocks = <&cru PCLK_WDT>;
1253                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1254         };
1255
1256         rktimer: rktimer@ff850000 {
1257                 compatible = "rockchip,rk3399-timer";
1258                 reg = <0x0 0xff850000 0x0 0x1000>;
1259                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1260                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1261                 clock-names = "pclk", "timer";
1262         };
1263
1264         spdif: spdif@ff870000 {
1265                 compatible = "rockchip,rk3399-spdif";
1266                 reg = <0x0 0xff870000 0x0 0x1000>;
1267                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1268                 dmas = <&dmac_bus 7>;
1269                 dma-names = "tx";
1270                 clock-names = "mclk", "hclk";
1271                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1272                 pinctrl-names = "default";
1273                 pinctrl-0 = <&spdif_bus>;
1274                 status = "disabled";
1275         };
1276
1277         i2s0: i2s@ff880000 {
1278                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1279                 reg = <0x0 0xff880000 0x0 0x1000>;
1280                 rockchip,grf = <&grf>;
1281                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1282                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1283                 dma-names = "tx", "rx";
1284                 clock-names = "i2s_clk", "i2s_hclk";
1285                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1286                 pinctrl-names = "default";
1287                 pinctrl-0 = <&i2s0_8ch_bus>;
1288                 status = "disabled";
1289         };
1290
1291         i2s1: i2s@ff890000 {
1292                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1293                 reg = <0x0 0xff890000 0x0 0x1000>;
1294                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1295                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1296                 dma-names = "tx", "rx";
1297                 clock-names = "i2s_clk", "i2s_hclk";
1298                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1299                 pinctrl-names = "default";
1300                 pinctrl-0 = <&i2s1_2ch_bus>;
1301                 status = "disabled";
1302         };
1303
1304         i2s2: i2s@ff8a0000 {
1305                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1306                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1307                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1308                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1309                 dma-names = "tx", "rx";
1310                 clock-names = "i2s_clk", "i2s_hclk";
1311                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1312                 status = "disabled";
1313         };
1314
1315         gpu: gpu@ff9a0000 {
1316                 compatible = "arm,malit860",
1317                              "arm,malit86x",
1318                              "arm,malit8xx",
1319                              "arm,mali-midgard";
1320
1321                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1322
1323                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1324                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1325                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1326                 interrupt-names = "GPU", "JOB", "MMU";
1327
1328                 clocks = <&cru ACLK_GPU>;
1329                 clock-names = "clk_mali";
1330                 #cooling-cells = <2>; /* min followed by max */
1331                 operating-points-v2 = <&gpu_opp_table>;
1332                 power-domains = <&power RK3399_PD_GPU>;
1333                 power-off-delay-ms = <200>;
1334                 status = "disabled";
1335
1336                 power_model {
1337                         compatible = "arm,mali-simple-power-model";
1338                         voltage = <900>;
1339                         frequency = <500>;
1340                         static-power = <300>;
1341                         dynamic-power = <1780>;
1342                         ts = <32000 4700 (-80) 2>;
1343                         thermal-zone = "gpu-thermal";
1344                 };
1345         };
1346
1347         gpu_opp_table: gpu_opp_table {
1348                 compatible = "operating-points-v2";
1349                 opp-shared;
1350
1351                 opp@200000000 {
1352                         opp-hz = /bits/ 64 <200000000>;
1353                         opp-microvolt = <900000>;
1354                 };
1355                 opp@300000000 {
1356                         opp-hz = /bits/ 64 <300000000>;
1357                         opp-microvolt = <900000>;
1358                 };
1359                 opp@400000000 {
1360                         opp-hz = /bits/ 64 <400000000>;
1361                         opp-microvolt = <900000>;
1362                 };
1363
1364         };
1365
1366         vopl: vop@ff8f0000 {
1367                 compatible = "rockchip,rk3399-vop-lit";
1368                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1369                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1370                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1371                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1372                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1373                 reset-names = "axi", "ahb", "dclk";
1374                 power-domains = <&power RK3399_PD_VOPL>;
1375                 iommus = <&vopl_mmu>;
1376                 status = "disabled";
1377
1378                 vopl_out: port {
1379                         #address-cells = <1>;
1380                         #size-cells = <0>;
1381
1382                         vopl_out_mipi: endpoint@0 {
1383                                 reg = <0>;
1384                                 remote-endpoint = <&mipi_in_vopl>;
1385                         };
1386
1387                         vopl_out_edp: endpoint@1 {
1388                                 reg = <1>;
1389                                 remote-endpoint = <&edp_in_vopl>;
1390                         };
1391
1392                         vopl_out_hdmi: endpoint@2 {
1393                                 reg = <2>;
1394                                 remote-endpoint = <&hdmi_in_vopl>;
1395                         };
1396                 };
1397         };
1398
1399         vopl_mmu: iommu@ff8f3f00 {
1400                 compatible = "rockchip,iommu";
1401                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1402                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1403                 interrupt-names = "vopl_mmu";
1404                 #iommu-cells = <0>;
1405                 status = "disabled";
1406         };
1407
1408         vopb: vop@ff900000 {
1409                 compatible = "rockchip,rk3399-vop-big";
1410                 reg = <0x0 0xff900000 0x0 0x3efc>;
1411                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1412                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1413                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1414                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1415                 reset-names = "axi", "ahb", "dclk";
1416                 power-domains = <&power RK3399_PD_VOPB>;
1417                 iommus = <&vopb_mmu>;
1418                 status = "disabled";
1419
1420                 vopb_out: port {
1421                         #address-cells = <1>;
1422                         #size-cells = <0>;
1423
1424                         vopb_out_edp: endpoint@0 {
1425                                 reg = <0>;
1426                                 remote-endpoint = <&edp_in_vopb>;
1427                         };
1428
1429                         vopb_out_mipi: endpoint@1 {
1430                                 reg = <1>;
1431                                 remote-endpoint = <&mipi_in_vopb>;
1432                         };
1433
1434                         vopb_out_hdmi: endpoint@2 {
1435                                 reg = <2>;
1436                                 remote-endpoint = <&hdmi_in_vopb>;
1437                         };
1438                 };
1439         };
1440
1441         vopb_mmu: iommu@ff903f00 {
1442                 compatible = "rockchip,iommu";
1443                 reg = <0x0 0xff903f00 0x0 0x100>;
1444                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1445                 interrupt-names = "vopb_mmu";
1446                 #iommu-cells = <0>;
1447                 status = "disabled";
1448         };
1449
1450         hdmi: hdmi@ff940000 {
1451                 compatible = "rockchip,rk3399-dw-hdmi";
1452                 reg = <0x0 0xff940000 0x0 0x20000>;
1453                 reg-io-width = <4>;
1454                 rockchip,grf = <&grf>;
1455                 power-domains = <&power RK3399_PD_HDCP>;
1456                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1457                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1458                 clock-names = "iahb", "isfr", "vpll", "grf";
1459                 status = "disabled";
1460
1461                 ports {
1462                         hdmi_in: port {
1463                                 #address-cells = <1>;
1464                                 #size-cells = <0>;
1465                                 hdmi_in_vopb: endpoint@0 {
1466                                         reg = <0>;
1467                                         remote-endpoint = <&vopb_out_hdmi>;
1468                                 };
1469                                 hdmi_in_vopl: endpoint@1 {
1470                                         reg = <1>;
1471                                         remote-endpoint = <&vopl_out_hdmi>;
1472                                 };
1473                         };
1474                 };
1475         };
1476
1477         mipi_dsi: mipi@ff960000 {
1478                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1479                 reg = <0x0 0xff960000 0x0 0x8000>;
1480                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1481                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1482                          <&cru SCLK_DPHY_TX0_CFG>;
1483                 clock-names = "ref", "pclk", "phy_cfg";
1484                 power-domains = <&power RK3399_PD_VIO>;
1485                 rockchip,grf = <&grf>;
1486                 #address-cells = <1>;
1487                 #size-cells = <0>;
1488                 status = "disabled";
1489
1490                 ports {
1491                         #address-cells = <1>;
1492                         #size-cells = <0>;
1493                         reg = <1>;
1494
1495                         mipi_in: port {
1496                                 #address-cells = <1>;
1497                                 #size-cells = <0>;
1498
1499                                 mipi_in_vopb: endpoint@0 {
1500                                         reg = <0>;
1501                                         remote-endpoint = <&vopb_out_mipi>;
1502                                 };
1503                                 mipi_in_vopl: endpoint@1 {
1504                                         reg = <1>;
1505                                         remote-endpoint = <&vopl_out_mipi>;
1506                                 };
1507                         };
1508                 };
1509         };
1510
1511         edp: edp@ff970000 {
1512                 compatible = "rockchip,rk3399-edp";
1513                 reg = <0x0 0xff970000 0x0 0x8000>;
1514                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1515                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1516                 clock-names = "dp", "pclk";
1517                 resets = <&cru SRST_P_EDP_CTRL>;
1518                 reset-names = "dp";
1519                 rockchip,grf = <&grf>;
1520                 status = "disabled";
1521                 pinctrl-names = "default";
1522                 pinctrl-0 = <&edp_hpd>;
1523
1524                 ports {
1525                         #address-cells = <1>;
1526                         #size-cells = <0>;
1527
1528                         edp_in: port@0 {
1529                                 reg = <0>;
1530                                 #address-cells = <1>;
1531                                 #size-cells = <0>;
1532
1533                                 edp_in_vopb: endpoint@0 {
1534                                         reg = <0>;
1535                                         remote-endpoint = <&vopb_out_edp>;
1536                                 };
1537
1538                                 edp_in_vopl: endpoint@1 {
1539                                         reg = <1>;
1540                                         remote-endpoint = <&vopl_out_edp>;
1541                                 };
1542                         };
1543                 };
1544         };
1545
1546         display_subsystem: display-subsystem {
1547                 compatible = "rockchip,display-subsystem";
1548                 ports = <&vopl_out>, <&vopb_out>;
1549                 status = "disabled";
1550         };
1551
1552         pinctrl: pinctrl {
1553                 compatible = "rockchip,rk3399-pinctrl";
1554                 rockchip,grf = <&grf>;
1555                 rockchip,pmu = <&pmugrf>;
1556                 #address-cells = <0x2>;
1557                 #size-cells = <0x2>;
1558                 ranges;
1559
1560                 gpio0: gpio0@ff720000 {
1561                         compatible = "rockchip,gpio-bank";
1562                         reg = <0x0 0xff720000 0x0 0x100>;
1563                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1564                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1565
1566                         gpio-controller;
1567                         #gpio-cells = <0x2>;
1568
1569                         interrupt-controller;
1570                         #interrupt-cells = <0x2>;
1571                 };
1572
1573                 gpio1: gpio1@ff730000 {
1574                         compatible = "rockchip,gpio-bank";
1575                         reg = <0x0 0xff730000 0x0 0x100>;
1576                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1577                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1578
1579                         gpio-controller;
1580                         #gpio-cells = <0x2>;
1581
1582                         interrupt-controller;
1583                         #interrupt-cells = <0x2>;
1584                 };
1585
1586                 gpio2: gpio2@ff780000 {
1587                         compatible = "rockchip,gpio-bank";
1588                         reg = <0x0 0xff780000 0x0 0x100>;
1589                         clocks = <&cru PCLK_GPIO2>;
1590                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1591
1592                         gpio-controller;
1593                         #gpio-cells = <0x2>;
1594
1595                         interrupt-controller;
1596                         #interrupt-cells = <0x2>;
1597                 };
1598
1599                 gpio3: gpio3@ff788000 {
1600                         compatible = "rockchip,gpio-bank";
1601                         reg = <0x0 0xff788000 0x0 0x100>;
1602                         clocks = <&cru PCLK_GPIO3>;
1603                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1604
1605                         gpio-controller;
1606                         #gpio-cells = <0x2>;
1607
1608                         interrupt-controller;
1609                         #interrupt-cells = <0x2>;
1610                 };
1611
1612                 gpio4: gpio4@ff790000 {
1613                         compatible = "rockchip,gpio-bank";
1614                         reg = <0x0 0xff790000 0x0 0x100>;
1615                         clocks = <&cru PCLK_GPIO4>;
1616                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1617
1618                         gpio-controller;
1619                         #gpio-cells = <0x2>;
1620
1621                         interrupt-controller;
1622                         #interrupt-cells = <0x2>;
1623                 };
1624
1625                 pcfg_pull_up: pcfg-pull-up {
1626                         bias-pull-up;
1627                 };
1628
1629                 pcfg_pull_down: pcfg-pull-down {
1630                         bias-pull-down;
1631                 };
1632
1633                 pcfg_pull_none: pcfg-pull-none {
1634                         bias-disable;
1635                 };
1636
1637                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1638                         bias-disable;
1639                         drive-strength = <12>;
1640                 };
1641
1642                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1643                         bias-pull-up;
1644                         drive-strength = <8>;
1645                 };
1646
1647                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1648                         bias-pull-down;
1649                         drive-strength = <4>;
1650                 };
1651
1652                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1653                         bias-pull-up;
1654                         drive-strength = <2>;
1655                 };
1656
1657                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1658                         bias-pull-down;
1659                         drive-strength = <12>;
1660                 };
1661
1662                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1663                         bias-disable;
1664                         drive-strength = <13>;
1665                 };
1666
1667                 emmc {
1668                         emmc_pwr: emmc-pwr {
1669                                 rockchip,pins =
1670                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1671                         };
1672                 };
1673
1674                 gmac {
1675                         rgmii_pins: rgmii-pins {
1676                                 rockchip,pins =
1677                                         /* mac_txclk */
1678                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1679                                         /* mac_rxclk */
1680                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1681                                         /* mac_mdio */
1682                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1683                                         /* mac_txen */
1684                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1685                                         /* mac_clk */
1686                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1687                                         /* mac_rxdv */
1688                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1689                                         /* mac_mdc */
1690                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1691                                         /* mac_rxd1 */
1692                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1693                                         /* mac_rxd0 */
1694                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1695                                         /* mac_txd1 */
1696                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1697                                         /* mac_txd0 */
1698                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1699                                         /* mac_rxd3 */
1700                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1701                                         /* mac_rxd2 */
1702                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1703                                         /* mac_txd3 */
1704                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1705                                         /* mac_txd2 */
1706                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1707                         };
1708
1709                         rmii_pins: rmii-pins {
1710                                 rockchip,pins =
1711                                         /* mac_mdio */
1712                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1713                                         /* mac_txen */
1714                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1715                                         /* mac_clk */
1716                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1717                                         /* mac_rxer */
1718                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1719                                         /* mac_rxdv */
1720                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1721                                         /* mac_mdc */
1722                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1723                                         /* mac_rxd1 */
1724                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1725                                         /* mac_rxd0 */
1726                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1727                                         /* mac_txd1 */
1728                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1729                                         /* mac_txd0 */
1730                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1731                         };
1732                 };
1733
1734                 i2c0 {
1735                         i2c0_xfer: i2c0-xfer {
1736                                 rockchip,pins =
1737                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1738                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1739                         };
1740                 };
1741
1742                 i2c1 {
1743                         i2c1_xfer: i2c1-xfer {
1744                                 rockchip,pins =
1745                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1746                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1747                         };
1748                 };
1749
1750                 i2c2 {
1751                         i2c2_xfer: i2c2-xfer {
1752                                 rockchip,pins =
1753                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1754                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1755                         };
1756                 };
1757
1758                 i2c3 {
1759                         i2c3_xfer: i2c3-xfer {
1760                                 rockchip,pins =
1761                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1762                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1763                         };
1764
1765                         i2c3_gpio: i2c3_gpio {
1766                                 rockchip,pins =
1767                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1768                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1769                         };
1770
1771                 };
1772
1773                 i2c4 {
1774                         i2c4_xfer: i2c4-xfer {
1775                                 rockchip,pins =
1776                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1777                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1778                         };
1779                 };
1780
1781                 i2c5 {
1782                         i2c5_xfer: i2c5-xfer {
1783                                 rockchip,pins =
1784                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1785                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1786                         };
1787                 };
1788
1789                 i2c6 {
1790                         i2c6_xfer: i2c6-xfer {
1791                                 rockchip,pins =
1792                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1793                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1794                         };
1795                 };
1796
1797                 i2c7 {
1798                         i2c7_xfer: i2c7-xfer {
1799                                 rockchip,pins =
1800                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1801                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1802                         };
1803                 };
1804
1805                 i2c8 {
1806                         i2c8_xfer: i2c8-xfer {
1807                                 rockchip,pins =
1808                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1809                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1810                         };
1811                 };
1812
1813                 i2s0 {
1814                         i2s0_8ch_bus: i2s0-8ch-bus {
1815                                 rockchip,pins =
1816                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1817                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1818                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1819                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1820                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1821                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1822                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1823                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1824                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1825                         };
1826                 };
1827
1828                 i2s1 {
1829                         i2s1_2ch_bus: i2s1-2ch-bus {
1830                                 rockchip,pins =
1831                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1832                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1833                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1834                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1835                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1836                         };
1837                 };
1838
1839                 sdio0 {
1840                         sdio0_bus1: sdio0-bus1 {
1841                                 rockchip,pins =
1842                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1843                         };
1844
1845                         sdio0_bus4: sdio0-bus4 {
1846                                 rockchip,pins =
1847                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1848                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1849                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1850                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1851                         };
1852
1853                         sdio0_cmd: sdio0-cmd {
1854                                 rockchip,pins =
1855                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1856                         };
1857
1858                         sdio0_clk: sdio0-clk {
1859                                 rockchip,pins =
1860                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1861                         };
1862
1863                         sdio0_cd: sdio0-cd {
1864                                 rockchip,pins =
1865                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1866                         };
1867
1868                         sdio0_pwr: sdio0-pwr {
1869                                 rockchip,pins =
1870                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1871                         };
1872
1873                         sdio0_bkpwr: sdio0-bkpwr {
1874                                 rockchip,pins =
1875                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1876                         };
1877
1878                         sdio0_wp: sdio0-wp {
1879                                 rockchip,pins =
1880                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1881                         };
1882
1883                         sdio0_int: sdio0-int {
1884                                 rockchip,pins =
1885                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1886                         };
1887                 };
1888
1889                 sdmmc {
1890                         sdmmc_bus1: sdmmc-bus1 {
1891                                 rockchip,pins =
1892                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1893                         };
1894
1895                         sdmmc_bus4: sdmmc-bus4 {
1896                                 rockchip,pins =
1897                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1898                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1899                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1900                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1901                         };
1902
1903                         sdmmc_clk: sdmmc-clk {
1904                                 rockchip,pins =
1905                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1906                         };
1907
1908                         sdmmc_cmd: sdmmc-cmd {
1909                                 rockchip,pins =
1910                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1911                         };
1912
1913                         sdmmc_cd: sdmcc-cd {
1914                                 rockchip,pins =
1915                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1916                         };
1917
1918                         sdmmc_wp: sdmmc-wp {
1919                                 rockchip,pins =
1920                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1921                         };
1922                 };
1923
1924                 spdif {
1925                         spdif_bus: spdif-bus {
1926                                 rockchip,pins =
1927                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1928                         };
1929
1930                         spdif_bus_1: spdif-bus-1 {
1931                                 rockchip,pins =
1932                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
1933                         };
1934                 };
1935
1936                 spi0 {
1937                         spi0_clk: spi0-clk {
1938                                 rockchip,pins =
1939                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1940                         };
1941                         spi0_cs0: spi0-cs0 {
1942                                 rockchip,pins =
1943                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1944                         };
1945                         spi0_cs1: spi0-cs1 {
1946                                 rockchip,pins =
1947                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1948                         };
1949                         spi0_tx: spi0-tx {
1950                                 rockchip,pins =
1951                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1952                         };
1953                         spi0_rx: spi0-rx {
1954                                 rockchip,pins =
1955                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1956                         };
1957                 };
1958
1959                 spi1 {
1960                         spi1_clk: spi1-clk {
1961                                 rockchip,pins =
1962                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1963                         };
1964                         spi1_cs0: spi1-cs0 {
1965                                 rockchip,pins =
1966                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1967                         };
1968                         spi1_rx: spi1-rx {
1969                                 rockchip,pins =
1970                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1971                         };
1972                         spi1_tx: spi1-tx {
1973                                 rockchip,pins =
1974                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1975                         };
1976                 };
1977
1978                 spi2 {
1979                         spi2_clk: spi2-clk {
1980                                 rockchip,pins =
1981                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1982                         };
1983                         spi2_cs0: spi2-cs0 {
1984                                 rockchip,pins =
1985                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1986                         };
1987                         spi2_rx: spi2-rx {
1988                                 rockchip,pins =
1989                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1990                         };
1991                         spi2_tx: spi2-tx {
1992                                 rockchip,pins =
1993                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1994                         };
1995                 };
1996
1997                 spi3 {
1998                         spi3_clk: spi3-clk {
1999                                 rockchip,pins =
2000                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2001                         };
2002                         spi3_cs0: spi3-cs0 {
2003                                 rockchip,pins =
2004                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2005                         };
2006                         spi3_rx: spi3-rx {
2007                                 rockchip,pins =
2008                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2009                         };
2010                         spi3_tx: spi3-tx {
2011                                 rockchip,pins =
2012                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2013                         };
2014                 };
2015
2016                 spi4 {
2017                         spi4_clk: spi4-clk {
2018                                 rockchip,pins =
2019                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2020                         };
2021                         spi4_cs0: spi4-cs0 {
2022                                 rockchip,pins =
2023                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2024                         };
2025                         spi4_rx: spi4-rx {
2026                                 rockchip,pins =
2027                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2028                         };
2029                         spi4_tx: spi4-tx {
2030                                 rockchip,pins =
2031                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2032                         };
2033                 };
2034
2035                 spi5 {
2036                         spi5_clk: spi5-clk {
2037                                 rockchip,pins =
2038                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2039                         };
2040                         spi5_cs0: spi5-cs0 {
2041                                 rockchip,pins =
2042                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2043                         };
2044                         spi5_rx: spi5-rx {
2045                                 rockchip,pins =
2046                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2047                         };
2048                         spi5_tx: spi5-tx {
2049                                 rockchip,pins =
2050                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2051                         };
2052                 };
2053
2054                 tsadc {
2055                         otp_gpio: otp-gpio {
2056                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2057                         };
2058
2059                         otp_out: otp-out {
2060                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2061                         };
2062                 };
2063
2064                 uart0 {
2065                         uart0_xfer: uart0-xfer {
2066                                 rockchip,pins =
2067                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2068                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2069                         };
2070
2071                         uart0_cts: uart0-cts {
2072                                 rockchip,pins =
2073                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2074                         };
2075
2076                         uart0_rts: uart0-rts {
2077                                 rockchip,pins =
2078                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2079                         };
2080                 };
2081
2082                 uart1 {
2083                         uart1_xfer: uart1-xfer {
2084                                 rockchip,pins =
2085                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2086                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2087                         };
2088                 };
2089
2090                 uart2a {
2091                         uart2a_xfer: uart2a-xfer {
2092                                 rockchip,pins =
2093                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2094                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2095                         };
2096                 };
2097
2098                 uart2b {
2099                         uart2b_xfer: uart2b-xfer {
2100                                 rockchip,pins =
2101                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2102                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2103                         };
2104                 };
2105
2106                 uart2c {
2107                         uart2c_xfer: uart2c-xfer {
2108                                 rockchip,pins =
2109                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2110                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2111                         };
2112                 };
2113
2114                 uart3 {
2115                         uart3_xfer: uart3-xfer {
2116                                 rockchip,pins =
2117                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2118                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2119                         };
2120
2121                         uart3_cts: uart3-cts {
2122                                 rockchip,pins =
2123                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2124                         };
2125
2126                         uart3_rts: uart3-rts {
2127                                 rockchip,pins =
2128                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2129                         };
2130                 };
2131
2132                 uart4 {
2133                         uart4_xfer: uart4-xfer {
2134                                 rockchip,pins =
2135                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2136                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2137                         };
2138                 };
2139
2140                 uarthdcp {
2141                         uarthdcp_xfer: uarthdcp-xfer {
2142                                 rockchip,pins =
2143                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2144                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2145                         };
2146                 };
2147
2148                 pwm0 {
2149                         pwm0_pin: pwm0-pin {
2150                                 rockchip,pins =
2151                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2152                         };
2153
2154                         vop0_pwm_pin: vop0-pwm-pin {
2155                                 rockchip,pins =
2156                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2157                         };
2158                 };
2159
2160                 pwm1 {
2161                         pwm1_pin: pwm1-pin {
2162                                 rockchip,pins =
2163                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2164                         };
2165
2166                         vop1_pwm_pin: vop1-pwm-pin {
2167                                 rockchip,pins =
2168                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2169                         };
2170                 };
2171
2172                 pwm2 {
2173                         pwm2_pin: pwm2-pin {
2174                                 rockchip,pins =
2175                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2176                         };
2177                 };
2178
2179                 pwm3a {
2180                         pwm3a_pin: pwm3a-pin {
2181                                 rockchip,pins =
2182                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2183                         };
2184                 };
2185
2186                 pwm3b {
2187                         pwm3b_pin: pwm3b-pin {
2188                                 rockchip,pins =
2189                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2190                         };
2191                 };
2192
2193                 edp {
2194                         edp_hpd: edp-hpd {
2195                                 rockchip,pins =
2196                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2197                         };
2198                 };
2199
2200                 hdmi {
2201                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2202                                 rockchip,pins =
2203                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2204                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2205                         };
2206
2207                         hdmi_cec: hdmi-cec {
2208                                 rockchip,pins =
2209                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2210                         };
2211                 };
2212
2213                 pcie {
2214                         pcie_clkreqn: pci-clkreqn {
2215                                 rockchip,pins =
2216                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2217                         };
2218
2219                         pcie_clkreqnb: pci-clkreqnb {
2220                                 rockchip,pins =
2221                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2222                         };
2223                 };
2224         };
2225 };