arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         clocks = <&cru ARMCLKL>;
 116                         operating-points-v2 = <&cluster0_opp>;
 117                 };
 118
 119                 cpu_l1: cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x1>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKL>;
 125                         operating-points-v2 = <&cluster0_opp>;
 126                 };
 127
 128                 cpu_l2: cpu@2 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x2>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                 };
 136
 137                 cpu_l3: cpu@3 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x3>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu_b0: cpu@100 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a72", "arm,armv8";
 149                         reg = <0x0 0x100>;
 150                         enable-method = "psci";
 151                         #cooling-cells = <2>; /* min followed by max */
 152                         clocks = <&cru ARMCLKB>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_b1: cpu@101 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a72", "arm,armv8";
 159                         reg = <0x0 0x101>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKB>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164         };
 165
 166         cluster0_opp: opp_table0 {
 167                 compatible = "operating-points-v2";
 168                 opp-shared;
 169
 170                 opp00 {
 171                         opp-hz = /bits/ 64 <408000000>;
 172                         opp-microvolt = <900000>;
 173                         clock-latency-ns = <40000>;
 174                 };
 175                 opp01 {
 176                         opp-hz = /bits/ 64 <600000000>;
 177                         opp-microvolt = <900000>;
 178                 };
 179                 opp02 {
 180                         opp-hz = /bits/ 64 <816000000>;
 181                         opp-microvolt = <900000>;
 182                 };
 183                 opp03 {
 184                         opp-hz = /bits/ 64 <1008000000>;
 185                         opp-microvolt = <900000>;
 186                 };
 187         };
 188
 189         cluster1_opp: opp_table1 {
 190                 compatible = "operating-points-v2";
 191                 opp-shared;
 192
 193                 opp00 {
 194                         opp-hz = /bits/ 64 <408000000>;
 195                         opp-microvolt = <900000>;
 196                         clock-latency-ns = <40000>;
 197                 };
 198                 opp01 {
 199                         opp-hz = /bits/ 64 <600000000>;
 200                         opp-microvolt = <900000>;
 201                 };
 202                 opp02 {
 203                         opp-hz = /bits/ 64 <816000000>;
 204                         opp-microvolt = <900000>;
 205                 };
 206                 opp03 {
 207                         opp-hz = /bits/ 64 <1008000000>;
 208                         opp-microvolt = <900000>;
 209                 };
 210                 opp04 {
 211                         opp-hz = /bits/ 64 <1200000000>;
 212                         opp-microvolt = <900000>;
 213                 };
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv8-timer";
 218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 222         };
 223
 224         arm-pmu {
 225                 compatible = "arm,armv8-pmuv3";
 226                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 227         };
 228
 229         xin24m: xin24m {
 230                 compatible = "fixed-clock";
 231                 #clock-cells = <0>;
 232                 clock-frequency = <24000000>;
 233                 clock-output-names = "xin24m";
 234         };
 235
 236         amba {
 237                 compatible = "arm,amba-bus";
 238                 #address-cells = <2>;
 239                 #size-cells = <2>;
 240                 ranges;
 241
 242                 dmac_bus: dma-controller@ff6d0000 {
 243                         compatible = "arm,pl330", "arm,primecell";
 244                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 245                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 247                         #dma-cells = <1>;
 248                         clocks = <&cru ACLK_DMAC0_PERILP>;
 249                         clock-names = "apb_pclk";
 250                 };
 251
 252                 dmac_peri: dma-controller@ff6e0000 {
 253                         compatible = "arm,pl330", "arm,primecell";
 254                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 255                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 256                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 257                         #dma-cells = <1>;
 258                         clocks = <&cru ACLK_DMAC1_PERILP>;
 259                         clock-names = "apb_pclk";
 260                 };
 261         };
 262
 263         gmac: eth@fe300000 {
 264                 compatible = "rockchip,rk3399-gmac";
 265                 reg = <0x0 0xfe300000 0x0 0x10000>;
 266                 rockchip,grf = <&grf>;
 267                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 268                 interrupt-names = "macirq";
 269                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 270                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 271                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 272                          <&cru PCLK_GMAC>;
 273                 clock-names = "stmmaceth", "mac_clk_rx",
 274                               "mac_clk_tx", "clk_mac_ref",
 275                               "clk_mac_refout", "aclk_mac",
 276                               "pclk_mac";
 277                 resets = <&cru SRST_A_GMAC>;
 278                 reset-names = "stmmaceth";
 279                 status = "disabled";
 280         };
 281
 282         emmc_phy: phy {
 283                 compatible = "rockchip,rk3399-emmc-phy";
 284                 reg-offset = <0xf780>;
 285                 #phy-cells = <0>;
 286                 rockchip,grf = <&grf>;
 287                 status = "disabled";
 288         };
 289
 290         sdio0: dwmmc@fe310000 {
 291                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 292                 reg = <0x0 0xfe310000 0x0 0x4000>;
 293                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 294                 clock-freq-min-max = <400000 150000000>;
 295                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 296                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 297                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 298                 fifo-depth = <0x100>;
 299                 status = "disabled";
 300         };
 301
 302         sdmmc: dwmmc@fe320000 {
 303                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 304                 reg = <0x0 0xfe320000 0x0 0x4000>;
 305                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 306                 clock-freq-min-max = <400000 150000000>;
 307                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 308                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 309                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 310                 fifo-depth = <0x100>;
 311                 status = "disabled";
 312         };
 313
 314         sdhci: sdhci@fe330000 {
 315                 compatible = "arasan,sdhci-5.1";
 316                 reg = <0x0 0xfe330000 0x0 0x10000>;
 317                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 318                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 319                 clock-names = "clk_xin", "clk_ahb";
 320                 phys = <&emmc_phy>;
 321                 phy-names = "phy_arasan";
 322                 status = "disabled";
 323         };
 324
 325         usb2phy: usb2phy {
 326                 compatible = "rockchip,rk3399-usb-phy";
 327                 rockchip,grf = <&grf>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330
 331                 usb2phy0: usb2-phy0 {
 332                         #phy-cells = <0>;
 333                         #clock-cells = <0>;
 334                         reg = <0xe458>;
 335                 };
 336
 337                 usb2phy1: usb2-phy1 {
 338                         #phy-cells = <0>;
 339                         #clock-cells = <0>;
 340                         reg = <0xe468>;
 341                 };
 342         };
 343
 344         usb_host0_echi: usb@fe380000 {
 345                 compatible = "generic-ehci";
 346                 reg = <0x0 0xfe380000 0x0 0x20000>;
 347                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 349                 clock-names = "hclk_host0", "hclk_host0_arb";
 350                 phys = <&usb2phy0>;
 351                 phy-names = "usb2_phy0";
 352                 status = "disabled";
 353         };
 354
 355         usb_host0_ohci: usb@fe3a0000 {
 356                 compatible = "generic-ohci";
 357                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 358                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 359                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 360                 clock-names = "hclk_host0", "hclk_host0_arb";
 361                 status = "disabled";
 362         };
 363
 364         usb_host1_echi: usb@fe3c0000 {
 365                 compatible = "generic-ehci";
 366                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 367                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 368                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 369                 clock-names = "hclk_host1", "hclk_host1_arb";
 370                 phys = <&usb2phy1>;
 371                 phy-names = "usb2_phy1";
 372                 status = "disabled";
 373         };
 374
 375         usb_host1_ohci: usb@fe3e0000 {
 376                 compatible = "generic-ohci";
 377                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 378                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 379                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 380                 clock-names = "hclk_host1", "hclk_host1_arb";
 381                 status = "disabled";
 382         };
 383
 384         usbdrd3_0: usb@fe800000 {
 385                 compatible = "rockchip,dwc3";
 386                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 387                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 388                          <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
 389                          <&cru ACLK_USB3_GRF>;
 390                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 391                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 392                               "aclk_usb3", "aclk_usb3_noc",
 393                               "aclk_usb3_grf";
 394                 #address-cells = <2>;
 395                 #size-cells = <2>;
 396                 ranges;
 397                 status = "disabled";
 398                 usbdrd_dwc3_0: dwc3 {
 399                         compatible = "snps,dwc3";
 400                         reg = <0x0 0xfe800000 0x0 0x100000>;
 401                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 402                         dr_mode = "otg";
 403                         tx-fifo-resize;
 404                         snps,dis_enblslpm_quirk;
 405                         snps,phyif_utmi_16_bits;
 406                         snps,dis_u2_freeclk_exists_quirk;
 407                         snps,dis_del_phy_power_chg_quirk;
 408                         status = "disabled";
 409                 };
 410         };
 411
 412         usbdrd3_1: usb@fe900000 {
 413                 compatible = "rockchip,dwc3";
 414                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 415                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 416                          <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
 417                          <&cru ACLK_USB3_GRF>;
 418                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 419                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 420                               "aclk_usb3", "aclk_usb3_noc",
 421                               "aclk_usb3_grf";
 422                 #address-cells = <2>;
 423                 #size-cells = <2>;
 424                 ranges;
 425                 status = "disabled";
 426                 usbdrd_dwc3_1: dwc3 {
 427                         compatible = "snps,dwc3";
 428                         reg = <0x0 0xfe900000 0x0 0x100000>;
 429                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 430                         dr_mode = "otg";
 431                         tx-fifo-resize;
 432                         snps,dis_enblslpm_quirk;
 433                         snps,phyif_utmi_16_bits;
 434                         snps,dis_u2_freeclk_exists_quirk;
 435                         snps,dis_del_phy_power_chg_quirk;
 436                         status = "disabled";
 437                 };
 438         };
 439
 440         gic: interrupt-controller@fee00000 {
 441                 compatible = "arm,gic-v3";
 442                 #interrupt-cells = <3>;
 443                 #address-cells = <2>;
 444                 #size-cells = <2>;
 445                 ranges;
 446                 interrupt-controller;
 447
 448                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 449                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 450                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 451                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 452                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 453                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 454                 its: interrupt-controller@fee20000 {
 455                         compatible = "arm,gic-v3-its";
 456                         msi-controller;
 457                         reg = <0x0 0xfee20000 0x0 0x20000>;
 458                 };
 459         };
 460
 461         saradc: saradc@ff100000 {
 462                 compatible = "rockchip,rk3399-saradc";
 463                 reg = <0x0 0xff100000 0x0 0x100>;
 464                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 465                 #io-channel-cells = <1>;
 466                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 467                 clock-names = "saradc", "apb_pclk";
 468                 status = "disabled";
 469         };
 470
 471         i2c0: i2c@ff3c0000 {
 472                 compatible = "rockchip,rk3399-i2c";
 473                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 474                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 475                 clock-names = "i2c", "pclk";
 476                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&i2c0_xfer>;
 479                 #address-cells = <1>;
 480                 #size-cells = <0>;
 481                 status = "disabled";
 482         };
 483
 484         i2c1: i2c@ff110000 {
 485                 compatible = "rockchip,rk3399-i2c";
 486                 reg = <0x0 0xff110000 0x0 0x1000>;
 487                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 488                 clock-names = "i2c", "pclk";
 489                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&i2c1_xfer>;
 492                 #address-cells = <1>;
 493                 #size-cells = <0>;
 494                 status = "disabled";
 495         };
 496
 497         i2c2: i2c@ff120000 {
 498                 compatible = "rockchip,rk3399-i2c";
 499                 reg = <0x0 0xff120000 0x0 0x1000>;
 500                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 501                 clock-names = "i2c", "pclk";
 502                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 503                 pinctrl-names = "default";
 504                 pinctrl-0 = <&i2c2_xfer>;
 505                 #address-cells = <1>;
 506                 #size-cells = <0>;
 507                 status = "disabled";
 508         };
 509
 510         i2c3: i2c@ff130000 {
 511                 compatible = "rockchip,rk3399-i2c";
 512                 reg = <0x0 0xff130000 0x0 0x1000>;
 513                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 514                 clock-names = "i2c", "pclk";
 515                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 516                 pinctrl-names = "default";
 517                 pinctrl-0 = <&i2c3_xfer>;
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 status = "disabled";
 521         };
 522
 523         i2c5: i2c@ff140000 {
 524                 compatible = "rockchip,rk3399-i2c";
 525                 reg = <0x0 0xff140000 0x0 0x1000>;
 526                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 527                 clock-names = "i2c", "pclk";
 528                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 529                 pinctrl-names = "default";
 530                 pinctrl-0 = <&i2c5_xfer>;
 531                 #address-cells = <1>;
 532                 #size-cells = <0>;
 533                 status = "disabled";
 534         };
 535
 536         i2c6: i2c@ff150000 {
 537                 compatible = "rockchip,rk3399-i2c";
 538                 reg = <0x0 0xff150000 0x0 0x1000>;
 539                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 540                 clock-names = "i2c", "pclk";
 541                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 542                 pinctrl-names = "default";
 543                 pinctrl-0 = <&i2c6_xfer>;
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546                 status = "disabled";
 547         };
 548
 549         i2c7: i2c@ff160000 {
 550                 compatible = "rockchip,rk3399-i2c";
 551                 reg = <0x0 0xff160000 0x0 0x1000>;
 552                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 553                 clock-names = "i2c", "pclk";
 554                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 555                 pinctrl-names = "default";
 556                 pinctrl-0 = <&i2c7_xfer>;
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 status = "disabled";
 560         };
 561
 562         uart0: serial@ff180000 {
 563                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 564                 reg = <0x0 0xff180000 0x0 0x100>;
 565                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 566                 clock-names = "baudclk", "apb_pclk";
 567                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 568                 reg-shift = <2>;
 569                 reg-io-width = <4>;
 570                 pinctrl-names = "default";
 571                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 572                 status = "disabled";
 573         };
 574
 575         uart1: serial@ff190000 {
 576                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 577                 reg = <0x0 0xff190000 0x0 0x100>;
 578                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 579                 clock-names = "baudclk", "apb_pclk";
 580                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 581                 reg-shift = <2>;
 582                 reg-io-width = <4>;
 583                 pinctrl-names = "default";
 584                 pinctrl-0 = <&uart1_xfer>;
 585                 status = "disabled";
 586         };
 587
 588         uart2: serial@ff1a0000 {
 589                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 590                 reg = <0x0 0xff1a0000 0x0 0x100>;
 591                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 592                 clock-names = "baudclk", "apb_pclk";
 593                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 594                 reg-shift = <2>;
 595                 reg-io-width = <4>;
 596                 pinctrl-names = "default";
 597                 pinctrl-0 = <&uart2c_xfer>;
 598                 status = "disabled";
 599         };
 600
 601         uart3: serial@ff1b0000 {
 602                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 603                 reg = <0x0 0xff1b0000 0x0 0x100>;
 604                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 605                 clock-names = "baudclk", "apb_pclk";
 606                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 607                 reg-shift = <2>;
 608                 reg-io-width = <4>;
 609                 pinctrl-names = "default";
 610                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 611                 status = "disabled";
 612         };
 613
 614         spi0: spi@ff1c0000 {
 615                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 616                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 617                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 618                 clock-names = "spiclk", "apb_pclk";
 619                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 620                 pinctrl-names = "default";
 621                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 622                 #address-cells = <1>;
 623                 #size-cells = <0>;
 624                 status = "disabled";
 625         };
 626
 627         spi1: spi@ff1d0000 {
 628                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 629                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 630                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 631                 clock-names = "spiclk", "apb_pclk";
 632                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 633                 pinctrl-names = "default";
 634                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 635                 #address-cells = <1>;
 636                 #size-cells = <0>;
 637                 status = "disabled";
 638         };
 639
 640         spi2: spi@ff1e0000 {
 641                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 642                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 643                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 644                 clock-names = "spiclk", "apb_pclk";
 645                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 646                 pinctrl-names = "default";
 647                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 648                 #address-cells = <1>;
 649                 #size-cells = <0>;
 650                 status = "disabled";
 651         };
 652
 653         spi4: spi@ff1f0000 {
 654                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 655                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 656                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 657                 clock-names = "spiclk", "apb_pclk";
 658                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 659                 pinctrl-names = "default";
 660                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 661                 #address-cells = <1>;
 662                 #size-cells = <0>;
 663                 status = "disabled";
 664         };
 665
 666         spi5: spi@ff200000 {
 667                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 668                 reg = <0x0 0xff200000 0x0 0x1000>;
 669                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 670                 clock-names = "spiclk", "apb_pclk";
 671                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 672                 pinctrl-names = "default";
 673                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 674                 #address-cells = <1>;
 675                 #size-cells = <0>;
 676                 status = "disabled";
 677         };
 678
 679         thermal-zones {
 680                 #include "rk3368-thermal.dtsi"
 681         };
 682
 683         tsadc: tsadc@ff260000 {
 684                 compatible = "rockchip,rk3399-tsadc";
 685                 reg = <0x0 0xff260000 0x0 0x100>;
 686                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 687                 rockchip,grf = <&grf>;
 688                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 689                 clock-names = "tsadc", "apb_pclk";
 690                 assigned-clocks = <&cru SCLK_TSADC>;
 691                 assigned-clock-rates = <750000>;
 692                 resets = <&cru SRST_TSADC>;
 693                 reset-names = "tsadc-apb";
 694                 pinctrl-names = "init", "default", "sleep";
 695                 pinctrl-0 = <&otp_gpio>;
 696                 pinctrl-1 = <&otp_out>;
 697                 pinctrl-2 = <&otp_gpio>;
 698                 #thermal-sensor-cells = <1>;
 699                 rockchip,hw-tshut-temp = <95000>;
 700                 status = "disabled";
 701         };
 702
 703         pmu: power-management@ff31000 {
 704                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 705                 reg = <0x0 0xff310000 0x0 0x1000>;
 706
 707                 power: power-controller {
 708                         status = "disabled";
 709                         compatible = "rockchip,rk3399-power-controller";
 710                         #power-domain-cells = <1>;
 711                         #address-cells = <1>;
 712                         #size-cells = <0>;
 713
 714                         pd_center {
 715                                 reg = <RK3399_PD_CENTER>;
 716                                 #address-cells = <1>;
 717                                 #size-cells = <0>;
 718
 719                                 pd_vdu {
 720                                         reg = <RK3399_PD_VDU>;
 721                                 };
 722                                 pd_vcodec {
 723                                         reg = <RK3399_PD_VCODEC>;
 724                                 };
 725                                 pd_iep {
 726                                         reg = <RK3399_PD_IEP>;
 727                                 };
 728                                 pd_rga {
 729                                         reg = <RK3399_PD_RGA>;
 730                                 };
 731                         };
 732                         pd_vio {
 733                                 reg = <RK3399_PD_VIO>;
 734                                 #address-cells = <1>;
 735                                 #size-cells = <0>;
 736
 737                                 pd_isp0 {
 738                                         reg = <RK3399_PD_ISP0>;
 739                                 };
 740                                 pd_isp1 {
 741                                         reg = <RK3399_PD_ISP1>;
 742                                 };
 743                                 pd_hdcp {
 744                                         reg = <RK3399_PD_HDCP>;
 745                                 };
 746                                 pd_vo {
 747                                         reg = <RK3399_PD_VO>;
 748                                         #address-cells = <1>;
 749                                         #size-cells = <0>;
 750
 751                                         pd_vopb {
 752                                                 reg = <RK3399_PD_VOPB>;
 753                                         };
 754                                         pd_vopl {
 755                                                 reg = <RK3399_PD_VOPL>;
 756                                         };
 757                                 };
 758                         };
 759                         pd_gpu {
 760                                 reg = <RK3399_PD_GPU>;
 761                         };
 762                 };
 763         };
 764
 765         pmugrf: syscon@ff320000 {
 766                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 767                 reg = <0x0 0xff320000 0x0 0x1000>;
 768         };
 769
 770         spi3: spi@ff350000 {
 771                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 772                 reg = <0x0 0xff350000 0x0 0x1000>;
 773                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 774                 clock-names = "spiclk", "apb_pclk";
 775                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 776                 pinctrl-names = "default";
 777                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 778                 #address-cells = <1>;
 779                 #size-cells = <0>;
 780                 status = "disabled";
 781         };
 782
 783         uart4: serial@ff370000 {
 784                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 785                 reg = <0x0 0xff370000 0x0 0x100>;
 786                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 787                 clock-names = "baudclk", "apb_pclk";
 788                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 789                 reg-shift = <2>;
 790                 reg-io-width = <4>;
 791                 pinctrl-names = "default";
 792                 pinctrl-0 = <&uart4_xfer>;
 793                 status = "disabled";
 794         };
 795
 796         i2c4: i2c@ff3d0000 {
 797                 compatible = "rockchip,rk3399-i2c";
 798                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 799                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 800                 clock-names = "i2c", "pclk";
 801                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 802                 pinctrl-names = "default";
 803                 pinctrl-0 = <&i2c4_xfer>;
 804                 #address-cells = <1>;
 805                 #size-cells = <0>;
 806                 status = "disabled";
 807         };
 808
 809         i2c8: i2c@ff3e0000 {
 810                 compatible = "rockchip,rk3399-i2c";
 811                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 812                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 813                 clock-names = "i2c", "pclk";
 814                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 815                 pinctrl-names = "default";
 816                 pinctrl-0 = <&i2c8_xfer>;
 817                 #address-cells = <1>;
 818                 #size-cells = <0>;
 819                 status = "disabled";
 820         };
 821
 822         pwm0: pwm@ff420000 {
 823                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 824                 reg = <0x0 0xff420000 0x0 0x10>;
 825                 #pwm-cells = <3>;
 826                 pinctrl-names = "default";
 827                 pinctrl-0 = <&pwm0_pin>;
 828                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 829                 clock-names = "pwm";
 830                 status = "disabled";
 831         };
 832
 833         pwm1: pwm@ff420010 {
 834                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 835                 reg = <0x0 0xff420010 0x0 0x10>;
 836                 #pwm-cells = <3>;
 837                 pinctrl-names = "default";
 838                 pinctrl-0 = <&pwm1_pin>;
 839                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 840                 clock-names = "pwm";
 841                 status = "disabled";
 842         };
 843
 844         pwm2: pwm@ff420020 {
 845                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 846                 reg = <0x0 0xff420020 0x0 0x10>;
 847                 #pwm-cells = <3>;
 848                 pinctrl-names = "default";
 849                 pinctrl-0 = <&pwm2_pin>;
 850                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 851                 clock-names = "pwm";
 852                 status = "disabled";
 853         };
 854
 855         pwm3: pwm@ff420030 {
 856                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 857                 reg = <0x0 0xff420030 0x0 0x10>;
 858                 #pwm-cells = <3>;
 859                 pinctrl-names = "default";
 860                 pinctrl-0 = <&pwm3a_pin>;
 861                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 862                 clock-names = "pwm";
 863                 status = "disabled";
 864         };
 865
 866         pmucru: pmu-clock-controller@ff750000 {
 867                 compatible = "rockchip,rk3399-pmucru";
 868                 reg = <0x0 0xff750000 0x0 0x1000>;
 869                 #clock-cells = <1>;
 870                 #reset-cells = <1>;
 871                 assigned-clocks = <&pmucru PLL_PPLL>;
 872                 assigned-clock-rates = <676000000>;
 873         };
 874
 875         cru: clock-controller@ff760000 {
 876                 compatible = "rockchip,rk3399-cru";
 877                 reg = <0x0 0xff760000 0x0 0x1000>;
 878                 #clock-cells = <1>;
 879                 #reset-cells = <1>;
 880                 assigned-clocks =
 881                         <&cru ARMCLKL>, <&cru ARMCLKB>,
 882                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 883                         <&cru PLL_NPLL>,
 884                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 885                         <&cru PCLK_PERIHP>,
 886                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 887                         <&cru PCLK_PERILP0>,
 888                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 889                 assigned-clock-rates =
 890                          <816000000>, <1008000000>,
 891                          <594000000>,  <800000000>,
 892                         <1000000000>,
 893                          <150000000>,   <75000000>,
 894                           <37500000>,
 895                          <100000000>,  <100000000>,
 896                           <50000000>,
 897                          <100000000>,   <50000000>;
 898         };
 899
 900         grf: syscon@ff770000 {
 901                 compatible = "rockchip,rk3399-grf", "syscon";
 902                 reg = <0x0 0xff770000 0x0 0x10000>;
 903         };
 904
 905         wdt0: watchdog@ff840000 {
 906                 compatible = "snps,dw-wdt";
 907                 reg = <0x0 0xff840000 0x0 0x100>;
 908                 clocks = <&cru PCLK_WDT>;
 909                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 910                 status = "disabled";
 911         };
 912
 913         spdif: spdif@ff870000 {
 914                 compatible = "rockchip,rk3399-spdif";
 915                 reg = <0x0 0xff870000 0x0 0x1000>;
 916                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 917                 dmas = <&dmac_bus 7>;
 918                 dma-names = "tx";
 919                 clock-names = "mclk", "hclk";
 920                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 921                 pinctrl-names = "default";
 922                 pinctrl-0 = <&spdif_bus>;
 923                 status = "disabled";
 924         };
 925
 926         i2s0: i2s@ff880000 {
 927                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 928                 reg = <0x0 0xff880000 0x0 0x1000>;
 929                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 930                 #address-cells = <1>;
 931                 #size-cells = <0>;
 932                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 933                 dma-names = "tx", "rx";
 934                 clock-names = "i2s_clk", "i2s_hclk";
 935                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
 936                 pinctrl-names = "default";
 937                 pinctrl-0 = <&i2s0_8ch_bus>;
 938                 status = "disabled";
 939         };
 940
 941         i2s1: i2s@ff890000 {
 942                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 943                 reg = <0x0 0xff890000 0x0 0x1000>;
 944                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 945                 #address-cells = <1>;
 946                 #size-cells = <0>;
 947                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 948                 dma-names = "tx", "rx";
 949                 clock-names = "i2s_clk", "i2s_hclk";
 950                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
 951                 pinctrl-names = "default";
 952                 pinctrl-0 = <&i2s1_2ch_bus>;
 953                 status = "disabled";
 954         };
 955
 956         i2s2: i2s@ff8a0000 {
 957                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 958                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 959                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 960                 #address-cells = <1>;
 961                 #size-cells = <0>;
 962                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 963                 dma-names = "tx", "rx";
 964                 clock-names = "i2s_clk", "i2s_hclk";
 965                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
 966                 status = "disabled";
 967         };
 968
 969         gpu: gpu@ff9a0000 {
 970                 compatible = "arm,malit860",
 971                              "arm,malit86x",
 972                              "arm,malit8xx",
 973                              "arm,mali-midgard";
 974
 975                 reg = <0x0 0xff9a0000 0x0 0x10000>;
 976
 977                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 978                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 979                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 980                 interrupt-names = "GPU", "JOB", "MMU";
 981
 982                 clocks = <&cru ACLK_GPU>;
 983                 clock-names = "clk_mali";
 984                 operating-points-v2 = <&gpu_opp_table>;
 985                 status = "disabled";
 986         };
 987
 988         gpu_opp_table: gpu_opp_table {
 989                 compatible = "operating-points-v2";
 990                 opp-shared;
 991
 992                 opp00 {
 993                         opp-hz = /bits/ 64 <200000000>;
 994                         opp-microvolt = <900000>;
 995                 };
 996                 opp01 {
 997                         opp-hz = /bits/ 64 <300000000>;
 998                         opp-microvolt = <900000>;
 999                 };
1000                 opp02 {
1001                         opp-hz = /bits/ 64 <400000000>;
1002                         opp-microvolt = <900000>;
1003                 };
1004                 opp03 {
1005                         opp-hz = /bits/ 64 <500000000>;
1006                         opp-microvolt = <900000>;
1007                 };
1008         };
1009
1010         vopl: vop@ff8f0000 {
1011                 compatible = "rockchip,rk3399-vop-lit";
1012                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1013                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1014                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1015                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1016                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1017                 reset-names = "axi", "ahb", "dclk";
1018                 iommus = <&vopl_mmu>;
1019                 status = "disabled";
1020
1021                 vopl_out: port {
1022                         #address-cells = <1>;
1023                         #size-cells = <0>;
1024
1025                         vopl_out_mipi: endpoint@1 {
1026                                 reg = <1>;
1027                                 remote-endpoint = <&mipi_in_vopl>;
1028                         };
1029                 };
1030         };
1031
1032         vopl_mmu: iommu@ff8f3f00 {
1033                 compatible = "rockchip,iommu";
1034                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1035                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1036                 interrupt-names = "vopl_mmu";
1037                 #iommu-cells = <0>;
1038                 status = "disabled";
1039         };
1040
1041         vopb: vop@ff900000 {
1042                 compatible = "rockchip,rk3399-vop-big";
1043                 reg = <0x0 0xff900000 0x0 0x3efc>;
1044                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1045                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1046                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1047                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1048                 reset-names = "axi", "ahb", "dclk";
1049                 iommus = <&vopb_mmu>;
1050                 status = "disabled";
1051
1052                 vopb_out: port {
1053                         #address-cells = <1>;
1054                         #size-cells = <0>;
1055
1056                         vopb_out_mipi: endpoint@1 {
1057                                 reg = <1>;
1058                                 remote-endpoint = <&mipi_in_vopb>;
1059                         };
1060                 };
1061         };
1062
1063         vopb_mmu: iommu@ff903f00 {
1064                 compatible = "rockchip,iommu";
1065                 reg = <0x0 0xff903f00 0x0 0x100>;
1066                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1067                 interrupt-names = "vopb_mmu";
1068                 #iommu-cells = <0>;
1069                 status = "disabled";
1070         };
1071
1072         mipi_dsi: mipi@ff960000 {
1073                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1074                 reg = <0x0 0xff960000 0x0 0x8000>;
1075                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1076                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1077                          <&cru SCLK_DPHY_TX0_CFG>;
1078                 clock-names = "ref", "pclk", "phy_cfg";
1079                 rockchip,grf = <&grf>;
1080                 #address-cells = <1>;
1081                 #size-cells = <0>;
1082                 status = "disabled";
1083
1084                 ports {
1085                         #address-cells = <1>;
1086                         #size-cells = <0>;
1087                         reg = <1>;
1088
1089                         mipi_in: port {
1090                                 #address-cells = <1>;
1091                                 #size-cells = <0>;
1092
1093                                 mipi_in_vopb: endpoint@0 {
1094                                         reg = <0>;
1095                                         remote-endpoint = <&vopb_out_mipi>;
1096                                 };
1097                                 mipi_in_vopl: endpoint@1 {
1098                                         reg = <1>;
1099                                         remote-endpoint = <&vopl_out_mipi>;
1100                                 };
1101                         };
1102                 };
1103         };
1104
1105         display_subsystem: display-subsystem {
1106                 compatible = "rockchip,display-subsystem";
1107                 ports = <&vopl_out>, <&vopb_out>;
1108                 status = "disabled";
1109         };
1110
1111         pinctrl: pinctrl {
1112                 compatible = "rockchip,rk3399-pinctrl";
1113                 rockchip,grf = <&grf>;
1114                 rockchip,pmu = <&pmugrf>;
1115                 #address-cells = <0x2>;
1116                 #size-cells = <0x2>;
1117                 ranges;
1118
1119                 gpio0: gpio0@ff720000 {
1120                         compatible = "rockchip,gpio-bank";
1121                         reg = <0x0 0xff720000 0x0 0x100>;
1122                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1123                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1124
1125                         gpio-controller;
1126                         #gpio-cells = <0x2>;
1127
1128                         interrupt-controller;
1129                         #interrupt-cells = <0x2>;
1130                 };
1131
1132                 gpio1: gpio1@ff730000 {
1133                         compatible = "rockchip,gpio-bank";
1134                         reg = <0x0 0xff730000 0x0 0x100>;
1135                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1136                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1137
1138                         gpio-controller;
1139                         #gpio-cells = <0x2>;
1140
1141                         interrupt-controller;
1142                         #interrupt-cells = <0x2>;
1143                 };
1144
1145                 gpio2: gpio2@ff780000 {
1146                         compatible = "rockchip,gpio-bank";
1147                         reg = <0x0 0xff780000 0x0 0x100>;
1148                         clocks = <&cru PCLK_GPIO2>;
1149                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1150
1151                         gpio-controller;
1152                         #gpio-cells = <0x2>;
1153
1154                         interrupt-controller;
1155                         #interrupt-cells = <0x2>;
1156                 };
1157
1158                 gpio3: gpio3@ff788000 {
1159                         compatible = "rockchip,gpio-bank";
1160                         reg = <0x0 0xff788000 0x0 0x100>;
1161                         clocks = <&cru PCLK_GPIO3>;
1162                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1163
1164                         gpio-controller;
1165                         #gpio-cells = <0x2>;
1166
1167                         interrupt-controller;
1168                         #interrupt-cells = <0x2>;
1169                 };
1170
1171                 gpio4: gpio4@ff790000 {
1172                         compatible = "rockchip,gpio-bank";
1173                         reg = <0x0 0xff790000 0x0 0x100>;
1174                         clocks = <&cru PCLK_GPIO4>;
1175                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1176
1177                         gpio-controller;
1178                         #gpio-cells = <0x2>;
1179
1180                         interrupt-controller;
1181                         #interrupt-cells = <0x2>;
1182                 };
1183
1184                 pcfg_pull_up: pcfg-pull-up {
1185                         bias-pull-up;
1186                 };
1187
1188                 pcfg_pull_down: pcfg-pull-down {
1189                         bias-pull-down;
1190                 };
1191
1192                 pcfg_pull_none: pcfg-pull-none {
1193                         bias-disable;
1194                 };
1195
1196                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1197                         bias-disable;
1198                         drive-strength = <12>;
1199                 };
1200
1201                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1202                         bias-pull-up;
1203                         drive-strength = <8>;
1204                 };
1205
1206                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1207                         bias-pull-down;
1208                         drive-strength = <4>;
1209                 };
1210
1211                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1212                         bias-pull-up;
1213                         drive-strength = <2>;
1214                 };
1215
1216                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1217                         bias-pull-down;
1218                         drive-strength = <12>;
1219                 };
1220
1221                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1222                         bias-disable;
1223                         drive-strength = <13>;
1224                 };
1225
1226                 emmc {
1227                         emmc_pwr: emmc-pwr {
1228                                 rockchip,pins =
1229                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1230                         };
1231                 };
1232
1233                 gmac {
1234                         rgmii_pins: rgmii-pins {
1235                                 rockchip,pins =
1236                                         /* mac_txclk */
1237                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1238                                         /* mac_rxclk */
1239                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1240                                         /* mac_mdio */
1241                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1242                                         /* mac_txen */
1243                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1244                                         /* mac_clk */
1245                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1246                                         /* mac_rxdv */
1247                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1248                                         /* mac_mdc */
1249                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1250                                         /* mac_rxd1 */
1251                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1252                                         /* mac_rxd0 */
1253                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1254                                         /* mac_txd1 */
1255                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1256                                         /* mac_txd0 */
1257                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1258                                         /* mac_rxd3 */
1259                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1260                                         /* mac_rxd2 */
1261                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1262                                         /* mac_txd3 */
1263                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1264                                         /* mac_txd2 */
1265                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1266                         };
1267
1268                         rmii_pins: rmii-pins {
1269                                 rockchip,pins =
1270                                         /* mac_mdio */
1271                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1272                                         /* mac_txen */
1273                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1274                                         /* mac_clk */
1275                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1276                                         /* mac_rxer */
1277                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1278                                         /* mac_rxdv */
1279                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1280                                         /* mac_mdc */
1281                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1282                                         /* mac_rxd1 */
1283                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1284                                         /* mac_rxd0 */
1285                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1286                                         /* mac_txd1 */
1287                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1288                                         /* mac_txd0 */
1289                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1290                         };
1291                 };
1292
1293                 i2c0 {
1294                         i2c0_xfer: i2c0-xfer {
1295                                 rockchip,pins =
1296                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1297                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1298                         };
1299                 };
1300
1301                 i2c1 {
1302                         i2c1_xfer: i2c1-xfer {
1303                                 rockchip,pins =
1304                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1305                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1306                         };
1307                 };
1308
1309                 i2c2 {
1310                         i2c2_xfer: i2c2-xfer {
1311                                 rockchip,pins =
1312                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1313                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1314                         };
1315                 };
1316
1317                 i2c3 {
1318                         i2c3_xfer: i2c3-xfer {
1319                                 rockchip,pins =
1320                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1321                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1322                         };
1323                 };
1324
1325                 i2c4 {
1326                         i2c4_xfer: i2c4-xfer {
1327                                 rockchip,pins =
1328                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1329                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1330                         };
1331                 };
1332
1333                 i2c5 {
1334                         i2c5_xfer: i2c5-xfer {
1335                                 rockchip,pins =
1336                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1337                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1338                         };
1339                 };
1340
1341                 i2c6 {
1342                         i2c6_xfer: i2c6-xfer {
1343                                 rockchip,pins =
1344                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1345                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1346                         };
1347                 };
1348
1349                 i2c7 {
1350                         i2c7_xfer: i2c7-xfer {
1351                                 rockchip,pins =
1352                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1353                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1354                         };
1355                 };
1356
1357                 i2c8 {
1358                         i2c8_xfer: i2c8-xfer {
1359                                 rockchip,pins =
1360                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1361                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1362                         };
1363                 };
1364
1365                 i2s0 {
1366                         i2s0_8ch_bus: i2s0-8ch-bus {
1367                                 rockchip,pins =
1368                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1369                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1370                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1371                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1372                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1373                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1374                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1375                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1376                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1377                         };
1378                 };
1379
1380                 i2s1 {
1381                         i2s1_2ch_bus: i2s1-2ch-bus {
1382                                 rockchip,pins =
1383                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1384                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1385                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1386                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1387                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1388                         };
1389                 };
1390
1391                 sdio0 {
1392                         sdio0_bus1: sdio0-bus1 {
1393                                 rockchip,pins =
1394                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1395                         };
1396
1397                         sdio0_bus4: sdio0-bus4 {
1398                                 rockchip,pins =
1399                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1400                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1401                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1402                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1403                         };
1404
1405                         sdio0_cmd: sdio0-cmd {
1406                                 rockchip,pins =
1407                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1408                         };
1409
1410                         sdio0_clk: sdio0-clk {
1411                                 rockchip,pins =
1412                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1413                         };
1414
1415                         sdio0_cd: sdio0-cd {
1416                                 rockchip,pins =
1417                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1418                         };
1419
1420                         sdio0_pwr: sdio0-pwr {
1421                                 rockchip,pins =
1422                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1423                         };
1424
1425                         sdio0_bkpwr: sdio0-bkpwr {
1426                                 rockchip,pins =
1427                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1428                         };
1429
1430                         sdio0_wp: sdio0-wp {
1431                                 rockchip,pins =
1432                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1433                         };
1434
1435                         sdio0_int: sdio0-int {
1436                                 rockchip,pins =
1437                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1438                         };
1439                 };
1440
1441                 sdmmc {
1442                         sdmmc_bus1: sdmmc-bus1 {
1443                                 rockchip,pins =
1444                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1445                         };
1446
1447                         sdmmc_bus4: sdmmc-bus4 {
1448                                 rockchip,pins =
1449                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1450                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1451                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1452                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1453                         };
1454
1455                         sdmmc_clk: sdmmc-clk {
1456                                 rockchip,pins =
1457                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1458                         };
1459
1460                         sdmmc_cmd: sdmmc-cmd {
1461                                 rockchip,pins =
1462                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1463                         };
1464
1465                         sdmmc_cd: sdmcc-cd {
1466                                 rockchip,pins =
1467                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1468                         };
1469
1470                         sdmmc_wp: sdmmc-wp {
1471                                 rockchip,pins =
1472                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1473                         };
1474                 };
1475
1476                 spdif {
1477                         spdif_bus: spdif-bus {
1478                                 rockchip,pins =
1479                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1480                         };
1481                 };
1482
1483                 spi0 {
1484                         spi0_clk: spi0-clk {
1485                                 rockchip,pins =
1486                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1487                         };
1488                         spi0_cs0: spi0-cs0 {
1489                                 rockchip,pins =
1490                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1491                         };
1492                         spi0_cs1: spi0-cs1 {
1493                                 rockchip,pins =
1494                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1495                         };
1496                         spi0_tx: spi0-tx {
1497                                 rockchip,pins =
1498                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1499                         };
1500                         spi0_rx: spi0-rx {
1501                                 rockchip,pins =
1502                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1503                         };
1504                 };
1505
1506                 spi1 {
1507                         spi1_clk: spi1-clk {
1508                                 rockchip,pins =
1509                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1510                         };
1511                         spi1_cs0: spi1-cs0 {
1512                                 rockchip,pins =
1513                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1514                         };
1515                         spi1_rx: spi1-rx {
1516                                 rockchip,pins =
1517                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1518                         };
1519                         spi1_tx: spi1-tx {
1520                                 rockchip,pins =
1521                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1522                         };
1523                 };
1524
1525                 spi2 {
1526                         spi2_clk: spi2-clk {
1527                                 rockchip,pins =
1528                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1529                         };
1530                         spi2_cs0: spi2-cs0 {
1531                                 rockchip,pins =
1532                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1533                         };
1534                         spi2_rx: spi2-rx {
1535                                 rockchip,pins =
1536                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1537                         };
1538                         spi2_tx: spi2-tx {
1539                                 rockchip,pins =
1540                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1541                         };
1542                 };
1543
1544                 spi3 {
1545                         spi3_clk: spi3-clk {
1546                                 rockchip,pins =
1547                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1548                         };
1549                         spi3_cs0: spi3-cs0 {
1550                                 rockchip,pins =
1551                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1552                         };
1553                         spi3_rx: spi3-rx {
1554                                 rockchip,pins =
1555                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1556                         };
1557                         spi3_tx: spi3-tx {
1558                                 rockchip,pins =
1559                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1560                         };
1561                 };
1562
1563                 spi4 {
1564                         spi4_clk: spi4-clk {
1565                                 rockchip,pins =
1566                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1567                         };
1568                         spi4_cs0: spi4-cs0 {
1569                                 rockchip,pins =
1570                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1571                         };
1572                         spi4_rx: spi4-rx {
1573                                 rockchip,pins =
1574                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1575                         };
1576                         spi4_tx: spi4-tx {
1577                                 rockchip,pins =
1578                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1579                         };
1580                 };
1581
1582                 spi5 {
1583                         spi5_clk: spi5-clk {
1584                                 rockchip,pins =
1585                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1586                         };
1587                         spi5_cs0: spi5-cs0 {
1588                                 rockchip,pins =
1589                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1590                         };
1591                         spi5_rx: spi5-rx {
1592                                 rockchip,pins =
1593                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1594                         };
1595                         spi5_tx: spi5-tx {
1596                                 rockchip,pins =
1597                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1598                         };
1599                 };
1600
1601                 tsadc {
1602                         otp_gpio: otp-gpio {
1603                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1604                         };
1605
1606                         otp_out: otp-out {
1607                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1608                         };
1609                 };
1610
1611                 uart0 {
1612                         uart0_xfer: uart0-xfer {
1613                                 rockchip,pins =
1614                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1615                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1616                         };
1617
1618                         uart0_cts: uart0-cts {
1619                                 rockchip,pins =
1620                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1621                         };
1622
1623                         uart0_rts: uart0-rts {
1624                                 rockchip,pins =
1625                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1626                         };
1627                 };
1628
1629                 uart1 {
1630                         uart1_xfer: uart1-xfer {
1631                                 rockchip,pins =
1632                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1633                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1634                         };
1635                 };
1636
1637                 uart2a {
1638                         uart2a_xfer: uart2a-xfer {
1639                                 rockchip,pins =
1640                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1641                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1642                         };
1643                 };
1644
1645                 uart2b {
1646                         uart2b_xfer: uart2b-xfer {
1647                                 rockchip,pins =
1648                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1649                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1650                         };
1651                 };
1652
1653                 uart2c {
1654                         uart2c_xfer: uart2c-xfer {
1655                                 rockchip,pins =
1656                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1657                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1658                         };
1659                 };
1660
1661                 uart3 {
1662                         uart3_xfer: uart3-xfer {
1663                                 rockchip,pins =
1664                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1665                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1666                         };
1667
1668                         uart3_cts: uart3-cts {
1669                                 rockchip,pins =
1670                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1671                         };
1672
1673                         uart3_rts: uart3-rts {
1674                                 rockchip,pins =
1675                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1676                         };
1677                 };
1678
1679                 uart4 {
1680                         uart4_xfer: uart4-xfer {
1681                                 rockchip,pins =
1682                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1683                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1684                         };
1685                 };
1686
1687                 uarthdcp {
1688                         uarthdcp_xfer: uarthdcp-xfer {
1689                                 rockchip,pins =
1690                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1691                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1692                         };
1693                 };
1694
1695                 pwm0 {
1696                         pwm0_pin: pwm0-pin {
1697                                 rockchip,pins =
1698                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1699                         };
1700
1701                         vop0_pwm_pin: vop0-pwm-pin {
1702                                 rockchip,pins =
1703                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1704                         };
1705                 };
1706
1707                 pwm1 {
1708                         pwm1_pin: pwm1-pin {
1709                                 rockchip,pins =
1710                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1711                         };
1712
1713                         vop1_pwm_pin: vop1-pwm-pin {
1714                                 rockchip,pins =
1715                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1716                         };
1717                 };
1718
1719                 pwm2 {
1720                         pwm2_pin: pwm2-pin {
1721                                 rockchip,pins =
1722                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1723                         };
1724                 };
1725
1726                 pwm3a {
1727                         pwm3a_pin: pwm3a-pin {
1728                                 rockchip,pins =
1729                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1730                         };
1731                 };
1732
1733                 pwm3b {
1734                         pwm3b_pin: pwm3b-pin {
1735                                 rockchip,pins =
1736                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1737                         };
1738                 };
1739
1740                 pmic {
1741                         pmic_int_l: pmic-int-l {
1742                                 rockchip,pins =
1743                                         <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
1744                         };
1745                 };
1746         };
1747 };