arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 #include "rk3399-dram-default-timing.dtsi"
  53
  54 / {
  55         compatible = "rockchip,rk3399";
  56
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 i2c6 = &i2c6;
  69                 i2c7 = &i2c7;
  70                 i2c8 = &i2c8;
  71                 serial0 = &uart0;
  72                 serial1 = &uart1;
  73                 serial2 = &uart2;
  74                 serial3 = &uart3;
  75                 serial4 = &uart4;
  76         };
  77
  78         psci {
  79                 compatible = "arm,psci-1.0";
  80                 method = "smc";
  81         };
  82
  83         cpus {
  84                 #address-cells = <2>;
  85                 #size-cells = <0>;
  86
  87                 cpu-map {
  88                         cluster0 {
  89                                 core0 {
  90                                         cpu = <&cpu_l0>;
  91                                 };
  92                                 core1 {
  93                                         cpu = <&cpu_l1>;
  94                                 };
  95                                 core2 {
  96                                         cpu = <&cpu_l2>;
  97                                 };
  98                                 core3 {
  99                                         cpu = <&cpu_l3>;
 100                                 };
 101                         };
 102
 103                         cluster1 {
 104                                 core0 {
 105                                         cpu = <&cpu_b0>;
 106                                 };
 107                                 core1 {
 108                                         cpu = <&cpu_b1>;
 109                                 };
 110                         };
 111                 };
 112
 113                 cpu_l0: cpu@0 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53", "arm,armv8";
 116                         reg = <0x0 0x0>;
 117                         enable-method = "psci";
 118                         #cooling-cells = <2>; /* min followed by max */
 119                         dynamic-power-coefficient = <100>;
 120                         clocks = <&cru ARMCLKL>;
 121                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 131                 };
 132
 133                 cpu_l2: cpu@2 {
 134                         device_type = "cpu";
 135                         compatible = "arm,cortex-a53", "arm,armv8";
 136                         reg = <0x0 0x2>;
 137                         enable-method = "psci";
 138                         clocks = <&cru ARMCLKL>;
 139                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 140                 };
 141
 142                 cpu_l3: cpu@3 {
 143                         device_type = "cpu";
 144                         compatible = "arm,cortex-a53", "arm,armv8";
 145                         reg = <0x0 0x3>;
 146                         enable-method = "psci";
 147                         clocks = <&cru ARMCLKL>;
 148                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 149                 };
 150
 151                 cpu_b0: cpu@100 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a72", "arm,armv8";
 154                         reg = <0x0 0x100>;
 155                         enable-method = "psci";
 156                         #cooling-cells = <2>; /* min followed by max */
 157                         dynamic-power-coefficient = <436>;
 158                         clocks = <&cru ARMCLKB>;
 159                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 160                 };
 161
 162                 cpu_b1: cpu@101 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-a72", "arm,armv8";
 165                         reg = <0x0 0x101>;
 166                         enable-method = "psci";
 167                         clocks = <&cru ARMCLKB>;
 168                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 169                 };
 170
 171                 idle-states {
 172                         entry-method = "psci";
 173
 174                         CPU_SLEEP: cpu-sleep {
 175                                 compatible = "arm,idle-state";
 176                                 local-timer-stop;
 177                                 arm,psci-suspend-param = <0x0010000>;
 178                                 entry-latency-us = <120>;
 179                                 exit-latency-us = <250>;
 180                                 min-residency-us = <900>;
 181                         };
 182
 183                         CLUSTER_SLEEP: cluster-sleep {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x1010000>;
 187                                 entry-latency-us = <400>;
 188                                 exit-latency-us = <500>;
 189                                 min-residency-us = <2000>;
 190                         };
 191                 };
 192         };
 193
 194         cpu_avs: cpu-avs {
 195                 cluster0-avs {
 196                         cluster-id = <0>;
 197                         min-volt = <800000>; /* uV */
 198                         min-freq = <408000>; /* KHz */
 199                         leakage-adjust-volt = <
 200                         /*  mA        mA         uV */
 201                             0         254        0
 202                         >;
 203                         nvmem-cells = <&cpul_leakage>;
 204                         nvmem-cell-names = "cpu_leakage";
 205                 };
 206                 cluster1-avs {
 207                         cluster-id = <1>;
 208                         min-volt = <800000>; /* uV */
 209                         min-freq = <408000>; /* KHz */
 210                         leakage-adjust-volt = <
 211                         /*  mA        mA         uV */
 212                             0         254        0
 213                         >;
 214                         nvmem-cells = <&cpub_leakage>;
 215                         nvmem-cell-names = "cpu_leakage";
 216                 };
 217         };
 218
 219         timer {
 220                 compatible = "arm,armv8-timer";
 221                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 222                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 223                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 224                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 225         };
 226
 227         pmu_a53 {
 228                 compatible = "arm,cortex-a53-pmu";
 229                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 230         };
 231
 232         pmu_a72 {
 233                 compatible = "arm,cortex-a72-pmu";
 234                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 235         };
 236
 237         xin24m: xin24m {
 238                 compatible = "fixed-clock";
 239                 #clock-cells = <0>;
 240                 clock-frequency = <24000000>;
 241                 clock-output-names = "xin24m";
 242         };
 243
 244         amba {
 245                 compatible = "arm,amba-bus";
 246                 #address-cells = <2>;
 247                 #size-cells = <2>;
 248                 ranges;
 249
 250                 dmac_bus: dma-controller@ff6d0000 {
 251                         compatible = "arm,pl330", "arm,primecell";
 252                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 253                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 254                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 255                         #dma-cells = <1>;
 256                         clocks = <&cru ACLK_DMAC0_PERILP>;
 257                         clock-names = "apb_pclk";
 258                         peripherals-req-type-burst;
 259                 };
 260
 261                 dmac_peri: dma-controller@ff6e0000 {
 262                         compatible = "arm,pl330", "arm,primecell";
 263                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 264                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 265                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 266                         #dma-cells = <1>;
 267                         clocks = <&cru ACLK_DMAC1_PERILP>;
 268                         clock-names = "apb_pclk";
 269                         peripherals-req-type-burst;
 270                 };
 271         };
 272
 273         gmac: eth@fe300000 {
 274                 compatible = "rockchip,rk3399-gmac";
 275                 reg = <0x0 0xfe300000 0x0 0x10000>;
 276                 rockchip,grf = <&grf>;
 277                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 278                 interrupt-names = "macirq";
 279                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 280                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 281                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 282                          <&cru PCLK_GMAC>;
 283                 clock-names = "stmmaceth", "mac_clk_rx",
 284                               "mac_clk_tx", "clk_mac_ref",
 285                               "clk_mac_refout", "aclk_mac",
 286                               "pclk_mac";
 287                 resets = <&cru SRST_A_GMAC>;
 288                 reset-names = "stmmaceth";
 289                 power-domains = <&power RK3399_PD_GMAC>;
 290                 status = "disabled";
 291         };
 292
 293         sdio0: dwmmc@fe310000 {
 294                 compatible = "rockchip,rk3399-dw-mshc",
 295                              "rockchip,rk3288-dw-mshc";
 296                 reg = <0x0 0xfe310000 0x0 0x4000>;
 297                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 298                 clock-freq-min-max = <400000 150000000>;
 299                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 300                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 301                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 302                 fifo-depth = <0x100>;
 303                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 304                 status = "disabled";
 305         };
 306
 307         sdmmc: dwmmc@fe320000 {
 308                 compatible = "rockchip,rk3399-dw-mshc",
 309                              "rockchip,rk3288-dw-mshc";
 310                 reg = <0x0 0xfe320000 0x0 0x4000>;
 311                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 312                 clock-freq-min-max = <400000 150000000>;
 313                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 314                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 315                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 316                 fifo-depth = <0x100>;
 317                 power-domains = <&power RK3399_PD_SD>;
 318                 status = "disabled";
 319         };
 320
 321         sdhci: sdhci@fe330000 {
 322                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 323                 reg = <0x0 0xfe330000 0x0 0x10000>;
 324                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 325                 arasan,soc-ctl-syscon = <&grf>;
 326                 assigned-clocks = <&cru SCLK_EMMC>;
 327                 assigned-clock-rates = <200000000>;
 328                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 329                 clock-names = "clk_xin", "clk_ahb";
 330                 clock-output-names = "emmc_cardclock";
 331                 #clock-cells = <0>;
 332                 phys = <&emmc_phy>;
 333                 phy-names = "phy_arasan";
 334                 power-domains = <&power RK3399_PD_EMMC>;
 335                 status = "disabled";
 336         };
 337
 338         usb_host0_ehci: usb@fe380000 {
 339                 compatible = "generic-ehci";
 340                 reg = <0x0 0xfe380000 0x0 0x20000>;
 341                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 342                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 343                          <&cru SCLK_USBPHY0_480M_SRC>;
 344                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 345                 phys = <&u2phy0_host>;
 346                 phy-names = "usb";
 347                 power-domains = <&power RK3399_PD_PERIHP>;
 348                 status = "disabled";
 349         };
 350
 351         usb_host0_ohci: usb@fe3a0000 {
 352                 compatible = "generic-ohci";
 353                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 354                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 355                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 356                          <&cru SCLK_USBPHY0_480M_SRC>;
 357                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 358                 phys = <&u2phy0_host>;
 359                 phy-names = "usb";
 360                 power-domains = <&power RK3399_PD_PERIHP>;
 361                 status = "disabled";
 362         };
 363
 364         usb_host1_ehci: usb@fe3c0000 {
 365                 compatible = "generic-ehci";
 366                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 367                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 368                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 369                          <&cru SCLK_USBPHY1_480M_SRC>;
 370                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 371                 phys = <&u2phy1_host>;
 372                 phy-names = "usb";
 373                 power-domains = <&power RK3399_PD_PERIHP>;
 374                 status = "disabled";
 375         };
 376
 377         usb_host1_ohci: usb@fe3e0000 {
 378                 compatible = "generic-ohci";
 379                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 380                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 381                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 382                          <&cru SCLK_USBPHY1_480M_SRC>;
 383                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 384                 phys = <&u2phy1_host>;
 385                 phy-names = "usb";
 386                 power-domains = <&power RK3399_PD_PERIHP>;
 387                 status = "disabled";
 388         };
 389
 390         usbdrd3_0: usb@fe800000 {
 391                 compatible = "rockchip,rk3399-dwc3";
 392                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 393                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 394                 clock-names = "ref_clk", "suspend_clk",
 395                               "bus_clk", "grf_clk";
 396                 power-domains = <&power RK3399_PD_USB3>;
 397                 resets = <&cru SRST_A_USB3_OTG0>;
 398                 reset-names = "usb3-otg";
 399                 #address-cells = <2>;
 400                 #size-cells = <2>;
 401                 ranges;
 402                 status = "disabled";
 403                 usbdrd_dwc3_0: dwc3@fe800000 {
 404                         compatible = "snps,dwc3";
 405                         reg = <0x0 0xfe800000 0x0 0x100000>;
 406                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 407                         dr_mode = "otg";
 408                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 409                         phy-names = "usb2-phy", "usb3-phy";
 410                         phy_type = "utmi_wide";
 411                         snps,dis_enblslpm_quirk;
 412                         snps,dis-u2-freeclk-exists-quirk;
 413                         snps,dis_u2_susphy_quirk;
 414                         snps,dis-del-phy-power-chg-quirk;
 415                         snps,xhci-slow-suspend-quirk;
 416                         status = "disabled";
 417                 };
 418         };
 419
 420         usbdrd3_1: usb@fe900000 {
 421                 compatible = "rockchip,rk3399-dwc3";
 422                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 423                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 424                 clock-names = "ref_clk", "suspend_clk",
 425                               "bus_clk", "grf_clk";
 426                 power-domains = <&power RK3399_PD_USB3>;
 427                 resets = <&cru SRST_A_USB3_OTG1>;
 428                 reset-names = "usb3-otg";
 429                 #address-cells = <2>;
 430                 #size-cells = <2>;
 431                 ranges;
 432                 status = "disabled";
 433                 usbdrd_dwc3_1: dwc3@fe900000 {
 434                         compatible = "snps,dwc3";
 435                         reg = <0x0 0xfe900000 0x0 0x100000>;
 436                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 437                         dr_mode = "host";
 438                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 439                         phy-names = "usb2-phy", "usb3-phy";
 440                         phy_type = "utmi_wide";
 441                         snps,dis_enblslpm_quirk;
 442                         snps,dis-u2-freeclk-exists-quirk;
 443                         snps,dis_u2_susphy_quirk;
 444                         snps,dis-del-phy-power-chg-quirk;
 445                         snps,xhci-slow-suspend-quirk;
 446                         status = "disabled";
 447                 };
 448         };
 449
 450         gic: interrupt-controller@fee00000 {
 451                 compatible = "arm,gic-v3";
 452                 #interrupt-cells = <4>;
 453                 #address-cells = <2>;
 454                 #size-cells = <2>;
 455                 ranges;
 456                 interrupt-controller;
 457
 458                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 459                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 460                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 461                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 462                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 463                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 464                 its: interrupt-controller@fee20000 {
 465                         compatible = "arm,gic-v3-its";
 466                         msi-controller;
 467                         reg = <0x0 0xfee20000 0x0 0x20000>;
 468                 };
 469
 470                 ppi-partitions {
 471                         part0: interrupt-partition-0 {
 472                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 473                         };
 474
 475                         part1: interrupt-partition-1 {
 476                                 affinity = <&cpu_b0 &cpu_b1>;
 477                         };
 478                 };
 479         };
 480
 481         saradc: saradc@ff100000 {
 482                 compatible = "rockchip,rk3399-saradc";
 483                 reg = <0x0 0xff100000 0x0 0x100>;
 484                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 485                 #io-channel-cells = <1>;
 486                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 487                 clock-names = "saradc", "apb_pclk";
 488                 resets = <&cru SRST_P_SARADC>;
 489                 reset-names = "saradc-apb";
 490                 status = "disabled";
 491         };
 492
 493         i2c0: i2c@ff3c0000 {
 494                 compatible = "rockchip,rk3399-i2c";
 495                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 496                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 497                 clock-names = "i2c", "pclk";
 498                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&i2c0_xfer>;
 501                 #address-cells = <1>;
 502                 #size-cells = <0>;
 503                 status = "disabled";
 504         };
 505
 506         i2c1: i2c@ff110000 {
 507                 compatible = "rockchip,rk3399-i2c";
 508                 reg = <0x0 0xff110000 0x0 0x1000>;
 509                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 510                 clock-names = "i2c", "pclk";
 511                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&i2c1_xfer>;
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 status = "disabled";
 517         };
 518
 519         i2c2: i2c@ff120000 {
 520                 compatible = "rockchip,rk3399-i2c";
 521                 reg = <0x0 0xff120000 0x0 0x1000>;
 522                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 523                 clock-names = "i2c", "pclk";
 524                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 525                 pinctrl-names = "default";
 526                 pinctrl-0 = <&i2c2_xfer>;
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 status = "disabled";
 530         };
 531
 532         i2c3: i2c@ff130000 {
 533                 compatible = "rockchip,rk3399-i2c";
 534                 reg = <0x0 0xff130000 0x0 0x1000>;
 535                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 536                 clock-names = "i2c", "pclk";
 537                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&i2c3_xfer>;
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 status = "disabled";
 543         };
 544
 545         i2c5: i2c@ff140000 {
 546                 compatible = "rockchip,rk3399-i2c";
 547                 reg = <0x0 0xff140000 0x0 0x1000>;
 548                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 549                 clock-names = "i2c", "pclk";
 550                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&i2c5_xfer>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 status = "disabled";
 556         };
 557
 558         i2c6: i2c@ff150000 {
 559                 compatible = "rockchip,rk3399-i2c";
 560                 reg = <0x0 0xff150000 0x0 0x1000>;
 561                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 562                 clock-names = "i2c", "pclk";
 563                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&i2c6_xfer>;
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 status = "disabled";
 569         };
 570
 571         i2c7: i2c@ff160000 {
 572                 compatible = "rockchip,rk3399-i2c";
 573                 reg = <0x0 0xff160000 0x0 0x1000>;
 574                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 575                 clock-names = "i2c", "pclk";
 576                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 577                 pinctrl-names = "default";
 578                 pinctrl-0 = <&i2c7_xfer>;
 579                 #address-cells = <1>;
 580                 #size-cells = <0>;
 581                 status = "disabled";
 582         };
 583
 584         uart0: serial@ff180000 {
 585                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 586                 reg = <0x0 0xff180000 0x0 0x100>;
 587                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 588                 clock-names = "baudclk", "apb_pclk";
 589                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 590                 reg-shift = <2>;
 591                 reg-io-width = <4>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 594                 status = "disabled";
 595         };
 596
 597         uart1: serial@ff190000 {
 598                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 599                 reg = <0x0 0xff190000 0x0 0x100>;
 600                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 601                 clock-names = "baudclk", "apb_pclk";
 602                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 603                 reg-shift = <2>;
 604                 reg-io-width = <4>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&uart1_xfer>;
 607                 status = "disabled";
 608         };
 609
 610         uart2: serial@ff1a0000 {
 611                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 612                 reg = <0x0 0xff1a0000 0x0 0x100>;
 613                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 614                 clock-names = "baudclk", "apb_pclk";
 615                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 616                 reg-shift = <2>;
 617                 reg-io-width = <4>;
 618                 pinctrl-names = "default";
 619                 pinctrl-0 = <&uart2c_xfer>;
 620                 status = "disabled";
 621         };
 622
 623         uart3: serial@ff1b0000 {
 624                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 625                 reg = <0x0 0xff1b0000 0x0 0x100>;
 626                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 627                 clock-names = "baudclk", "apb_pclk";
 628                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 629                 reg-shift = <2>;
 630                 reg-io-width = <4>;
 631                 pinctrl-names = "default";
 632                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 633                 status = "disabled";
 634         };
 635
 636         spi0: spi@ff1c0000 {
 637                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 638                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 639                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 640                 clock-names = "spiclk", "apb_pclk";
 641                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 642                 pinctrl-names = "default";
 643                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 644                 #address-cells = <1>;
 645                 #size-cells = <0>;
 646                 status = "disabled";
 647         };
 648
 649         spi1: spi@ff1d0000 {
 650                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 651                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 652                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 653                 clock-names = "spiclk", "apb_pclk";
 654                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 655                 pinctrl-names = "default";
 656                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 657                 #address-cells = <1>;
 658                 #size-cells = <0>;
 659                 status = "disabled";
 660         };
 661
 662         spi2: spi@ff1e0000 {
 663                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 664                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 665                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 666                 clock-names = "spiclk", "apb_pclk";
 667                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 668                 pinctrl-names = "default";
 669                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 670                 #address-cells = <1>;
 671                 #size-cells = <0>;
 672                 status = "disabled";
 673         };
 674
 675         spi4: spi@ff1f0000 {
 676                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 677                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 678                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 679                 clock-names = "spiclk", "apb_pclk";
 680                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 681                 pinctrl-names = "default";
 682                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 683                 #address-cells = <1>;
 684                 #size-cells = <0>;
 685                 status = "disabled";
 686         };
 687
 688         spi5: spi@ff200000 {
 689                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 690                 reg = <0x0 0xff200000 0x0 0x1000>;
 691                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 692                 clock-names = "spiclk", "apb_pclk";
 693                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 694                 pinctrl-names = "default";
 695                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 696                 #address-cells = <1>;
 697                 #size-cells = <0>;
 698                 status = "disabled";
 699         };
 700
 701         thermal-zones {
 702                 soc_thermal: soc-thermal {
 703                         polling-delay-passive = <20>; /* milliseconds */
 704                         polling-delay = <1000>; /* milliseconds */
 705                         sustainable-power = <1000>; /* milliwatts */
 706
 707                         thermal-sensors = <&tsadc 0>;
 708
 709                         trips {
 710                                 threshold: trip-point@0 {
 711                                         temperature = <70000>; /* millicelsius */
 712                                         hysteresis = <2000>; /* millicelsius */
 713                                         type = "passive";
 714                                 };
 715                                 target: trip-point@1 {
 716                                         temperature = <85000>; /* millicelsius */
 717                                         hysteresis = <2000>; /* millicelsius */
 718                                         type = "passive";
 719                                 };
 720                                 soc_crit: soc-crit {
 721                                         temperature = <95000>; /* millicelsius */
 722                                         hysteresis = <2000>; /* millicelsius */
 723                                         type = "critical";
 724                                 };
 725                         };
 726
 727                         cooling-maps {
 728                                 map0 {
 729                                         trip = <&target>;
 730                                         cooling-device =
 731                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 732                                         contribution = <4096>;
 733                                 };
 734                                 map1 {
 735                                         trip = <&target>;
 736                                         cooling-device =
 737                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 738                                         contribution = <1024>;
 739                                 };
 740                                 map2 {
 741                                         trip = <&target>;
 742                                         cooling-device =
 743                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 744                                         contribution = <4096>;
 745                                 };
 746                         };
 747                 };
 748
 749                 gpu_thermal: gpu-thermal {
 750                         polling-delay-passive = <100>; /* milliseconds */
 751                         polling-delay = <1000>; /* milliseconds */
 752
 753                         thermal-sensors = <&tsadc 1>;
 754                 };
 755         };
 756
 757         tsadc: tsadc@ff260000 {
 758                 compatible = "rockchip,rk3399-tsadc";
 759                 reg = <0x0 0xff260000 0x0 0x100>;
 760                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 761                 rockchip,grf = <&grf>;
 762                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 763                 clock-names = "tsadc", "apb_pclk";
 764                 assigned-clocks = <&cru SCLK_TSADC>;
 765                 assigned-clock-rates = <750000>;
 766                 resets = <&cru SRST_TSADC>;
 767                 reset-names = "tsadc-apb";
 768                 pinctrl-names = "init", "default", "sleep";
 769                 pinctrl-0 = <&otp_gpio>;
 770                 pinctrl-1 = <&otp_out>;
 771                 pinctrl-2 = <&otp_gpio>;
 772                 #thermal-sensor-cells = <1>;
 773                 rockchip,hw-tshut-temp = <95000>;
 774                 status = "disabled";
 775         };
 776
 777         qos_emmc: qos@ffa58000 {
 778                 compatible = "syscon";
 779                 reg = <0x0 0xffa58000 0x0 0x20>;
 780         };
 781
 782         qos_gmac: qos@ffa5c000 {
 783                 compatible = "syscon";
 784                 reg = <0x0 0xffa5c000 0x0 0x20>;
 785         };
 786
 787         qos_pcie: qos@ffa60080 {
 788                 compatible = "syscon";
 789                 reg = <0x0 0xffa60080 0x0 0x20>;
 790         };
 791
 792         qos_usb_host0: qos@ffa60100 {
 793                 compatible = "syscon";
 794                 reg = <0x0 0xffa60100 0x0 0x20>;
 795         };
 796
 797         qos_usb_host1: qos@ffa60180 {
 798                 compatible = "syscon";
 799                 reg = <0x0 0xffa60180 0x0 0x20>;
 800         };
 801
 802         qos_usb_otg0: qos@ffa70000 {
 803                 compatible = "syscon";
 804                 reg = <0x0 0xffa70000 0x0 0x20>;
 805         };
 806
 807         qos_usb_otg1: qos@ffa70080 {
 808                 compatible = "syscon";
 809                 reg = <0x0 0xffa70080 0x0 0x20>;
 810         };
 811
 812         qos_sd: qos@ffa74000 {
 813                 compatible = "syscon";
 814                 reg = <0x0 0xffa74000 0x0 0x20>;
 815         };
 816
 817         qos_sdioaudio: qos@ffa76000 {
 818                 compatible = "syscon";
 819                 reg = <0x0 0xffa76000 0x0 0x20>;
 820         };
 821
 822         qos_hdcp: qos@ffa90000 {
 823                 compatible = "syscon";
 824                 reg = <0x0 0xffa90000 0x0 0x20>;
 825         };
 826
 827         qos_iep: qos@ffa98000 {
 828                 compatible = "syscon";
 829                 reg = <0x0 0xffa98000 0x0 0x20>;
 830         };
 831
 832         qos_isp0_m0: qos@ffaa0000 {
 833                 compatible = "syscon";
 834                 reg = <0x0 0xffaa0000 0x0 0x20>;
 835         };
 836
 837         qos_isp0_m1: qos@ffaa0080 {
 838                 compatible = "syscon";
 839                 reg = <0x0 0xffaa0080 0x0 0x20>;
 840         };
 841
 842         qos_isp1_m0: qos@ffaa8000 {
 843                 compatible = "syscon";
 844                 reg = <0x0 0xffaa8000 0x0 0x20>;
 845         };
 846
 847         qos_isp1_m1: qos@ffaa8080 {
 848                 compatible = "syscon";
 849                 reg = <0x0 0xffaa8080 0x0 0x20>;
 850         };
 851
 852         qos_rga_r: qos@ffab0000 {
 853                 compatible = "syscon";
 854                 reg = <0x0 0xffab0000 0x0 0x20>;
 855         };
 856
 857         qos_rga_w: qos@ffab0080 {
 858                 compatible = "syscon";
 859                 reg = <0x0 0xffab0080 0x0 0x20>;
 860         };
 861
 862         qos_video_m0: qos@ffab8000 {
 863                 compatible = "syscon";
 864                 reg = <0x0 0xffab8000 0x0 0x20>;
 865         };
 866
 867         qos_video_m1_r: qos@ffac0000 {
 868                 compatible = "syscon";
 869                 reg = <0x0 0xffac0000 0x0 0x20>;
 870         };
 871
 872         qos_video_m1_w: qos@ffac0080 {
 873                 compatible = "syscon";
 874                 reg = <0x0 0xffac0080 0x0 0x20>;
 875         };
 876
 877         qos_vop_big_r: qos@ffac8000 {
 878                 compatible = "syscon";
 879                 reg = <0x0 0xffac8000 0x0 0x20>;
 880         };
 881
 882         qos_vop_big_w: qos@ffac8080 {
 883                 compatible = "syscon";
 884                 reg = <0x0 0xffac8080 0x0 0x20>;
 885         };
 886
 887         qos_vop_little: qos@ffad0000 {
 888                 compatible = "syscon";
 889                 reg = <0x0 0xffad0000 0x0 0x20>;
 890         };
 891
 892         qos_perihp: qos@ffad8080 {
 893                 compatible = "syscon";
 894                 reg = <0x0 0xffad8080 0x0 0x20>;
 895         };
 896
 897         qos_gpu: qos@ffae0000 {
 898                 compatible = "syscon";
 899                 reg = <0x0 0xffae0000 0x0 0x20>;
 900         };
 901
 902         pmu: power-management@ff310000 {
 903                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 904                 reg = <0x0 0xff310000 0x0 0x1000>;
 905
 906                 /*
 907                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 908                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 909                  * Some of the power domains are grouped together for every
 910                  * voltage domain.
 911                  * The detail contents as below.
 912                  */
 913                 power: power-controller {
 914                         compatible = "rockchip,rk3399-power-controller";
 915                         #power-domain-cells = <1>;
 916                         #address-cells = <1>;
 917                         #size-cells = <0>;
 918
 919                         /* These power domains are grouped by VD_CENTER */
 920                         pd_iep@RK3399_PD_IEP {
 921                                 reg = <RK3399_PD_IEP>;
 922                                 clocks = <&cru ACLK_IEP>,
 923                                          <&cru HCLK_IEP>;
 924                                 pm_qos = <&qos_iep>;
 925                         };
 926                         pd_rga@RK3399_PD_RGA {
 927                                 reg = <RK3399_PD_RGA>;
 928                                 clocks = <&cru ACLK_RGA>,
 929                                          <&cru HCLK_RGA>;
 930                                 pm_qos = <&qos_rga_r>,
 931                                          <&qos_rga_w>;
 932                         };
 933                         pd_vcodec@RK3399_PD_VCODEC {
 934                                 reg = <RK3399_PD_VCODEC>;
 935                                 clocks = <&cru ACLK_VCODEC>,
 936                                          <&cru HCLK_VCODEC>;
 937                                 pm_qos = <&qos_video_m0>;
 938                         };
 939                         pd_vdu@RK3399_PD_VDU {
 940                                 reg = <RK3399_PD_VDU>;
 941                                 clocks = <&cru ACLK_VDU>,
 942                                          <&cru HCLK_VDU>;
 943                                 pm_qos = <&qos_video_m1_r>,
 944                                          <&qos_video_m1_w>;
 945                         };
 946
 947                         /* These power domains are grouped by VD_GPU */
 948                         pd_gpu@RK3399_PD_GPU {
 949                                 reg = <RK3399_PD_GPU>;
 950                                 clocks = <&cru ACLK_GPU>;
 951                                 pm_qos = <&qos_gpu>;
 952                         };
 953
 954                         /* These power domains are grouped by VD_LOGIC */
 955                         pd_edp@RK3399_PD_EDP {
 956                                 reg = <RK3399_PD_EDP>;
 957                                 clocks = <&cru PCLK_EDP_CTRL>;
 958                         };
 959                         pd_emmc@RK3399_PD_EMMC {
 960                                 reg = <RK3399_PD_EMMC>;
 961                                 clocks = <&cru ACLK_EMMC>;
 962                                 pm_qos = <&qos_emmc>;
 963                         };
 964                         pd_gmac@RK3399_PD_GMAC {
 965                                 reg = <RK3399_PD_GMAC>;
 966                                 clocks = <&cru ACLK_GMAC>,
 967                                          <&cru PCLK_GMAC>;
 968                                 pm_qos = <&qos_gmac>;
 969                         };
 970                         pd_perihp@RK3399_PD_PERIHP {
 971                                 reg = <RK3399_PD_PERIHP>;
 972                                 #address-cells = <1>;
 973                                 #size-cells = <0>;
 974                                 clocks = <&cru ACLK_PERIHP>;
 975                                 pm_qos = <&qos_perihp>,
 976                                          <&qos_pcie>,
 977                                          <&qos_usb_host0>,
 978                                          <&qos_usb_host1>;
 979
 980                                 pd_sd@RK3399_PD_SD {
 981                                         reg = <RK3399_PD_SD>;
 982                                         clocks = <&cru HCLK_SDMMC>,
 983                                                  <&cru SCLK_SDMMC>;
 984                                         pm_qos = <&qos_sd>;
 985                                 };
 986                         };
 987                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
 988                                 reg = <RK3399_PD_SDIOAUDIO>;
 989                                 clocks = <&cru HCLK_SDIO>;
 990                                 pm_qos = <&qos_sdioaudio>;
 991                         };
 992                         pd_usb3@RK3399_PD_USB3 {
 993                                 reg = <RK3399_PD_USB3>;
 994                                 clocks = <&cru ACLK_USB3>;
 995                                 pm_qos = <&qos_usb_otg0>,
 996                                          <&qos_usb_otg1>;
 997                         };
 998                         pd_vio@RK3399_PD_VIO {
 999                                 reg = <RK3399_PD_VIO>;
1000                                 #address-cells = <1>;
1001                                 #size-cells = <0>;
1002
1003                                 pd_hdcp@RK3399_PD_HDCP {
1004                                         reg = <RK3399_PD_HDCP>;
1005                                         clocks = <&cru ACLK_HDCP>,
1006                                                  <&cru HCLK_HDCP>,
1007                                                  <&cru PCLK_HDCP>;
1008                                         pm_qos = <&qos_hdcp>;
1009                                 };
1010                                 pd_isp0@RK3399_PD_ISP0 {
1011                                         reg = <RK3399_PD_ISP0>;
1012                                         clocks = <&cru ACLK_ISP0>,
1013                                                  <&cru HCLK_ISP0>;
1014                                         pm_qos = <&qos_isp0_m0>,
1015                                                  <&qos_isp0_m1>;
1016                                 };
1017                                 pd_isp1@RK3399_PD_ISP1 {
1018                                         reg = <RK3399_PD_ISP1>;
1019                                         clocks = <&cru ACLK_ISP1>,
1020                                                  <&cru HCLK_ISP1>;
1021                                         pm_qos = <&qos_isp1_m0>,
1022                                                  <&qos_isp1_m1>;
1023                                 };
1024                                 pd_tcpc0@RK3399_PD_TCPC0 {
1025                                         reg = <RK3399_PD_TCPD0>;
1026                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1027                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1028                                 };
1029                                 pd_tcpc1@RK3399_PD_TCPC1 {
1030                                         reg = <RK3399_PD_TCPD1>;
1031                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1032                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1033                                 };
1034                                 pd_vo@RK3399_PD_VO {
1035                                         reg = <RK3399_PD_VO>;
1036                                         #address-cells = <1>;
1037                                         #size-cells = <0>;
1038
1039                                         pd_vopb@RK3399_PD_VOPB {
1040                                                 reg = <RK3399_PD_VOPB>;
1041                                                 clocks = <&cru ACLK_VOP0>,
1042                                                          <&cru HCLK_VOP0>;
1043                                                 pm_qos = <&qos_vop_big_r>,
1044                                                          <&qos_vop_big_w>;
1045                                         };
1046                                         pd_vopl@RK3399_PD_VOPL {
1047                                                 reg = <RK3399_PD_VOPL>;
1048                                                 clocks = <&cru ACLK_VOP1>,
1049                                                          <&cru HCLK_VOP1>;
1050                                                 pm_qos = <&qos_vop_little>;
1051                                         };
1052                                 };
1053                         };
1054                 };
1055         };
1056
1057         pmugrf: syscon@ff320000 {
1058                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1059                 reg = <0x0 0xff320000 0x0 0x1000>;
1060
1061                 pmu_io_domains: pmu-io-domains {
1062                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1063                         status = "disabled";
1064                 };
1065
1066                 reboot-mode {
1067                         compatible = "syscon-reboot-mode";
1068                         offset = <0x300>;
1069                         mode-bootloader = <BOOT_LOADER>;
1070                         mode-charge = <BOOT_CHARGING>;
1071                         mode-fastboot = <BOOT_FASTBOOT>;
1072                         mode-loader = <BOOT_LOADER>;
1073                         mode-normal = <BOOT_NORMAL>;
1074                         mode-recovery = <BOOT_RECOVERY>;
1075                         mode-ums = <BOOT_UMS>;
1076                 };
1077
1078                 pmu_pvtm: pmu-pvtm {
1079                         compatible = "rockchip,rk3399-pmu-pvtm";
1080                         clocks = <&pmucru SCLK_PVTM_PMU>;
1081                         clock-names = "pmu";
1082                         status = "disabled";
1083                 };
1084         };
1085
1086         spi3: spi@ff350000 {
1087                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1088                 reg = <0x0 0xff350000 0x0 0x1000>;
1089                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1090                 clock-names = "spiclk", "apb_pclk";
1091                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1092                 pinctrl-names = "default";
1093                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1094                 #address-cells = <1>;
1095                 #size-cells = <0>;
1096                 status = "disabled";
1097         };
1098
1099         uart4: serial@ff370000 {
1100                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1101                 reg = <0x0 0xff370000 0x0 0x100>;
1102                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1103                 clock-names = "baudclk", "apb_pclk";
1104                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1105                 reg-shift = <2>;
1106                 reg-io-width = <4>;
1107                 pinctrl-names = "default";
1108                 pinctrl-0 = <&uart4_xfer>;
1109                 status = "disabled";
1110         };
1111
1112         i2c4: i2c@ff3d0000 {
1113                 compatible = "rockchip,rk3399-i2c";
1114                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1115                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1116                 clock-names = "i2c", "pclk";
1117                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1118                 pinctrl-names = "default";
1119                 pinctrl-0 = <&i2c4_xfer>;
1120                 #address-cells = <1>;
1121                 #size-cells = <0>;
1122                 status = "disabled";
1123         };
1124
1125         i2c8: i2c@ff3e0000 {
1126                 compatible = "rockchip,rk3399-i2c";
1127                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1128                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1129                 clock-names = "i2c", "pclk";
1130                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1131                 pinctrl-names = "default";
1132                 pinctrl-0 = <&i2c8_xfer>;
1133                 #address-cells = <1>;
1134                 #size-cells = <0>;
1135                 status = "disabled";
1136         };
1137
1138         pcie_phy: phy@e220 {
1139                 compatible = "rockchip,rk3399-pcie-phy";
1140                 #phy-cells = <0>;
1141                 rockchip,grf = <&grf>;
1142                 clocks = <&cru SCLK_PCIEPHY_REF>;
1143                 clock-names = "refclk";
1144                 resets = <&cru SRST_PCIEPHY>;
1145                 reset-names = "phy";
1146                 status = "disabled";
1147         };
1148
1149         pcie0: pcie@f8000000 {
1150                 compatible = "rockchip,rk3399-pcie";
1151                 #address-cells = <3>;
1152                 #size-cells = <2>;
1153                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1154                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1155                 clock-names = "aclk", "aclk-perf",
1156                               "hclk", "pm";
1157                 bus-range = <0x0 0x1>;
1158                 max-link-speed = <1>;
1159                 msi-map = <0x0 &its 0x0 0x1000>;
1160                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1161                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1162                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1163                 interrupt-names = "sys", "legacy", "client";
1164                 #interrupt-cells = <1>;
1165                 interrupt-map-mask = <0 0 0 7>;
1166                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1167                                 <0 0 0 2 &pcie0_intc 1>,
1168                                 <0 0 0 3 &pcie0_intc 2>,
1169                                 <0 0 0 4 &pcie0_intc 3>;
1170                 phys = <&pcie_phy>;
1171                 phy-names = "pcie-phy";
1172                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1173                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1174                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1175                       <0x0 0xfd000000 0x0 0x1000000>;
1176                 reg-names = "axi-base", "apb-base";
1177                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1178                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1179                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1180                          <&cru SRST_A_PCIE>;
1181                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1182                               "pm", "pclk", "aclk";
1183                 status = "disabled";
1184                 pcie0_intc: interrupt-controller {
1185                         interrupt-controller;
1186                         #address-cells = <0>;
1187                         #interrupt-cells = <1>;
1188                 };
1189         };
1190
1191         pwm0: pwm@ff420000 {
1192                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1193                 reg = <0x0 0xff420000 0x0 0x10>;
1194                 #pwm-cells = <3>;
1195                 pinctrl-names = "default";
1196                 pinctrl-0 = <&pwm0_pin>;
1197                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1198                 clock-names = "pwm";
1199                 status = "disabled";
1200         };
1201
1202         pwm1: pwm@ff420010 {
1203                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1204                 reg = <0x0 0xff420010 0x0 0x10>;
1205                 #pwm-cells = <3>;
1206                 pinctrl-names = "default";
1207                 pinctrl-0 = <&pwm1_pin>;
1208                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1209                 clock-names = "pwm";
1210                 status = "disabled";
1211         };
1212
1213         pwm2: pwm@ff420020 {
1214                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1215                 reg = <0x0 0xff420020 0x0 0x10>;
1216                 #pwm-cells = <3>;
1217                 pinctrl-names = "default";
1218                 pinctrl-0 = <&pwm2_pin>;
1219                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1220                 clock-names = "pwm";
1221                 status = "disabled";
1222         };
1223
1224         pwm3: pwm@ff420030 {
1225                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1226                 reg = <0x0 0xff420030 0x0 0x10>;
1227                 #pwm-cells = <3>;
1228                 pinctrl-names = "default";
1229                 pinctrl-0 = <&pwm3a_pin>;
1230                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1231                 clock-names = "pwm";
1232                 status = "disabled";
1233         };
1234
1235         dfi: dfi@ff630000 {
1236                 reg = <0x00 0xff630000 0x00 0x4000>;
1237                 compatible = "rockchip,rk3399-dfi";
1238                 rockchip,pmu = <&pmugrf>;
1239                 clocks = <&cru PCLK_DDR_MON>;
1240                 clock-names = "pclk_ddr_mon";
1241                 status = "disabled";
1242         };
1243
1244         dmc: dmc {
1245                 compatible = "rockchip,rk3399-dmc";
1246                 devfreq-events = <&dfi>;
1247                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1248                 clocks = <&cru SCLK_DDRCLK>;
1249                 clock-names = "dmc_clk";
1250                 ddr_timing = <&ddr_timing>;
1251                 status = "disabled";
1252         };
1253
1254         rga: rga@ff680000 {
1255                 compatible = "rockchip,rk3399-rga";
1256                 reg = <0x0 0xff680000 0x0 0x10000>;
1257                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1258                 interrupt-names = "rga";
1259                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1260                 clock-names = "aclk", "hclk", "sclk";
1261                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1262                 reset-names = "core", "axi", "ahb";
1263                 power-domains = <&power RK3399_PD_RGA>;
1264                 status = "disabled";
1265         };
1266
1267         efuse0: efuse@ff690000 {
1268                 compatible = "rockchip,rk3399-efuse";
1269                 reg = <0x0 0xff690000 0x0 0x80>;
1270                 #address-cells = <1>;
1271                 #size-cells = <1>;
1272                 clocks = <&cru PCLK_EFUSE1024NS>;
1273                 clock-names = "pclk_efuse";
1274
1275                 /* Data cells */
1276                 cpul_leakage: cpul-leakage {
1277                         reg = <0x1a 0x1>;
1278                 };
1279                 cpub_leakage: cpub-leakage {
1280                         reg = <0x17 0x1>;
1281                 };
1282                 gpu_leakage: gpu-leakage {
1283                         reg = <0x18 0x1>;
1284                 };
1285                 center_leakage: center-leakage {
1286                         reg = <0x19 0x1>;
1287                 };
1288                 logic_leakage: logic-leakage {
1289                         reg = <0x1b 0x1>;
1290                 };
1291                 wafer_info: wafer-info {
1292                         reg = <0x1c 0x1>;
1293                 };
1294         };
1295
1296         pmucru: pmu-clock-controller@ff750000 {
1297                 compatible = "rockchip,rk3399-pmucru";
1298                 reg = <0x0 0xff750000 0x0 0x1000>;
1299                 #clock-cells = <1>;
1300                 #reset-cells = <1>;
1301                 assigned-clocks = <&pmucru PLL_PPLL>;
1302                 assigned-clock-rates = <676000000>;
1303         };
1304
1305         cru: clock-controller@ff760000 {
1306                 compatible = "rockchip,rk3399-cru";
1307                 reg = <0x0 0xff760000 0x0 0x1000>;
1308                 #clock-cells = <1>;
1309                 #reset-cells = <1>;
1310                 assigned-clocks =
1311                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1312                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1313                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1314                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1315                         <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1316                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1317                         <&cru PCLK_PERIHP>,
1318                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1319                         <&cru PCLK_PERILP0>,
1320                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1321                 assigned-clock-rates =
1322                          <400000000>,  <200000000>,
1323                          <400000000>,  <200000000>,
1324                          <816000000>, <816000000>,
1325                          <594000000>,  <800000000>,
1326                          <200000000>, <1000000000>,
1327                          <150000000>,   <75000000>,
1328                           <37500000>,
1329                          <100000000>,  <100000000>,
1330                           <50000000>,
1331                          <100000000>,   <50000000>;
1332         };
1333
1334         grf: syscon@ff770000 {
1335                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1336                 reg = <0x0 0xff770000 0x0 0x10000>;
1337                 #address-cells = <1>;
1338                 #size-cells = <1>;
1339
1340                 io_domains: io-domains {
1341                         compatible = "rockchip,rk3399-io-voltage-domain";
1342                         status = "disabled";
1343                 };
1344
1345                 emmc_phy: phy@f780 {
1346                         compatible = "rockchip,rk3399-emmc-phy";
1347                         reg = <0xf780 0x24>;
1348                         clocks = <&sdhci>;
1349                         clock-names = "emmcclk";
1350                         #phy-cells = <0>;
1351                         status = "disabled";
1352                 };
1353
1354                 u2phy0: usb2-phy@e450 {
1355                         compatible = "rockchip,rk3399-usb2phy";
1356                         reg = <0xe450 0x10>;
1357                         clocks = <&cru SCLK_USB2PHY0_REF>;
1358                         clock-names = "phyclk";
1359                         #clock-cells = <0>;
1360                         clock-output-names = "clk_usbphy0_480m";
1361                         status = "disabled";
1362
1363                         u2phy0_otg: otg-port {
1364                                 #phy-cells = <0>;
1365                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1366                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1367                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1368                                 interrupt-names = "otg-bvalid", "otg-id",
1369                                                   "linestate";
1370                                 status = "disabled";
1371                         };
1372
1373                         u2phy0_host: host-port {
1374                                 #phy-cells = <0>;
1375                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1376                                 interrupt-names = "linestate";
1377                                 status = "disabled";
1378                         };
1379                 };
1380
1381                 u2phy1: usb2-phy@e460 {
1382                         compatible = "rockchip,rk3399-usb2phy";
1383                         reg = <0xe460 0x10>;
1384                         clocks = <&cru SCLK_USB2PHY1_REF>;
1385                         clock-names = "phyclk";
1386                         #clock-cells = <0>;
1387                         clock-output-names = "clk_usbphy1_480m";
1388                         status = "disabled";
1389
1390                         u2phy1_otg: otg-port {
1391                                 #phy-cells = <0>;
1392                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1393                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1394                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1395                                 interrupt-names = "otg-bvalid", "otg-id",
1396                                                   "linestate";
1397                                 status = "disabled";
1398                         };
1399
1400                         u2phy1_host: host-port {
1401                                 #phy-cells = <0>;
1402                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1403                                 interrupt-names = "linestate";
1404                                 status = "disabled";
1405                         };
1406                 };
1407
1408                 pvtm: pvtm {
1409                         compatible = "rockchip,rk3399-pvtm";
1410                         clocks = <&cru SCLK_PVTM_CORE_L>,
1411                                  <&cru SCLK_PVTM_CORE_B>,
1412                                  <&cru SCLK_PVTM_GPU>,
1413                                  <&cru SCLK_PVTM_DDR>;
1414                         clock-names = "core_l", "core_b", "gpu", "ddr";
1415                         status = "disabled";
1416                 };
1417         };
1418
1419         tcphy0: phy@ff7c0000 {
1420                 compatible = "rockchip,rk3399-typec-phy";
1421                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1422                 rockchip,grf = <&grf>;
1423                 #phy-cells = <1>;
1424                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1425                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1426                 clock-names = "tcpdcore", "tcpdphy-ref";
1427                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1428                 assigned-clock-rates = <50000000>;
1429                 power-domains = <&power RK3399_PD_TCPD0>;
1430                 resets = <&cru SRST_UPHY0>,
1431                          <&cru SRST_UPHY0_PIPE_L00>,
1432                          <&cru SRST_P_UPHY0_TCPHY>;
1433                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1434                 rockchip,typec-conn-dir = <0xe580 0 16>;
1435                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1436                 rockchip,usb3-host-disable = <0x2434 0 16>;
1437                 rockchip,usb3-host-port = <0x2434 12 28>;
1438                 rockchip,external-psm = <0xe588 14 30>;
1439                 rockchip,pipe-status = <0xe5c0 0 0>;
1440                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1441                 status = "disabled";
1442
1443                 tcphy0_dp: dp-port {
1444                         #phy-cells = <0>;
1445                 };
1446
1447                 tcphy0_usb3: usb3-port {
1448                         #phy-cells = <0>;
1449                 };
1450         };
1451
1452         tcphy1: phy@ff800000 {
1453                 compatible = "rockchip,rk3399-typec-phy";
1454                 reg = <0x0 0xff800000 0x0 0x40000>;
1455                 rockchip,grf = <&grf>;
1456                 #phy-cells = <1>;
1457                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1458                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1459                 clock-names = "tcpdcore", "tcpdphy-ref";
1460                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1461                 assigned-clock-rates = <50000000>;
1462                 power-domains = <&power RK3399_PD_TCPD1>;
1463                 resets = <&cru SRST_UPHY1>,
1464                          <&cru SRST_UPHY1_PIPE_L00>,
1465                          <&cru SRST_P_UPHY1_TCPHY>;
1466                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1467                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1468                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1469                 rockchip,usb3-host-disable = <0x2444 0 16>;
1470                 rockchip,usb3-host-port = <0x2444 12 28>;
1471                 rockchip,external-psm = <0xe594 14 30>;
1472                 rockchip,pipe-status = <0xe5c0 16 16>;
1473                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1474                 status = "disabled";
1475
1476                 tcphy1_dp: dp-port {
1477                         #phy-cells = <0>;
1478                 };
1479
1480                 tcphy1_usb3: usb3-port {
1481                         #phy-cells = <0>;
1482                 };
1483         };
1484
1485         watchdog@ff848000 {
1486                 compatible = "snps,dw-wdt";
1487                 reg = <0x0 0xff848000 0x0 0x100>;
1488                 clocks = <&cru PCLK_WDT>;
1489                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1490         };
1491
1492         rktimer: rktimer@ff850000 {
1493                 compatible = "rockchip,rk3399-timer";
1494                 reg = <0x0 0xff850000 0x0 0x1000>;
1495                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1496                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1497                 clock-names = "pclk", "timer";
1498         };
1499
1500         spdif: spdif@ff870000 {
1501                 compatible = "rockchip,rk3399-spdif";
1502                 reg = <0x0 0xff870000 0x0 0x1000>;
1503                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1504                 dmas = <&dmac_bus 7>;
1505                 dma-names = "tx";
1506                 clock-names = "mclk", "hclk";
1507                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1508                 pinctrl-names = "default";
1509                 pinctrl-0 = <&spdif_bus>;
1510                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1511                 status = "disabled";
1512         };
1513
1514         i2s0: i2s@ff880000 {
1515                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1516                 reg = <0x0 0xff880000 0x0 0x1000>;
1517                 rockchip,grf = <&grf>;
1518                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1519                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1520                 dma-names = "tx", "rx";
1521                 clock-names = "i2s_clk", "i2s_hclk";
1522                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1523                 pinctrl-names = "default";
1524                 pinctrl-0 = <&i2s0_8ch_bus>;
1525                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1526                 status = "disabled";
1527         };
1528
1529         i2s1: i2s@ff890000 {
1530                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1531                 reg = <0x0 0xff890000 0x0 0x1000>;
1532                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1533                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1534                 dma-names = "tx", "rx";
1535                 clock-names = "i2s_clk", "i2s_hclk";
1536                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1537                 pinctrl-names = "default";
1538                 pinctrl-0 = <&i2s1_2ch_bus>;
1539                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1540                 status = "disabled";
1541         };
1542
1543         i2s2: i2s@ff8a0000 {
1544                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1545                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1546                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1547                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1548                 dma-names = "tx", "rx";
1549                 clock-names = "i2s_clk", "i2s_hclk";
1550                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1551                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1552                 status = "disabled";
1553         };
1554
1555         gpu: gpu@ff9a0000 {
1556                 compatible = "arm,malit860",
1557                              "arm,malit86x",
1558                              "arm,malit8xx",
1559                              "arm,mali-midgard";
1560
1561                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1562
1563                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1564                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1565                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1566                 interrupt-names = "GPU", "JOB", "MMU";
1567
1568                 clocks = <&cru ACLK_GPU>;
1569                 clock-names = "clk_mali";
1570                 #cooling-cells = <2>; /* min followed by max */
1571                 power-domains = <&power RK3399_PD_GPU>;
1572                 power-off-delay-ms = <200>;
1573                 status = "disabled";
1574
1575                 gpu_power_model: power_model {
1576                         compatible = "arm,mali-simple-power-model";
1577                         voltage = <900>;
1578                         frequency = <500>;
1579                         static-power = <300>;
1580                         dynamic-power = <396>;
1581                         ts = <32000 4700 (-80) 2>;
1582                         thermal-zone = "gpu-thermal";
1583                 };
1584         };
1585
1586         vopl: vop@ff8f0000 {
1587                 compatible = "rockchip,rk3399-vop-lit";
1588                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1589                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1590                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1591                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1592                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1593                 reset-names = "axi", "ahb", "dclk";
1594                 power-domains = <&power RK3399_PD_VOPL>;
1595                 iommus = <&vopl_mmu>;
1596                 status = "disabled";
1597
1598                 vopl_out: port {
1599                         #address-cells = <1>;
1600                         #size-cells = <0>;
1601
1602                         vopl_out_mipi: endpoint@0 {
1603                                 reg = <0>;
1604                                 remote-endpoint = <&mipi_in_vopl>;
1605                         };
1606
1607                         vopl_out_edp: endpoint@1 {
1608                                 reg = <1>;
1609                                 remote-endpoint = <&edp_in_vopl>;
1610                         };
1611
1612                         vopl_out_hdmi: endpoint@2 {
1613                                 reg = <2>;
1614                                 remote-endpoint = <&hdmi_in_vopl>;
1615                         };
1616                 };
1617         };
1618
1619         vop1_pwm: voppwm@ff8f01a0 {
1620                 compatible = "rockchip,vop-pwm";
1621                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1622                 #pwm-cells = <3>;
1623                 pinctrl-names = "default";
1624                 pinctrl-0 = <&vop1_pwm_pin>;
1625                 clocks = <&cru SCLK_VOP1_PWM>;
1626                 clock-names = "pwm";
1627                 status = "disabled";
1628         };
1629
1630         vopl_mmu: iommu@ff8f3f00 {
1631                 compatible = "rockchip,iommu";
1632                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1633                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1634                 interrupt-names = "vopl_mmu";
1635                 #iommu-cells = <0>;
1636                 status = "disabled";
1637         };
1638
1639         vopb: vop@ff900000 {
1640                 compatible = "rockchip,rk3399-vop-big";
1641                 reg = <0x0 0xff900000 0x0 0x3efc>;
1642                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1643                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1644                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1645                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1646                 reset-names = "axi", "ahb", "dclk";
1647                 power-domains = <&power RK3399_PD_VOPB>;
1648                 iommus = <&vopb_mmu>;
1649                 status = "disabled";
1650
1651                 vopb_out: port {
1652                         #address-cells = <1>;
1653                         #size-cells = <0>;
1654
1655                         vopb_out_edp: endpoint@0 {
1656                                 reg = <0>;
1657                                 remote-endpoint = <&edp_in_vopb>;
1658                         };
1659
1660                         vopb_out_mipi: endpoint@1 {
1661                                 reg = <1>;
1662                                 remote-endpoint = <&mipi_in_vopb>;
1663                         };
1664
1665                         vopb_out_hdmi: endpoint@2 {
1666                                 reg = <2>;
1667                                 remote-endpoint = <&hdmi_in_vopb>;
1668                         };
1669                 };
1670         };
1671
1672         vop0_pwm: voppwm@ff9001a0 {
1673                 compatible = "rockchip,vop-pwm";
1674                 reg = <0x0 0xff9001a0 0x0 0x10>;
1675                 #pwm-cells = <3>;
1676                 pinctrl-names = "default";
1677                 pinctrl-0 = <&vop0_pwm_pin>;
1678                 clocks = <&cru SCLK_VOP0_PWM>;
1679                 clock-names = "pwm";
1680                 status = "disabled";
1681         };
1682
1683         vopb_mmu: iommu@ff903f00 {
1684                 compatible = "rockchip,iommu";
1685                 reg = <0x0 0xff903f00 0x0 0x100>;
1686                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1687                 interrupt-names = "vopb_mmu";
1688                 #iommu-cells = <0>;
1689                 status = "disabled";
1690         };
1691
1692         isp0_mmu: iommu@ff914000 {
1693                 compatible = "rockchip,iommu";
1694                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1695                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1696                 interrupt-names = "isp0_mmu";
1697                 #iommu-cells = <0>;
1698                 rk_iommu,disable_reset_quirk;
1699                 status = "disabled";
1700         };
1701
1702         isp1_mmu: iommu@ff924000 {
1703                 compatible = "rockchip,iommu";
1704                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1705                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1706                 interrupt-names = "isp1_mmu";
1707                 #iommu-cells = <0>;
1708                 rk_iommu,disable_reset_quirk;
1709                 status = "disabled";
1710         };
1711
1712         hdmi: hdmi@ff940000 {
1713                 compatible = "rockchip,rk3399-dw-hdmi";
1714                 reg = <0x0 0xff940000 0x0 0x20000>;
1715                 reg-io-width = <4>;
1716                 rockchip,grf = <&grf>;
1717                 power-domains = <&power RK3399_PD_HDCP>;
1718                 pinctrl-names = "default";
1719                 pinctrl-0 = <&hdmi_i2c_xfer>;
1720                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1721                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1722                 clock-names = "iahb", "isfr", "vpll", "grf";
1723                 status = "disabled";
1724
1725                 ports {
1726                         hdmi_in: port {
1727                                 #address-cells = <1>;
1728                                 #size-cells = <0>;
1729                                 hdmi_in_vopb: endpoint@0 {
1730                                         reg = <0>;
1731                                         remote-endpoint = <&vopb_out_hdmi>;
1732                                 };
1733                                 hdmi_in_vopl: endpoint@1 {
1734                                         reg = <1>;
1735                                         remote-endpoint = <&vopl_out_hdmi>;
1736                                 };
1737                         };
1738                 };
1739         };
1740
1741         mipi_dsi: mipi@ff960000 {
1742                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1743                 reg = <0x0 0xff960000 0x0 0x8000>;
1744                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1745                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1746                          <&cru SCLK_DPHY_TX0_CFG>;
1747                 clock-names = "ref", "pclk", "phy_cfg";
1748                 power-domains = <&power RK3399_PD_VIO>;
1749                 rockchip,grf = <&grf>;
1750                 #address-cells = <1>;
1751                 #size-cells = <0>;
1752                 status = "disabled";
1753
1754                 ports {
1755                         #address-cells = <1>;
1756                         #size-cells = <0>;
1757                         reg = <1>;
1758
1759                         mipi_in: port {
1760                                 #address-cells = <1>;
1761                                 #size-cells = <0>;
1762
1763                                 mipi_in_vopb: endpoint@0 {
1764                                         reg = <0>;
1765                                         remote-endpoint = <&vopb_out_mipi>;
1766                                 };
1767                                 mipi_in_vopl: endpoint@1 {
1768                                         reg = <1>;
1769                                         remote-endpoint = <&vopl_out_mipi>;
1770                                 };
1771                         };
1772                 };
1773         };
1774
1775         edp: edp@ff970000 {
1776                 compatible = "rockchip,rk3399-edp";
1777                 reg = <0x0 0xff970000 0x0 0x8000>;
1778                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1779                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1780                 clock-names = "dp", "pclk";
1781                 power-domains = <&power RK3399_PD_EDP>;
1782                 resets = <&cru SRST_P_EDP_CTRL>;
1783                 reset-names = "dp";
1784                 rockchip,grf = <&grf>;
1785                 status = "disabled";
1786                 pinctrl-names = "default";
1787                 pinctrl-0 = <&edp_hpd>;
1788
1789                 ports {
1790                         #address-cells = <1>;
1791                         #size-cells = <0>;
1792
1793                         edp_in: port@0 {
1794                                 reg = <0>;
1795                                 #address-cells = <1>;
1796                                 #size-cells = <0>;
1797
1798                                 edp_in_vopb: endpoint@0 {
1799                                         reg = <0>;
1800                                         remote-endpoint = <&vopb_out_edp>;
1801                                 };
1802
1803                                 edp_in_vopl: endpoint@1 {
1804                                         reg = <1>;
1805                                         remote-endpoint = <&vopl_out_edp>;
1806                                 };
1807                         };
1808                 };
1809         };
1810
1811         display_subsystem: display-subsystem {
1812                 compatible = "rockchip,display-subsystem";
1813                 ports = <&vopl_out>, <&vopb_out>;
1814                 status = "disabled";
1815         };
1816
1817         pinctrl: pinctrl {
1818                 compatible = "rockchip,rk3399-pinctrl";
1819                 rockchip,grf = <&grf>;
1820                 rockchip,pmu = <&pmugrf>;
1821                 #address-cells = <0x2>;
1822                 #size-cells = <0x2>;
1823                 ranges;
1824
1825                 gpio0: gpio0@ff720000 {
1826                         compatible = "rockchip,gpio-bank";
1827                         reg = <0x0 0xff720000 0x0 0x100>;
1828                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1829                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1830
1831                         gpio-controller;
1832                         #gpio-cells = <0x2>;
1833
1834                         interrupt-controller;
1835                         #interrupt-cells = <0x2>;
1836                 };
1837
1838                 gpio1: gpio1@ff730000 {
1839                         compatible = "rockchip,gpio-bank";
1840                         reg = <0x0 0xff730000 0x0 0x100>;
1841                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1842                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1843
1844                         gpio-controller;
1845                         #gpio-cells = <0x2>;
1846
1847                         interrupt-controller;
1848                         #interrupt-cells = <0x2>;
1849                 };
1850
1851                 gpio2: gpio2@ff780000 {
1852                         compatible = "rockchip,gpio-bank";
1853                         reg = <0x0 0xff780000 0x0 0x100>;
1854                         clocks = <&cru PCLK_GPIO2>;
1855                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1856
1857                         gpio-controller;
1858                         #gpio-cells = <0x2>;
1859
1860                         interrupt-controller;
1861                         #interrupt-cells = <0x2>;
1862                 };
1863
1864                 gpio3: gpio3@ff788000 {
1865                         compatible = "rockchip,gpio-bank";
1866                         reg = <0x0 0xff788000 0x0 0x100>;
1867                         clocks = <&cru PCLK_GPIO3>;
1868                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1869
1870                         gpio-controller;
1871                         #gpio-cells = <0x2>;
1872
1873                         interrupt-controller;
1874                         #interrupt-cells = <0x2>;
1875                 };
1876
1877                 gpio4: gpio4@ff790000 {
1878                         compatible = "rockchip,gpio-bank";
1879                         reg = <0x0 0xff790000 0x0 0x100>;
1880                         clocks = <&cru PCLK_GPIO4>;
1881                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1882
1883                         gpio-controller;
1884                         #gpio-cells = <0x2>;
1885
1886                         interrupt-controller;
1887                         #interrupt-cells = <0x2>;
1888                 };
1889
1890                 pcfg_pull_up: pcfg-pull-up {
1891                         bias-pull-up;
1892                 };
1893
1894                 pcfg_pull_down: pcfg-pull-down {
1895                         bias-pull-down;
1896                 };
1897
1898                 pcfg_pull_none: pcfg-pull-none {
1899                         bias-disable;
1900                 };
1901
1902                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1903                         bias-pull-up;
1904                         drive-strength = <20>;
1905                 };
1906
1907                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1908                         bias-disable;
1909                         drive-strength = <20>;
1910                 };
1911
1912                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1913                         bias-disable;
1914                         drive-strength = <18>;
1915                 };
1916
1917                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1918                         bias-disable;
1919                         drive-strength = <12>;
1920                 };
1921
1922                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1923                         bias-pull-up;
1924                         drive-strength = <8>;
1925                 };
1926
1927                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1928                         bias-pull-down;
1929                         drive-strength = <4>;
1930                 };
1931
1932                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1933                         bias-pull-up;
1934                         drive-strength = <2>;
1935                 };
1936
1937                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1938                         bias-pull-down;
1939                         drive-strength = <12>;
1940                 };
1941
1942                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1943                         bias-disable;
1944                         drive-strength = <13>;
1945                 };
1946
1947                 pcfg_output_high: pcfg-output-high {
1948                         output-high;
1949                 };
1950
1951                 pcfg_output_low: pcfg-output-low {
1952                         output-low;
1953                 };
1954
1955                 pcfg_input: pcfg-input {
1956                         input-enable;
1957                 };
1958
1959                 emmc {
1960                         emmc_pwr: emmc-pwr {
1961                                 rockchip,pins =
1962                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1963                         };
1964                 };
1965
1966                 gmac {
1967                         rgmii_pins: rgmii-pins {
1968                                 rockchip,pins =
1969                                         /* mac_txclk */
1970                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1971                                         /* mac_rxclk */
1972                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1973                                         /* mac_mdio */
1974                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1975                                         /* mac_txen */
1976                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1977                                         /* mac_clk */
1978                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1979                                         /* mac_rxdv */
1980                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1981                                         /* mac_mdc */
1982                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1983                                         /* mac_rxd1 */
1984                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1985                                         /* mac_rxd0 */
1986                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1987                                         /* mac_txd1 */
1988                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1989                                         /* mac_txd0 */
1990                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1991                                         /* mac_rxd3 */
1992                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1993                                         /* mac_rxd2 */
1994                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1995                                         /* mac_txd3 */
1996                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1997                                         /* mac_txd2 */
1998                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1999                         };
2000
2001                         rmii_pins: rmii-pins {
2002                                 rockchip,pins =
2003                                         /* mac_mdio */
2004                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2005                                         /* mac_txen */
2006                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2007                                         /* mac_clk */
2008                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2009                                         /* mac_rxer */
2010                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2011                                         /* mac_rxdv */
2012                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2013                                         /* mac_mdc */
2014                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2015                                         /* mac_rxd1 */
2016                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2017                                         /* mac_rxd0 */
2018                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2019                                         /* mac_txd1 */
2020                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2021                                         /* mac_txd0 */
2022                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2023                         };
2024                 };
2025
2026                 i2c0 {
2027                         i2c0_xfer: i2c0-xfer {
2028                                 rockchip,pins =
2029                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2030                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2031                         };
2032                 };
2033
2034                 i2c1 {
2035                         i2c1_xfer: i2c1-xfer {
2036                                 rockchip,pins =
2037                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2038                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2039                         };
2040                 };
2041
2042                 i2c2 {
2043                         i2c2_xfer: i2c2-xfer {
2044                                 rockchip,pins =
2045                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2046                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2047                         };
2048                 };
2049
2050                 i2c3 {
2051                         i2c3_xfer: i2c3-xfer {
2052                                 rockchip,pins =
2053                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2054                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2055                         };
2056
2057                         i2c3_gpio: i2c3_gpio {
2058                                 rockchip,pins =
2059                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2060                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2061                         };
2062
2063                 };
2064
2065                 i2c4 {
2066                         i2c4_xfer: i2c4-xfer {
2067                                 rockchip,pins =
2068                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2069                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2070                         };
2071                 };
2072
2073                 i2c5 {
2074                         i2c5_xfer: i2c5-xfer {
2075                                 rockchip,pins =
2076                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2077                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2078                         };
2079                 };
2080
2081                 i2c6 {
2082                         i2c6_xfer: i2c6-xfer {
2083                                 rockchip,pins =
2084                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2085                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2086                         };
2087                 };
2088
2089                 i2c7 {
2090                         i2c7_xfer: i2c7-xfer {
2091                                 rockchip,pins =
2092                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2093                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2094                         };
2095                 };
2096
2097                 i2c8 {
2098                         i2c8_xfer: i2c8-xfer {
2099                                 rockchip,pins =
2100                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2101                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2102                         };
2103                 };
2104
2105                 i2s0 {
2106                         i2s0_8ch_bus: i2s0-8ch-bus {
2107                                 rockchip,pins =
2108                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2109                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2110                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2111                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2112                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2113                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2114                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2115                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2116                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2117                         };
2118                 };
2119
2120                 i2s1 {
2121                         i2s1_2ch_bus: i2s1-2ch-bus {
2122                                 rockchip,pins =
2123                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2124                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2125                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2126                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2127                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2128                         };
2129                 };
2130
2131                 sdio0 {
2132                         sdio0_bus1: sdio0-bus1 {
2133                                 rockchip,pins =
2134                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2135                         };
2136
2137                         sdio0_bus4: sdio0-bus4 {
2138                                 rockchip,pins =
2139                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2140                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2141                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2142                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2143                         };
2144
2145                         sdio0_cmd: sdio0-cmd {
2146                                 rockchip,pins =
2147                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2148                         };
2149
2150                         sdio0_clk: sdio0-clk {
2151                                 rockchip,pins =
2152                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2153                         };
2154
2155                         sdio0_cd: sdio0-cd {
2156                                 rockchip,pins =
2157                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2158                         };
2159
2160                         sdio0_pwr: sdio0-pwr {
2161                                 rockchip,pins =
2162                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2163                         };
2164
2165                         sdio0_bkpwr: sdio0-bkpwr {
2166                                 rockchip,pins =
2167                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2168                         };
2169
2170                         sdio0_wp: sdio0-wp {
2171                                 rockchip,pins =
2172                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2173                         };
2174
2175                         sdio0_int: sdio0-int {
2176                                 rockchip,pins =
2177                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2178                         };
2179                 };
2180
2181                 sdmmc {
2182                         sdmmc_bus1: sdmmc-bus1 {
2183                                 rockchip,pins =
2184                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2185                         };
2186
2187                         sdmmc_bus4: sdmmc-bus4 {
2188                                 rockchip,pins =
2189                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2190                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2191                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2192                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2193                         };
2194
2195                         sdmmc_clk: sdmmc-clk {
2196                                 rockchip,pins =
2197                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2198                         };
2199
2200                         sdmmc_cmd: sdmmc-cmd {
2201                                 rockchip,pins =
2202                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2203                         };
2204
2205                         sdmmc_cd: sdmcc-cd {
2206                                 rockchip,pins =
2207                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2208                         };
2209
2210                         sdmmc_wp: sdmmc-wp {
2211                                 rockchip,pins =
2212                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2213                         };
2214                 };
2215
2216                 spdif {
2217                         spdif_bus: spdif-bus {
2218                                 rockchip,pins =
2219                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2220                         };
2221
2222                         spdif_bus_1: spdif-bus-1 {
2223                                 rockchip,pins =
2224                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2225                         };
2226                 };
2227
2228                 spi0 {
2229                         spi0_clk: spi0-clk {
2230                                 rockchip,pins =
2231                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2232                         };
2233                         spi0_cs0: spi0-cs0 {
2234                                 rockchip,pins =
2235                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2236                         };
2237                         spi0_cs1: spi0-cs1 {
2238                                 rockchip,pins =
2239                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2240                         };
2241                         spi0_tx: spi0-tx {
2242                                 rockchip,pins =
2243                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2244                         };
2245                         spi0_rx: spi0-rx {
2246                                 rockchip,pins =
2247                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2248                         };
2249                 };
2250
2251                 spi1 {
2252                         spi1_clk: spi1-clk {
2253                                 rockchip,pins =
2254                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2255                         };
2256                         spi1_cs0: spi1-cs0 {
2257                                 rockchip,pins =
2258                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2259                         };
2260                         spi1_rx: spi1-rx {
2261                                 rockchip,pins =
2262                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2263                         };
2264                         spi1_tx: spi1-tx {
2265                                 rockchip,pins =
2266                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2267                         };
2268                 };
2269
2270                 spi2 {
2271                         spi2_clk: spi2-clk {
2272                                 rockchip,pins =
2273                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2274                         };
2275                         spi2_cs0: spi2-cs0 {
2276                                 rockchip,pins =
2277                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2278                         };
2279                         spi2_rx: spi2-rx {
2280                                 rockchip,pins =
2281                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2282                         };
2283                         spi2_tx: spi2-tx {
2284                                 rockchip,pins =
2285                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2286                         };
2287                 };
2288
2289                 spi3 {
2290                         spi3_clk: spi3-clk {
2291                                 rockchip,pins =
2292                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2293                         };
2294                         spi3_cs0: spi3-cs0 {
2295                                 rockchip,pins =
2296                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2297                         };
2298                         spi3_rx: spi3-rx {
2299                                 rockchip,pins =
2300                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2301                         };
2302                         spi3_tx: spi3-tx {
2303                                 rockchip,pins =
2304                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2305                         };
2306                 };
2307
2308                 spi4 {
2309                         spi4_clk: spi4-clk {
2310                                 rockchip,pins =
2311                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2312                         };
2313                         spi4_cs0: spi4-cs0 {
2314                                 rockchip,pins =
2315                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2316                         };
2317                         spi4_rx: spi4-rx {
2318                                 rockchip,pins =
2319                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2320                         };
2321                         spi4_tx: spi4-tx {
2322                                 rockchip,pins =
2323                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2324                         };
2325                 };
2326
2327                 spi5 {
2328                         spi5_clk: spi5-clk {
2329                                 rockchip,pins =
2330                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2331                         };
2332                         spi5_cs0: spi5-cs0 {
2333                                 rockchip,pins =
2334                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2335                         };
2336                         spi5_rx: spi5-rx {
2337                                 rockchip,pins =
2338                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2339                         };
2340                         spi5_tx: spi5-tx {
2341                                 rockchip,pins =
2342                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2343                         };
2344                 };
2345
2346                 tsadc {
2347                         otp_gpio: otp-gpio {
2348                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2349                         };
2350
2351                         otp_out: otp-out {
2352                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2353                         };
2354                 };
2355
2356                 uart0 {
2357                         uart0_xfer: uart0-xfer {
2358                                 rockchip,pins =
2359                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2360                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2361                         };
2362
2363                         uart0_cts: uart0-cts {
2364                                 rockchip,pins =
2365                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2366                         };
2367
2368                         uart0_rts: uart0-rts {
2369                                 rockchip,pins =
2370                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2371                         };
2372                 };
2373
2374                 uart1 {
2375                         uart1_xfer: uart1-xfer {
2376                                 rockchip,pins =
2377                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2378                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2379                         };
2380                 };
2381
2382                 uart2a {
2383                         uart2a_xfer: uart2a-xfer {
2384                                 rockchip,pins =
2385                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2386                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2387                         };
2388                 };
2389
2390                 uart2b {
2391                         uart2b_xfer: uart2b-xfer {
2392                                 rockchip,pins =
2393                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2394                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2395                         };
2396                 };
2397
2398                 uart2c {
2399                         uart2c_xfer: uart2c-xfer {
2400                                 rockchip,pins =
2401                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2402                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2403                         };
2404                 };
2405
2406                 uart3 {
2407                         uart3_xfer: uart3-xfer {
2408                                 rockchip,pins =
2409                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2410                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2411                         };
2412
2413                         uart3_cts: uart3-cts {
2414                                 rockchip,pins =
2415                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2416                         };
2417
2418                         uart3_rts: uart3-rts {
2419                                 rockchip,pins =
2420                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2421                         };
2422                 };
2423
2424                 uart4 {
2425                         uart4_xfer: uart4-xfer {
2426                                 rockchip,pins =
2427                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2428                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2429                         };
2430                 };
2431
2432                 uarthdcp {
2433                         uarthdcp_xfer: uarthdcp-xfer {
2434                                 rockchip,pins =
2435                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2436                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2437                         };
2438                 };
2439
2440                 pwm0 {
2441                         pwm0_pin: pwm0-pin {
2442                                 rockchip,pins =
2443                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2444                         };
2445
2446                         vop0_pwm_pin: vop0-pwm-pin {
2447                                 rockchip,pins =
2448                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2449                         };
2450                 };
2451
2452                 pwm1 {
2453                         pwm1_pin: pwm1-pin {
2454                                 rockchip,pins =
2455                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2456                         };
2457
2458                         vop1_pwm_pin: vop1-pwm-pin {
2459                                 rockchip,pins =
2460                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2461                         };
2462                 };
2463
2464                 pwm2 {
2465                         pwm2_pin: pwm2-pin {
2466                                 rockchip,pins =
2467                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2468                         };
2469                 };
2470
2471                 pwm3a {
2472                         pwm3a_pin: pwm3a-pin {
2473                                 rockchip,pins =
2474                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2475                         };
2476                 };
2477
2478                 pwm3b {
2479                         pwm3b_pin: pwm3b-pin {
2480                                 rockchip,pins =
2481                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2482                         };
2483                 };
2484
2485                 edp {
2486                         edp_hpd: edp-hpd {
2487                                 rockchip,pins =
2488                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2489                         };
2490                 };
2491
2492                 hdmi {
2493                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2494                                 rockchip,pins =
2495                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2496                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2497                         };
2498
2499                         hdmi_cec: hdmi-cec {
2500                                 rockchip,pins =
2501                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2502                         };
2503                 };
2504
2505                 pcie {
2506                         pcie_clkreqn: pci-clkreqn {
2507                                 rockchip,pins =
2508                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2509                         };
2510
2511                         pcie_clkreqnb: pci-clkreqnb {
2512                                 rockchip,pins =
2513                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2514                         };
2515                 };
2516         };
2517 };