arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <100>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <436>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp@408000000 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp@600000000 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp@816000000 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp@1008000000 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp@1200000000 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp@1416000000 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp@408000000 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@600000000 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp@816000000 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp@1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 261         };
 262
 263         pmu_a53 {
 264                 compatible = "arm,cortex-a53-pmu";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 266         };
 267
 268         pmu_a72 {
 269                 compatible = "arm,cortex-a72-pmu";
 270                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 271         };
 272
 273         xin24m: xin24m {
 274                 compatible = "fixed-clock";
 275                 #clock-cells = <0>;
 276                 clock-frequency = <24000000>;
 277                 clock-output-names = "xin24m";
 278         };
 279
 280         amba {
 281                 compatible = "arm,amba-bus";
 282                 #address-cells = <2>;
 283                 #size-cells = <2>;
 284                 ranges;
 285
 286                 dmac_bus: dma-controller@ff6d0000 {
 287                         compatible = "arm,pl330", "arm,primecell";
 288                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 289                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 290                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 291                         #dma-cells = <1>;
 292                         clocks = <&cru ACLK_DMAC0_PERILP>;
 293                         clock-names = "apb_pclk";
 294                         peripherals-req-type-burst;
 295                 };
 296
 297                 dmac_peri: dma-controller@ff6e0000 {
 298                         compatible = "arm,pl330", "arm,primecell";
 299                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 300                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 301                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 302                         #dma-cells = <1>;
 303                         clocks = <&cru ACLK_DMAC1_PERILP>;
 304                         clock-names = "apb_pclk";
 305                         peripherals-req-type-burst;
 306                 };
 307         };
 308
 309         gmac: eth@fe300000 {
 310                 compatible = "rockchip,rk3399-gmac";
 311                 reg = <0x0 0xfe300000 0x0 0x10000>;
 312                 rockchip,grf = <&grf>;
 313                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 interrupt-names = "macirq";
 315                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 316                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 317                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 318                          <&cru PCLK_GMAC>;
 319                 clock-names = "stmmaceth", "mac_clk_rx",
 320                               "mac_clk_tx", "clk_mac_ref",
 321                               "clk_mac_refout", "aclk_mac",
 322                               "pclk_mac";
 323                 resets = <&cru SRST_A_GMAC>;
 324                 reset-names = "stmmaceth";
 325                 status = "disabled";
 326         };
 327
 328         emmc_phy: phy {
 329                 compatible = "rockchip,rk3399-emmc-phy";
 330                 reg-offset = <0xf780>;
 331                 #phy-cells = <0>;
 332                 rockchip,grf = <&grf>;
 333                 ctrl-base = <0xfe330000>;
 334                 status = "disabled";
 335         };
 336
 337         sdio0: dwmmc@fe310000 {
 338                 compatible = "rockchip,rk3399-dw-mshc",
 339                              "rockchip,rk3288-dw-mshc";
 340                 reg = <0x0 0xfe310000 0x0 0x4000>;
 341                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 342                 clock-freq-min-max = <400000 150000000>;
 343                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 344                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 345                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 346                 fifo-depth = <0x100>;
 347                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 348                 status = "disabled";
 349         };
 350
 351         sdmmc: dwmmc@fe320000 {
 352                 compatible = "rockchip,rk3399-dw-mshc",
 353                              "rockchip,rk3288-dw-mshc";
 354                 reg = <0x0 0xfe320000 0x0 0x4000>;
 355                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 356                 clock-freq-min-max = <400000 150000000>;
 357                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 358                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 359                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 360                 fifo-depth = <0x100>;
 361                 power-domains = <&power RK3399_PD_SD>;
 362                 status = "disabled";
 363         };
 364
 365         sdhci: sdhci@fe330000 {
 366                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 367                 reg = <0x0 0xfe330000 0x0 0x10000>;
 368                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 369                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 370                 clock-names = "clk_xin", "clk_ahb";
 371                 assigned-clocks = <&cru SCLK_EMMC>;
 372                 assigned-clock-parents = <&cru PLL_CPLL>;
 373                 assigned-clock-rates = <200000000>;
 374                 phys = <&emmc_phy>;
 375                 phy-names = "phy_arasan";
 376                 power-domains = <&power RK3399_PD_EMMC>;
 377                 status = "disabled";
 378         };
 379
 380         usb_host0_ehci: usb@fe380000 {
 381                 compatible = "generic-ehci";
 382                 reg = <0x0 0xfe380000 0x0 0x20000>;
 383                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 384                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 385                          <&cru SCLK_USBPHY0_480M_SRC>;
 386                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 387                 phys = <&u2phy0_host>;
 388                 phy-names = "usb";
 389                 status = "disabled";
 390         };
 391
 392         usb_host0_ohci: usb@fe3a0000 {
 393                 compatible = "generic-ohci";
 394                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 395                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 396                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 397                          <&cru SCLK_USBPHY0_480M_SRC>;
 398                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 399                 phys = <&u2phy0_host>;
 400                 phy-names = "usb";
 401                 status = "disabled";
 402         };
 403
 404         usb_host1_ehci: usb@fe3c0000 {
 405                 compatible = "generic-ehci";
 406                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 407                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 408                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 409                          <&cru SCLK_USBPHY1_480M_SRC>;
 410                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 411                 phys = <&u2phy1_host>;
 412                 phy-names = "usb";
 413                 status = "disabled";
 414         };
 415
 416         usb_host1_ohci: usb@fe3e0000 {
 417                 compatible = "generic-ohci";
 418                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 419                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 420                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 421                          <&cru SCLK_USBPHY1_480M_SRC>;
 422                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 423                 phys = <&u2phy1_host>;
 424                 phy-names = "usb";
 425                 status = "disabled";
 426         };
 427
 428         usbdrd3_0: usb@fe800000 {
 429                 compatible = "rockchip,dwc3";
 430                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 431                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 432                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 433                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 434                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 435                               "aclk_usb3", "aclk_usb3_grf";
 436                 #address-cells = <2>;
 437                 #size-cells = <2>;
 438                 ranges;
 439                 status = "disabled";
 440                 usbdrd_dwc3_0: dwc3@fe800000 {
 441                         compatible = "snps,dwc3";
 442                         reg = <0x0 0xfe800000 0x0 0x100000>;
 443                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 444                         dr_mode = "otg";
 445                         phys = <&u2phy0_otg>;
 446                         phy-names = "usb2-phy";
 447                         snps,dis_enblslpm_quirk;
 448                         snps,phyif_utmi_16_bits;
 449                         snps,dis_u2_freeclk_exists_quirk;
 450                         snps,dis_del_phy_power_chg_quirk;
 451                         snps,xhci_slow_suspend_quirk;
 452                         status = "disabled";
 453                 };
 454         };
 455
 456         usbdrd3_1: usb@fe900000 {
 457                 compatible = "rockchip,dwc3";
 458                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 459                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 460                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 461                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 462                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 463                               "aclk_usb3", "aclk_usb3_grf";
 464                 #address-cells = <2>;
 465                 #size-cells = <2>;
 466                 ranges;
 467                 status = "disabled";
 468                 usbdrd_dwc3_1: dwc3@fe900000 {
 469                         compatible = "snps,dwc3";
 470                         reg = <0x0 0xfe900000 0x0 0x100000>;
 471                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 472                         dr_mode = "otg";
 473                         phys = <&u2phy1_otg>;
 474                         phy-names = "usb2-phy";
 475                         snps,dis_enblslpm_quirk;
 476                         snps,phyif_utmi_16_bits;
 477                         snps,dis_u2_freeclk_exists_quirk;
 478                         snps,dis_del_phy_power_chg_quirk;
 479                         snps,xhci_slow_suspend_quirk;
 480                         status = "disabled";
 481                 };
 482         };
 483
 484         gic: interrupt-controller@fee00000 {
 485                 compatible = "arm,gic-v3";
 486                 #interrupt-cells = <4>;
 487                 #address-cells = <2>;
 488                 #size-cells = <2>;
 489                 ranges;
 490                 interrupt-controller;
 491
 492                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 493                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 494                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 495                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 496                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 497                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 498                 its: interrupt-controller@fee20000 {
 499                         compatible = "arm,gic-v3-its";
 500                         msi-controller;
 501                         reg = <0x0 0xfee20000 0x0 0x20000>;
 502                 };
 503
 504                 ppi-partitions {
 505                         part0: interrupt-partition-0 {
 506                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 507                         };
 508
 509                         part1: interrupt-partition-1 {
 510                                 affinity = <&cpu_b0 &cpu_b1>;
 511                         };
 512                 };
 513         };
 514
 515         saradc: saradc@ff100000 {
 516                 compatible = "rockchip,rk3399-saradc";
 517                 reg = <0x0 0xff100000 0x0 0x100>;
 518                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 519                 #io-channel-cells = <1>;
 520                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 521                 clock-names = "saradc", "apb_pclk";
 522                 status = "disabled";
 523         };
 524
 525         i2c0: i2c@ff3c0000 {
 526                 compatible = "rockchip,rk3399-i2c";
 527                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 528                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 529                 clock-names = "i2c", "pclk";
 530                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 531                 pinctrl-names = "default";
 532                 pinctrl-0 = <&i2c0_xfer>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 status = "disabled";
 536         };
 537
 538         i2c1: i2c@ff110000 {
 539                 compatible = "rockchip,rk3399-i2c";
 540                 reg = <0x0 0xff110000 0x0 0x1000>;
 541                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 542                 clock-names = "i2c", "pclk";
 543                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 544                 pinctrl-names = "default";
 545                 pinctrl-0 = <&i2c1_xfer>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 status = "disabled";
 549         };
 550
 551         i2c2: i2c@ff120000 {
 552                 compatible = "rockchip,rk3399-i2c";
 553                 reg = <0x0 0xff120000 0x0 0x1000>;
 554                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 555                 clock-names = "i2c", "pclk";
 556                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&i2c2_xfer>;
 559                 #address-cells = <1>;
 560                 #size-cells = <0>;
 561                 status = "disabled";
 562         };
 563
 564         i2c3: i2c@ff130000 {
 565                 compatible = "rockchip,rk3399-i2c";
 566                 reg = <0x0 0xff130000 0x0 0x1000>;
 567                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 568                 clock-names = "i2c", "pclk";
 569                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 570                 pinctrl-names = "default";
 571                 pinctrl-0 = <&i2c3_xfer>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 status = "disabled";
 575         };
 576
 577         i2c5: i2c@ff140000 {
 578                 compatible = "rockchip,rk3399-i2c";
 579                 reg = <0x0 0xff140000 0x0 0x1000>;
 580                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 581                 clock-names = "i2c", "pclk";
 582                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 583                 pinctrl-names = "default";
 584                 pinctrl-0 = <&i2c5_xfer>;
 585                 #address-cells = <1>;
 586                 #size-cells = <0>;
 587                 status = "disabled";
 588         };
 589
 590         i2c6: i2c@ff150000 {
 591                 compatible = "rockchip,rk3399-i2c";
 592                 reg = <0x0 0xff150000 0x0 0x1000>;
 593                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 594                 clock-names = "i2c", "pclk";
 595                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 596                 pinctrl-names = "default";
 597                 pinctrl-0 = <&i2c6_xfer>;
 598                 #address-cells = <1>;
 599                 #size-cells = <0>;
 600                 status = "disabled";
 601         };
 602
 603         i2c7: i2c@ff160000 {
 604                 compatible = "rockchip,rk3399-i2c";
 605                 reg = <0x0 0xff160000 0x0 0x1000>;
 606                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 607                 clock-names = "i2c", "pclk";
 608                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 609                 pinctrl-names = "default";
 610                 pinctrl-0 = <&i2c7_xfer>;
 611                 #address-cells = <1>;
 612                 #size-cells = <0>;
 613                 status = "disabled";
 614         };
 615
 616         uart0: serial@ff180000 {
 617                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 618                 reg = <0x0 0xff180000 0x0 0x100>;
 619                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 620                 clock-names = "baudclk", "apb_pclk";
 621                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 622                 reg-shift = <2>;
 623                 reg-io-width = <4>;
 624                 pinctrl-names = "default";
 625                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 626                 status = "disabled";
 627         };
 628
 629         uart1: serial@ff190000 {
 630                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 631                 reg = <0x0 0xff190000 0x0 0x100>;
 632                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 633                 clock-names = "baudclk", "apb_pclk";
 634                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 635                 reg-shift = <2>;
 636                 reg-io-width = <4>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&uart1_xfer>;
 639                 status = "disabled";
 640         };
 641
 642         uart2: serial@ff1a0000 {
 643                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 644                 reg = <0x0 0xff1a0000 0x0 0x100>;
 645                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 646                 clock-names = "baudclk", "apb_pclk";
 647                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 648                 reg-shift = <2>;
 649                 reg-io-width = <4>;
 650                 pinctrl-names = "default";
 651                 pinctrl-0 = <&uart2c_xfer>;
 652                 status = "disabled";
 653         };
 654
 655         uart3: serial@ff1b0000 {
 656                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 657                 reg = <0x0 0xff1b0000 0x0 0x100>;
 658                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 659                 clock-names = "baudclk", "apb_pclk";
 660                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 661                 reg-shift = <2>;
 662                 reg-io-width = <4>;
 663                 pinctrl-names = "default";
 664                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 665                 status = "disabled";
 666         };
 667
 668         spi0: spi@ff1c0000 {
 669                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 670                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 671                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 672                 clock-names = "spiclk", "apb_pclk";
 673                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 674                 pinctrl-names = "default";
 675                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 676                 #address-cells = <1>;
 677                 #size-cells = <0>;
 678                 status = "disabled";
 679         };
 680
 681         spi1: spi@ff1d0000 {
 682                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 683                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 684                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 685                 clock-names = "spiclk", "apb_pclk";
 686                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 687                 pinctrl-names = "default";
 688                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 689                 #address-cells = <1>;
 690                 #size-cells = <0>;
 691                 status = "disabled";
 692         };
 693
 694         spi2: spi@ff1e0000 {
 695                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 696                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 697                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 698                 clock-names = "spiclk", "apb_pclk";
 699                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 700                 pinctrl-names = "default";
 701                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 702                 #address-cells = <1>;
 703                 #size-cells = <0>;
 704                 status = "disabled";
 705         };
 706
 707         spi4: spi@ff1f0000 {
 708                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 709                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 710                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 711                 clock-names = "spiclk", "apb_pclk";
 712                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 713                 pinctrl-names = "default";
 714                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 715                 #address-cells = <1>;
 716                 #size-cells = <0>;
 717                 status = "disabled";
 718         };
 719
 720         spi5: spi@ff200000 {
 721                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 722                 reg = <0x0 0xff200000 0x0 0x1000>;
 723                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 724                 clock-names = "spiclk", "apb_pclk";
 725                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 726                 pinctrl-names = "default";
 727                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 728                 #address-cells = <1>;
 729                 #size-cells = <0>;
 730                 status = "disabled";
 731         };
 732
 733         thermal-zones {
 734                 soc_thermal: soc-thermal {
 735                         polling-delay-passive = <20>; /* milliseconds */
 736                         polling-delay = <1000>; /* milliseconds */
 737                         sustainable-power = <1000>; /* milliwatts */
 738
 739                         thermal-sensors = <&tsadc 0>;
 740
 741                         trips {
 742                                 threshold: trip-point@0 {
 743                                         temperature = <70000>; /* millicelsius */
 744                                         hysteresis = <2000>; /* millicelsius */
 745                                         type = "passive";
 746                                 };
 747                                 target: trip-point@1 {
 748                                         temperature = <85000>; /* millicelsius */
 749                                         hysteresis = <2000>; /* millicelsius */
 750                                         type = "passive";
 751                                 };
 752                                 soc_crit: soc-crit {
 753                                         temperature = <95000>; /* millicelsius */
 754                                         hysteresis = <2000>; /* millicelsius */
 755                                         type = "critical";
 756                                 };
 757                         };
 758
 759                         cooling-maps {
 760                                 map0 {
 761                                         trip = <&target>;
 762                                         cooling-device =
 763                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 764                                         contribution = <4096>;
 765                                 };
 766                                 map1 {
 767                                         trip = <&target>;
 768                                         cooling-device =
 769                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 770                                         contribution = <1024>;
 771                                 };
 772                                 map2 {
 773                                         trip = <&target>;
 774                                         cooling-device =
 775                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 776                                         contribution = <4096>;
 777                                 };
 778                         };
 779                 };
 780
 781                 gpu_thermal: gpu-thermal {
 782                         polling-delay-passive = <100>; /* milliseconds */
 783                         polling-delay = <1000>; /* milliseconds */
 784
 785                         thermal-sensors = <&tsadc 1>;
 786                 };
 787         };
 788
 789         tsadc: tsadc@ff260000 {
 790                 compatible = "rockchip,rk3399-tsadc";
 791                 reg = <0x0 0xff260000 0x0 0x100>;
 792                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 793                 rockchip,grf = <&grf>;
 794                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 795                 clock-names = "tsadc", "apb_pclk";
 796                 assigned-clocks = <&cru SCLK_TSADC>;
 797                 assigned-clock-rates = <750000>;
 798                 resets = <&cru SRST_TSADC>;
 799                 reset-names = "tsadc-apb";
 800                 pinctrl-names = "init", "default", "sleep";
 801                 pinctrl-0 = <&otp_gpio>;
 802                 pinctrl-1 = <&otp_out>;
 803                 pinctrl-2 = <&otp_gpio>;
 804                 #thermal-sensor-cells = <1>;
 805                 rockchip,hw-tshut-temp = <95000>;
 806                 status = "disabled";
 807         };
 808
 809         qos_emmc: qos@ffa58000 {
 810                 compatible = "syscon";
 811                 reg = <0x0 0xffa58000 0x0 0x20>;
 812         };
 813
 814         qos_gmac: qos@ffa5c000 {
 815                 compatible = "syscon";
 816                 reg = <0x0 0xffa5c000 0x0 0x20>;
 817         };
 818
 819         qos_pcie: qos@ffa60080 {
 820                 compatible = "syscon";
 821                 reg = <0x0 0xffa60080 0x0 0x20>;
 822         };
 823
 824         qos_usb_host0: qos@ffa60100 {
 825                 compatible = "syscon";
 826                 reg = <0x0 0xffa60100 0x0 0x20>;
 827         };
 828
 829         qos_usb_host1: qos@ffa60180 {
 830                 compatible = "syscon";
 831                 reg = <0x0 0xffa60180 0x0 0x20>;
 832         };
 833
 834         qos_usb_otg0: qos@ffa70000 {
 835                 compatible = "syscon";
 836                 reg = <0x0 0xffa70000 0x0 0x20>;
 837         };
 838
 839         qos_usb_otg1: qos@ffa70080 {
 840                 compatible = "syscon";
 841                 reg = <0x0 0xffa70080 0x0 0x20>;
 842         };
 843
 844         qos_sd: qos@ffa74000 {
 845                 compatible = "syscon";
 846                 reg = <0x0 0xffa74000 0x0 0x20>;
 847         };
 848
 849         qos_sdioaudio: qos@ffa76000 {
 850                 compatible = "syscon";
 851                 reg = <0x0 0xffa76000 0x0 0x20>;
 852         };
 853
 854         qos_hdcp: qos@ffa90000 {
 855                 compatible = "syscon";
 856                 reg = <0x0 0xffa90000 0x0 0x20>;
 857         };
 858
 859         qos_iep: qos@ffa98000 {
 860                 compatible = "syscon";
 861                 reg = <0x0 0xffa98000 0x0 0x20>;
 862         };
 863
 864         qos_isp0_m0: qos@ffaa0000 {
 865                 compatible = "syscon";
 866                 reg = <0x0 0xffaa0000 0x0 0x20>;
 867         };
 868
 869         qos_isp0_m1: qos@ffaa0080 {
 870                 compatible = "syscon";
 871                 reg = <0x0 0xffaa0080 0x0 0x20>;
 872         };
 873
 874         qos_isp1_m0: qos@ffaa8000 {
 875                 compatible = "syscon";
 876                 reg = <0x0 0xffaa8000 0x0 0x20>;
 877         };
 878
 879         qos_isp1_m1: qos@ffaa8080 {
 880                 compatible = "syscon";
 881                 reg = <0x0 0xffaa8080 0x0 0x20>;
 882         };
 883
 884         qos_rga_r: qos@ffab0000 {
 885                 compatible = "syscon";
 886                 reg = <0x0 0xffab0000 0x0 0x20>;
 887         };
 888
 889         qos_rga_w: qos@ffab0080 {
 890                 compatible = "syscon";
 891                 reg = <0x0 0xffab0080 0x0 0x20>;
 892         };
 893
 894         qos_video_m0: qos@ffab8000 {
 895                 compatible = "syscon";
 896                 reg = <0x0 0xffab8000 0x0 0x20>;
 897         };
 898
 899         qos_video_m1_r: qos@ffac0000 {
 900                 compatible = "syscon";
 901                 reg = <0x0 0xffac0000 0x0 0x20>;
 902         };
 903
 904         qos_video_m1_w: qos@ffac0080 {
 905                 compatible = "syscon";
 906                 reg = <0x0 0xffac0080 0x0 0x20>;
 907         };
 908
 909         qos_vop_big_r: qos@ffac8000 {
 910                 compatible = "syscon";
 911                 reg = <0x0 0xffac8000 0x0 0x20>;
 912         };
 913
 914         qos_vop_big_w: qos@ffac8080 {
 915                 compatible = "syscon";
 916                 reg = <0x0 0xffac8080 0x0 0x20>;
 917         };
 918
 919         qos_vop_little: qos@ffad0000 {
 920                 compatible = "syscon";
 921                 reg = <0x0 0xffad0000 0x0 0x20>;
 922         };
 923
 924         qos_perihp: qos@ffad8080 {
 925                 compatible = "syscon";
 926                 reg = <0x0 0xffad8080 0x0 0x20>;
 927         };
 928
 929         qos_gpu: qos@ffae0000 {
 930                 compatible = "syscon";
 931                 reg = <0x0 0xffae0000 0x0 0x20>;
 932         };
 933
 934         pmu: power-management@ff310000 {
 935                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 936                 reg = <0x0 0xff310000 0x0 0x1000>;
 937
 938                 /*
 939                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 940                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 941                  * Some of the power domains are grouped together for every
 942                  * voltage domain.
 943                  * The detail contents as below.
 944                  */
 945                 power: power-controller {
 946                         compatible = "rockchip,rk3399-power-controller";
 947                         #power-domain-cells = <1>;
 948                         #address-cells = <1>;
 949                         #size-cells = <0>;
 950
 951                         /* These power domains are grouped by VD_CENTER */
 952                         pd_iep@RK3399_PD_IEP {
 953                                 reg = <RK3399_PD_IEP>;
 954                                 clocks = <&cru ACLK_IEP>,
 955                                          <&cru HCLK_IEP>;
 956                                 pm_qos = <&qos_iep>;
 957                         };
 958                         pd_rga@RK3399_PD_RGA {
 959                                 reg = <RK3399_PD_RGA>;
 960                                 clocks = <&cru ACLK_RGA>,
 961                                          <&cru HCLK_RGA>;
 962                                 pm_qos = <&qos_rga_r>,
 963                                          <&qos_rga_w>;
 964                         };
 965                         pd_vcodec@RK3399_PD_VCODEC {
 966                                 reg = <RK3399_PD_VCODEC>;
 967                                 clocks = <&cru ACLK_VCODEC>,
 968                                          <&cru HCLK_VCODEC>;
 969                                 pm_qos = <&qos_video_m0>;
 970                         };
 971                         pd_vdu@RK3399_PD_VDU {
 972                                 reg = <RK3399_PD_VDU>;
 973                                 clocks = <&cru ACLK_VDU>,
 974                                          <&cru HCLK_VDU>;
 975                                 pm_qos = <&qos_video_m1_r>,
 976                                          <&qos_video_m1_w>;
 977                         };
 978
 979                         /* These power domains are grouped by VD_GPU */
 980                         pd_gpu@RK3399_PD_GPU {
 981                                 reg = <RK3399_PD_GPU>;
 982                                 clocks = <&cru ACLK_GPU>;
 983                                 pm_qos = <&qos_gpu>;
 984                         };
 985
 986                         /* These power domains are grouped by VD_LOGIC */
 987                         pd_emmc@RK3399_PD_EMMC {
 988                                 reg = <RK3399_PD_EMMC>;
 989                                 clocks = <&cru ACLK_EMMC>;
 990                                 pm_qos = <&qos_emmc>;
 991                         };
 992                         pd_gmac@RK3399_PD_GMAC {
 993                                 reg = <RK3399_PD_GMAC>;
 994                                 clocks = <&cru ACLK_GMAC>;
 995                                 pm_qos = <&qos_gmac>;
 996                         };
 997                         pd_perihp@RK3399_PD_PERIHP {
 998                                 reg = <RK3399_PD_PERIHP>;
 999                                 clocks = <&cru ACLK_PERIHP>;
1000                                 pm_qos = <&qos_perihp>,
1001                                          <&qos_pcie>,
1002                                          <&qos_usb_host0>,
1003                                          <&qos_usb_host1>;
1004                         };
1005                         pd_sd@RK3399_PD_SD {
1006                                 reg = <RK3399_PD_SD>;
1007                                 clocks = <&cru HCLK_SDMMC>;
1008                                 pm_qos = <&qos_sd>;
1009                         };
1010                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1011                                 reg = <RK3399_PD_SDIOAUDIO>;
1012                                 clocks = <&cru HCLK_SDIO>;
1013                                 pm_qos = <&qos_sdioaudio>;
1014                         };
1015                         pd_usb3@RK3399_PD_USB3 {
1016                                 reg = <RK3399_PD_USB3>;
1017                                 clocks = <&cru ACLK_USB3>;
1018                                 pm_qos = <&qos_usb_otg0>,
1019                                          <&qos_usb_otg1>;
1020                         };
1021                         pd_vio@RK3399_PD_VIO {
1022                                 reg = <RK3399_PD_VIO>;
1023                                 #address-cells = <1>;
1024                                 #size-cells = <0>;
1025
1026                                 pd_hdcp@RK3399_PD_HDCP {
1027                                         reg = <RK3399_PD_HDCP>;
1028                                         clocks = <&cru ACLK_HDCP>,
1029                                                  <&cru HCLK_HDCP>,
1030                                                  <&cru PCLK_HDCP>;
1031                                         pm_qos = <&qos_hdcp>;
1032                                 };
1033                                 pd_isp0@RK3399_PD_ISP0 {
1034                                         reg = <RK3399_PD_ISP0>;
1035                                         clocks = <&cru ACLK_ISP0>,
1036                                                  <&cru HCLK_ISP0>;
1037                                         pm_qos = <&qos_isp0_m0>,
1038                                                  <&qos_isp0_m1>;
1039                                 };
1040                                 pd_isp1@RK3399_PD_ISP1 {
1041                                         reg = <RK3399_PD_ISP1>;
1042                                         clocks = <&cru ACLK_ISP1>,
1043                                                  <&cru HCLK_ISP1>;
1044                                         pm_qos = <&qos_isp1_m0>,
1045                                                  <&qos_isp1_m1>;
1046                                 };
1047                                 pd_vo@RK3399_PD_VO {
1048                                         reg = <RK3399_PD_VO>;
1049                                         #address-cells = <1>;
1050                                         #size-cells = <0>;
1051
1052                                         pd_vopb@RK3399_PD_VOPB {
1053                                                 reg = <RK3399_PD_VOPB>;
1054                                                 clocks = <&cru ACLK_VOP0>,
1055                                                          <&cru HCLK_VOP0>;
1056                                                 pm_qos = <&qos_vop_big_r>,
1057                                                          <&qos_vop_big_w>;
1058                                         };
1059                                         pd_vopl@RK3399_PD_VOPL {
1060                                                 reg = <RK3399_PD_VOPL>;
1061                                                 clocks = <&cru ACLK_VOP1>,
1062                                                          <&cru HCLK_VOP1>;
1063                                                 pm_qos = <&qos_vop_little>;
1064                                         };
1065                                 };
1066                         };
1067                 };
1068         };
1069
1070         pmugrf: syscon@ff320000 {
1071                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1072                 reg = <0x0 0xff320000 0x0 0x1000>;
1073
1074                 reboot-mode {
1075                         compatible = "syscon-reboot-mode";
1076                         offset = <0x300>;
1077                         mode-bootloader = <BOOT_LOADER>;
1078                         mode-charge = <BOOT_CHARGING>;
1079                         mode-fastboot = <BOOT_FASTBOOT>;
1080                         mode-loader = <BOOT_LOADER>;
1081                         mode-normal = <BOOT_NORMAL>;
1082                         mode-recovery = <BOOT_RECOVERY>;
1083                 };
1084         };
1085
1086         spi3: spi@ff350000 {
1087                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1088                 reg = <0x0 0xff350000 0x0 0x1000>;
1089                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1090                 clock-names = "spiclk", "apb_pclk";
1091                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1092                 pinctrl-names = "default";
1093                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1094                 #address-cells = <1>;
1095                 #size-cells = <0>;
1096                 status = "disabled";
1097         };
1098
1099         uart4: serial@ff370000 {
1100                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1101                 reg = <0x0 0xff370000 0x0 0x100>;
1102                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1103                 clock-names = "baudclk", "apb_pclk";
1104                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1105                 reg-shift = <2>;
1106                 reg-io-width = <4>;
1107                 pinctrl-names = "default";
1108                 pinctrl-0 = <&uart4_xfer>;
1109                 status = "disabled";
1110         };
1111
1112         i2c4: i2c@ff3d0000 {
1113                 compatible = "rockchip,rk3399-i2c";
1114                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1115                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1116                 clock-names = "i2c", "pclk";
1117                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1118                 pinctrl-names = "default";
1119                 pinctrl-0 = <&i2c4_xfer>;
1120                 #address-cells = <1>;
1121                 #size-cells = <0>;
1122                 status = "disabled";
1123         };
1124
1125         i2c8: i2c@ff3e0000 {
1126                 compatible = "rockchip,rk3399-i2c";
1127                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1128                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1129                 clock-names = "i2c", "pclk";
1130                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1131                 pinctrl-names = "default";
1132                 pinctrl-0 = <&i2c8_xfer>;
1133                 #address-cells = <1>;
1134                 #size-cells = <0>;
1135                 status = "disabled";
1136         };
1137
1138         pcie0: pcie@f8000000 {
1139                 compatible = "rockchip,rk3399-pcie";
1140                 #address-cells = <3>;
1141                 #size-cells = <2>;
1142                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1143                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1144                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1145                               "hclk_pcie", "clk_pciephy_ref";
1146                 bus-range = <0x0 0x1>;
1147                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1148                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1149                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1150                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1151                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1152                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1153                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1154                       < 0x0 0xfd000000 0x0 0x1000000 >;
1155                 reg-name = "axi-base", "apb-base";
1156                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1157                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1158                          <&cru SRST_PCIE_PIPE>;
1159                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1160                               "mgmt-sticky-rst", "pipe-rst";
1161                 rockchip,grf = <&grf>;
1162                 pcie-conf = <0xe220>;
1163                 pcie-status = <0xe2a4>;
1164                 pcie-laneoff = <0xe214>;
1165                 power-domains = <&power RK3399_PD_PERIHP>;
1166                 msi-parent = <&its>;
1167                 #interrupt-cells = <1>;
1168                 interrupt-map-mask = <0 0 0 7>;
1169                 interrupt-map = <0 0 0 1 &pcie0 1>,
1170                                 <0 0 0 2 &pcie0 2>,
1171                                 <0 0 0 3 &pcie0 3>,
1172                                 <0 0 0 4 &pcie0 4>;
1173                 status = "disabled";
1174                 pcie_intc: interrupt-controller {
1175                         interrupt-controller;
1176                         #address-cells = <0>;
1177                         #interrupt-cells = <1>;
1178                 };
1179         };
1180
1181         pwm0: pwm@ff420000 {
1182                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1183                 reg = <0x0 0xff420000 0x0 0x10>;
1184                 #pwm-cells = <3>;
1185                 pinctrl-names = "default";
1186                 pinctrl-0 = <&pwm0_pin>;
1187                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1188                 clock-names = "pwm";
1189                 status = "disabled";
1190         };
1191
1192         pwm1: pwm@ff420010 {
1193                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1194                 reg = <0x0 0xff420010 0x0 0x10>;
1195                 #pwm-cells = <3>;
1196                 pinctrl-names = "default";
1197                 pinctrl-0 = <&pwm1_pin>;
1198                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1199                 clock-names = "pwm";
1200                 status = "disabled";
1201         };
1202
1203         pwm2: pwm@ff420020 {
1204                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1205                 reg = <0x0 0xff420020 0x0 0x10>;
1206                 #pwm-cells = <3>;
1207                 pinctrl-names = "default";
1208                 pinctrl-0 = <&pwm2_pin>;
1209                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1210                 clock-names = "pwm";
1211                 status = "disabled";
1212         };
1213
1214         pwm3: pwm@ff420030 {
1215                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1216                 reg = <0x0 0xff420030 0x0 0x10>;
1217                 #pwm-cells = <3>;
1218                 pinctrl-names = "default";
1219                 pinctrl-0 = <&pwm3a_pin>;
1220                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1221                 clock-names = "pwm";
1222                 status = "disabled";
1223         };
1224
1225         rga: rga@ff680000 {
1226                 compatible = "rockchip,rk3399-rga";
1227                 reg = <0x0 0xff680000 0x0 0x10000>;
1228                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1229                 interrupt-names = "rga";
1230                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1231                 clock-names = "aclk", "hclk", "sclk";
1232                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1233                 reset-names = "core", "axi", "ahb";
1234                 power-domains = <&power RK3399_PD_RGA>;
1235                 status = "disabled";
1236         };
1237
1238         pmucru: pmu-clock-controller@ff750000 {
1239                 compatible = "rockchip,rk3399-pmucru";
1240                 reg = <0x0 0xff750000 0x0 0x1000>;
1241                 #clock-cells = <1>;
1242                 #reset-cells = <1>;
1243                 assigned-clocks = <&pmucru PLL_PPLL>;
1244                 assigned-clock-rates = <676000000>;
1245         };
1246
1247         cru: clock-controller@ff760000 {
1248                 compatible = "rockchip,rk3399-cru";
1249                 reg = <0x0 0xff760000 0x0 0x1000>;
1250                 #clock-cells = <1>;
1251                 #reset-cells = <1>;
1252                 assigned-clocks =
1253                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1254                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1255                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1256                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1257                         <&cru PLL_NPLL>,
1258                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1259                         <&cru PCLK_PERIHP>,
1260                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1261                         <&cru PCLK_PERILP0>,
1262                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1263                 assigned-clock-rates =
1264                          <400000000>,  <200000000>,
1265                          <400000000>,  <200000000>,
1266                          <816000000>, <816000000>,
1267                          <594000000>,  <800000000>,
1268                         <1000000000>,
1269                          <150000000>,   <75000000>,
1270                           <37500000>,
1271                          <100000000>,  <100000000>,
1272                           <50000000>,
1273                          <100000000>,   <50000000>;
1274         };
1275
1276         grf: syscon@ff770000 {
1277                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1278                 reg = <0x0 0xff770000 0x0 0x10000>;
1279                 #address-cells = <1>;
1280                 #size-cells = <1>;
1281
1282                 u2phy0: usb2-phy@e450 {
1283                         compatible = "rockchip,rk3399-usb2phy";
1284                         reg = <0xe450 0x10>;
1285                         clocks = <&cru SCLK_USB2PHY0_REF>;
1286                         clock-names = "phyclk";
1287                         #clock-cells = <0>;
1288                         clock-output-names = "clk_usbphy0_480m";
1289                         status = "disabled";
1290
1291                         u2phy0_otg: otg-port {
1292                                 #phy-cells = <0>;
1293                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1294                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1295                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1296                                 interrupt-names = "otg-bvalid", "otg-id",
1297                                                   "linestate";
1298                                 status = "disabled";
1299                         };
1300
1301                         u2phy0_host: host-port {
1302                                 #phy-cells = <0>;
1303                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1304                                 interrupt-names = "linestate";
1305                                 status = "disabled";
1306                         };
1307                 };
1308
1309                 u2phy1: usb2-phy@e460 {
1310                         compatible = "rockchip,rk3399-usb2phy";
1311                         reg = <0xe460 0x10>;
1312                         clocks = <&cru SCLK_USB2PHY1_REF>;
1313                         clock-names = "phyclk";
1314                         #clock-cells = <0>;
1315                         clock-output-names = "clk_usbphy1_480m";
1316                         status = "disabled";
1317
1318                         u2phy1_otg: otg-port {
1319                                 #phy-cells = <0>;
1320                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1321                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1322                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1323                                 interrupt-names = "otg-bvalid", "otg-id",
1324                                                   "linestate";
1325                                 status = "disabled";
1326                         };
1327
1328                         u2phy1_host: host-port {
1329                                 #phy-cells = <0>;
1330                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1331                                 interrupt-names = "linestate";
1332                                 status = "disabled";
1333                         };
1334                 };
1335         };
1336
1337         tcphy0: phy@ff7c0000 {
1338                 compatible = "rockchip,rk3399-typec-phy";
1339                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1340                 rockchip,grf = <&grf>;
1341                 #phy-cells = <0>;
1342                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1343                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1344                 clock-names = "tcpdcore", "tcpdphy-ref";
1345                 resets = <&cru SRST_UPHY0>,
1346                          <&cru SRST_UPHY0_PIPE_L00>,
1347                          <&cru SRST_P_UPHY0_TCPHY>;
1348                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1349                 rockchip,typec-conn-dir = <0xe580 0 16>;
1350                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1351                 rockchip,external-psm = <0xe588 14 30>;
1352                 rockchip,pipe-status = <0xe5c0 0 0>;
1353                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1354                 status = "disabled";
1355         };
1356
1357         tcphy1: phy@ff800000 {
1358                 compatible = "rockchip,rk3399-typec-phy";
1359                 reg = <0x0 0xff800000 0x0 0x40000>;
1360                 rockchip,grf = <&grf>;
1361                 #phy-cells = <0>;
1362                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1363                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1364                 clock-names = "tcpdcore", "tcpdphy-ref";
1365                 resets = <&cru SRST_UPHY1>,
1366                          <&cru SRST_UPHY1_PIPE_L00>,
1367                          <&cru SRST_P_UPHY1_TCPHY>;
1368                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1369                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1370                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1371                 rockchip,external-psm = <0xe594 14 30>;
1372                 rockchip,pipe-status = <0xe5c0 16 16>;
1373                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1374                 status = "disabled";
1375         };
1376
1377         watchdog@ff840000 {
1378                 compatible = "snps,dw-wdt";
1379                 reg = <0x0 0xff840000 0x0 0x100>;
1380                 clocks = <&cru PCLK_WDT>;
1381                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1382         };
1383
1384         rktimer: rktimer@ff850000 {
1385                 compatible = "rockchip,rk3399-timer";
1386                 reg = <0x0 0xff850000 0x0 0x1000>;
1387                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1388                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1389                 clock-names = "pclk", "timer";
1390         };
1391
1392         spdif: spdif@ff870000 {
1393                 compatible = "rockchip,rk3399-spdif";
1394                 reg = <0x0 0xff870000 0x0 0x1000>;
1395                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1396                 dmas = <&dmac_bus 7>;
1397                 dma-names = "tx";
1398                 clock-names = "mclk", "hclk";
1399                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1400                 pinctrl-names = "default";
1401                 pinctrl-0 = <&spdif_bus>;
1402                 status = "disabled";
1403         };
1404
1405         i2s0: i2s@ff880000 {
1406                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1407                 reg = <0x0 0xff880000 0x0 0x1000>;
1408                 rockchip,grf = <&grf>;
1409                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1410                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1411                 dma-names = "tx", "rx";
1412                 clock-names = "i2s_clk", "i2s_hclk";
1413                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1414                 pinctrl-names = "default";
1415                 pinctrl-0 = <&i2s0_8ch_bus>;
1416                 status = "disabled";
1417         };
1418
1419         i2s1: i2s@ff890000 {
1420                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1421                 reg = <0x0 0xff890000 0x0 0x1000>;
1422                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1423                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1424                 dma-names = "tx", "rx";
1425                 clock-names = "i2s_clk", "i2s_hclk";
1426                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1427                 pinctrl-names = "default";
1428                 pinctrl-0 = <&i2s1_2ch_bus>;
1429                 status = "disabled";
1430         };
1431
1432         i2s2: i2s@ff8a0000 {
1433                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1434                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1435                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1436                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1437                 dma-names = "tx", "rx";
1438                 clock-names = "i2s_clk", "i2s_hclk";
1439                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1440                 status = "disabled";
1441         };
1442
1443         gpu: gpu@ff9a0000 {
1444                 compatible = "arm,malit860",
1445                              "arm,malit86x",
1446                              "arm,malit8xx",
1447                              "arm,mali-midgard";
1448
1449                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1450
1451                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1452                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1453                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1454                 interrupt-names = "GPU", "JOB", "MMU";
1455
1456                 clocks = <&cru ACLK_GPU>;
1457                 clock-names = "clk_mali";
1458                 #cooling-cells = <2>; /* min followed by max */
1459                 operating-points-v2 = <&gpu_opp_table>;
1460                 power-domains = <&power RK3399_PD_GPU>;
1461                 power-off-delay-ms = <200>;
1462                 status = "disabled";
1463
1464                 gpu_power_model: power_model {
1465                         compatible = "arm,mali-simple-power-model";
1466                         voltage = <900>;
1467                         frequency = <500>;
1468                         static-power = <300>;
1469                         dynamic-power = <396>;
1470                         ts = <32000 4700 (-80) 2>;
1471                         thermal-zone = "gpu-thermal";
1472                 };
1473         };
1474
1475         gpu_opp_table: gpu_opp_table {
1476                 compatible = "operating-points-v2";
1477                 opp-shared;
1478
1479                 opp@200000000 {
1480                         opp-hz = /bits/ 64 <200000000>;
1481                         opp-microvolt = <900000>;
1482                 };
1483                 opp@300000000 {
1484                         opp-hz = /bits/ 64 <300000000>;
1485                         opp-microvolt = <900000>;
1486                 };
1487                 opp@400000000 {
1488                         opp-hz = /bits/ 64 <400000000>;
1489                         opp-microvolt = <900000>;
1490                 };
1491
1492         };
1493
1494         vopl: vop@ff8f0000 {
1495                 compatible = "rockchip,rk3399-vop-lit";
1496                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1497                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1498                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1499                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1500                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1501                 reset-names = "axi", "ahb", "dclk";
1502                 power-domains = <&power RK3399_PD_VOPL>;
1503                 iommus = <&vopl_mmu>;
1504                 status = "disabled";
1505
1506                 vopl_out: port {
1507                         #address-cells = <1>;
1508                         #size-cells = <0>;
1509
1510                         vopl_out_mipi: endpoint@0 {
1511                                 reg = <0>;
1512                                 remote-endpoint = <&mipi_in_vopl>;
1513                         };
1514
1515                         vopl_out_edp: endpoint@1 {
1516                                 reg = <1>;
1517                                 remote-endpoint = <&edp_in_vopl>;
1518                         };
1519
1520                         vopl_out_hdmi: endpoint@2 {
1521                                 reg = <2>;
1522                                 remote-endpoint = <&hdmi_in_vopl>;
1523                         };
1524                 };
1525         };
1526
1527         vopl_mmu: iommu@ff8f3f00 {
1528                 compatible = "rockchip,iommu";
1529                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1530                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1531                 interrupt-names = "vopl_mmu";
1532                 #iommu-cells = <0>;
1533                 status = "disabled";
1534         };
1535
1536         vopb: vop@ff900000 {
1537                 compatible = "rockchip,rk3399-vop-big";
1538                 reg = <0x0 0xff900000 0x0 0x3efc>;
1539                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1540                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1541                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1542                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1543                 reset-names = "axi", "ahb", "dclk";
1544                 power-domains = <&power RK3399_PD_VOPB>;
1545                 iommus = <&vopb_mmu>;
1546                 status = "disabled";
1547
1548                 vopb_out: port {
1549                         #address-cells = <1>;
1550                         #size-cells = <0>;
1551
1552                         vopb_out_edp: endpoint@0 {
1553                                 reg = <0>;
1554                                 remote-endpoint = <&edp_in_vopb>;
1555                         };
1556
1557                         vopb_out_mipi: endpoint@1 {
1558                                 reg = <1>;
1559                                 remote-endpoint = <&mipi_in_vopb>;
1560                         };
1561
1562                         vopb_out_hdmi: endpoint@2 {
1563                                 reg = <2>;
1564                                 remote-endpoint = <&hdmi_in_vopb>;
1565                         };
1566                 };
1567         };
1568
1569         vopb_mmu: iommu@ff903f00 {
1570                 compatible = "rockchip,iommu";
1571                 reg = <0x0 0xff903f00 0x0 0x100>;
1572                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1573                 interrupt-names = "vopb_mmu";
1574                 #iommu-cells = <0>;
1575                 status = "disabled";
1576         };
1577
1578         hdmi: hdmi@ff940000 {
1579                 compatible = "rockchip,rk3399-dw-hdmi";
1580                 reg = <0x0 0xff940000 0x0 0x20000>;
1581                 reg-io-width = <4>;
1582                 rockchip,grf = <&grf>;
1583                 power-domains = <&power RK3399_PD_HDCP>;
1584                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1585                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1586                 clock-names = "iahb", "isfr", "vpll", "grf";
1587                 status = "disabled";
1588
1589                 ports {
1590                         hdmi_in: port {
1591                                 #address-cells = <1>;
1592                                 #size-cells = <0>;
1593                                 hdmi_in_vopb: endpoint@0 {
1594                                         reg = <0>;
1595                                         remote-endpoint = <&vopb_out_hdmi>;
1596                                 };
1597                                 hdmi_in_vopl: endpoint@1 {
1598                                         reg = <1>;
1599                                         remote-endpoint = <&vopl_out_hdmi>;
1600                                 };
1601                         };
1602                 };
1603         };
1604
1605         mipi_dsi: mipi@ff960000 {
1606                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1607                 reg = <0x0 0xff960000 0x0 0x8000>;
1608                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1609                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1610                          <&cru SCLK_DPHY_TX0_CFG>;
1611                 clock-names = "ref", "pclk", "phy_cfg";
1612                 power-domains = <&power RK3399_PD_VIO>;
1613                 rockchip,grf = <&grf>;
1614                 #address-cells = <1>;
1615                 #size-cells = <0>;
1616                 status = "disabled";
1617
1618                 ports {
1619                         #address-cells = <1>;
1620                         #size-cells = <0>;
1621                         reg = <1>;
1622
1623                         mipi_in: port {
1624                                 #address-cells = <1>;
1625                                 #size-cells = <0>;
1626
1627                                 mipi_in_vopb: endpoint@0 {
1628                                         reg = <0>;
1629                                         remote-endpoint = <&vopb_out_mipi>;
1630                                 };
1631                                 mipi_in_vopl: endpoint@1 {
1632                                         reg = <1>;
1633                                         remote-endpoint = <&vopl_out_mipi>;
1634                                 };
1635                         };
1636                 };
1637         };
1638
1639         edp: edp@ff970000 {
1640                 compatible = "rockchip,rk3399-edp";
1641                 reg = <0x0 0xff970000 0x0 0x8000>;
1642                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1643                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1644                 clock-names = "dp", "pclk";
1645                 resets = <&cru SRST_P_EDP_CTRL>;
1646                 reset-names = "dp";
1647                 rockchip,grf = <&grf>;
1648                 status = "disabled";
1649                 pinctrl-names = "default";
1650                 pinctrl-0 = <&edp_hpd>;
1651
1652                 ports {
1653                         #address-cells = <1>;
1654                         #size-cells = <0>;
1655
1656                         edp_in: port@0 {
1657                                 reg = <0>;
1658                                 #address-cells = <1>;
1659                                 #size-cells = <0>;
1660
1661                                 edp_in_vopb: endpoint@0 {
1662                                         reg = <0>;
1663                                         remote-endpoint = <&vopb_out_edp>;
1664                                 };
1665
1666                                 edp_in_vopl: endpoint@1 {
1667                                         reg = <1>;
1668                                         remote-endpoint = <&vopl_out_edp>;
1669                                 };
1670                         };
1671                 };
1672         };
1673
1674         display_subsystem: display-subsystem {
1675                 compatible = "rockchip,display-subsystem";
1676                 ports = <&vopl_out>, <&vopb_out>;
1677                 status = "disabled";
1678         };
1679
1680         pinctrl: pinctrl {
1681                 compatible = "rockchip,rk3399-pinctrl";
1682                 rockchip,grf = <&grf>;
1683                 rockchip,pmu = <&pmugrf>;
1684                 #address-cells = <0x2>;
1685                 #size-cells = <0x2>;
1686                 ranges;
1687
1688                 gpio0: gpio0@ff720000 {
1689                         compatible = "rockchip,gpio-bank";
1690                         reg = <0x0 0xff720000 0x0 0x100>;
1691                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1692                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1693
1694                         gpio-controller;
1695                         #gpio-cells = <0x2>;
1696
1697                         interrupt-controller;
1698                         #interrupt-cells = <0x2>;
1699                 };
1700
1701                 gpio1: gpio1@ff730000 {
1702                         compatible = "rockchip,gpio-bank";
1703                         reg = <0x0 0xff730000 0x0 0x100>;
1704                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1705                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1706
1707                         gpio-controller;
1708                         #gpio-cells = <0x2>;
1709
1710                         interrupt-controller;
1711                         #interrupt-cells = <0x2>;
1712                 };
1713
1714                 gpio2: gpio2@ff780000 {
1715                         compatible = "rockchip,gpio-bank";
1716                         reg = <0x0 0xff780000 0x0 0x100>;
1717                         clocks = <&cru PCLK_GPIO2>;
1718                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1719
1720                         gpio-controller;
1721                         #gpio-cells = <0x2>;
1722
1723                         interrupt-controller;
1724                         #interrupt-cells = <0x2>;
1725                 };
1726
1727                 gpio3: gpio3@ff788000 {
1728                         compatible = "rockchip,gpio-bank";
1729                         reg = <0x0 0xff788000 0x0 0x100>;
1730                         clocks = <&cru PCLK_GPIO3>;
1731                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1732
1733                         gpio-controller;
1734                         #gpio-cells = <0x2>;
1735
1736                         interrupt-controller;
1737                         #interrupt-cells = <0x2>;
1738                 };
1739
1740                 gpio4: gpio4@ff790000 {
1741                         compatible = "rockchip,gpio-bank";
1742                         reg = <0x0 0xff790000 0x0 0x100>;
1743                         clocks = <&cru PCLK_GPIO4>;
1744                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1745
1746                         gpio-controller;
1747                         #gpio-cells = <0x2>;
1748
1749                         interrupt-controller;
1750                         #interrupt-cells = <0x2>;
1751                 };
1752
1753                 pcfg_pull_up: pcfg-pull-up {
1754                         bias-pull-up;
1755                 };
1756
1757                 pcfg_pull_down: pcfg-pull-down {
1758                         bias-pull-down;
1759                 };
1760
1761                 pcfg_pull_none: pcfg-pull-none {
1762                         bias-disable;
1763                 };
1764
1765                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1766                         bias-pull-up;
1767                         drive-strength = <20>;
1768                 };
1769
1770                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1771                         bias-disable;
1772                         drive-strength = <20>;
1773                 };
1774
1775                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1776                         bias-disable;
1777                         drive-strength = <18>;
1778                 };
1779
1780                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1781                         bias-disable;
1782                         drive-strength = <12>;
1783                 };
1784
1785                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1786                         bias-pull-up;
1787                         drive-strength = <8>;
1788                 };
1789
1790                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1791                         bias-pull-down;
1792                         drive-strength = <4>;
1793                 };
1794
1795                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1796                         bias-pull-up;
1797                         drive-strength = <2>;
1798                 };
1799
1800                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1801                         bias-pull-down;
1802                         drive-strength = <12>;
1803                 };
1804
1805                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1806                         bias-disable;
1807                         drive-strength = <13>;
1808                 };
1809
1810                 emmc {
1811                         emmc_pwr: emmc-pwr {
1812                                 rockchip,pins =
1813                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1814                         };
1815                 };
1816
1817                 gmac {
1818                         rgmii_pins: rgmii-pins {
1819                                 rockchip,pins =
1820                                         /* mac_txclk */
1821                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1822                                         /* mac_rxclk */
1823                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1824                                         /* mac_mdio */
1825                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1826                                         /* mac_txen */
1827                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1828                                         /* mac_clk */
1829                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1830                                         /* mac_rxdv */
1831                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1832                                         /* mac_mdc */
1833                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1834                                         /* mac_rxd1 */
1835                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1836                                         /* mac_rxd0 */
1837                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1838                                         /* mac_txd1 */
1839                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1840                                         /* mac_txd0 */
1841                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1842                                         /* mac_rxd3 */
1843                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1844                                         /* mac_rxd2 */
1845                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1846                                         /* mac_txd3 */
1847                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1848                                         /* mac_txd2 */
1849                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1850                         };
1851
1852                         rmii_pins: rmii-pins {
1853                                 rockchip,pins =
1854                                         /* mac_mdio */
1855                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1856                                         /* mac_txen */
1857                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1858                                         /* mac_clk */
1859                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1860                                         /* mac_rxer */
1861                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1862                                         /* mac_rxdv */
1863                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1864                                         /* mac_mdc */
1865                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1866                                         /* mac_rxd1 */
1867                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1868                                         /* mac_rxd0 */
1869                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1870                                         /* mac_txd1 */
1871                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1872                                         /* mac_txd0 */
1873                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1874                         };
1875                 };
1876
1877                 i2c0 {
1878                         i2c0_xfer: i2c0-xfer {
1879                                 rockchip,pins =
1880                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1881                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1882                         };
1883                 };
1884
1885                 i2c1 {
1886                         i2c1_xfer: i2c1-xfer {
1887                                 rockchip,pins =
1888                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1889                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1890                         };
1891                 };
1892
1893                 i2c2 {
1894                         i2c2_xfer: i2c2-xfer {
1895                                 rockchip,pins =
1896                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1897                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1898                         };
1899                 };
1900
1901                 i2c3 {
1902                         i2c3_xfer: i2c3-xfer {
1903                                 rockchip,pins =
1904                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1905                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1906                         };
1907
1908                         i2c3_gpio: i2c3_gpio {
1909                                 rockchip,pins =
1910                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1911                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1912                         };
1913
1914                 };
1915
1916                 i2c4 {
1917                         i2c4_xfer: i2c4-xfer {
1918                                 rockchip,pins =
1919                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1920                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1921                         };
1922                 };
1923
1924                 i2c5 {
1925                         i2c5_xfer: i2c5-xfer {
1926                                 rockchip,pins =
1927                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1928                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1929                         };
1930                 };
1931
1932                 i2c6 {
1933                         i2c6_xfer: i2c6-xfer {
1934                                 rockchip,pins =
1935                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1936                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1937                         };
1938                 };
1939
1940                 i2c7 {
1941                         i2c7_xfer: i2c7-xfer {
1942                                 rockchip,pins =
1943                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1944                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1945                         };
1946                 };
1947
1948                 i2c8 {
1949                         i2c8_xfer: i2c8-xfer {
1950                                 rockchip,pins =
1951                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1952                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1953                         };
1954                 };
1955
1956                 i2s0 {
1957                         i2s0_8ch_bus: i2s0-8ch-bus {
1958                                 rockchip,pins =
1959                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1960                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1961                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1962                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1963                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1964                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1965                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1966                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1967                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1968                         };
1969                 };
1970
1971                 i2s1 {
1972                         i2s1_2ch_bus: i2s1-2ch-bus {
1973                                 rockchip,pins =
1974                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1975                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1976                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1977                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1978                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1979                         };
1980                 };
1981
1982                 sdio0 {
1983                         sdio0_bus1: sdio0-bus1 {
1984                                 rockchip,pins =
1985                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1986                         };
1987
1988                         sdio0_bus4: sdio0-bus4 {
1989                                 rockchip,pins =
1990                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1991                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1992                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1993                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1994                         };
1995
1996                         sdio0_cmd: sdio0-cmd {
1997                                 rockchip,pins =
1998                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1999                         };
2000
2001                         sdio0_clk: sdio0-clk {
2002                                 rockchip,pins =
2003                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2004                         };
2005
2006                         sdio0_cd: sdio0-cd {
2007                                 rockchip,pins =
2008                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2009                         };
2010
2011                         sdio0_pwr: sdio0-pwr {
2012                                 rockchip,pins =
2013                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2014                         };
2015
2016                         sdio0_bkpwr: sdio0-bkpwr {
2017                                 rockchip,pins =
2018                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2019                         };
2020
2021                         sdio0_wp: sdio0-wp {
2022                                 rockchip,pins =
2023                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2024                         };
2025
2026                         sdio0_int: sdio0-int {
2027                                 rockchip,pins =
2028                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2029                         };
2030                 };
2031
2032                 sdmmc {
2033                         sdmmc_bus1: sdmmc-bus1 {
2034                                 rockchip,pins =
2035                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2036                         };
2037
2038                         sdmmc_bus4: sdmmc-bus4 {
2039                                 rockchip,pins =
2040                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2041                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2042                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2043                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2044                         };
2045
2046                         sdmmc_clk: sdmmc-clk {
2047                                 rockchip,pins =
2048                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2049                         };
2050
2051                         sdmmc_cmd: sdmmc-cmd {
2052                                 rockchip,pins =
2053                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2054                         };
2055
2056                         sdmmc_cd: sdmcc-cd {
2057                                 rockchip,pins =
2058                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2059                         };
2060
2061                         sdmmc_wp: sdmmc-wp {
2062                                 rockchip,pins =
2063                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2064                         };
2065                 };
2066
2067                 spdif {
2068                         spdif_bus: spdif-bus {
2069                                 rockchip,pins =
2070                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2071                         };
2072
2073                         spdif_bus_1: spdif-bus-1 {
2074                                 rockchip,pins =
2075                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2076                         };
2077                 };
2078
2079                 spi0 {
2080                         spi0_clk: spi0-clk {
2081                                 rockchip,pins =
2082                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2083                         };
2084                         spi0_cs0: spi0-cs0 {
2085                                 rockchip,pins =
2086                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2087                         };
2088                         spi0_cs1: spi0-cs1 {
2089                                 rockchip,pins =
2090                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2091                         };
2092                         spi0_tx: spi0-tx {
2093                                 rockchip,pins =
2094                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2095                         };
2096                         spi0_rx: spi0-rx {
2097                                 rockchip,pins =
2098                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2099                         };
2100                 };
2101
2102                 spi1 {
2103                         spi1_clk: spi1-clk {
2104                                 rockchip,pins =
2105                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2106                         };
2107                         spi1_cs0: spi1-cs0 {
2108                                 rockchip,pins =
2109                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2110                         };
2111                         spi1_rx: spi1-rx {
2112                                 rockchip,pins =
2113                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2114                         };
2115                         spi1_tx: spi1-tx {
2116                                 rockchip,pins =
2117                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2118                         };
2119                 };
2120
2121                 spi2 {
2122                         spi2_clk: spi2-clk {
2123                                 rockchip,pins =
2124                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2125                         };
2126                         spi2_cs0: spi2-cs0 {
2127                                 rockchip,pins =
2128                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2129                         };
2130                         spi2_rx: spi2-rx {
2131                                 rockchip,pins =
2132                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2133                         };
2134                         spi2_tx: spi2-tx {
2135                                 rockchip,pins =
2136                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2137                         };
2138                 };
2139
2140                 spi3 {
2141                         spi3_clk: spi3-clk {
2142                                 rockchip,pins =
2143                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2144                         };
2145                         spi3_cs0: spi3-cs0 {
2146                                 rockchip,pins =
2147                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2148                         };
2149                         spi3_rx: spi3-rx {
2150                                 rockchip,pins =
2151                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2152                         };
2153                         spi3_tx: spi3-tx {
2154                                 rockchip,pins =
2155                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2156                         };
2157                 };
2158
2159                 spi4 {
2160                         spi4_clk: spi4-clk {
2161                                 rockchip,pins =
2162                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2163                         };
2164                         spi4_cs0: spi4-cs0 {
2165                                 rockchip,pins =
2166                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2167                         };
2168                         spi4_rx: spi4-rx {
2169                                 rockchip,pins =
2170                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2171                         };
2172                         spi4_tx: spi4-tx {
2173                                 rockchip,pins =
2174                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2175                         };
2176                 };
2177
2178                 spi5 {
2179                         spi5_clk: spi5-clk {
2180                                 rockchip,pins =
2181                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2182                         };
2183                         spi5_cs0: spi5-cs0 {
2184                                 rockchip,pins =
2185                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2186                         };
2187                         spi5_rx: spi5-rx {
2188                                 rockchip,pins =
2189                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2190                         };
2191                         spi5_tx: spi5-tx {
2192                                 rockchip,pins =
2193                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2194                         };
2195                 };
2196
2197                 tsadc {
2198                         otp_gpio: otp-gpio {
2199                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2200                         };
2201
2202                         otp_out: otp-out {
2203                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2204                         };
2205                 };
2206
2207                 uart0 {
2208                         uart0_xfer: uart0-xfer {
2209                                 rockchip,pins =
2210                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2211                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2212                         };
2213
2214                         uart0_cts: uart0-cts {
2215                                 rockchip,pins =
2216                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2217                         };
2218
2219                         uart0_rts: uart0-rts {
2220                                 rockchip,pins =
2221                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2222                         };
2223                 };
2224
2225                 uart1 {
2226                         uart1_xfer: uart1-xfer {
2227                                 rockchip,pins =
2228                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2229                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2230                         };
2231                 };
2232
2233                 uart2a {
2234                         uart2a_xfer: uart2a-xfer {
2235                                 rockchip,pins =
2236                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2237                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2238                         };
2239                 };
2240
2241                 uart2b {
2242                         uart2b_xfer: uart2b-xfer {
2243                                 rockchip,pins =
2244                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2245                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2246                         };
2247                 };
2248
2249                 uart2c {
2250                         uart2c_xfer: uart2c-xfer {
2251                                 rockchip,pins =
2252                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2253                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2254                         };
2255                 };
2256
2257                 uart3 {
2258                         uart3_xfer: uart3-xfer {
2259                                 rockchip,pins =
2260                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2261                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2262                         };
2263
2264                         uart3_cts: uart3-cts {
2265                                 rockchip,pins =
2266                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2267                         };
2268
2269                         uart3_rts: uart3-rts {
2270                                 rockchip,pins =
2271                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2272                         };
2273                 };
2274
2275                 uart4 {
2276                         uart4_xfer: uart4-xfer {
2277                                 rockchip,pins =
2278                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2279                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2280                         };
2281                 };
2282
2283                 uarthdcp {
2284                         uarthdcp_xfer: uarthdcp-xfer {
2285                                 rockchip,pins =
2286                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2287                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2288                         };
2289                 };
2290
2291                 pwm0 {
2292                         pwm0_pin: pwm0-pin {
2293                                 rockchip,pins =
2294                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2295                         };
2296
2297                         vop0_pwm_pin: vop0-pwm-pin {
2298                                 rockchip,pins =
2299                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2300                         };
2301                 };
2302
2303                 pwm1 {
2304                         pwm1_pin: pwm1-pin {
2305                                 rockchip,pins =
2306                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2307                         };
2308
2309                         vop1_pwm_pin: vop1-pwm-pin {
2310                                 rockchip,pins =
2311                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2312                         };
2313                 };
2314
2315                 pwm2 {
2316                         pwm2_pin: pwm2-pin {
2317                                 rockchip,pins =
2318                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2319                         };
2320                 };
2321
2322                 pwm3a {
2323                         pwm3a_pin: pwm3a-pin {
2324                                 rockchip,pins =
2325                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2326                         };
2327                 };
2328
2329                 pwm3b {
2330                         pwm3b_pin: pwm3b-pin {
2331                                 rockchip,pins =
2332                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2333                         };
2334                 };
2335
2336                 edp {
2337                         edp_hpd: edp-hpd {
2338                                 rockchip,pins =
2339                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2340                         };
2341                 };
2342
2343                 hdmi {
2344                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2345                                 rockchip,pins =
2346                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2347                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2348                         };
2349
2350                         hdmi_cec: hdmi-cec {
2351                                 rockchip,pins =
2352                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2353                         };
2354                 };
2355
2356                 pcie {
2357                         pcie_clkreqn: pci-clkreqn {
2358                                 rockchip,pins =
2359                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2360                         };
2361
2362                         pcie_clkreqnb: pci-clkreqnb {
2363                                 rockchip,pins =
2364                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2365                         };
2366                 };
2367         };
2368 };