arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <121>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <1068>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp@408000000 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp@600000000 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp@816000000 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp@1008000000 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp@1200000000 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp@1416000000 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp@408000000 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@600000000 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp@816000000 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp@1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 261         };
 262
 263         arm-pmu {
 264                 compatible = "arm,armv8-pmuv3";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 266         };
 267
 268         xin24m: xin24m {
 269                 compatible = "fixed-clock";
 270                 #clock-cells = <0>;
 271                 clock-frequency = <24000000>;
 272                 clock-output-names = "xin24m";
 273         };
 274
 275         amba {
 276                 compatible = "arm,amba-bus";
 277                 #address-cells = <2>;
 278                 #size-cells = <2>;
 279                 ranges;
 280
 281                 dmac_bus: dma-controller@ff6d0000 {
 282                         compatible = "arm,pl330", "arm,primecell";
 283                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 284                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 286                         #dma-cells = <1>;
 287                         clocks = <&cru ACLK_DMAC0_PERILP>;
 288                         clock-names = "apb_pclk";
 289                         peripherals-req-type-burst;
 290                 };
 291
 292                 dmac_peri: dma-controller@ff6e0000 {
 293                         compatible = "arm,pl330", "arm,primecell";
 294                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 295                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 297                         #dma-cells = <1>;
 298                         clocks = <&cru ACLK_DMAC1_PERILP>;
 299                         clock-names = "apb_pclk";
 300                         peripherals-req-type-burst;
 301                 };
 302         };
 303
 304         gmac: eth@fe300000 {
 305                 compatible = "rockchip,rk3399-gmac";
 306                 reg = <0x0 0xfe300000 0x0 0x10000>;
 307                 rockchip,grf = <&grf>;
 308                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 309                 interrupt-names = "macirq";
 310                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 311                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 312                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 313                          <&cru PCLK_GMAC>;
 314                 clock-names = "stmmaceth", "mac_clk_rx",
 315                               "mac_clk_tx", "clk_mac_ref",
 316                               "clk_mac_refout", "aclk_mac",
 317                               "pclk_mac";
 318                 resets = <&cru SRST_A_GMAC>;
 319                 reset-names = "stmmaceth";
 320                 status = "disabled";
 321         };
 322
 323         emmc_phy: phy {
 324                 compatible = "rockchip,rk3399-emmc-phy";
 325                 reg-offset = <0xf780>;
 326                 #phy-cells = <0>;
 327                 rockchip,grf = <&grf>;
 328                 ctrl-base = <0xfe330000>;
 329                 status = "disabled";
 330         };
 331
 332         sdio0: dwmmc@fe310000 {
 333                 compatible = "rockchip,rk3399-dw-mshc",
 334                              "rockchip,rk3288-dw-mshc";
 335                 reg = <0x0 0xfe310000 0x0 0x4000>;
 336                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 337                 clock-freq-min-max = <400000 150000000>;
 338                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 339                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 340                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 341                 fifo-depth = <0x100>;
 342                 status = "disabled";
 343         };
 344
 345         sdmmc: dwmmc@fe320000 {
 346                 compatible = "rockchip,rk3399-dw-mshc",
 347                              "rockchip,rk3288-dw-mshc";
 348                 reg = <0x0 0xfe320000 0x0 0x4000>;
 349                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 350                 clock-freq-min-max = <400000 150000000>;
 351                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 352                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 353                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 354                 fifo-depth = <0x100>;
 355                 status = "disabled";
 356         };
 357
 358         sdhci: sdhci@fe330000 {
 359                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 360                 reg = <0x0 0xfe330000 0x0 0x10000>;
 361                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 362                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 363                 clock-names = "clk_xin", "clk_ahb";
 364                 assigned-clocks = <&cru SCLK_EMMC>;
 365                 assigned-clock-parents = <&cru PLL_CPLL>;
 366                 assigned-clock-rates = <200000000>;
 367                 phys = <&emmc_phy>;
 368                 phy-names = "phy_arasan";
 369                 status = "disabled";
 370         };
 371
 372         usb2phy: usb2phy {
 373                 compatible = "rockchip,rk3399-usb-phy";
 374                 rockchip,grf = <&grf>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377
 378                 usb2phy0: usb2-phy0 {
 379                         #phy-cells = <0>;
 380                         #clock-cells = <0>;
 381                         reg = <0xe458>;
 382                 };
 383
 384                 usb2phy1: usb2-phy1 {
 385                         #phy-cells = <0>;
 386                         #clock-cells = <0>;
 387                         reg = <0xe468>;
 388                 };
 389         };
 390
 391         usb_host0_ehci: usb@fe380000 {
 392                 compatible = "generic-ehci";
 393                 reg = <0x0 0xfe380000 0x0 0x20000>;
 394                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 395                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 396                 clock-names = "hclk_host0", "hclk_host0_arb";
 397                 phys = <&usb2phy0>;
 398                 phy-names = "usb2_phy0";
 399                 status = "disabled";
 400         };
 401
 402         usb_host0_ohci: usb@fe3a0000 {
 403                 compatible = "generic-ohci";
 404                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 405                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 407                 clock-names = "hclk_host0", "hclk_host0_arb";
 408                 status = "disabled";
 409         };
 410
 411         usb_host1_ehci: usb@fe3c0000 {
 412                 compatible = "generic-ehci";
 413                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 414                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 416                 clock-names = "hclk_host1", "hclk_host1_arb";
 417                 phys = <&usb2phy1>;
 418                 phy-names = "usb2_phy1";
 419                 status = "disabled";
 420         };
 421
 422         usb_host1_ohci: usb@fe3e0000 {
 423                 compatible = "generic-ohci";
 424                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 425                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 427                 clock-names = "hclk_host1", "hclk_host1_arb";
 428                 status = "disabled";
 429         };
 430
 431         usbdrd3_0: usb@fe800000 {
 432                 compatible = "rockchip,dwc3";
 433                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 434                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 435                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 436                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 437                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 438                               "aclk_usb3", "aclk_usb3_grf";
 439                 #address-cells = <2>;
 440                 #size-cells = <2>;
 441                 ranges;
 442                 status = "disabled";
 443                 usbdrd_dwc3_0: dwc3@fe800000 {
 444                         compatible = "snps,dwc3";
 445                         reg = <0x0 0xfe800000 0x0 0x100000>;
 446                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 447                         dr_mode = "otg";
 448                         snps,dis_enblslpm_quirk;
 449                         snps,phyif_utmi_16_bits;
 450                         snps,dis_u2_freeclk_exists_quirk;
 451                         snps,dis_del_phy_power_chg_quirk;
 452                         snps,xhci_slow_suspend_quirk;
 453                         status = "disabled";
 454                 };
 455         };
 456
 457         usbdrd3_1: usb@fe900000 {
 458                 compatible = "rockchip,dwc3";
 459                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 460                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 461                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 462                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 463                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 464                               "aclk_usb3", "aclk_usb3_grf";
 465                 #address-cells = <2>;
 466                 #size-cells = <2>;
 467                 ranges;
 468                 status = "disabled";
 469                 usbdrd_dwc3_1: dwc3@fe900000 {
 470                         compatible = "snps,dwc3";
 471                         reg = <0x0 0xfe900000 0x0 0x100000>;
 472                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 473                         dr_mode = "otg";
 474                         snps,dis_enblslpm_quirk;
 475                         snps,phyif_utmi_16_bits;
 476                         snps,dis_u2_freeclk_exists_quirk;
 477                         snps,dis_del_phy_power_chg_quirk;
 478                         snps,xhci_slow_suspend_quirk;
 479                         status = "disabled";
 480                 };
 481         };
 482
 483         gic: interrupt-controller@fee00000 {
 484                 compatible = "arm,gic-v3";
 485                 #interrupt-cells = <3>;
 486                 #address-cells = <2>;
 487                 #size-cells = <2>;
 488                 ranges;
 489                 interrupt-controller;
 490
 491                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 492                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 493                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 494                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 495                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 496                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 497                 its: interrupt-controller@fee20000 {
 498                         compatible = "arm,gic-v3-its";
 499                         msi-controller;
 500                         reg = <0x0 0xfee20000 0x0 0x20000>;
 501                 };
 502         };
 503
 504         saradc: saradc@ff100000 {
 505                 compatible = "rockchip,rk3399-saradc";
 506                 reg = <0x0 0xff100000 0x0 0x100>;
 507                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 508                 #io-channel-cells = <1>;
 509                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 510                 clock-names = "saradc", "apb_pclk";
 511                 status = "disabled";
 512         };
 513
 514         i2c0: i2c@ff3c0000 {
 515                 compatible = "rockchip,rk3399-i2c";
 516                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 517                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 518                 clock-names = "i2c", "pclk";
 519                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&i2c0_xfer>;
 522                 #address-cells = <1>;
 523                 #size-cells = <0>;
 524                 status = "disabled";
 525         };
 526
 527         i2c1: i2c@ff110000 {
 528                 compatible = "rockchip,rk3399-i2c";
 529                 reg = <0x0 0xff110000 0x0 0x1000>;
 530                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 531                 clock-names = "i2c", "pclk";
 532                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&i2c1_xfer>;
 535                 #address-cells = <1>;
 536                 #size-cells = <0>;
 537                 status = "disabled";
 538         };
 539
 540         i2c2: i2c@ff120000 {
 541                 compatible = "rockchip,rk3399-i2c";
 542                 reg = <0x0 0xff120000 0x0 0x1000>;
 543                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 544                 clock-names = "i2c", "pclk";
 545                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&i2c2_xfer>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         i2c3: i2c@ff130000 {
 554                 compatible = "rockchip,rk3399-i2c";
 555                 reg = <0x0 0xff130000 0x0 0x1000>;
 556                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 557                 clock-names = "i2c", "pclk";
 558                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c3_xfer>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 status = "disabled";
 564         };
 565
 566         i2c5: i2c@ff140000 {
 567                 compatible = "rockchip,rk3399-i2c";
 568                 reg = <0x0 0xff140000 0x0 0x1000>;
 569                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 570                 clock-names = "i2c", "pclk";
 571                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c5_xfer>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 status = "disabled";
 577         };
 578
 579         i2c6: i2c@ff150000 {
 580                 compatible = "rockchip,rk3399-i2c";
 581                 reg = <0x0 0xff150000 0x0 0x1000>;
 582                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 583                 clock-names = "i2c", "pclk";
 584                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&i2c6_xfer>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 status = "disabled";
 590         };
 591
 592         i2c7: i2c@ff160000 {
 593                 compatible = "rockchip,rk3399-i2c";
 594                 reg = <0x0 0xff160000 0x0 0x1000>;
 595                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 596                 clock-names = "i2c", "pclk";
 597                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&i2c7_xfer>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 status = "disabled";
 603         };
 604
 605         uart0: serial@ff180000 {
 606                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 607                 reg = <0x0 0xff180000 0x0 0x100>;
 608                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 609                 clock-names = "baudclk", "apb_pclk";
 610                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 611                 reg-shift = <2>;
 612                 reg-io-width = <4>;
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 615                 status = "disabled";
 616         };
 617
 618         uart1: serial@ff190000 {
 619                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 620                 reg = <0x0 0xff190000 0x0 0x100>;
 621                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 622                 clock-names = "baudclk", "apb_pclk";
 623                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 624                 reg-shift = <2>;
 625                 reg-io-width = <4>;
 626                 pinctrl-names = "default";
 627                 pinctrl-0 = <&uart1_xfer>;
 628                 status = "disabled";
 629         };
 630
 631         uart2: serial@ff1a0000 {
 632                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 633                 reg = <0x0 0xff1a0000 0x0 0x100>;
 634                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 635                 clock-names = "baudclk", "apb_pclk";
 636                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 637                 reg-shift = <2>;
 638                 reg-io-width = <4>;
 639                 pinctrl-names = "default";
 640                 pinctrl-0 = <&uart2c_xfer>;
 641                 status = "disabled";
 642         };
 643
 644         uart3: serial@ff1b0000 {
 645                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 646                 reg = <0x0 0xff1b0000 0x0 0x100>;
 647                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 648                 clock-names = "baudclk", "apb_pclk";
 649                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 650                 reg-shift = <2>;
 651                 reg-io-width = <4>;
 652                 pinctrl-names = "default";
 653                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 654                 status = "disabled";
 655         };
 656
 657         spi0: spi@ff1c0000 {
 658                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 659                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 660                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 661                 clock-names = "spiclk", "apb_pclk";
 662                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 663                 pinctrl-names = "default";
 664                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 665                 #address-cells = <1>;
 666                 #size-cells = <0>;
 667                 status = "disabled";
 668         };
 669
 670         spi1: spi@ff1d0000 {
 671                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 672                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 673                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 674                 clock-names = "spiclk", "apb_pclk";
 675                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 678                 #address-cells = <1>;
 679                 #size-cells = <0>;
 680                 status = "disabled";
 681         };
 682
 683         spi2: spi@ff1e0000 {
 684                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 685                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 686                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 687                 clock-names = "spiclk", "apb_pclk";
 688                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 689                 pinctrl-names = "default";
 690                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 691                 #address-cells = <1>;
 692                 #size-cells = <0>;
 693                 status = "disabled";
 694         };
 695
 696         spi4: spi@ff1f0000 {
 697                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 698                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 699                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 700                 clock-names = "spiclk", "apb_pclk";
 701                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 702                 pinctrl-names = "default";
 703                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 704                 #address-cells = <1>;
 705                 #size-cells = <0>;
 706                 status = "disabled";
 707         };
 708
 709         spi5: spi@ff200000 {
 710                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 711                 reg = <0x0 0xff200000 0x0 0x1000>;
 712                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 713                 clock-names = "spiclk", "apb_pclk";
 714                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 715                 pinctrl-names = "default";
 716                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719                 status = "disabled";
 720         };
 721
 722         thermal-zones {
 723                 soc_thermal: soc-thermal {
 724                         polling-delay-passive = <20>; /* milliseconds */
 725                         polling-delay = <1000>; /* milliseconds */
 726                         sustainable-power = <1600>; /* milliwatts */
 727
 728                         thermal-sensors = <&tsadc 0>;
 729
 730                         trips {
 731                                 threshold: trip-point@0 {
 732                                         temperature = <70000>; /* millicelsius */
 733                                         hysteresis = <2000>; /* millicelsius */
 734                                         type = "passive";
 735                                 };
 736                                 target: trip-point@1 {
 737                                         temperature = <85000>; /* millicelsius */
 738                                         hysteresis = <2000>; /* millicelsius */
 739                                         type = "passive";
 740                                 };
 741                                 soc_crit: soc-crit {
 742                                         temperature = <95000>; /* millicelsius */
 743                                         hysteresis = <2000>; /* millicelsius */
 744                                         type = "critical";
 745                                 };
 746                         };
 747
 748                         cooling-maps {
 749                                 map0 {
 750                                         trip = <&target>;
 751                                         cooling-device =
 752                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 753                                         contribution = <10240>;
 754                                 };
 755                                 map1 {
 756                                         trip = <&target>;
 757                                         cooling-device =
 758                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 759                                         contribution = <1024>;
 760                                 };
 761                                 map2 {
 762                                         trip = <&target>;
 763                                         cooling-device =
 764                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 765                                         contribution = <10240>;
 766                                 };
 767                         };
 768                 };
 769
 770                 gpu_thermal: gpu-thermal {
 771                         polling-delay-passive = <100>; /* milliseconds */
 772                         polling-delay = <1000>; /* milliseconds */
 773
 774                         thermal-sensors = <&tsadc 1>;
 775                 };
 776         };
 777
 778         tsadc: tsadc@ff260000 {
 779                 compatible = "rockchip,rk3399-tsadc";
 780                 reg = <0x0 0xff260000 0x0 0x100>;
 781                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 782                 rockchip,grf = <&grf>;
 783                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 784                 clock-names = "tsadc", "apb_pclk";
 785                 assigned-clocks = <&cru SCLK_TSADC>;
 786                 assigned-clock-rates = <750000>;
 787                 resets = <&cru SRST_TSADC>;
 788                 reset-names = "tsadc-apb";
 789                 pinctrl-names = "init", "default", "sleep";
 790                 pinctrl-0 = <&otp_gpio>;
 791                 pinctrl-1 = <&otp_out>;
 792                 pinctrl-2 = <&otp_gpio>;
 793                 #thermal-sensor-cells = <1>;
 794                 rockchip,hw-tshut-temp = <95000>;
 795                 status = "disabled";
 796         };
 797
 798         qos_hdcp: qos@ffa90000 {
 799                 compatible = "syscon";
 800                 reg = <0x0 0xffa90000 0x0 0x20>;
 801         };
 802
 803         qos_iep: qos@ffa98000 {
 804                 compatible = "syscon";
 805                 reg = <0x0 0xffa98000 0x0 0x20>;
 806         };
 807
 808         qos_isp0_m0: qos@ffaa0000 {
 809                 compatible = "syscon";
 810                 reg = <0x0 0xffaa0000 0x0 0x20>;
 811         };
 812
 813         qos_isp0_m1: qos@ffaa0080 {
 814                 compatible = "syscon";
 815                 reg = <0x0 0xffaa0080 0x0 0x20>;
 816         };
 817
 818         qos_isp1_m0: qos@ffaa8000 {
 819                 compatible = "syscon";
 820                 reg = <0x0 0xffaa8000 0x0 0x20>;
 821         };
 822
 823         qos_isp1_m1: qos@ffaa8080 {
 824                 compatible = "syscon";
 825                 reg = <0x0 0xffaa8080 0x0 0x20>;
 826         };
 827
 828         qos_rga_r: qos@ffab0000 {
 829                 compatible = "syscon";
 830                 reg = <0x0 0xffab0000 0x0 0x20>;
 831         };
 832
 833         qos_rga_w: qos@ffab0080 {
 834                 compatible = "syscon";
 835                 reg = <0x0 0xffab0080 0x0 0x20>;
 836         };
 837
 838         qos_video_m0: qos@ffab8000 {
 839                 compatible = "syscon";
 840                 reg = <0x0 0xffab8000 0x0 0x20>;
 841         };
 842
 843         qos_video_m1_r: qos@ffac0000 {
 844                 compatible = "syscon";
 845                 reg = <0x0 0xffac0000 0x0 0x20>;
 846         };
 847
 848         qos_video_m1_w: qos@ffac0080 {
 849                 compatible = "syscon";
 850                 reg = <0x0 0xffac0080 0x0 0x20>;
 851         };
 852
 853         qos_vop_big_r: qos@ffac8000 {
 854                 compatible = "syscon";
 855                 reg = <0x0 0xffac8000 0x0 0x20>;
 856         };
 857
 858         qos_vop_big_w: qos@ffac8080 {
 859                 compatible = "syscon";
 860                 reg = <0x0 0xffac8080 0x0 0x20>;
 861         };
 862
 863         qos_vop_little: qos@ffad0000 {
 864                 compatible = "syscon";
 865                 reg = <0x0 0xffad0000 0x0 0x20>;
 866         };
 867
 868         qos_gpu: qos@ffae0000 {
 869                 compatible = "syscon";
 870                 reg = <0x0 0xffae0000 0x0 0x20>;
 871         };
 872
 873         pmu: power-management@ff310000 {
 874                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 875                 reg = <0x0 0xff310000 0x0 0x1000>;
 876
 877                 /*
 878                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 879                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 880                  * Some of the power domains are grouped together for every
 881                  * voltage domain.
 882                  * The detail contents as below.
 883                  */
 884                 power: power-controller {
 885                         compatible = "rockchip,rk3399-power-controller";
 886                         #power-domain-cells = <1>;
 887                         #address-cells = <1>;
 888                         #size-cells = <0>;
 889
 890                         /* These power domains are grouped by VD_CENTER */
 891                         pd_iep@RK3399_PD_IEP {
 892                                 reg = <RK3399_PD_IEP>;
 893                                 clocks = <&cru ACLK_IEP>,
 894                                          <&cru HCLK_IEP>;
 895                                 pm_qos = <&qos_iep>;
 896                         };
 897                         pd_rga@RK3399_PD_RGA {
 898                                 reg = <RK3399_PD_RGA>;
 899                                 clocks = <&cru ACLK_RGA>,
 900                                          <&cru HCLK_RGA>;
 901                                 pm_qos = <&qos_rga_r>,
 902                                          <&qos_rga_w>;
 903                         };
 904                         pd_vcodec@RK3399_PD_VCODEC {
 905                                 reg = <RK3399_PD_VCODEC>;
 906                                 clocks = <&cru ACLK_VCODEC>,
 907                                          <&cru HCLK_VCODEC>;
 908                                 pm_qos = <&qos_video_m0>;
 909                         };
 910                         pd_vdu@RK3399_PD_VDU {
 911                                 reg = <RK3399_PD_VDU>;
 912                                 clocks = <&cru ACLK_VDU>,
 913                                          <&cru HCLK_VDU>;
 914                                 pm_qos = <&qos_video_m1_r>,
 915                                          <&qos_video_m1_w>;
 916                         };
 917
 918                         /* These power domains are grouped by VD_GPU */
 919                         pd_gpu@RK3399_PD_GPU {
 920                                 reg = <RK3399_PD_GPU>;
 921                                 clocks = <&cru ACLK_GPU>;
 922                                 pm_qos = <&qos_gpu>;
 923                         };
 924
 925                         /* These power domains are grouped by VD_LOGIC */
 926                         pd_vio@RK3399_PD_VIO {
 927                                 reg = <RK3399_PD_VIO>;
 928                                 #address-cells = <1>;
 929                                 #size-cells = <0>;
 930
 931                                 pd_hdcp@RK3399_PD_HDCP {
 932                                         reg = <RK3399_PD_HDCP>;
 933                                         clocks = <&cru ACLK_HDCP>,
 934                                                  <&cru HCLK_HDCP>,
 935                                                  <&cru PCLK_HDCP>;
 936                                         pm_qos = <&qos_hdcp>;
 937                                 };
 938                                 pd_isp0@RK3399_PD_ISP0 {
 939                                         reg = <RK3399_PD_ISP0>;
 940                                         clocks = <&cru ACLK_ISP0>,
 941                                                  <&cru HCLK_ISP0>;
 942                                         pm_qos = <&qos_isp0_m0>,
 943                                                  <&qos_isp0_m1>;
 944                                 };
 945                                 pd_isp1@RK3399_PD_ISP1 {
 946                                         reg = <RK3399_PD_ISP1>;
 947                                         clocks = <&cru ACLK_ISP1>,
 948                                                  <&cru HCLK_ISP1>;
 949                                         pm_qos = <&qos_isp1_m0>,
 950                                                  <&qos_isp1_m1>;
 951                                 };
 952                                 pd_vo@RK3399_PD_VO {
 953                                         reg = <RK3399_PD_VO>;
 954                                         #address-cells = <1>;
 955                                         #size-cells = <0>;
 956
 957                                         pd_vopb@RK3399_PD_VOPB {
 958                                                 reg = <RK3399_PD_VOPB>;
 959                                                 clocks = <&cru ACLK_VOP0>,
 960                                                          <&cru HCLK_VOP0>;
 961                                                 pm_qos = <&qos_vop_big_r>,
 962                                                          <&qos_vop_big_w>;
 963                                         };
 964                                         pd_vopl@RK3399_PD_VOPL {
 965                                                 reg = <RK3399_PD_VOPL>;
 966                                                 clocks = <&cru ACLK_VOP1>,
 967                                                          <&cru HCLK_VOP1>;
 968                                                 pm_qos = <&qos_vop_little>;
 969                                         };
 970                                 };
 971                         };
 972                 };
 973         };
 974
 975         pmugrf: syscon@ff320000 {
 976                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 977                 reg = <0x0 0xff320000 0x0 0x1000>;
 978
 979                 reboot-mode {
 980                         compatible = "syscon-reboot-mode";
 981                         offset = <0x300>;
 982                         mode-normal = <BOOT_NORMAL>;
 983                         mode-recovery = <BOOT_RECOVERY>;
 984                         mode-bootloader = <BOOT_FASTBOOT>;
 985                         mode-loader = <BOOT_LOADER>;
 986                 };
 987         };
 988
 989         spi3: spi@ff350000 {
 990                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 991                 reg = <0x0 0xff350000 0x0 0x1000>;
 992                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 993                 clock-names = "spiclk", "apb_pclk";
 994                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 995                 pinctrl-names = "default";
 996                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 997                 #address-cells = <1>;
 998                 #size-cells = <0>;
 999                 status = "disabled";
1000         };
1001
1002         uart4: serial@ff370000 {
1003                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1004                 reg = <0x0 0xff370000 0x0 0x100>;
1005                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1006                 clock-names = "baudclk", "apb_pclk";
1007                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1008                 reg-shift = <2>;
1009                 reg-io-width = <4>;
1010                 pinctrl-names = "default";
1011                 pinctrl-0 = <&uart4_xfer>;
1012                 status = "disabled";
1013         };
1014
1015         i2c4: i2c@ff3d0000 {
1016                 compatible = "rockchip,rk3399-i2c";
1017                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1018                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1019                 clock-names = "i2c", "pclk";
1020                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1021                 pinctrl-names = "default";
1022                 pinctrl-0 = <&i2c4_xfer>;
1023                 #address-cells = <1>;
1024                 #size-cells = <0>;
1025                 status = "disabled";
1026         };
1027
1028         i2c8: i2c@ff3e0000 {
1029                 compatible = "rockchip,rk3399-i2c";
1030                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1031                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1032                 clock-names = "i2c", "pclk";
1033                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1034                 pinctrl-names = "default";
1035                 pinctrl-0 = <&i2c8_xfer>;
1036                 #address-cells = <1>;
1037                 #size-cells = <0>;
1038                 status = "disabled";
1039         };
1040
1041         pcie0: pcie@f8000000 {
1042                 compatible = "rockchip,rk3399-pcie";
1043                 #address-cells = <3>;
1044                 #size-cells = <2>;
1045                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1046                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1047                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1048                               "hclk_pcie", "clk_pciephy_ref";
1049                 bus-range = <0x0 0x1>;
1050                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1051                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1052                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1053                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1054                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1055                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1056                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1057                       < 0x0 0xfd000000 0x0 0x1000000 >;
1058                 reg-name = "axi-base", "apb-base";
1059                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1060                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1061                          <&cru SRST_PCIE_PIPE>;
1062                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1063                               "mgmt-sticky-rst", "pipe-rst";
1064                 rockchip,grf = <&grf>;
1065                 pcie-conf = <0xe220>;
1066                 pcie-status = <0xe2a4>;
1067                 pcie-laneoff = <0xe214>;
1068                 msi-parent = <&its>;
1069                 #interrupt-cells = <1>;
1070                 interrupt-map-mask = <0 0 0 7>;
1071                 interrupt-map = <0 0 0 1 &pcie0 1>,
1072                                 <0 0 0 2 &pcie0 2>,
1073                                 <0 0 0 3 &pcie0 3>,
1074                                 <0 0 0 4 &pcie0 4>;
1075                 status = "disabled";
1076                 pcie_intc: interrupt-controller {
1077                         interrupt-controller;
1078                         #address-cells = <0>;
1079                         #interrupt-cells = <1>;
1080                 };
1081         };
1082
1083         pwm0: pwm@ff420000 {
1084                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1085                 reg = <0x0 0xff420000 0x0 0x10>;
1086                 #pwm-cells = <3>;
1087                 pinctrl-names = "default";
1088                 pinctrl-0 = <&pwm0_pin>;
1089                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1090                 clock-names = "pwm";
1091                 status = "disabled";
1092         };
1093
1094         pwm1: pwm@ff420010 {
1095                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1096                 reg = <0x0 0xff420010 0x0 0x10>;
1097                 #pwm-cells = <3>;
1098                 pinctrl-names = "default";
1099                 pinctrl-0 = <&pwm1_pin>;
1100                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1101                 clock-names = "pwm";
1102                 status = "disabled";
1103         };
1104
1105         pwm2: pwm@ff420020 {
1106                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1107                 reg = <0x0 0xff420020 0x0 0x10>;
1108                 #pwm-cells = <3>;
1109                 pinctrl-names = "default";
1110                 pinctrl-0 = <&pwm2_pin>;
1111                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1112                 clock-names = "pwm";
1113                 status = "disabled";
1114         };
1115
1116         pwm3: pwm@ff420030 {
1117                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1118                 reg = <0x0 0xff420030 0x0 0x10>;
1119                 #pwm-cells = <3>;
1120                 pinctrl-names = "default";
1121                 pinctrl-0 = <&pwm3a_pin>;
1122                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1123                 clock-names = "pwm";
1124                 status = "disabled";
1125         };
1126
1127         rga: rga@ff680000 {
1128                 compatible = "rockchip,rk3399-rga";
1129                 reg = <0x0 0xff680000 0x0 0x10000>;
1130                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1131                 interrupt-names = "rga";
1132                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1133                 clock-names = "aclk", "hclk", "sclk";
1134                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1135                 reset-names = "core", "axi", "ahb";
1136                 status = "disabled";
1137         };
1138
1139         pmucru: pmu-clock-controller@ff750000 {
1140                 compatible = "rockchip,rk3399-pmucru";
1141                 reg = <0x0 0xff750000 0x0 0x1000>;
1142                 #clock-cells = <1>;
1143                 #reset-cells = <1>;
1144                 assigned-clocks = <&pmucru PLL_PPLL>;
1145                 assigned-clock-rates = <676000000>;
1146         };
1147
1148         cru: clock-controller@ff760000 {
1149                 compatible = "rockchip,rk3399-cru";
1150                 reg = <0x0 0xff760000 0x0 0x1000>;
1151                 #clock-cells = <1>;
1152                 #reset-cells = <1>;
1153                 assigned-clocks =
1154                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1155                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1156                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1157                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1158                         <&cru PLL_NPLL>,
1159                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1160                         <&cru PCLK_PERIHP>,
1161                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1162                         <&cru PCLK_PERILP0>,
1163                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1164                 assigned-clock-rates =
1165                          <400000000>,  <200000000>,
1166                          <400000000>,  <200000000>,
1167                          <816000000>, <816000000>,
1168                          <594000000>,  <800000000>,
1169                         <1000000000>,
1170                          <150000000>,   <75000000>,
1171                           <37500000>,
1172                          <100000000>,  <100000000>,
1173                           <50000000>,
1174                          <100000000>,   <50000000>;
1175         };
1176
1177         grf: syscon@ff770000 {
1178                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1179                 reg = <0x0 0xff770000 0x0 0x10000>;
1180                 #address-cells = <1>;
1181                 #size-cells = <1>;
1182
1183                 u2phy0: usb2-phy@e450 {
1184                         compatible = "rockchip,rk3399-usb2phy";
1185                         reg = <0xe450 0x10>;
1186                         clocks = <&cru SCLK_USB2PHY0_REF>;
1187                         clock-names = "phyclk";
1188                         #clock-cells = <0>;
1189                         clock-output-names = "clk_usbphy0_480m";
1190                         status = "disabled";
1191
1192                         u2phy0_otg: otg-port {
1193                                 #phy-cells = <0>;
1194                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1195                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1196                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1197                                 interrupt-names = "otg-bvalid", "otg-id",
1198                                                   "linestate";
1199                                 status = "disabled";
1200                         };
1201                 };
1202         };
1203
1204         tcphy0: phy@ff7c0000 {
1205                 compatible = "rockchip,rk3399-typec-phy";
1206                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1207                 rockchip,grf = <&grf>;
1208                 #phy-cells = <0>;
1209                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1210                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1211                 clock-names = "tcpdcore", "tcpdphy-ref";
1212                 resets = <&cru SRST_UPHY0>,
1213                          <&cru SRST_UPHY0_PIPE_L00>,
1214                          <&cru SRST_P_UPHY0_TCPHY>;
1215                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1216                 rockchip,typec-conn-dir = <0xe580 0 16>;
1217                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1218                 rockchip,external-psm = <0xe588 14 30>;
1219                 rockchip,pipe-status = <0xe5c0 0 0>;
1220                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1221                 status = "disabled";
1222         };
1223
1224         tcphy1: phy@ff800000 {
1225                 compatible = "rockchip,rk3399-typec-phy";
1226                 reg = <0x0 0xff800000 0x0 0x40000>;
1227                 rockchip,grf = <&grf>;
1228                 #phy-cells = <0>;
1229                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1230                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1231                 clock-names = "tcpdcore", "tcpdphy-ref";
1232                 resets = <&cru SRST_UPHY1>,
1233                          <&cru SRST_UPHY1_PIPE_L00>,
1234                          <&cru SRST_P_UPHY1_TCPHY>;
1235                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1236                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1237                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1238                 rockchip,external-psm = <0xe594 14 30>;
1239                 rockchip,pipe-status = <0xe5c0 16 16>;
1240                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1241                 status = "disabled";
1242         };
1243
1244         watchdog@ff840000 {
1245                 compatible = "snps,dw-wdt";
1246                 reg = <0x0 0xff840000 0x0 0x100>;
1247                 clocks = <&cru PCLK_WDT>;
1248                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1249         };
1250
1251         rktimer: rktimer@ff850000 {
1252                 compatible = "rockchip,rk3399-timer";
1253                 reg = <0x0 0xff850000 0x0 0x1000>;
1254                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1255                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1256                 clock-names = "pclk", "timer";
1257         };
1258
1259         spdif: spdif@ff870000 {
1260                 compatible = "rockchip,rk3399-spdif";
1261                 reg = <0x0 0xff870000 0x0 0x1000>;
1262                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1263                 dmas = <&dmac_bus 7>;
1264                 dma-names = "tx";
1265                 clock-names = "mclk", "hclk";
1266                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1267                 pinctrl-names = "default";
1268                 pinctrl-0 = <&spdif_bus>;
1269                 status = "disabled";
1270         };
1271
1272         i2s0: i2s@ff880000 {
1273                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1274                 reg = <0x0 0xff880000 0x0 0x1000>;
1275                 rockchip,grf = <&grf>;
1276                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1277                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1278                 dma-names = "tx", "rx";
1279                 clock-names = "i2s_clk", "i2s_hclk";
1280                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1281                 pinctrl-names = "default";
1282                 pinctrl-0 = <&i2s0_8ch_bus>;
1283                 status = "disabled";
1284         };
1285
1286         i2s1: i2s@ff890000 {
1287                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1288                 reg = <0x0 0xff890000 0x0 0x1000>;
1289                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1290                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1291                 dma-names = "tx", "rx";
1292                 clock-names = "i2s_clk", "i2s_hclk";
1293                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1294                 pinctrl-names = "default";
1295                 pinctrl-0 = <&i2s1_2ch_bus>;
1296                 status = "disabled";
1297         };
1298
1299         i2s2: i2s@ff8a0000 {
1300                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1301                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1302                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1303                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1304                 dma-names = "tx", "rx";
1305                 clock-names = "i2s_clk", "i2s_hclk";
1306                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1307                 status = "disabled";
1308         };
1309
1310         gpu: gpu@ff9a0000 {
1311                 compatible = "arm,malit860",
1312                              "arm,malit86x",
1313                              "arm,malit8xx",
1314                              "arm,mali-midgard";
1315
1316                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1317
1318                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1319                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1320                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1321                 interrupt-names = "GPU", "JOB", "MMU";
1322
1323                 clocks = <&cru ACLK_GPU>;
1324                 clock-names = "clk_mali";
1325                 #cooling-cells = <2>; /* min followed by max */
1326                 operating-points-v2 = <&gpu_opp_table>;
1327                 power-domains = <&power RK3399_PD_GPU>;
1328                 power-off-delay-ms = <200>;
1329                 status = "disabled";
1330
1331                 power_model {
1332                         compatible = "arm,mali-simple-power-model";
1333                         voltage = <900>;
1334                         frequency = <500>;
1335                         static-power = <300>;
1336                         dynamic-power = <1780>;
1337                         ts = <32000 4700 (-80) 2>;
1338                         thermal-zone = "gpu-thermal";
1339                 };
1340         };
1341
1342         gpu_opp_table: gpu_opp_table {
1343                 compatible = "operating-points-v2";
1344                 opp-shared;
1345
1346                 opp@200000000 {
1347                         opp-hz = /bits/ 64 <200000000>;
1348                         opp-microvolt = <900000>;
1349                 };
1350                 opp@300000000 {
1351                         opp-hz = /bits/ 64 <300000000>;
1352                         opp-microvolt = <900000>;
1353                 };
1354                 opp@400000000 {
1355                         opp-hz = /bits/ 64 <400000000>;
1356                         opp-microvolt = <900000>;
1357                 };
1358
1359         };
1360
1361         vopl: vop@ff8f0000 {
1362                 compatible = "rockchip,rk3399-vop-lit";
1363                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1364                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1365                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1366                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1367                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1368                 reset-names = "axi", "ahb", "dclk";
1369                 power-domains = <&power RK3399_PD_VOPL>;
1370                 iommus = <&vopl_mmu>;
1371                 status = "disabled";
1372
1373                 vopl_out: port {
1374                         #address-cells = <1>;
1375                         #size-cells = <0>;
1376
1377                         vopl_out_mipi: endpoint@0 {
1378                                 reg = <0>;
1379                                 remote-endpoint = <&mipi_in_vopl>;
1380                         };
1381
1382                         vopl_out_edp: endpoint@1 {
1383                                 reg = <1>;
1384                                 remote-endpoint = <&edp_in_vopl>;
1385                         };
1386
1387                         vopl_out_hdmi: endpoint@2 {
1388                                 reg = <2>;
1389                                 remote-endpoint = <&hdmi_in_vopl>;
1390                         };
1391                 };
1392         };
1393
1394         vopl_mmu: iommu@ff8f3f00 {
1395                 compatible = "rockchip,iommu";
1396                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1397                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1398                 interrupt-names = "vopl_mmu";
1399                 #iommu-cells = <0>;
1400                 status = "disabled";
1401         };
1402
1403         vopb: vop@ff900000 {
1404                 compatible = "rockchip,rk3399-vop-big";
1405                 reg = <0x0 0xff900000 0x0 0x3efc>;
1406                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1407                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1408                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1409                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1410                 reset-names = "axi", "ahb", "dclk";
1411                 power-domains = <&power RK3399_PD_VOPB>;
1412                 iommus = <&vopb_mmu>;
1413                 status = "disabled";
1414
1415                 vopb_out: port {
1416                         #address-cells = <1>;
1417                         #size-cells = <0>;
1418
1419                         vopb_out_edp: endpoint@0 {
1420                                 reg = <0>;
1421                                 remote-endpoint = <&edp_in_vopb>;
1422                         };
1423
1424                         vopb_out_mipi: endpoint@1 {
1425                                 reg = <1>;
1426                                 remote-endpoint = <&mipi_in_vopb>;
1427                         };
1428
1429                         vopb_out_hdmi: endpoint@2 {
1430                                 reg = <2>;
1431                                 remote-endpoint = <&hdmi_in_vopb>;
1432                         };
1433                 };
1434         };
1435
1436         vopb_mmu: iommu@ff903f00 {
1437                 compatible = "rockchip,iommu";
1438                 reg = <0x0 0xff903f00 0x0 0x100>;
1439                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1440                 interrupt-names = "vopb_mmu";
1441                 #iommu-cells = <0>;
1442                 status = "disabled";
1443         };
1444
1445         hdmi: hdmi@ff940000 {
1446                 compatible = "rockchip,rk3399-dw-hdmi";
1447                 reg = <0x0 0xff940000 0x0 0x20000>;
1448                 reg-io-width = <4>;
1449                 rockchip,grf = <&grf>;
1450                 power-domains = <&power RK3399_PD_HDCP>;
1451                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1452                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1453                 clock-names = "iahb", "isfr", "vpll", "grf";
1454                 status = "disabled";
1455
1456                 ports {
1457                         hdmi_in: port {
1458                                 #address-cells = <1>;
1459                                 #size-cells = <0>;
1460                                 hdmi_in_vopb: endpoint@0 {
1461                                         reg = <0>;
1462                                         remote-endpoint = <&vopb_out_hdmi>;
1463                                 };
1464                                 hdmi_in_vopl: endpoint@1 {
1465                                         reg = <1>;
1466                                         remote-endpoint = <&vopl_out_hdmi>;
1467                                 };
1468                         };
1469                 };
1470         };
1471
1472         mipi_dsi: mipi@ff960000 {
1473                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1474                 reg = <0x0 0xff960000 0x0 0x8000>;
1475                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1476                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1477                          <&cru SCLK_DPHY_TX0_CFG>;
1478                 clock-names = "ref", "pclk", "phy_cfg";
1479                 power-domains = <&power RK3399_PD_VIO>;
1480                 rockchip,grf = <&grf>;
1481                 #address-cells = <1>;
1482                 #size-cells = <0>;
1483                 status = "disabled";
1484
1485                 ports {
1486                         #address-cells = <1>;
1487                         #size-cells = <0>;
1488                         reg = <1>;
1489
1490                         mipi_in: port {
1491                                 #address-cells = <1>;
1492                                 #size-cells = <0>;
1493
1494                                 mipi_in_vopb: endpoint@0 {
1495                                         reg = <0>;
1496                                         remote-endpoint = <&vopb_out_mipi>;
1497                                 };
1498                                 mipi_in_vopl: endpoint@1 {
1499                                         reg = <1>;
1500                                         remote-endpoint = <&vopl_out_mipi>;
1501                                 };
1502                         };
1503                 };
1504         };
1505
1506         edp: edp@ff970000 {
1507                 compatible = "rockchip,rk3399-edp";
1508                 reg = <0x0 0xff970000 0x0 0x8000>;
1509                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1510                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1511                 clock-names = "dp", "pclk";
1512                 resets = <&cru SRST_P_EDP_CTRL>;
1513                 reset-names = "dp";
1514                 rockchip,grf = <&grf>;
1515                 status = "disabled";
1516                 pinctrl-names = "default";
1517                 pinctrl-0 = <&edp_hpd>;
1518
1519                 ports {
1520                         #address-cells = <1>;
1521                         #size-cells = <0>;
1522
1523                         edp_in: port@0 {
1524                                 reg = <0>;
1525                                 #address-cells = <1>;
1526                                 #size-cells = <0>;
1527
1528                                 edp_in_vopb: endpoint@0 {
1529                                         reg = <0>;
1530                                         remote-endpoint = <&vopb_out_edp>;
1531                                 };
1532
1533                                 edp_in_vopl: endpoint@1 {
1534                                         reg = <1>;
1535                                         remote-endpoint = <&vopl_out_edp>;
1536                                 };
1537                         };
1538                 };
1539         };
1540
1541         display_subsystem: display-subsystem {
1542                 compatible = "rockchip,display-subsystem";
1543                 ports = <&vopl_out>, <&vopb_out>;
1544                 status = "disabled";
1545         };
1546
1547         pinctrl: pinctrl {
1548                 compatible = "rockchip,rk3399-pinctrl";
1549                 rockchip,grf = <&grf>;
1550                 rockchip,pmu = <&pmugrf>;
1551                 #address-cells = <0x2>;
1552                 #size-cells = <0x2>;
1553                 ranges;
1554
1555                 gpio0: gpio0@ff720000 {
1556                         compatible = "rockchip,gpio-bank";
1557                         reg = <0x0 0xff720000 0x0 0x100>;
1558                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1559                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1560
1561                         gpio-controller;
1562                         #gpio-cells = <0x2>;
1563
1564                         interrupt-controller;
1565                         #interrupt-cells = <0x2>;
1566                 };
1567
1568                 gpio1: gpio1@ff730000 {
1569                         compatible = "rockchip,gpio-bank";
1570                         reg = <0x0 0xff730000 0x0 0x100>;
1571                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1572                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1573
1574                         gpio-controller;
1575                         #gpio-cells = <0x2>;
1576
1577                         interrupt-controller;
1578                         #interrupt-cells = <0x2>;
1579                 };
1580
1581                 gpio2: gpio2@ff780000 {
1582                         compatible = "rockchip,gpio-bank";
1583                         reg = <0x0 0xff780000 0x0 0x100>;
1584                         clocks = <&cru PCLK_GPIO2>;
1585                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1586
1587                         gpio-controller;
1588                         #gpio-cells = <0x2>;
1589
1590                         interrupt-controller;
1591                         #interrupt-cells = <0x2>;
1592                 };
1593
1594                 gpio3: gpio3@ff788000 {
1595                         compatible = "rockchip,gpio-bank";
1596                         reg = <0x0 0xff788000 0x0 0x100>;
1597                         clocks = <&cru PCLK_GPIO3>;
1598                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1599
1600                         gpio-controller;
1601                         #gpio-cells = <0x2>;
1602
1603                         interrupt-controller;
1604                         #interrupt-cells = <0x2>;
1605                 };
1606
1607                 gpio4: gpio4@ff790000 {
1608                         compatible = "rockchip,gpio-bank";
1609                         reg = <0x0 0xff790000 0x0 0x100>;
1610                         clocks = <&cru PCLK_GPIO4>;
1611                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1612
1613                         gpio-controller;
1614                         #gpio-cells = <0x2>;
1615
1616                         interrupt-controller;
1617                         #interrupt-cells = <0x2>;
1618                 };
1619
1620                 pcfg_pull_up: pcfg-pull-up {
1621                         bias-pull-up;
1622                 };
1623
1624                 pcfg_pull_down: pcfg-pull-down {
1625                         bias-pull-down;
1626                 };
1627
1628                 pcfg_pull_none: pcfg-pull-none {
1629                         bias-disable;
1630                 };
1631
1632                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1633                         bias-disable;
1634                         drive-strength = <12>;
1635                 };
1636
1637                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1638                         bias-pull-up;
1639                         drive-strength = <8>;
1640                 };
1641
1642                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1643                         bias-pull-down;
1644                         drive-strength = <4>;
1645                 };
1646
1647                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1648                         bias-pull-up;
1649                         drive-strength = <2>;
1650                 };
1651
1652                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1653                         bias-pull-down;
1654                         drive-strength = <12>;
1655                 };
1656
1657                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1658                         bias-disable;
1659                         drive-strength = <13>;
1660                 };
1661
1662                 emmc {
1663                         emmc_pwr: emmc-pwr {
1664                                 rockchip,pins =
1665                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1666                         };
1667                 };
1668
1669                 gmac {
1670                         rgmii_pins: rgmii-pins {
1671                                 rockchip,pins =
1672                                         /* mac_txclk */
1673                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1674                                         /* mac_rxclk */
1675                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1676                                         /* mac_mdio */
1677                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1678                                         /* mac_txen */
1679                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1680                                         /* mac_clk */
1681                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1682                                         /* mac_rxdv */
1683                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1684                                         /* mac_mdc */
1685                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1686                                         /* mac_rxd1 */
1687                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1688                                         /* mac_rxd0 */
1689                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1690                                         /* mac_txd1 */
1691                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1692                                         /* mac_txd0 */
1693                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1694                                         /* mac_rxd3 */
1695                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1696                                         /* mac_rxd2 */
1697                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1698                                         /* mac_txd3 */
1699                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1700                                         /* mac_txd2 */
1701                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1702                         };
1703
1704                         rmii_pins: rmii-pins {
1705                                 rockchip,pins =
1706                                         /* mac_mdio */
1707                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1708                                         /* mac_txen */
1709                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1710                                         /* mac_clk */
1711                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1712                                         /* mac_rxer */
1713                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1714                                         /* mac_rxdv */
1715                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1716                                         /* mac_mdc */
1717                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1718                                         /* mac_rxd1 */
1719                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1720                                         /* mac_rxd0 */
1721                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1722                                         /* mac_txd1 */
1723                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1724                                         /* mac_txd0 */
1725                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1726                         };
1727                 };
1728
1729                 i2c0 {
1730                         i2c0_xfer: i2c0-xfer {
1731                                 rockchip,pins =
1732                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1733                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1734                         };
1735                 };
1736
1737                 i2c1 {
1738                         i2c1_xfer: i2c1-xfer {
1739                                 rockchip,pins =
1740                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1741                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1742                         };
1743                 };
1744
1745                 i2c2 {
1746                         i2c2_xfer: i2c2-xfer {
1747                                 rockchip,pins =
1748                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1749                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1750                         };
1751                 };
1752
1753                 i2c3 {
1754                         i2c3_xfer: i2c3-xfer {
1755                                 rockchip,pins =
1756                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1757                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1758                         };
1759
1760                         i2c3_gpio: i2c3_gpio {
1761                                 rockchip,pins =
1762                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1763                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1764                         };
1765
1766                 };
1767
1768                 i2c4 {
1769                         i2c4_xfer: i2c4-xfer {
1770                                 rockchip,pins =
1771                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1772                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1773                         };
1774                 };
1775
1776                 i2c5 {
1777                         i2c5_xfer: i2c5-xfer {
1778                                 rockchip,pins =
1779                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1780                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1781                         };
1782                 };
1783
1784                 i2c6 {
1785                         i2c6_xfer: i2c6-xfer {
1786                                 rockchip,pins =
1787                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1788                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1789                         };
1790                 };
1791
1792                 i2c7 {
1793                         i2c7_xfer: i2c7-xfer {
1794                                 rockchip,pins =
1795                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1796                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1797                         };
1798                 };
1799
1800                 i2c8 {
1801                         i2c8_xfer: i2c8-xfer {
1802                                 rockchip,pins =
1803                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1804                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1805                         };
1806                 };
1807
1808                 i2s0 {
1809                         i2s0_8ch_bus: i2s0-8ch-bus {
1810                                 rockchip,pins =
1811                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1812                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1813                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1814                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1815                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1816                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1817                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1818                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1819                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1820                         };
1821                 };
1822
1823                 i2s1 {
1824                         i2s1_2ch_bus: i2s1-2ch-bus {
1825                                 rockchip,pins =
1826                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1827                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1828                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1829                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1830                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1831                         };
1832                 };
1833
1834                 sdio0 {
1835                         sdio0_bus1: sdio0-bus1 {
1836                                 rockchip,pins =
1837                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1838                         };
1839
1840                         sdio0_bus4: sdio0-bus4 {
1841                                 rockchip,pins =
1842                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1843                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1844                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1845                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1846                         };
1847
1848                         sdio0_cmd: sdio0-cmd {
1849                                 rockchip,pins =
1850                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1851                         };
1852
1853                         sdio0_clk: sdio0-clk {
1854                                 rockchip,pins =
1855                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1856                         };
1857
1858                         sdio0_cd: sdio0-cd {
1859                                 rockchip,pins =
1860                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1861                         };
1862
1863                         sdio0_pwr: sdio0-pwr {
1864                                 rockchip,pins =
1865                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1866                         };
1867
1868                         sdio0_bkpwr: sdio0-bkpwr {
1869                                 rockchip,pins =
1870                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1871                         };
1872
1873                         sdio0_wp: sdio0-wp {
1874                                 rockchip,pins =
1875                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1876                         };
1877
1878                         sdio0_int: sdio0-int {
1879                                 rockchip,pins =
1880                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1881                         };
1882                 };
1883
1884                 sdmmc {
1885                         sdmmc_bus1: sdmmc-bus1 {
1886                                 rockchip,pins =
1887                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1888                         };
1889
1890                         sdmmc_bus4: sdmmc-bus4 {
1891                                 rockchip,pins =
1892                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1893                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1894                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1895                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1896                         };
1897
1898                         sdmmc_clk: sdmmc-clk {
1899                                 rockchip,pins =
1900                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1901                         };
1902
1903                         sdmmc_cmd: sdmmc-cmd {
1904                                 rockchip,pins =
1905                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1906                         };
1907
1908                         sdmmc_cd: sdmcc-cd {
1909                                 rockchip,pins =
1910                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1911                         };
1912
1913                         sdmmc_wp: sdmmc-wp {
1914                                 rockchip,pins =
1915                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1916                         };
1917                 };
1918
1919                 spdif {
1920                         spdif_bus: spdif-bus {
1921                                 rockchip,pins =
1922                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1923                         };
1924
1925                         spdif_bus_1: spdif-bus-1 {
1926                                 rockchip,pins =
1927                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
1928                         };
1929                 };
1930
1931                 spi0 {
1932                         spi0_clk: spi0-clk {
1933                                 rockchip,pins =
1934                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1935                         };
1936                         spi0_cs0: spi0-cs0 {
1937                                 rockchip,pins =
1938                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1939                         };
1940                         spi0_cs1: spi0-cs1 {
1941                                 rockchip,pins =
1942                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1943                         };
1944                         spi0_tx: spi0-tx {
1945                                 rockchip,pins =
1946                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1947                         };
1948                         spi0_rx: spi0-rx {
1949                                 rockchip,pins =
1950                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1951                         };
1952                 };
1953
1954                 spi1 {
1955                         spi1_clk: spi1-clk {
1956                                 rockchip,pins =
1957                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1958                         };
1959                         spi1_cs0: spi1-cs0 {
1960                                 rockchip,pins =
1961                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1962                         };
1963                         spi1_rx: spi1-rx {
1964                                 rockchip,pins =
1965                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1966                         };
1967                         spi1_tx: spi1-tx {
1968                                 rockchip,pins =
1969                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1970                         };
1971                 };
1972
1973                 spi2 {
1974                         spi2_clk: spi2-clk {
1975                                 rockchip,pins =
1976                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1977                         };
1978                         spi2_cs0: spi2-cs0 {
1979                                 rockchip,pins =
1980                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1981                         };
1982                         spi2_rx: spi2-rx {
1983                                 rockchip,pins =
1984                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1985                         };
1986                         spi2_tx: spi2-tx {
1987                                 rockchip,pins =
1988                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1989                         };
1990                 };
1991
1992                 spi3 {
1993                         spi3_clk: spi3-clk {
1994                                 rockchip,pins =
1995                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1996                         };
1997                         spi3_cs0: spi3-cs0 {
1998                                 rockchip,pins =
1999                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2000                         };
2001                         spi3_rx: spi3-rx {
2002                                 rockchip,pins =
2003                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2004                         };
2005                         spi3_tx: spi3-tx {
2006                                 rockchip,pins =
2007                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2008                         };
2009                 };
2010
2011                 spi4 {
2012                         spi4_clk: spi4-clk {
2013                                 rockchip,pins =
2014                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2015                         };
2016                         spi4_cs0: spi4-cs0 {
2017                                 rockchip,pins =
2018                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2019                         };
2020                         spi4_rx: spi4-rx {
2021                                 rockchip,pins =
2022                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2023                         };
2024                         spi4_tx: spi4-tx {
2025                                 rockchip,pins =
2026                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2027                         };
2028                 };
2029
2030                 spi5 {
2031                         spi5_clk: spi5-clk {
2032                                 rockchip,pins =
2033                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2034                         };
2035                         spi5_cs0: spi5-cs0 {
2036                                 rockchip,pins =
2037                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2038                         };
2039                         spi5_rx: spi5-rx {
2040                                 rockchip,pins =
2041                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2042                         };
2043                         spi5_tx: spi5-tx {
2044                                 rockchip,pins =
2045                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2046                         };
2047                 };
2048
2049                 tsadc {
2050                         otp_gpio: otp-gpio {
2051                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2052                         };
2053
2054                         otp_out: otp-out {
2055                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2056                         };
2057                 };
2058
2059                 uart0 {
2060                         uart0_xfer: uart0-xfer {
2061                                 rockchip,pins =
2062                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2063                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2064                         };
2065
2066                         uart0_cts: uart0-cts {
2067                                 rockchip,pins =
2068                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2069                         };
2070
2071                         uart0_rts: uart0-rts {
2072                                 rockchip,pins =
2073                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2074                         };
2075                 };
2076
2077                 uart1 {
2078                         uart1_xfer: uart1-xfer {
2079                                 rockchip,pins =
2080                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2081                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2082                         };
2083                 };
2084
2085                 uart2a {
2086                         uart2a_xfer: uart2a-xfer {
2087                                 rockchip,pins =
2088                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2089                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2090                         };
2091                 };
2092
2093                 uart2b {
2094                         uart2b_xfer: uart2b-xfer {
2095                                 rockchip,pins =
2096                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2097                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2098                         };
2099                 };
2100
2101                 uart2c {
2102                         uart2c_xfer: uart2c-xfer {
2103                                 rockchip,pins =
2104                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2105                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2106                         };
2107                 };
2108
2109                 uart3 {
2110                         uart3_xfer: uart3-xfer {
2111                                 rockchip,pins =
2112                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2113                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2114                         };
2115
2116                         uart3_cts: uart3-cts {
2117                                 rockchip,pins =
2118                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2119                         };
2120
2121                         uart3_rts: uart3-rts {
2122                                 rockchip,pins =
2123                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2124                         };
2125                 };
2126
2127                 uart4 {
2128                         uart4_xfer: uart4-xfer {
2129                                 rockchip,pins =
2130                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2131                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2132                         };
2133                 };
2134
2135                 uarthdcp {
2136                         uarthdcp_xfer: uarthdcp-xfer {
2137                                 rockchip,pins =
2138                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2139                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2140                         };
2141                 };
2142
2143                 pwm0 {
2144                         pwm0_pin: pwm0-pin {
2145                                 rockchip,pins =
2146                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2147                         };
2148
2149                         vop0_pwm_pin: vop0-pwm-pin {
2150                                 rockchip,pins =
2151                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2152                         };
2153                 };
2154
2155                 pwm1 {
2156                         pwm1_pin: pwm1-pin {
2157                                 rockchip,pins =
2158                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2159                         };
2160
2161                         vop1_pwm_pin: vop1-pwm-pin {
2162                                 rockchip,pins =
2163                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2164                         };
2165                 };
2166
2167                 pwm2 {
2168                         pwm2_pin: pwm2-pin {
2169                                 rockchip,pins =
2170                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2171                         };
2172                 };
2173
2174                 pwm3a {
2175                         pwm3a_pin: pwm3a-pin {
2176                                 rockchip,pins =
2177                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2178                         };
2179                 };
2180
2181                 pwm3b {
2182                         pwm3b_pin: pwm3b-pin {
2183                                 rockchip,pins =
2184                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2185                         };
2186                 };
2187
2188                 edp {
2189                         edp_hpd: edp-hpd {
2190                                 rockchip,pins =
2191                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2192                         };
2193                 };
2194
2195                 hdmi {
2196                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2197                                 rockchip,pins =
2198                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2199                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2200                         };
2201
2202                         hdmi_cec: hdmi-cec {
2203                                 rockchip,pins =
2204                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2205                         };
2206                 };
2207
2208                 pcie {
2209                         pcie_clkreqn: pci-clkreqn {
2210                                 rockchip,pins =
2211                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2212                         };
2213
2214                         pcie_clkreqnb: pci-clkreqnb {
2215                                 rockchip,pins =
2216                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2217                         };
2218                 };
2219         };
2220 };