arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/suspend/rockchip-rk3399.h>
  51 #include <dt-bindings/thermal/thermal.h>
  52
  53 #include "rk3399-dram-default-timing.dtsi"
  54
  55 / {
  56         compatible = "rockchip,rk3399";
  57
  58         interrupt-parent = <&gic>;
  59         #address-cells = <2>;
  60         #size-cells = <2>;
  61
  62         aliases {
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 i2c6 = &i2c6;
  70                 i2c7 = &i2c7;
  71                 i2c8 = &i2c8;
  72                 serial0 = &uart0;
  73                 serial1 = &uart1;
  74                 serial2 = &uart2;
  75                 serial3 = &uart3;
  76                 serial4 = &uart4;
  77                 dsi0 = &dsi;
  78                 dsi1 = &dsi1;
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <100>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 120                 };
 121
 122                 cpu_l1: cpu@1 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x1>;
 126                         enable-method = "psci";
 127                         clocks = <&cru ARMCLKL>;
 128                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 129                 };
 130
 131                 cpu_l2: cpu@2 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-a53", "arm,armv8";
 134                         reg = <0x0 0x2>;
 135                         enable-method = "psci";
 136                         clocks = <&cru ARMCLKL>;
 137                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 138                 };
 139
 140                 cpu_l3: cpu@3 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a53", "arm,armv8";
 143                         reg = <0x0 0x3>;
 144                         enable-method = "psci";
 145                         clocks = <&cru ARMCLKL>;
 146                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 147                 };
 148
 149                 cpu_b0: cpu@100 {
 150                         device_type = "cpu";
 151                         compatible = "arm,cortex-a72", "arm,armv8";
 152                         reg = <0x0 0x100>;
 153                         enable-method = "psci";
 154                         #cooling-cells = <2>; /* min followed by max */
 155                         dynamic-power-coefficient = <436>;
 156                         clocks = <&cru ARMCLKB>;
 157                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 158                 };
 159
 160                 cpu_b1: cpu@101 {
 161                         device_type = "cpu";
 162                         compatible = "arm,cortex-a72", "arm,armv8";
 163                         reg = <0x0 0x101>;
 164                         enable-method = "psci";
 165                         clocks = <&cru ARMCLKB>;
 166                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 167                 };
 168
 169                 idle-states {
 170                         entry-method = "psci";
 171
 172                         CPU_SLEEP: cpu-sleep {
 173                                 compatible = "arm,idle-state";
 174                                 local-timer-stop;
 175                                 arm,psci-suspend-param = <0x0010000>;
 176                                 entry-latency-us = <120>;
 177                                 exit-latency-us = <250>;
 178                                 min-residency-us = <900>;
 179                         };
 180
 181                         CLUSTER_SLEEP: cluster-sleep {
 182                                 compatible = "arm,idle-state";
 183                                 local-timer-stop;
 184                                 arm,psci-suspend-param = <0x1010000>;
 185                                 entry-latency-us = <400>;
 186                                 exit-latency-us = <500>;
 187                                 min-residency-us = <2000>;
 188                         };
 189                 };
 190         };
 191
 192         pmu_a53 {
 193                 compatible = "arm,cortex-a53-pmu";
 194                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 195         };
 196
 197         pmu_a72 {
 198                 compatible = "arm,cortex-a72-pmu";
 199                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 200         };
 201
 202         psci {
 203                 compatible = "arm,psci-1.0";
 204                 method = "smc";
 205         };
 206
 207         cpuinfo {
 208                 compatible = "rockchip,cpuinfo";
 209                 nvmem-cells = <&efuse_id>;
 210                 nvmem-cell-names = "id";
 211         };
 212
 213         timer {
 214                 compatible = "arm,armv8-timer";
 215                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 216                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 217                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 218                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 219         };
 220
 221         xin24m: xin24m {
 222                 compatible = "fixed-clock";
 223                 clock-frequency = <24000000>;
 224                 clock-output-names = "xin24m";
 225                 #clock-cells = <0>;
 226         };
 227
 228         dummy_cpll: dummy_cpll {
 229                 compatible = "fixed-clock";
 230                 clock-frequency = <0>;
 231                 clock-output-names = "dummy_cpll";
 232                 #clock-cells = <0>;
 233         };
 234
 235         dummy_vpll: dummy_vpll {
 236                 compatible = "fixed-clock";
 237                 clock-frequency = <0>;
 238                 clock-output-names = "dummy_vpll";
 239                 #clock-cells = <0>;
 240         };
 241
 242         amba {
 243                 compatible = "arm,amba-bus";
 244                 #address-cells = <2>;
 245                 #size-cells = <2>;
 246                 ranges;
 247
 248                 dmac_bus: dma-controller@ff6d0000 {
 249                         compatible = "arm,pl330", "arm,primecell";
 250                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 251                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 252                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 253                         #dma-cells = <1>;
 254                         clocks = <&cru ACLK_DMAC0_PERILP>;
 255                         clock-names = "apb_pclk";
 256                         peripherals-req-type-burst;
 257                 };
 258
 259                 dmac_peri: dma-controller@ff6e0000 {
 260                         compatible = "arm,pl330", "arm,primecell";
 261                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 262                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 263                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 264                         #dma-cells = <1>;
 265                         clocks = <&cru ACLK_DMAC1_PERILP>;
 266                         clock-names = "apb_pclk";
 267                         peripherals-req-type-burst;
 268                 };
 269         };
 270
 271         gmac: ethernet@fe300000 {
 272                 compatible = "rockchip,rk3399-gmac";
 273                 reg = <0x0 0xfe300000 0x0 0x10000>;
 274                 rockchip,grf = <&grf>;
 275                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 276                 interrupt-names = "macirq";
 277                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 278                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 279                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 280                          <&cru PCLK_GMAC>;
 281                 clock-names = "stmmaceth", "mac_clk_rx",
 282                               "mac_clk_tx", "clk_mac_ref",
 283                               "clk_mac_refout", "aclk_mac",
 284                               "pclk_mac";
 285                 resets = <&cru SRST_A_GMAC>;
 286                 reset-names = "stmmaceth";
 287                 power-domains = <&power RK3399_PD_GMAC>;
 288                 status = "disabled";
 289         };
 290
 291         sdio0: dwmmc@fe310000 {
 292                 compatible = "rockchip,rk3399-dw-mshc",
 293                              "rockchip,rk3288-dw-mshc";
 294                 reg = <0x0 0xfe310000 0x0 0x4000>;
 295                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 296                 clock-freq-min-max = <400000 150000000>;
 297                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 298                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 299                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 300                 fifo-depth = <0x100>;
 301                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 302                 status = "disabled";
 303         };
 304
 305         sdmmc: dwmmc@fe320000 {
 306                 compatible = "rockchip,rk3399-dw-mshc",
 307                              "rockchip,rk3288-dw-mshc";
 308                 reg = <0x0 0xfe320000 0x0 0x4000>;
 309                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 310                 clock-freq-min-max = <400000 150000000>;
 311                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 312                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 313                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 314                 fifo-depth = <0x100>;
 315                 power-domains = <&power RK3399_PD_SD>;
 316                 status = "disabled";
 317         };
 318
 319         sdhci: sdhci@fe330000 {
 320                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 321                 reg = <0x0 0xfe330000 0x0 0x10000>;
 322                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 323                 arasan,soc-ctl-syscon = <&grf>;
 324                 assigned-clocks = <&cru SCLK_EMMC>;
 325                 assigned-clock-rates = <200000000>;
 326                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 327                 clock-names = "clk_xin", "clk_ahb";
 328                 clock-output-names = "emmc_cardclock";
 329                 #clock-cells = <0>;
 330                 phys = <&emmc_phy>;
 331                 phy-names = "phy_arasan";
 332                 power-domains = <&power RK3399_PD_EMMC>;
 333                 status = "disabled";
 334         };
 335
 336         usb_host0_ehci: usb@fe380000 {
 337                 compatible = "generic-ehci";
 338                 reg = <0x0 0xfe380000 0x0 0x20000>;
 339                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 340                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 341                          <&cru SCLK_USBPHY0_480M_SRC>;
 342                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 343                 phys = <&u2phy0_host>;
 344                 phy-names = "usb";
 345                 power-domains = <&power RK3399_PD_PERIHP>;
 346                 status = "disabled";
 347         };
 348
 349         usb_host0_ohci: usb@fe3a0000 {
 350                 compatible = "generic-ohci";
 351                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 352                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 353                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 354                          <&cru SCLK_USBPHY0_480M_SRC>;
 355                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 356                 phys = <&u2phy0_host>;
 357                 phy-names = "usb";
 358                 power-domains = <&power RK3399_PD_PERIHP>;
 359                 status = "disabled";
 360         };
 361
 362         usb_host1_ehci: usb@fe3c0000 {
 363                 compatible = "generic-ehci";
 364                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 365                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 366                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 367                          <&cru SCLK_USBPHY1_480M_SRC>;
 368                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 369                 phys = <&u2phy1_host>;
 370                 phy-names = "usb";
 371                 power-domains = <&power RK3399_PD_PERIHP>;
 372                 status = "disabled";
 373         };
 374
 375         usb_host1_ohci: usb@fe3e0000 {
 376                 compatible = "generic-ohci";
 377                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 378                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 379                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 380                          <&cru SCLK_USBPHY1_480M_SRC>;
 381                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 382                 phys = <&u2phy1_host>;
 383                 phy-names = "usb";
 384                 power-domains = <&power RK3399_PD_PERIHP>;
 385                 status = "disabled";
 386         };
 387
 388         usbdrd3_0: usb@fe800000 {
 389                 compatible = "rockchip,rk3399-dwc3";
 390                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 391                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 392                 clock-names = "ref_clk", "suspend_clk",
 393                               "bus_clk", "grf_clk";
 394                 power-domains = <&power RK3399_PD_USB3>;
 395                 resets = <&cru SRST_A_USB3_OTG0>;
 396                 reset-names = "usb3-otg";
 397                 #address-cells = <2>;
 398                 #size-cells = <2>;
 399                 ranges;
 400                 status = "disabled";
 401                 usbdrd_dwc3_0: dwc3@fe800000 {
 402                         compatible = "snps,dwc3";
 403                         reg = <0x0 0xfe800000 0x0 0x100000>;
 404                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 405                         dr_mode = "otg";
 406                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 407                         phy-names = "usb2-phy", "usb3-phy";
 408                         phy_type = "utmi_wide";
 409                         snps,dis_enblslpm_quirk;
 410                         snps,dis-u2-freeclk-exists-quirk;
 411                         snps,dis_u2_susphy_quirk;
 412                         snps,dis-del-phy-power-chg-quirk;
 413                         snps,tx-ipgap-linecheck-dis-quirk;
 414                         snps,xhci-slow-suspend-quirk;
 415                         snps,usb3-warm-reset-on-resume-quirk;
 416                         status = "disabled";
 417                 };
 418         };
 419
 420         usbdrd3_1: usb@fe900000 {
 421                 compatible = "rockchip,rk3399-dwc3";
 422                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 423                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 424                 clock-names = "ref_clk", "suspend_clk",
 425                               "bus_clk", "grf_clk";
 426                 power-domains = <&power RK3399_PD_USB3>;
 427                 resets = <&cru SRST_A_USB3_OTG1>;
 428                 reset-names = "usb3-otg";
 429                 #address-cells = <2>;
 430                 #size-cells = <2>;
 431                 ranges;
 432                 status = "disabled";
 433                 usbdrd_dwc3_1: dwc3@fe900000 {
 434                         compatible = "snps,dwc3";
 435                         reg = <0x0 0xfe900000 0x0 0x100000>;
 436                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 437                         dr_mode = "host";
 438                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 439                         phy-names = "usb2-phy", "usb3-phy";
 440                         phy_type = "utmi_wide";
 441                         snps,dis_enblslpm_quirk;
 442                         snps,dis-u2-freeclk-exists-quirk;
 443                         snps,dis_u2_susphy_quirk;
 444                         snps,dis-del-phy-power-chg-quirk;
 445                         snps,tx-ipgap-linecheck-dis-quirk;
 446                         snps,xhci-slow-suspend-quirk;
 447                         snps,usb3-warm-reset-on-resume-quirk;
 448                         status = "disabled";
 449                 };
 450         };
 451
 452         cdn_dp: dp@fec00000 {
 453                 compatible = "rockchip,rk3399-cdn-dp";
 454                 reg = <0x0 0xfec00000 0x0 0x100000>;
 455                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 456                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 457                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 458                 clock-names = "core-clk", "pclk", "spdif", "grf";
 459                 assigned-clocks = <&cru SCLK_DP_CORE>;
 460                 assigned-clock-rates = <100000000>;
 461                 power-domains = <&power RK3399_PD_HDCP>;
 462                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 463                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 464                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 465                 reset-names = "spdif", "dptx", "apb", "core";
 466                 rockchip,grf = <&grf>;
 467                 #address-cells = <1>;
 468                 #size-cells = <0>;
 469                 #sound-dai-cells = <1>;
 470                 status = "disabled";
 471
 472                 ports {
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475
 476                         dp_in: port {
 477                                 #address-cells = <1>;
 478                                 #size-cells = <0>;
 479                                 dp_in_vopb: endpoint@0 {
 480                                         reg = <0>;
 481                                         remote-endpoint = <&vopb_out_dp>;
 482                                 };
 483
 484                                 dp_in_vopl: endpoint@1 {
 485                                         reg = <1>;
 486                                         remote-endpoint = <&vopl_out_dp>;
 487                                 };
 488                         };
 489                 };
 490         };
 491
 492         gic: interrupt-controller@fee00000 {
 493                 compatible = "arm,gic-v3";
 494                 #interrupt-cells = <4>;
 495                 #address-cells = <2>;
 496                 #size-cells = <2>;
 497                 ranges;
 498                 interrupt-controller;
 499
 500                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 501                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 502                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 503                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 504                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 505                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 506                 its: interrupt-controller@fee20000 {
 507                         compatible = "arm,gic-v3-its";
 508                         msi-controller;
 509                         reg = <0x0 0xfee20000 0x0 0x20000>;
 510                 };
 511
 512                 ppi-partitions {
 513                         ppi_cluster0: interrupt-partition-0 {
 514                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 515                         };
 516
 517                         ppi_cluster1: interrupt-partition-1 {
 518                                 affinity = <&cpu_b0 &cpu_b1>;
 519                         };
 520                 };
 521         };
 522
 523         saradc: saradc@ff100000 {
 524                 compatible = "rockchip,rk3399-saradc";
 525                 reg = <0x0 0xff100000 0x0 0x100>;
 526                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 527                 #io-channel-cells = <1>;
 528                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 529                 clock-names = "saradc", "apb_pclk";
 530                 resets = <&cru SRST_P_SARADC>;
 531                 reset-names = "saradc-apb";
 532                 status = "disabled";
 533         };
 534
 535         i2c0: i2c@ff3c0000 {
 536                 compatible = "rockchip,rk3399-i2c";
 537                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 538                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 539                 clock-names = "i2c", "pclk";
 540                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 541                 pinctrl-names = "default";
 542                 pinctrl-0 = <&i2c0_xfer>;
 543                 #address-cells = <1>;
 544                 #size-cells = <0>;
 545                 status = "disabled";
 546         };
 547
 548         i2c1: i2c@ff110000 {
 549                 compatible = "rockchip,rk3399-i2c";
 550                 reg = <0x0 0xff110000 0x0 0x1000>;
 551                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 552                 clock-names = "i2c", "pclk";
 553                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 554                 pinctrl-names = "default";
 555                 pinctrl-0 = <&i2c1_xfer>;
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 status = "disabled";
 559         };
 560
 561         i2c2: i2c@ff120000 {
 562                 compatible = "rockchip,rk3399-i2c";
 563                 reg = <0x0 0xff120000 0x0 0x1000>;
 564                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 565                 clock-names = "i2c", "pclk";
 566                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 567                 pinctrl-names = "default";
 568                 pinctrl-0 = <&i2c2_xfer>;
 569                 #address-cells = <1>;
 570                 #size-cells = <0>;
 571                 status = "disabled";
 572         };
 573
 574         i2c3: i2c@ff130000 {
 575                 compatible = "rockchip,rk3399-i2c";
 576                 reg = <0x0 0xff130000 0x0 0x1000>;
 577                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 578                 clock-names = "i2c", "pclk";
 579                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&i2c3_xfer>;
 582                 #address-cells = <1>;
 583                 #size-cells = <0>;
 584                 status = "disabled";
 585         };
 586
 587         i2c5: i2c@ff140000 {
 588                 compatible = "rockchip,rk3399-i2c";
 589                 reg = <0x0 0xff140000 0x0 0x1000>;
 590                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 591                 clock-names = "i2c", "pclk";
 592                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 593                 pinctrl-names = "default";
 594                 pinctrl-0 = <&i2c5_xfer>;
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 status = "disabled";
 598         };
 599
 600         i2c6: i2c@ff150000 {
 601                 compatible = "rockchip,rk3399-i2c";
 602                 reg = <0x0 0xff150000 0x0 0x1000>;
 603                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 604                 clock-names = "i2c", "pclk";
 605                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 606                 pinctrl-names = "default";
 607                 pinctrl-0 = <&i2c6_xfer>;
 608                 #address-cells = <1>;
 609                 #size-cells = <0>;
 610                 status = "disabled";
 611         };
 612
 613         i2c7: i2c@ff160000 {
 614                 compatible = "rockchip,rk3399-i2c";
 615                 reg = <0x0 0xff160000 0x0 0x1000>;
 616                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 617                 clock-names = "i2c", "pclk";
 618                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&i2c7_xfer>;
 621                 #address-cells = <1>;
 622                 #size-cells = <0>;
 623                 status = "disabled";
 624         };
 625
 626         uart0: serial@ff180000 {
 627                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 628                 reg = <0x0 0xff180000 0x0 0x100>;
 629                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 630                 clock-names = "baudclk", "apb_pclk";
 631                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 632                 reg-shift = <2>;
 633                 reg-io-width = <4>;
 634                 pinctrl-names = "default";
 635                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 636                 status = "disabled";
 637         };
 638
 639         uart1: serial@ff190000 {
 640                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 641                 reg = <0x0 0xff190000 0x0 0x100>;
 642                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 643                 clock-names = "baudclk", "apb_pclk";
 644                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 645                 reg-shift = <2>;
 646                 reg-io-width = <4>;
 647                 pinctrl-names = "default";
 648                 pinctrl-0 = <&uart1_xfer>;
 649                 status = "disabled";
 650         };
 651
 652         uart2: serial@ff1a0000 {
 653                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 654                 reg = <0x0 0xff1a0000 0x0 0x100>;
 655                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 656                 clock-names = "baudclk", "apb_pclk";
 657                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 658                 reg-shift = <2>;
 659                 reg-io-width = <4>;
 660                 pinctrl-names = "default";
 661                 pinctrl-0 = <&uart2c_xfer>;
 662                 status = "disabled";
 663         };
 664
 665         uart3: serial@ff1b0000 {
 666                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 667                 reg = <0x0 0xff1b0000 0x0 0x100>;
 668                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 669                 clock-names = "baudclk", "apb_pclk";
 670                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 671                 reg-shift = <2>;
 672                 reg-io-width = <4>;
 673                 pinctrl-names = "default";
 674                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 675                 status = "disabled";
 676         };
 677
 678         spi0: spi@ff1c0000 {
 679                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 680                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 681                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 682                 clock-names = "spiclk", "apb_pclk";
 683                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 684                 pinctrl-names = "default";
 685                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 686                 #address-cells = <1>;
 687                 #size-cells = <0>;
 688                 status = "disabled";
 689         };
 690
 691         spi1: spi@ff1d0000 {
 692                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 693                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 694                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 695                 clock-names = "spiclk", "apb_pclk";
 696                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 697                 pinctrl-names = "default";
 698                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 699                 #address-cells = <1>;
 700                 #size-cells = <0>;
 701                 status = "disabled";
 702         };
 703
 704         spi2: spi@ff1e0000 {
 705                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 706                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 707                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 708                 clock-names = "spiclk", "apb_pclk";
 709                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 710                 pinctrl-names = "default";
 711                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 712                 #address-cells = <1>;
 713                 #size-cells = <0>;
 714                 status = "disabled";
 715         };
 716
 717         spi4: spi@ff1f0000 {
 718                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 719                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 720                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 721                 clock-names = "spiclk", "apb_pclk";
 722                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 723                 pinctrl-names = "default";
 724                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 725                 #address-cells = <1>;
 726                 #size-cells = <0>;
 727                 status = "disabled";
 728         };
 729
 730         spi5: spi@ff200000 {
 731                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 732                 reg = <0x0 0xff200000 0x0 0x1000>;
 733                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 734                 clock-names = "spiclk", "apb_pclk";
 735                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 736                 pinctrl-names = "default";
 737                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 738                 #address-cells = <1>;
 739                 #size-cells = <0>;
 740                 status = "disabled";
 741         };
 742
 743         thermal_zones: thermal-zones {
 744                 soc_thermal: soc-thermal {
 745                         polling-delay-passive = <20>; /* milliseconds */
 746                         polling-delay = <1000>; /* milliseconds */
 747                         sustainable-power = <1000>; /* milliwatts */
 748
 749                         thermal-sensors = <&tsadc 0>;
 750
 751                         trips {
 752                                 threshold: trip-point@0 {
 753                                         temperature = <70000>; /* millicelsius */
 754                                         hysteresis = <2000>; /* millicelsius */
 755                                         type = "passive";
 756                                 };
 757                                 target: trip-point@1 {
 758                                         temperature = <85000>; /* millicelsius */
 759                                         hysteresis = <2000>; /* millicelsius */
 760                                         type = "passive";
 761                                 };
 762                                 soc_crit: soc-crit {
 763                                         temperature = <95000>; /* millicelsius */
 764                                         hysteresis = <2000>; /* millicelsius */
 765                                         type = "critical";
 766                                 };
 767                         };
 768
 769                         cooling-maps {
 770                                 map0 {
 771                                         trip = <&target>;
 772                                         cooling-device =
 773                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 774                                         contribution = <4096>;
 775                                 };
 776                                 map1 {
 777                                         trip = <&target>;
 778                                         cooling-device =
 779                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 780                                         contribution = <1024>;
 781                                 };
 782                                 map2 {
 783                                         trip = <&target>;
 784                                         cooling-device =
 785                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 786                                         contribution = <4096>;
 787                                 };
 788                         };
 789                 };
 790
 791                 gpu_thermal: gpu-thermal {
 792                         polling-delay-passive = <100>; /* milliseconds */
 793                         polling-delay = <1000>; /* milliseconds */
 794
 795                         thermal-sensors = <&tsadc 1>;
 796                 };
 797         };
 798
 799         tsadc: tsadc@ff260000 {
 800                 compatible = "rockchip,rk3399-tsadc";
 801                 reg = <0x0 0xff260000 0x0 0x100>;
 802                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 803                 rockchip,grf = <&grf>;
 804                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 805                 clock-names = "tsadc", "apb_pclk";
 806                 assigned-clocks = <&cru SCLK_TSADC>;
 807                 assigned-clock-rates = <750000>;
 808                 resets = <&cru SRST_TSADC>;
 809                 reset-names = "tsadc-apb";
 810                 pinctrl-names = "init", "default", "sleep";
 811                 pinctrl-0 = <&otp_gpio>;
 812                 pinctrl-1 = <&otp_out>;
 813                 pinctrl-2 = <&otp_gpio>;
 814                 #thermal-sensor-cells = <1>;
 815                 rockchip,hw-tshut-temp = <95000>;
 816                 status = "disabled";
 817         };
 818
 819         qos_emmc: qos@ffa58000 {
 820                 compatible = "syscon";
 821                 reg = <0x0 0xffa58000 0x0 0x20>;
 822         };
 823
 824         qos_gmac: qos@ffa5c000 {
 825                 compatible = "syscon";
 826                 reg = <0x0 0xffa5c000 0x0 0x20>;
 827         };
 828
 829         qos_pcie: qos@ffa60080 {
 830                 compatible = "syscon";
 831                 reg = <0x0 0xffa60080 0x0 0x20>;
 832         };
 833
 834         qos_usb_host0: qos@ffa60100 {
 835                 compatible = "syscon";
 836                 reg = <0x0 0xffa60100 0x0 0x20>;
 837         };
 838
 839         qos_usb_host1: qos@ffa60180 {
 840                 compatible = "syscon";
 841                 reg = <0x0 0xffa60180 0x0 0x20>;
 842         };
 843
 844         qos_usb_otg0: qos@ffa70000 {
 845                 compatible = "syscon";
 846                 reg = <0x0 0xffa70000 0x0 0x20>;
 847         };
 848
 849         qos_usb_otg1: qos@ffa70080 {
 850                 compatible = "syscon";
 851                 reg = <0x0 0xffa70080 0x0 0x20>;
 852         };
 853
 854         qos_sd: qos@ffa74000 {
 855                 compatible = "syscon";
 856                 reg = <0x0 0xffa74000 0x0 0x20>;
 857         };
 858
 859         qos_sdioaudio: qos@ffa76000 {
 860                 compatible = "syscon";
 861                 reg = <0x0 0xffa76000 0x0 0x20>;
 862         };
 863
 864         qos_hdcp: qos@ffa90000 {
 865                 compatible = "syscon";
 866                 reg = <0x0 0xffa90000 0x0 0x20>;
 867         };
 868
 869         qos_iep: qos@ffa98000 {
 870                 compatible = "syscon";
 871                 reg = <0x0 0xffa98000 0x0 0x20>;
 872         };
 873
 874         qos_isp0_m0: qos@ffaa0000 {
 875                 compatible = "syscon";
 876                 reg = <0x0 0xffaa0000 0x0 0x20>;
 877         };
 878
 879         qos_isp0_m1: qos@ffaa0080 {
 880                 compatible = "syscon";
 881                 reg = <0x0 0xffaa0080 0x0 0x20>;
 882         };
 883
 884         qos_isp1_m0: qos@ffaa8000 {
 885                 compatible = "syscon";
 886                 reg = <0x0 0xffaa8000 0x0 0x20>;
 887         };
 888
 889         qos_isp1_m1: qos@ffaa8080 {
 890                 compatible = "syscon";
 891                 reg = <0x0 0xffaa8080 0x0 0x20>;
 892         };
 893
 894         qos_rga_r: qos@ffab0000 {
 895                 compatible = "syscon";
 896                 reg = <0x0 0xffab0000 0x0 0x20>;
 897         };
 898
 899         qos_rga_w: qos@ffab0080 {
 900                 compatible = "syscon";
 901                 reg = <0x0 0xffab0080 0x0 0x20>;
 902         };
 903
 904         qos_video_m0: qos@ffab8000 {
 905                 compatible = "syscon";
 906                 reg = <0x0 0xffab8000 0x0 0x20>;
 907         };
 908
 909         qos_video_m1_r: qos@ffac0000 {
 910                 compatible = "syscon";
 911                 reg = <0x0 0xffac0000 0x0 0x20>;
 912         };
 913
 914         qos_video_m1_w: qos@ffac0080 {
 915                 compatible = "syscon";
 916                 reg = <0x0 0xffac0080 0x0 0x20>;
 917         };
 918
 919         qos_vop_big_r: qos@ffac8000 {
 920                 compatible = "syscon";
 921                 reg = <0x0 0xffac8000 0x0 0x20>;
 922         };
 923
 924         qos_vop_big_w: qos@ffac8080 {
 925                 compatible = "syscon";
 926                 reg = <0x0 0xffac8080 0x0 0x20>;
 927         };
 928
 929         qos_vop_little: qos@ffad0000 {
 930                 compatible = "syscon";
 931                 reg = <0x0 0xffad0000 0x0 0x20>;
 932         };
 933
 934         qos_perihp: qos@ffad8080 {
 935                 compatible = "syscon";
 936                 reg = <0x0 0xffad8080 0x0 0x20>;
 937         };
 938
 939         qos_gpu: qos@ffae0000 {
 940                 compatible = "syscon";
 941                 reg = <0x0 0xffae0000 0x0 0x20>;
 942         };
 943
 944         pmu: power-management@ff310000 {
 945                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 946                 reg = <0x0 0xff310000 0x0 0x1000>;
 947
 948                 /*
 949                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 950                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 951                  * Some of the power domains are grouped together for every
 952                  * voltage domain.
 953                  * The detail contents as below.
 954                  */
 955                 power: power-controller {
 956                         compatible = "rockchip,rk3399-power-controller";
 957                         #power-domain-cells = <1>;
 958                         #address-cells = <1>;
 959                         #size-cells = <0>;
 960
 961                         /* These power domains are grouped by VD_CENTER */
 962                         pd_iep@RK3399_PD_IEP {
 963                                 reg = <RK3399_PD_IEP>;
 964                                 clocks = <&cru ACLK_IEP>,
 965                                          <&cru HCLK_IEP>;
 966                                 pm_qos = <&qos_iep>;
 967                         };
 968                         pd_rga@RK3399_PD_RGA {
 969                                 reg = <RK3399_PD_RGA>;
 970                                 clocks = <&cru ACLK_RGA>,
 971                                          <&cru HCLK_RGA>;
 972                                 pm_qos = <&qos_rga_r>,
 973                                          <&qos_rga_w>;
 974                         };
 975                         pd_vcodec@RK3399_PD_VCODEC {
 976                                 reg = <RK3399_PD_VCODEC>;
 977                                 clocks = <&cru ACLK_VCODEC>,
 978                                          <&cru HCLK_VCODEC>;
 979                                 pm_qos = <&qos_video_m0>;
 980                         };
 981                         pd_vdu@RK3399_PD_VDU {
 982                                 reg = <RK3399_PD_VDU>;
 983                                 clocks = <&cru ACLK_VDU>,
 984                                          <&cru HCLK_VDU>;
 985                                 pm_qos = <&qos_video_m1_r>,
 986                                          <&qos_video_m1_w>;
 987                         };
 988
 989                         /* These power domains are grouped by VD_GPU */
 990                         pd_gpu@RK3399_PD_GPU {
 991                                 reg = <RK3399_PD_GPU>;
 992                                 clocks = <&cru ACLK_GPU>;
 993                                 pm_qos = <&qos_gpu>;
 994                         };
 995
 996                         /* These power domains are grouped by VD_LOGIC */
 997                         pd_edp@RK3399_PD_EDP {
 998                                 reg = <RK3399_PD_EDP>;
 999                                 clocks = <&cru PCLK_EDP_CTRL>;
1000                         };
1001                         pd_emmc@RK3399_PD_EMMC {
1002                                 reg = <RK3399_PD_EMMC>;
1003                                 clocks = <&cru ACLK_EMMC>;
1004                                 pm_qos = <&qos_emmc>;
1005                         };
1006                         pd_gmac@RK3399_PD_GMAC {
1007                                 reg = <RK3399_PD_GMAC>;
1008                                 clocks = <&cru ACLK_GMAC>,
1009                                          <&cru PCLK_GMAC>;
1010                                 pm_qos = <&qos_gmac>;
1011                         };
1012                         pd_perihp@RK3399_PD_PERIHP {
1013                                 reg = <RK3399_PD_PERIHP>;
1014                                 #address-cells = <1>;
1015                                 #size-cells = <0>;
1016                                 clocks = <&cru ACLK_PERIHP>;
1017                                 pm_qos = <&qos_perihp>,
1018                                          <&qos_pcie>,
1019                                          <&qos_usb_host0>,
1020                                          <&qos_usb_host1>;
1021
1022                                 pd_sd@RK3399_PD_SD {
1023                                         reg = <RK3399_PD_SD>;
1024                                         clocks = <&cru HCLK_SDMMC>,
1025                                                  <&cru SCLK_SDMMC>;
1026                                         pm_qos = <&qos_sd>;
1027                                 };
1028                         };
1029                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1030                                 reg = <RK3399_PD_SDIOAUDIO>;
1031                                 clocks = <&cru HCLK_SDIO>;
1032                                 pm_qos = <&qos_sdioaudio>;
1033                         };
1034                         pd_usb3@RK3399_PD_USB3 {
1035                                 reg = <RK3399_PD_USB3>;
1036                                 clocks = <&cru ACLK_USB3>;
1037                                 pm_qos = <&qos_usb_otg0>,
1038                                          <&qos_usb_otg1>;
1039                         };
1040                         pd_vio@RK3399_PD_VIO {
1041                                 reg = <RK3399_PD_VIO>;
1042                                 #address-cells = <1>;
1043                                 #size-cells = <0>;
1044
1045                                 pd_hdcp@RK3399_PD_HDCP {
1046                                         reg = <RK3399_PD_HDCP>;
1047                                         clocks = <&cru ACLK_HDCP>,
1048                                                  <&cru HCLK_HDCP>,
1049                                                  <&cru PCLK_HDCP>;
1050                                         pm_qos = <&qos_hdcp>;
1051                                 };
1052                                 pd_isp0@RK3399_PD_ISP0 {
1053                                         reg = <RK3399_PD_ISP0>;
1054                                         clocks = <&cru ACLK_ISP0>,
1055                                                  <&cru HCLK_ISP0>;
1056                                         pm_qos = <&qos_isp0_m0>,
1057                                                  <&qos_isp0_m1>;
1058                                 };
1059                                 pd_isp1@RK3399_PD_ISP1 {
1060                                         reg = <RK3399_PD_ISP1>;
1061                                         clocks = <&cru ACLK_ISP1>,
1062                                                  <&cru HCLK_ISP1>;
1063                                         pm_qos = <&qos_isp1_m0>,
1064                                                  <&qos_isp1_m1>;
1065                                 };
1066                                 pd_tcpc0@RK3399_PD_TCPC0 {
1067                                         reg = <RK3399_PD_TCPD0>;
1068                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1069                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1070                                 };
1071                                 pd_tcpc1@RK3399_PD_TCPC1 {
1072                                         reg = <RK3399_PD_TCPD1>;
1073                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1074                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1075                                 };
1076                                 pd_vo@RK3399_PD_VO {
1077                                         reg = <RK3399_PD_VO>;
1078                                         #address-cells = <1>;
1079                                         #size-cells = <0>;
1080
1081                                         pd_vopb@RK3399_PD_VOPB {
1082                                                 reg = <RK3399_PD_VOPB>;
1083                                                 clocks = <&cru ACLK_VOP0>,
1084                                                          <&cru HCLK_VOP0>;
1085                                                 pm_qos = <&qos_vop_big_r>,
1086                                                          <&qos_vop_big_w>;
1087                                         };
1088                                         pd_vopl@RK3399_PD_VOPL {
1089                                                 reg = <RK3399_PD_VOPL>;
1090                                                 clocks = <&cru ACLK_VOP1>,
1091                                                          <&cru HCLK_VOP1>;
1092                                                 pm_qos = <&qos_vop_little>;
1093                                         };
1094                                 };
1095                         };
1096                 };
1097         };
1098
1099         pmugrf: syscon@ff320000 {
1100                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1101                 reg = <0x0 0xff320000 0x0 0x1000>;
1102                 #address-cells = <1>;
1103                 #size-cells = <1>;
1104
1105                 pmu_io_domains: io-domains {
1106                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1107                         status = "disabled";
1108                 };
1109
1110                 reboot-mode {
1111                         compatible = "syscon-reboot-mode";
1112                         offset = <0x300>;
1113                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
1114                         mode-charge = <BOOT_CHARGING>;
1115                         mode-fastboot = <BOOT_FASTBOOT>;
1116                         mode-loader = <BOOT_BL_DOWNLOAD>;
1117                         mode-normal = <BOOT_NORMAL>;
1118                         mode-recovery = <BOOT_RECOVERY>;
1119                         mode-ums = <BOOT_UMS>;
1120                 };
1121
1122                 pmu_pvtm: pmu-pvtm {
1123                         compatible = "rockchip,rk3399-pmu-pvtm";
1124                         clocks = <&pmucru SCLK_PVTM_PMU>;
1125                         clock-names = "pmu";
1126                         status = "disabled";
1127                 };
1128         };
1129
1130         spi3: spi@ff350000 {
1131                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1132                 reg = <0x0 0xff350000 0x0 0x1000>;
1133                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1134                 clock-names = "spiclk", "apb_pclk";
1135                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1136                 pinctrl-names = "default";
1137                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1138                 #address-cells = <1>;
1139                 #size-cells = <0>;
1140                 status = "disabled";
1141         };
1142
1143         uart4: serial@ff370000 {
1144                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1145                 reg = <0x0 0xff370000 0x0 0x100>;
1146                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1147                 clock-names = "baudclk", "apb_pclk";
1148                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1149                 reg-shift = <2>;
1150                 reg-io-width = <4>;
1151                 pinctrl-names = "default";
1152                 pinctrl-0 = <&uart4_xfer>;
1153                 status = "disabled";
1154         };
1155
1156         i2c4: i2c@ff3d0000 {
1157                 compatible = "rockchip,rk3399-i2c";
1158                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1159                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1160                 clock-names = "i2c", "pclk";
1161                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1162                 pinctrl-names = "default";
1163                 pinctrl-0 = <&i2c4_xfer>;
1164                 #address-cells = <1>;
1165                 #size-cells = <0>;
1166                 status = "disabled";
1167         };
1168
1169         i2c8: i2c@ff3e0000 {
1170                 compatible = "rockchip,rk3399-i2c";
1171                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1172                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1173                 clock-names = "i2c", "pclk";
1174                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1175                 pinctrl-names = "default";
1176                 pinctrl-0 = <&i2c8_xfer>;
1177                 #address-cells = <1>;
1178                 #size-cells = <0>;
1179                 status = "disabled";
1180         };
1181
1182         pcie_phy: phy@e220 {
1183                 compatible = "rockchip,rk3399-pcie-phy";
1184                 #phy-cells = <0>;
1185                 rockchip,grf = <&grf>;
1186                 clocks = <&cru SCLK_PCIEPHY_REF>;
1187                 clock-names = "refclk";
1188                 resets = <&cru SRST_PCIEPHY>;
1189                 reset-names = "phy";
1190                 status = "disabled";
1191         };
1192
1193         pcie0: pcie@f8000000 {
1194                 compatible = "rockchip,rk3399-pcie";
1195                 #address-cells = <3>;
1196                 #size-cells = <2>;
1197                 aspm-no-l0s;
1198                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1199                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1200                 clock-names = "aclk", "aclk-perf",
1201                               "hclk", "pm";
1202                 bus-range = <0x0 0x1>;
1203                 max-link-speed = <1>;
1204                 linux,pci-domain = <0>;
1205                 msi-map = <0x0 &its 0x0 0x1000>;
1206                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1207                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1208                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1209                 interrupt-names = "sys", "legacy", "client";
1210                 #interrupt-cells = <1>;
1211                 interrupt-map-mask = <0 0 0 7>;
1212                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1213                                 <0 0 0 2 &pcie0_intc 1>,
1214                                 <0 0 0 3 &pcie0_intc 2>,
1215                                 <0 0 0 4 &pcie0_intc 3>;
1216                 phys = <&pcie_phy>;
1217                 phy-names = "pcie-phy";
1218                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1219                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1220                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1221                       <0x0 0xfd000000 0x0 0x1000000>;
1222                 reg-names = "axi-base", "apb-base";
1223                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1224                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1225                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1226                          <&cru SRST_A_PCIE>;
1227                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1228                               "pm", "pclk", "aclk";
1229                 status = "disabled";
1230                 pcie0_intc: interrupt-controller {
1231                         interrupt-controller;
1232                         #address-cells = <0>;
1233                         #interrupt-cells = <1>;
1234                 };
1235         };
1236
1237         pwm0: pwm@ff420000 {
1238                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1239                 reg = <0x0 0xff420000 0x0 0x10>;
1240                 #pwm-cells = <3>;
1241                 pinctrl-names = "default";
1242                 pinctrl-0 = <&pwm0_pin>;
1243                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1244                 clock-names = "pwm";
1245                 status = "disabled";
1246         };
1247
1248         pwm1: pwm@ff420010 {
1249                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1250                 reg = <0x0 0xff420010 0x0 0x10>;
1251                 #pwm-cells = <3>;
1252                 pinctrl-names = "default";
1253                 pinctrl-0 = <&pwm1_pin>;
1254                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1255                 clock-names = "pwm";
1256                 status = "disabled";
1257         };
1258
1259         pwm2: pwm@ff420020 {
1260                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1261                 reg = <0x0 0xff420020 0x0 0x10>;
1262                 #pwm-cells = <3>;
1263                 pinctrl-names = "default";
1264                 pinctrl-0 = <&pwm2_pin>;
1265                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1266                 clock-names = "pwm";
1267                 status = "disabled";
1268         };
1269
1270         pwm3: pwm@ff420030 {
1271                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1272                 reg = <0x0 0xff420030 0x0 0x10>;
1273                 #pwm-cells = <3>;
1274                 pinctrl-names = "default";
1275                 pinctrl-0 = <&pwm3a_pin>;
1276                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1277                 clock-names = "pwm";
1278                 status = "disabled";
1279         };
1280
1281         dfi: dfi@ff630000 {
1282                 reg = <0x00 0xff630000 0x00 0x4000>;
1283                 compatible = "rockchip,rk3399-dfi";
1284                 rockchip,pmu = <&pmugrf>;
1285                 clocks = <&cru PCLK_DDR_MON>;
1286                 clock-names = "pclk_ddr_mon";
1287                 status = "disabled";
1288         };
1289
1290         dmc: dmc {
1291                 compatible = "rockchip,rk3399-dmc";
1292                 devfreq-events = <&dfi>;
1293                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1294                 clocks = <&cru SCLK_DDRCLK>;
1295                 clock-names = "dmc_clk";
1296                 ddr_timing = <&ddr_timing>;
1297                 status = "disabled";
1298         };
1299
1300         vpu: vpu_service@ff650000 {
1301                 compatible = "rockchip,vpu_service";
1302                 rockchip,grf = <&grf>;
1303                 iommus = <&vpu_mmu>;
1304                 iommu_enabled = <1>;
1305                 reg = <0x0 0xff650000 0x0 0x800>;
1306                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
1307                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1308                 interrupt-names = "irq_dec", "irq_enc";
1309                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1310                 clock-names = "aclk_vcodec", "hclk_vcodec";
1311                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1312                 reset-names = "video_h", "video_a";
1313                 power-domains = <&power RK3399_PD_VCODEC>;
1314                 name = "vpu_service";
1315                 dev_mode = <0>;
1316                 /* 0 means ion, 1 means drm */
1317                 allocator = <1>;
1318                 status = "disabled";
1319         };
1320
1321         vpu_mmu: iommu@ff650800 {
1322                 compatible = "rockchip,iommu";
1323                 reg = <0x0 0xff650800 0x0 0x40>;
1324                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1325                 interrupt-names = "vpu_mmu";
1326                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1327                 clock-names = "aclk", "hclk";
1328                 power-domains = <&power RK3399_PD_VCODEC>;
1329                 #iommu-cells = <0>;
1330         };
1331
1332         rkvdec: rkvdec@ff660000 {
1333                 compatible = "rockchip,rkvdec";
1334                 rockchip,grf = <&grf>;
1335                 iommus = <&vdec_mmu>;
1336                 iommu_enabled = <1>;
1337                 reg = <0x0 0xff660000 0x0 0x400>;
1338                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1339                 interrupt-names = "irq_dec";
1340                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1341                          <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1342                 clock-names = "aclk_vcodec", "hclk_vcodec",
1343                               "clk_cabac", "clk_core";
1344                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
1345                         <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
1346                         <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
1347                 reset-names = "video_h", "video_a", "video_core", "video_cabac",
1348                                 "niu_a", "niu_h";
1349                 power-domains = <&power RK3399_PD_VDU>;
1350                 dev_mode = <2>;
1351                 name = "rkvdec";
1352                 /* 0 means ion, 1 means drm */
1353                 allocator = <1>;
1354                 status = "disabled";
1355         };
1356
1357         vdec_mmu: iommu@ff660480 {
1358                 compatible = "rockchip,iommu";
1359                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1360                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1361                 interrupt-names = "vdec_mmu";
1362                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1363                 clock-names = "aclk", "hclk";
1364                 power-domains = <&power RK3399_PD_VDU>;
1365                 #iommu-cells = <0>;
1366         };
1367
1368         iep: iep@ff670000 {
1369                 compatible = "rockchip,iep";
1370                 iommu_enabled = <1>;
1371                 iommus = <&iep_mmu>;
1372                 reg = <0x0 0xff670000 0x0 0x800>;
1373                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1374                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1375                 clock-names = "aclk_iep", "hclk_iep";
1376                 power-domains = <&power RK3399_PD_IEP>;
1377                 allocator = <1>;
1378                 version = <2>;
1379                 status = "disabled";
1380         };
1381
1382         iep_mmu: iommu@ff670800 {
1383                 compatible = "rockchip,iommu";
1384                 reg = <0x0 0xff670800 0x0 0x40>;
1385                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1386                 interrupt-names = "iep_mmu";
1387                 #iommu-cells = <0>;
1388                 status = "disabled";
1389         };
1390
1391         rga: rga@ff680000 {
1392                 compatible = "rockchip,rk3399-rga";
1393                 reg = <0x0 0xff680000 0x0 0x10000>;
1394                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1395                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1396                 clock-names = "aclk", "hclk", "sclk";
1397                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1398                 reset-names = "core", "axi", "ahb";
1399                 power-domains = <&power RK3399_PD_RGA>;
1400         };
1401
1402         efuse0: efuse@ff690000 {
1403                 compatible = "rockchip,rk3399-efuse";
1404                 reg = <0x0 0xff690000 0x0 0x80>;
1405                 #address-cells = <1>;
1406                 #size-cells = <1>;
1407                 clocks = <&cru PCLK_EFUSE1024NS>;
1408                 clock-names = "pclk_efuse";
1409
1410                 /* Data cells */
1411                 efuse_id: id {
1412                         reg = <0x07 0x10>;
1413                 };
1414                 cpul_leakage: cpul-leakage {
1415                         reg = <0x1a 0x1>;
1416                 };
1417                 cpub_leakage: cpub-leakage {
1418                         reg = <0x17 0x1>;
1419                 };
1420                 gpu_leakage: gpu-leakage {
1421                         reg = <0x18 0x1>;
1422                 };
1423                 center_leakage: center-leakage {
1424                         reg = <0x19 0x1>;
1425                 };
1426                 logic_leakage: logic-leakage {
1427                         reg = <0x1b 0x1>;
1428                 };
1429                 wafer_info: wafer-info {
1430                         reg = <0x1c 0x1>;
1431                 };
1432         };
1433
1434         pmucru: pmu-clock-controller@ff750000 {
1435                 compatible = "rockchip,rk3399-pmucru";
1436                 reg = <0x0 0xff750000 0x0 0x1000>;
1437                 #clock-cells = <1>;
1438                 #reset-cells = <1>;
1439                 assigned-clocks = <&pmucru PLL_PPLL>;
1440                 assigned-clock-rates = <676000000>;
1441         };
1442
1443         cru: clock-controller@ff760000 {
1444                 compatible = "rockchip,rk3399-cru";
1445                 reg = <0x0 0xff760000 0x0 0x1000>;
1446                 #clock-cells = <1>;
1447                 #reset-cells = <1>;
1448                 assigned-clocks =
1449                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1450                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1451                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1452                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1453                         <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1454                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1455                         <&cru PCLK_PERIHP>,
1456                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1457                         <&cru PCLK_PERILP0>,
1458                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1459                 assigned-clock-rates =
1460                          <400000000>,  <200000000>,
1461                          <400000000>,  <200000000>,
1462                          <816000000>, <816000000>,
1463                          <594000000>,  <800000000>,
1464                          <200000000>, <1000000000>,
1465                          <150000000>,   <75000000>,
1466                           <37500000>,
1467                          <100000000>,  <100000000>,
1468                           <50000000>,
1469                          <100000000>,   <50000000>;
1470         };
1471
1472         grf: syscon@ff770000 {
1473                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1474                 reg = <0x0 0xff770000 0x0 0x10000>;
1475                 #address-cells = <1>;
1476                 #size-cells = <1>;
1477
1478                 io_domains: io-domains {
1479                         compatible = "rockchip,rk3399-io-voltage-domain";
1480                         status = "disabled";
1481                 };
1482
1483                 emmc_phy: phy@f780 {
1484                         compatible = "rockchip,rk3399-emmc-phy";
1485                         reg = <0xf780 0x24>;
1486                         clocks = <&sdhci>;
1487                         clock-names = "emmcclk";
1488                         #phy-cells = <0>;
1489                         status = "disabled";
1490                 };
1491
1492                 u2phy0: usb2-phy@e450 {
1493                         compatible = "rockchip,rk3399-usb2phy";
1494                         reg = <0xe450 0x10>;
1495                         clocks = <&cru SCLK_USB2PHY0_REF>;
1496                         clock-names = "phyclk";
1497                         #clock-cells = <0>;
1498                         clock-output-names = "clk_usbphy0_480m";
1499                         status = "disabled";
1500
1501                         u2phy0_otg: otg-port {
1502                                 #phy-cells = <0>;
1503                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1504                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1505                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1506                                 interrupt-names = "otg-bvalid", "otg-id",
1507                                                   "linestate";
1508                                 status = "disabled";
1509                         };
1510
1511                         u2phy0_host: host-port {
1512                                 #phy-cells = <0>;
1513                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1514                                 interrupt-names = "linestate";
1515                                 status = "disabled";
1516                         };
1517                 };
1518
1519                 u2phy1: usb2-phy@e460 {
1520                         compatible = "rockchip,rk3399-usb2phy";
1521                         reg = <0xe460 0x10>;
1522                         clocks = <&cru SCLK_USB2PHY1_REF>;
1523                         clock-names = "phyclk";
1524                         #clock-cells = <0>;
1525                         clock-output-names = "clk_usbphy1_480m";
1526                         status = "disabled";
1527
1528                         u2phy1_otg: otg-port {
1529                                 #phy-cells = <0>;
1530                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1531                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1532                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1533                                 interrupt-names = "otg-bvalid", "otg-id",
1534                                                   "linestate";
1535                                 status = "disabled";
1536                         };
1537
1538                         u2phy1_host: host-port {
1539                                 #phy-cells = <0>;
1540                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1541                                 interrupt-names = "linestate";
1542                                 status = "disabled";
1543                         };
1544                 };
1545
1546                 pvtm: pvtm {
1547                         compatible = "rockchip,rk3399-pvtm";
1548                         clocks = <&cru SCLK_PVTM_CORE_L>,
1549                                  <&cru SCLK_PVTM_CORE_B>,
1550                                  <&cru SCLK_PVTM_GPU>,
1551                                  <&cru SCLK_PVTM_DDR>;
1552                         clock-names = "core_l", "core_b", "gpu", "ddr";
1553                         status = "disabled";
1554                 };
1555         };
1556
1557         tcphy0: phy@ff7c0000 {
1558                 compatible = "rockchip,rk3399-typec-phy";
1559                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1560                 rockchip,grf = <&grf>;
1561                 #phy-cells = <1>;
1562                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1563                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1564                 clock-names = "tcpdcore", "tcpdphy-ref";
1565                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1566                 assigned-clock-rates = <50000000>;
1567                 power-domains = <&power RK3399_PD_TCPD0>;
1568                 resets = <&cru SRST_UPHY0>,
1569                          <&cru SRST_UPHY0_PIPE_L00>,
1570                          <&cru SRST_P_UPHY0_TCPHY>;
1571                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1572                 rockchip,typec-conn-dir = <0xe580 0 16>;
1573                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1574                 rockchip,usb3-host-disable = <0x2434 0 16>;
1575                 rockchip,usb3-host-port = <0x2434 12 28>;
1576                 rockchip,external-psm = <0xe588 14 30>;
1577                 rockchip,pipe-status = <0xe5c0 0 0>;
1578                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1579                 status = "disabled";
1580
1581                 tcphy0_dp: dp-port {
1582                         #phy-cells = <0>;
1583                 };
1584
1585                 tcphy0_usb3: usb3-port {
1586                         #phy-cells = <0>;
1587                 };
1588         };
1589
1590         tcphy1: phy@ff800000 {
1591                 compatible = "rockchip,rk3399-typec-phy";
1592                 reg = <0x0 0xff800000 0x0 0x40000>;
1593                 rockchip,grf = <&grf>;
1594                 #phy-cells = <1>;
1595                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1596                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1597                 clock-names = "tcpdcore", "tcpdphy-ref";
1598                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1599                 assigned-clock-rates = <50000000>;
1600                 power-domains = <&power RK3399_PD_TCPD1>;
1601                 resets = <&cru SRST_UPHY1>,
1602                          <&cru SRST_UPHY1_PIPE_L00>,
1603                          <&cru SRST_P_UPHY1_TCPHY>;
1604                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1605                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1606                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1607                 rockchip,usb3-host-disable = <0x2444 0 16>;
1608                 rockchip,usb3-host-port = <0x2444 12 28>;
1609                 rockchip,external-psm = <0xe594 14 30>;
1610                 rockchip,pipe-status = <0xe5c0 16 16>;
1611                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1612                 status = "disabled";
1613
1614                 tcphy1_dp: dp-port {
1615                         #phy-cells = <0>;
1616                 };
1617
1618                 tcphy1_usb3: usb3-port {
1619                         #phy-cells = <0>;
1620                 };
1621         };
1622
1623         watchdog@ff848000 {
1624                 compatible = "snps,dw-wdt";
1625                 reg = <0x0 0xff848000 0x0 0x100>;
1626                 clocks = <&cru PCLK_WDT>;
1627                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1628         };
1629
1630         rktimer: rktimer@ff850000 {
1631                 compatible = "rockchip,rk3399-timer";
1632                 reg = <0x0 0xff850000 0x0 0x1000>;
1633                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1634                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1635                 clock-names = "pclk", "timer";
1636         };
1637
1638         spdif: spdif@ff870000 {
1639                 compatible = "rockchip,rk3399-spdif";
1640                 reg = <0x0 0xff870000 0x0 0x1000>;
1641                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1642                 dmas = <&dmac_bus 7>;
1643                 dma-names = "tx";
1644                 clock-names = "mclk", "hclk";
1645                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1646                 pinctrl-names = "default";
1647                 pinctrl-0 = <&spdif_bus>;
1648                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1649                 status = "disabled";
1650         };
1651
1652         i2s0: i2s@ff880000 {
1653                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1654                 reg = <0x0 0xff880000 0x0 0x1000>;
1655                 rockchip,grf = <&grf>;
1656                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1657                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1658                 dma-names = "tx", "rx";
1659                 clock-names = "i2s_clk", "i2s_hclk";
1660                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1661                 pinctrl-names = "default";
1662                 pinctrl-0 = <&i2s0_8ch_bus>;
1663                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1664                 status = "disabled";
1665         };
1666
1667         i2s1: i2s@ff890000 {
1668                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1669                 reg = <0x0 0xff890000 0x0 0x1000>;
1670                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1671                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1672                 dma-names = "tx", "rx";
1673                 clock-names = "i2s_clk", "i2s_hclk";
1674                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1675                 pinctrl-names = "default";
1676                 pinctrl-0 = <&i2s1_2ch_bus>;
1677                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1678                 status = "disabled";
1679         };
1680
1681         i2s2: i2s@ff8a0000 {
1682                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1683                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1684                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1685                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1686                 dma-names = "tx", "rx";
1687                 clock-names = "i2s_clk", "i2s_hclk";
1688                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1689                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1690                 status = "disabled";
1691         };
1692
1693         gpu: gpu@ff9a0000 {
1694                 compatible = "arm,malit860",
1695                              "arm,malit86x",
1696                              "arm,malit8xx",
1697                              "arm,mali-midgard";
1698
1699                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1700
1701                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1702                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1703                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1704                 interrupt-names = "GPU", "JOB", "MMU";
1705
1706                 clocks = <&cru ACLK_GPU>;
1707                 clock-names = "clk_mali";
1708                 #cooling-cells = <2>; /* min followed by max */
1709                 power-domains = <&power RK3399_PD_GPU>;
1710                 power-off-delay-ms = <200>;
1711                 status = "disabled";
1712
1713                 gpu_power_model: power_model {
1714                         compatible = "arm,mali-simple-power-model";
1715                         voltage = <900>;
1716                         frequency = <500>;
1717                         static-power = <300>;
1718                         dynamic-power = <396>;
1719                         ts = <32000 4700 (-80) 2>;
1720                         thermal-zone = "gpu-thermal";
1721                 };
1722         };
1723
1724         vopl: vop@ff8f0000 {
1725                 compatible = "rockchip,rk3399-vop-lit";
1726                 reg = <0x0 0xff8f0000 0x0 0x600>,
1727                         <0x0 0xff8f1c00 0x0 0x200>,
1728                         <0x0 0xff8f2000 0x0 0x400>;
1729                 reg-names = "regs", "cabc_lut", "gamma_lut";
1730                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1731                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>, <&cru DCLK_VOP1_DIV>;
1732                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
1733                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1734                 reset-names = "axi", "ahb", "dclk";
1735                 power-domains = <&power RK3399_PD_VOPL>;
1736                 iommus = <&vopl_mmu>;
1737                 status = "disabled";
1738
1739                 vopl_out: port {
1740                         #address-cells = <1>;
1741                         #size-cells = <0>;
1742
1743                         vopl_out_dsi: endpoint@0 {
1744                                 reg = <0>;
1745                                 remote-endpoint = <&dsi_in_vopl>;
1746                         };
1747
1748                         vopl_out_edp: endpoint@1 {
1749                                 reg = <1>;
1750                                 remote-endpoint = <&edp_in_vopl>;
1751                         };
1752
1753                         vopl_out_hdmi: endpoint@2 {
1754                                 reg = <2>;
1755                                 remote-endpoint = <&hdmi_in_vopl>;
1756                         };
1757
1758                         vopl_out_dp: endpoint@3 {
1759                                 reg = <3>;
1760                                 remote-endpoint = <&dp_in_vopl>;
1761                         };
1762
1763                         vopl_out_dsi1: endpoint@4 {
1764                                 reg = <4>;
1765                                 remote-endpoint = <&dsi1_in_vopl>;
1766                         };
1767                 };
1768         };
1769
1770         vop1_pwm: voppwm@ff8f01a0 {
1771                 compatible = "rockchip,vop-pwm";
1772                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1773                 #pwm-cells = <3>;
1774                 pinctrl-names = "default";
1775                 pinctrl-0 = <&vop1_pwm_pin>;
1776                 clocks = <&cru SCLK_VOP1_PWM>;
1777                 clock-names = "pwm";
1778                 status = "disabled";
1779         };
1780
1781         vopl_mmu: iommu@ff8f3f00 {
1782                 compatible = "rockchip,iommu";
1783                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1784                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1785                 interrupt-names = "vopl_mmu";
1786                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1787                 clock-names = "aclk", "hclk";
1788                 power-domains = <&power RK3399_PD_VOPL>;
1789                 #iommu-cells = <0>;
1790                 status = "disabled";
1791         };
1792
1793         vopb: vop@ff900000 {
1794                 compatible = "rockchip,rk3399-vop-big";
1795                 reg = <0x0 0xff900000 0x0 0x600>,
1796                         <0x0 0xff901c00 0x0 0x200>,
1797                         <0x0 0xff902000 0x0 0x1000>;
1798                 reg-names = "regs", "cabc_lut", "gamma_lut";
1799                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1800                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>, <&cru DCLK_VOP0_DIV>;
1801                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
1802                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1803                 reset-names = "axi", "ahb", "dclk";
1804                 power-domains = <&power RK3399_PD_VOPB>;
1805                 iommus = <&vopb_mmu>;
1806                 status = "disabled";
1807
1808                 vopb_out: port {
1809                         #address-cells = <1>;
1810                         #size-cells = <0>;
1811
1812                         vopb_out_edp: endpoint@0 {
1813                                 reg = <0>;
1814                                 remote-endpoint = <&edp_in_vopb>;
1815                         };
1816
1817                         vopb_out_dsi: endpoint@1 {
1818                                 reg = <1>;
1819                                 remote-endpoint = <&dsi_in_vopb>;
1820                         };
1821
1822                         vopb_out_hdmi: endpoint@2 {
1823                                 reg = <2>;
1824                                 remote-endpoint = <&hdmi_in_vopb>;
1825                         };
1826
1827                         vopb_out_dp: endpoint@3 {
1828                                 reg = <3>;
1829                                 remote-endpoint = <&dp_in_vopb>;
1830                         };
1831
1832                         vopb_out_dsi1: endpoint@4 {
1833                                 reg = <4>;
1834                                 remote-endpoint = <&dsi1_in_vopb>;
1835                         };
1836                 };
1837         };
1838
1839         vop0_pwm: voppwm@ff9001a0 {
1840                 compatible = "rockchip,vop-pwm";
1841                 reg = <0x0 0xff9001a0 0x0 0x10>;
1842                 #pwm-cells = <3>;
1843                 pinctrl-names = "default";
1844                 pinctrl-0 = <&vop0_pwm_pin>;
1845                 clocks = <&cru SCLK_VOP0_PWM>;
1846                 clock-names = "pwm";
1847                 status = "disabled";
1848         };
1849
1850         vopb_mmu: iommu@ff903f00 {
1851                 compatible = "rockchip,iommu";
1852                 reg = <0x0 0xff903f00 0x0 0x100>;
1853                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1854                 interrupt-names = "vopb_mmu";
1855                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1856                 clock-names = "aclk", "hclk";
1857                 power-domains = <&power RK3399_PD_VOPB>;
1858                 #iommu-cells = <0>;
1859                 status = "disabled";
1860         };
1861
1862         isp0_mmu: iommu@ff914000 {
1863                 compatible = "rockchip,iommu";
1864                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1865                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1866                 interrupt-names = "isp0_mmu";
1867                 #iommu-cells = <0>;
1868                 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1869                 clock-names = "aclk", "hclk";
1870                 power-domains = <&power RK3399_PD_ISP0>;
1871                 rk_iommu,disable_reset_quirk;
1872                 status = "disabled";
1873         };
1874
1875         isp1_mmu: iommu@ff924000 {
1876                 compatible = "rockchip,iommu";
1877                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1878                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1879                 interrupt-names = "isp1_mmu";
1880                 #iommu-cells = <0>;
1881                 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1882                 clock-names = "aclk", "hclk";
1883                 power-domains = <&power RK3399_PD_ISP1>;
1884                 rk_iommu,disable_reset_quirk;
1885                 status = "disabled";
1886         };
1887
1888         hdmi: hdmi@ff940000 {
1889                 compatible = "rockchip,rk3399-dw-hdmi";
1890                 reg = <0x0 0xff940000 0x0 0x20000>;
1891                 reg-io-width = <4>;
1892                 rockchip,grf = <&grf>;
1893                 pinctrl-names = "default";
1894                 pinctrl-0 = <&hdmi_i2c_xfer>;
1895                 power-domains = <&power RK3399_PD_HDCP>;
1896                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1897                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1898                 clock-names = "iahb", "isfr", "vpll", "grf";
1899                 status = "disabled";
1900
1901                 ports {
1902                         hdmi_in: port {
1903                                 #address-cells = <1>;
1904                                 #size-cells = <0>;
1905                                 hdmi_in_vopb: endpoint@0 {
1906                                         reg = <0>;
1907                                         remote-endpoint = <&vopb_out_hdmi>;
1908                                 };
1909                                 hdmi_in_vopl: endpoint@1 {
1910                                         reg = <1>;
1911                                         remote-endpoint = <&vopl_out_hdmi>;
1912                                 };
1913                         };
1914                 };
1915         };
1916
1917         dsi: dsi@ff960000 {
1918                 compatible = "rockchip,rk3399-mipi-dsi";
1919                 reg = <0x0 0xff960000 0x0 0x8000>;
1920                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1921                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1922                          <&cru SCLK_DPHY_TX0_CFG>;
1923                 clock-names = "ref", "pclk", "phy_cfg";
1924                 resets = <&cru SRST_P_MIPI_DSI0>;
1925                 reset-names = "apb";
1926                 power-domains = <&power RK3399_PD_VIO>;
1927                 rockchip,grf = <&grf>;
1928
1929                 #address-cells = <1>;
1930                 #size-cells = <0>;
1931                 status = "disabled";
1932
1933                 ports {
1934
1935                         #address-cells = <1>;
1936                         #size-cells = <0>;
1937                         reg = <1>;
1938
1939                         port {
1940                                 #address-cells = <1>;
1941                                 #size-cells = <0>;
1942
1943                                 dsi_in_vopb: endpoint@0 {
1944                                         reg = <0>;
1945                                         remote-endpoint = <&vopb_out_dsi>;
1946                                 };
1947
1948                                 dsi_in_vopl: endpoint@1 {
1949                                         reg = <1>;
1950                                         remote-endpoint = <&vopl_out_dsi>;
1951                                 };
1952                         };
1953                 };
1954         };
1955
1956         dsi1: dsi@ff968000 {
1957                 compatible = "rockchip,rk3399-mipi-dsi";
1958                 reg = <0x0 0xff968000 0x0 0x8000>;
1959                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1960                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1961                          <&cru SCLK_DPHY_TX1RX1_CFG>;
1962                 clock-names = "ref", "pclk", "phy_cfg";
1963                 resets = <&cru SRST_P_MIPI_DSI1>;
1964                 reset-names = "apb";
1965                 power-domains = <&power RK3399_PD_VIO>;
1966                 rockchip,grf = <&grf>;
1967                 #address-cells = <1>;
1968                 #size-cells = <0>;
1969                 status = "disabled";
1970
1971                 ports {
1972                         port {
1973                                 #address-cells = <1>;
1974                                 #size-cells = <0>;
1975
1976                                 dsi1_in_vopb: endpoint@0 {
1977                                         reg = <0>;
1978                                         remote-endpoint = <&vopb_out_dsi1>;
1979                                 };
1980
1981                                 dsi1_in_vopl: endpoint@1 {
1982                                         reg = <1>;
1983                                         remote-endpoint = <&vopl_out_dsi1>;
1984                                 };
1985                         };
1986                 };
1987         };
1988
1989         edp: edp@ff970000 {
1990                 compatible = "rockchip,rk3399-edp";
1991                 reg = <0x0 0xff970000 0x0 0x8000>;
1992                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1993                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1994                 clock-names = "dp", "pclk";
1995                 power-domains = <&power RK3399_PD_EDP>;
1996                 resets = <&cru SRST_P_EDP_CTRL>;
1997                 reset-names = "dp";
1998                 rockchip,grf = <&grf>;
1999                 status = "disabled";
2000                 pinctrl-names = "default";
2001                 pinctrl-0 = <&edp_hpd>;
2002
2003                 ports {
2004                         #address-cells = <1>;
2005                         #size-cells = <0>;
2006
2007                         edp_in: port@0 {
2008                                 reg = <0>;
2009                                 #address-cells = <1>;
2010                                 #size-cells = <0>;
2011
2012                                 edp_in_vopb: endpoint@0 {
2013                                         reg = <0>;
2014                                         remote-endpoint = <&vopb_out_edp>;
2015                                 };
2016
2017                                 edp_in_vopl: endpoint@1 {
2018                                         reg = <1>;
2019                                         remote-endpoint = <&vopl_out_edp>;
2020                                 };
2021                         };
2022                 };
2023         };
2024
2025         display_subsystem: display-subsystem {
2026                 compatible = "rockchip,display-subsystem";
2027                 ports = <&vopl_out>, <&vopb_out>;
2028                 clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>;
2029                 clock-names = "hdmi-tmds-pll", "default-vop-pll";
2030                 status = "disabled";
2031         };
2032
2033         pinctrl: pinctrl {
2034                 compatible = "rockchip,rk3399-pinctrl";
2035                 rockchip,grf = <&grf>;
2036                 rockchip,pmu = <&pmugrf>;
2037                 #address-cells = <0x2>;
2038                 #size-cells = <0x2>;
2039                 ranges;
2040
2041                 gpio0: gpio0@ff720000 {
2042                         compatible = "rockchip,gpio-bank";
2043                         reg = <0x0 0xff720000 0x0 0x100>;
2044                         clocks = <&pmucru PCLK_GPIO0_PMU>;
2045                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
2046
2047                         gpio-controller;
2048                         #gpio-cells = <0x2>;
2049
2050                         interrupt-controller;
2051                         #interrupt-cells = <0x2>;
2052                 };
2053
2054                 gpio1: gpio1@ff730000 {
2055                         compatible = "rockchip,gpio-bank";
2056                         reg = <0x0 0xff730000 0x0 0x100>;
2057                         clocks = <&pmucru PCLK_GPIO1_PMU>;
2058                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
2059
2060                         gpio-controller;
2061                         #gpio-cells = <0x2>;
2062
2063                         interrupt-controller;
2064                         #interrupt-cells = <0x2>;
2065                 };
2066
2067                 gpio2: gpio2@ff780000 {
2068                         compatible = "rockchip,gpio-bank";
2069                         reg = <0x0 0xff780000 0x0 0x100>;
2070                         clocks = <&cru PCLK_GPIO2>;
2071                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
2072
2073                         gpio-controller;
2074                         #gpio-cells = <0x2>;
2075
2076                         interrupt-controller;
2077                         #interrupt-cells = <0x2>;
2078                 };
2079
2080                 gpio3: gpio3@ff788000 {
2081                         compatible = "rockchip,gpio-bank";
2082                         reg = <0x0 0xff788000 0x0 0x100>;
2083                         clocks = <&cru PCLK_GPIO3>;
2084                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2085
2086                         gpio-controller;
2087                         #gpio-cells = <0x2>;
2088
2089                         interrupt-controller;
2090                         #interrupt-cells = <0x2>;
2091                 };
2092
2093                 gpio4: gpio4@ff790000 {
2094                         compatible = "rockchip,gpio-bank";
2095                         reg = <0x0 0xff790000 0x0 0x100>;
2096                         clocks = <&cru PCLK_GPIO4>;
2097                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2098
2099                         gpio-controller;
2100                         #gpio-cells = <0x2>;
2101
2102                         interrupt-controller;
2103                         #interrupt-cells = <0x2>;
2104                 };
2105
2106                 pcfg_pull_up: pcfg-pull-up {
2107                         bias-pull-up;
2108                 };
2109
2110                 pcfg_pull_down: pcfg-pull-down {
2111                         bias-pull-down;
2112                 };
2113
2114                 pcfg_pull_none: pcfg-pull-none {
2115                         bias-disable;
2116                 };
2117
2118                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2119                         bias-pull-up;
2120                         drive-strength = <20>;
2121                 };
2122
2123                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2124                         bias-disable;
2125                         drive-strength = <20>;
2126                 };
2127
2128                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2129                         bias-disable;
2130                         drive-strength = <18>;
2131                 };
2132
2133                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2134                         bias-disable;
2135                         drive-strength = <12>;
2136                 };
2137
2138                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2139                         bias-pull-up;
2140                         drive-strength = <8>;
2141                 };
2142
2143                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2144                         bias-pull-down;
2145                         drive-strength = <4>;
2146                 };
2147
2148                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2149                         bias-pull-up;
2150                         drive-strength = <2>;
2151                 };
2152
2153                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2154                         bias-pull-down;
2155                         drive-strength = <12>;
2156                 };
2157
2158                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2159                         bias-disable;
2160                         drive-strength = <13>;
2161                 };
2162
2163                 pcfg_output_high: pcfg-output-high {
2164                         output-high;
2165                 };
2166
2167                 pcfg_output_low: pcfg-output-low {
2168                         output-low;
2169                 };
2170
2171                 pcfg_input: pcfg-input {
2172                         input-enable;
2173                 };
2174
2175                 emmc {
2176                         emmc_pwr: emmc-pwr {
2177                                 rockchip,pins =
2178                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
2179                         };
2180                 };
2181
2182                 gmac {
2183                         rgmii_pins: rgmii-pins {
2184                                 rockchip,pins =
2185                                         /* mac_txclk */
2186                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2187                                         /* mac_rxclk */
2188                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2189                                         /* mac_mdio */
2190                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2191                                         /* mac_txen */
2192                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2193                                         /* mac_clk */
2194                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2195                                         /* mac_rxdv */
2196                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2197                                         /* mac_mdc */
2198                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2199                                         /* mac_rxd1 */
2200                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2201                                         /* mac_rxd0 */
2202                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2203                                         /* mac_txd1 */
2204                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2205                                         /* mac_txd0 */
2206                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2207                                         /* mac_rxd3 */
2208                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2209                                         /* mac_rxd2 */
2210                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2211                                         /* mac_txd3 */
2212                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2213                                         /* mac_txd2 */
2214                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2215                         };
2216
2217                         rmii_pins: rmii-pins {
2218                                 rockchip,pins =
2219                                         /* mac_mdio */
2220                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2221                                         /* mac_txen */
2222                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2223                                         /* mac_clk */
2224                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2225                                         /* mac_rxer */
2226                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2227                                         /* mac_rxdv */
2228                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2229                                         /* mac_mdc */
2230                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2231                                         /* mac_rxd1 */
2232                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2233                                         /* mac_rxd0 */
2234                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2235                                         /* mac_txd1 */
2236                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2237                                         /* mac_txd0 */
2238                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2239                         };
2240                 };
2241
2242                 i2c0 {
2243                         i2c0_xfer: i2c0-xfer {
2244                                 rockchip,pins =
2245                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2246                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2247                         };
2248                 };
2249
2250                 i2c1 {
2251                         i2c1_xfer: i2c1-xfer {
2252                                 rockchip,pins =
2253                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2254                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2255                         };
2256                 };
2257
2258                 i2c2 {
2259                         i2c2_xfer: i2c2-xfer {
2260                                 rockchip,pins =
2261                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2262                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2263                         };
2264                 };
2265
2266                 i2c3 {
2267                         i2c3_xfer: i2c3-xfer {
2268                                 rockchip,pins =
2269                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2270                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2271                         };
2272
2273                         i2c3_gpio: i2c3_gpio {
2274                                 rockchip,pins =
2275                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2276                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2277                         };
2278
2279                 };
2280
2281                 i2c4 {
2282                         i2c4_xfer: i2c4-xfer {
2283                                 rockchip,pins =
2284                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2285                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2286                         };
2287                 };
2288
2289                 i2c5 {
2290                         i2c5_xfer: i2c5-xfer {
2291                                 rockchip,pins =
2292                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2293                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2294                         };
2295                 };
2296
2297                 i2c6 {
2298                         i2c6_xfer: i2c6-xfer {
2299                                 rockchip,pins =
2300                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2301                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2302                         };
2303                 };
2304
2305                 i2c7 {
2306                         i2c7_xfer: i2c7-xfer {
2307                                 rockchip,pins =
2308                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2309                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2310                         };
2311                 };
2312
2313                 i2c8 {
2314                         i2c8_xfer: i2c8-xfer {
2315                                 rockchip,pins =
2316                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2317                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2318                         };
2319                 };
2320
2321                 i2s0 {
2322                         i2s0_8ch_bus: i2s0-8ch-bus {
2323                                 rockchip,pins =
2324                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2325                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2326                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2327                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2328                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2329                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2330                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2331                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2332                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2333                         };
2334                 };
2335
2336                 i2s1 {
2337                         i2s1_2ch_bus: i2s1-2ch-bus {
2338                                 rockchip,pins =
2339                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2340                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2341                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2342                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2343                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2344                         };
2345                 };
2346
2347                 sdio0 {
2348                         sdio0_bus1: sdio0-bus1 {
2349                                 rockchip,pins =
2350                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2351                         };
2352
2353                         sdio0_bus4: sdio0-bus4 {
2354                                 rockchip,pins =
2355                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2356                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2357                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2358                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2359                         };
2360
2361                         sdio0_cmd: sdio0-cmd {
2362                                 rockchip,pins =
2363                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2364                         };
2365
2366                         sdio0_clk: sdio0-clk {
2367                                 rockchip,pins =
2368                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2369                         };
2370
2371                         sdio0_cd: sdio0-cd {
2372                                 rockchip,pins =
2373                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2374                         };
2375
2376                         sdio0_pwr: sdio0-pwr {
2377                                 rockchip,pins =
2378                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2379                         };
2380
2381                         sdio0_bkpwr: sdio0-bkpwr {
2382                                 rockchip,pins =
2383                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2384                         };
2385
2386                         sdio0_wp: sdio0-wp {
2387                                 rockchip,pins =
2388                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2389                         };
2390
2391                         sdio0_int: sdio0-int {
2392                                 rockchip,pins =
2393                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2394                         };
2395                 };
2396
2397                 sdmmc {
2398                         sdmmc_bus1: sdmmc-bus1 {
2399                                 rockchip,pins =
2400                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2401                         };
2402
2403                         sdmmc_bus4: sdmmc-bus4 {
2404                                 rockchip,pins =
2405                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2406                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2407                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2408                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2409                         };
2410
2411                         sdmmc_clk: sdmmc-clk {
2412                                 rockchip,pins =
2413                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2414                         };
2415
2416                         sdmmc_cmd: sdmmc-cmd {
2417                                 rockchip,pins =
2418                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2419                         };
2420
2421                         sdmmc_cd: sdmcc-cd {
2422                                 rockchip,pins =
2423                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2424                         };
2425
2426                         sdmmc_wp: sdmmc-wp {
2427                                 rockchip,pins =
2428                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2429                         };
2430                 };
2431
2432                 spdif {
2433                         spdif_bus: spdif-bus {
2434                                 rockchip,pins =
2435                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2436                         };
2437
2438                         spdif_bus_1: spdif-bus-1 {
2439                                 rockchip,pins =
2440                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2441                         };
2442                 };
2443
2444                 spi0 {
2445                         spi0_clk: spi0-clk {
2446                                 rockchip,pins =
2447                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2448                         };
2449                         spi0_cs0: spi0-cs0 {
2450                                 rockchip,pins =
2451                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2452                         };
2453                         spi0_cs1: spi0-cs1 {
2454                                 rockchip,pins =
2455                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2456                         };
2457                         spi0_tx: spi0-tx {
2458                                 rockchip,pins =
2459                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2460                         };
2461                         spi0_rx: spi0-rx {
2462                                 rockchip,pins =
2463                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2464                         };
2465                 };
2466
2467                 spi1 {
2468                         spi1_clk: spi1-clk {
2469                                 rockchip,pins =
2470                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2471                         };
2472                         spi1_cs0: spi1-cs0 {
2473                                 rockchip,pins =
2474                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2475                         };
2476                         spi1_rx: spi1-rx {
2477                                 rockchip,pins =
2478                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2479                         };
2480                         spi1_tx: spi1-tx {
2481                                 rockchip,pins =
2482                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2483                         };
2484                 };
2485
2486                 spi2 {
2487                         spi2_clk: spi2-clk {
2488                                 rockchip,pins =
2489                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2490                         };
2491                         spi2_cs0: spi2-cs0 {
2492                                 rockchip,pins =
2493                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2494                         };
2495                         spi2_rx: spi2-rx {
2496                                 rockchip,pins =
2497                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2498                         };
2499                         spi2_tx: spi2-tx {
2500                                 rockchip,pins =
2501                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2502                         };
2503                 };
2504
2505                 spi3 {
2506                         spi3_clk: spi3-clk {
2507                                 rockchip,pins =
2508                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2509                         };
2510                         spi3_cs0: spi3-cs0 {
2511                                 rockchip,pins =
2512                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2513                         };
2514                         spi3_rx: spi3-rx {
2515                                 rockchip,pins =
2516                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2517                         };
2518                         spi3_tx: spi3-tx {
2519                                 rockchip,pins =
2520                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2521                         };
2522                 };
2523
2524                 spi4 {
2525                         spi4_clk: spi4-clk {
2526                                 rockchip,pins =
2527                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2528                         };
2529                         spi4_cs0: spi4-cs0 {
2530                                 rockchip,pins =
2531                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2532                         };
2533                         spi4_rx: spi4-rx {
2534                                 rockchip,pins =
2535                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2536                         };
2537                         spi4_tx: spi4-tx {
2538                                 rockchip,pins =
2539                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2540                         };
2541                 };
2542
2543                 spi5 {
2544                         spi5_clk: spi5-clk {
2545                                 rockchip,pins =
2546                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2547                         };
2548                         spi5_cs0: spi5-cs0 {
2549                                 rockchip,pins =
2550                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2551                         };
2552                         spi5_rx: spi5-rx {
2553                                 rockchip,pins =
2554                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2555                         };
2556                         spi5_tx: spi5-tx {
2557                                 rockchip,pins =
2558                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2559                         };
2560                 };
2561
2562                 tsadc {
2563                         otp_gpio: otp-gpio {
2564                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2565                         };
2566
2567                         otp_out: otp-out {
2568                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2569                         };
2570                 };
2571
2572                 uart0 {
2573                         uart0_xfer: uart0-xfer {
2574                                 rockchip,pins =
2575                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2576                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2577                         };
2578
2579                         uart0_cts: uart0-cts {
2580                                 rockchip,pins =
2581                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2582                         };
2583
2584                         uart0_rts: uart0-rts {
2585                                 rockchip,pins =
2586                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2587                         };
2588                 };
2589
2590                 uart1 {
2591                         uart1_xfer: uart1-xfer {
2592                                 rockchip,pins =
2593                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2594                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2595                         };
2596                 };
2597
2598                 uart2a {
2599                         uart2a_xfer: uart2a-xfer {
2600                                 rockchip,pins =
2601                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2602                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2603                         };
2604                 };
2605
2606                 uart2b {
2607                         uart2b_xfer: uart2b-xfer {
2608                                 rockchip,pins =
2609                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2610                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2611                         };
2612                 };
2613
2614                 uart2c {
2615                         uart2c_xfer: uart2c-xfer {
2616                                 rockchip,pins =
2617                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2618                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2619                         };
2620                 };
2621
2622                 uart3 {
2623                         uart3_xfer: uart3-xfer {
2624                                 rockchip,pins =
2625                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2626                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2627                         };
2628
2629                         uart3_cts: uart3-cts {
2630                                 rockchip,pins =
2631                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2632                         };
2633
2634                         uart3_rts: uart3-rts {
2635                                 rockchip,pins =
2636                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2637                         };
2638                 };
2639
2640                 uart4 {
2641                         uart4_xfer: uart4-xfer {
2642                                 rockchip,pins =
2643                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2644                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2645                         };
2646                 };
2647
2648                 uarthdcp {
2649                         uarthdcp_xfer: uarthdcp-xfer {
2650                                 rockchip,pins =
2651                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2652                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2653                         };
2654                 };
2655
2656                 pwm0 {
2657                         pwm0_pin: pwm0-pin {
2658                                 rockchip,pins =
2659                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2660                         };
2661
2662                         vop0_pwm_pin: vop0-pwm-pin {
2663                                 rockchip,pins =
2664                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2665                         };
2666                 };
2667
2668                 pwm1 {
2669                         pwm1_pin: pwm1-pin {
2670                                 rockchip,pins =
2671                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2672                         };
2673
2674                         vop1_pwm_pin: vop1-pwm-pin {
2675                                 rockchip,pins =
2676                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2677                         };
2678                 };
2679
2680                 pwm2 {
2681                         pwm2_pin: pwm2-pin {
2682                                 rockchip,pins =
2683                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2684                         };
2685                 };
2686
2687                 pwm3a {
2688                         pwm3a_pin: pwm3a-pin {
2689                                 rockchip,pins =
2690                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2691                         };
2692                 };
2693
2694                 pwm3b {
2695                         pwm3b_pin: pwm3b-pin {
2696                                 rockchip,pins =
2697                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2698                         };
2699                 };
2700
2701                 edp {
2702                         edp_hpd: edp-hpd {
2703                                 rockchip,pins =
2704                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2705                         };
2706                 };
2707
2708                 hdmi {
2709                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2710                                 rockchip,pins =
2711                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2712                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2713                         };
2714
2715                         hdmi_cec: hdmi-cec {
2716                                 rockchip,pins =
2717                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2718                         };
2719                 };
2720
2721                 pcie {
2722                         pcie_clkreqn: pci-clkreqn {
2723                                 rockchip,pins =
2724                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2725                         };
2726
2727                         pcie_clkreqnb: pci-clkreqnb {
2728                                 rockchip,pins =
2729                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2730                         };
2731
2732                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2733                                 /*
2734                                  * Since our pcie doesn't support
2735                                  * ClockPM(CPM), we want to hack this as
2736                                  * gpio, so the EP could be able to
2737                                  * de-assert it along and make ClockPM(CPM)
2738                                  * work.
2739                                  */
2740                                 rockchip,pins =
2741                                         <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
2742                         };
2743
2744                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2745                                 rockchip,pins =
2746                                         <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
2747                         };
2748                 };
2749         };
2750
2751         rockchip_suspend: rockchip-suspend {
2752                 compatible = "rockchip,pm-rk3399";
2753                 status = "disabled";
2754                 rockchip,sleep-debug-en = <0>;
2755                 rockchip,virtual-poweroff = <0>;
2756                 rockchip,sleep-mode-config = <
2757                         (0
2758                         | RKPM_SLP_ARMPD
2759                         | RKPM_SLP_PERILPPD
2760                         | RKPM_SLP_DDR_RET
2761                         | RKPM_SLP_PLLPD
2762                         | RKPM_SLP_OSC_DIS
2763                         | RKPM_SLP_CENTER_PD
2764                         | RKPM_SLP_AP_PWROFF
2765                         )
2766                 >;
2767                 rockchip,wakeup-config = <
2768                         (0
2769                         | RKPM_GPIO_WKUP_EN
2770                         )
2771                 >;
2772         };
2773 };