arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <121>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <1068>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp00 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp01 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp02 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp03 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp04 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp05 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp00 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp01 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp02 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp03 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp04 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 261         };
 262
 263         arm-pmu {
 264                 compatible = "arm,armv8-pmuv3";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 266         };
 267
 268         xin24m: xin24m {
 269                 compatible = "fixed-clock";
 270                 #clock-cells = <0>;
 271                 clock-frequency = <24000000>;
 272                 clock-output-names = "xin24m";
 273         };
 274
 275         amba {
 276                 compatible = "arm,amba-bus";
 277                 #address-cells = <2>;
 278                 #size-cells = <2>;
 279                 ranges;
 280
 281                 dmac_bus: dma-controller@ff6d0000 {
 282                         compatible = "arm,pl330", "arm,primecell";
 283                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 284                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 286                         #dma-cells = <1>;
 287                         clocks = <&cru ACLK_DMAC0_PERILP>;
 288                         clock-names = "apb_pclk";
 289                 };
 290
 291                 dmac_peri: dma-controller@ff6e0000 {
 292                         compatible = "arm,pl330", "arm,primecell";
 293                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 294                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 295                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 296                         #dma-cells = <1>;
 297                         clocks = <&cru ACLK_DMAC1_PERILP>;
 298                         clock-names = "apb_pclk";
 299                 };
 300         };
 301
 302         gmac: eth@fe300000 {
 303                 compatible = "rockchip,rk3399-gmac";
 304                 reg = <0x0 0xfe300000 0x0 0x10000>;
 305                 rockchip,grf = <&grf>;
 306                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 307                 interrupt-names = "macirq";
 308                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 309                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 310                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 311                          <&cru PCLK_GMAC>;
 312                 clock-names = "stmmaceth", "mac_clk_rx",
 313                               "mac_clk_tx", "clk_mac_ref",
 314                               "clk_mac_refout", "aclk_mac",
 315                               "pclk_mac";
 316                 resets = <&cru SRST_A_GMAC>;
 317                 reset-names = "stmmaceth";
 318                 status = "disabled";
 319         };
 320
 321         emmc_phy: phy {
 322                 compatible = "rockchip,rk3399-emmc-phy";
 323                 reg-offset = <0xf780>;
 324                 #phy-cells = <0>;
 325                 rockchip,grf = <&grf>;
 326                 ctrl-base = <0xfe330000>;
 327                 status = "disabled";
 328         };
 329
 330         sdio0: dwmmc@fe310000 {
 331                 compatible = "rockchip,rk3399-dw-mshc",
 332                              "rockchip,rk3288-dw-mshc";
 333                 reg = <0x0 0xfe310000 0x0 0x4000>;
 334                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 335                 clock-freq-min-max = <400000 150000000>;
 336                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 337                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 338                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 339                 fifo-depth = <0x100>;
 340                 status = "disabled";
 341         };
 342
 343         sdmmc: dwmmc@fe320000 {
 344                 compatible = "rockchip,rk3399-dw-mshc",
 345                              "rockchip,rk3288-dw-mshc";
 346                 reg = <0x0 0xfe320000 0x0 0x4000>;
 347                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 348                 clock-freq-min-max = <400000 150000000>;
 349                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 350                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 351                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 352                 fifo-depth = <0x100>;
 353                 status = "disabled";
 354         };
 355
 356         sdhci: sdhci@fe330000 {
 357                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 358                 reg = <0x0 0xfe330000 0x0 0x10000>;
 359                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 360                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 361                 clock-names = "clk_xin", "clk_ahb";
 362                 assigned-clocks = <&cru SCLK_EMMC>;
 363                 assigned-clock-parents = <&cru PLL_CPLL>;
 364                 assigned-clock-rates = <200000000>;
 365                 phys = <&emmc_phy>;
 366                 phy-names = "phy_arasan";
 367                 status = "disabled";
 368         };
 369
 370         usb2phy: usb2phy {
 371                 compatible = "rockchip,rk3399-usb-phy";
 372                 rockchip,grf = <&grf>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375
 376                 usb2phy0: usb2-phy0 {
 377                         #phy-cells = <0>;
 378                         #clock-cells = <0>;
 379                         reg = <0xe458>;
 380                 };
 381
 382                 usb2phy1: usb2-phy1 {
 383                         #phy-cells = <0>;
 384                         #clock-cells = <0>;
 385                         reg = <0xe468>;
 386                 };
 387         };
 388
 389         usb_host0_ehci: usb@fe380000 {
 390                 compatible = "generic-ehci";
 391                 reg = <0x0 0xfe380000 0x0 0x20000>;
 392                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 393                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 394                 clock-names = "hclk_host0", "hclk_host0_arb";
 395                 phys = <&usb2phy0>;
 396                 phy-names = "usb2_phy0";
 397                 status = "disabled";
 398         };
 399
 400         usb_host0_ohci: usb@fe3a0000 {
 401                 compatible = "generic-ohci";
 402                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 403                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 404                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 405                 clock-names = "hclk_host0", "hclk_host0_arb";
 406                 status = "disabled";
 407         };
 408
 409         usb_host1_ehci: usb@fe3c0000 {
 410                 compatible = "generic-ehci";
 411                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 412                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 413                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 414                 clock-names = "hclk_host1", "hclk_host1_arb";
 415                 phys = <&usb2phy1>;
 416                 phy-names = "usb2_phy1";
 417                 status = "disabled";
 418         };
 419
 420         usb_host1_ohci: usb@fe3e0000 {
 421                 compatible = "generic-ohci";
 422                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 423                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 424                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 425                 clock-names = "hclk_host1", "hclk_host1_arb";
 426                 status = "disabled";
 427         };
 428
 429         usbdrd3_0: usb@fe800000 {
 430                 compatible = "rockchip,dwc3";
 431                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 432                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 433                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 434                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 435                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 436                               "aclk_usb3", "aclk_usb3_grf";
 437                 #address-cells = <2>;
 438                 #size-cells = <2>;
 439                 ranges;
 440                 status = "disabled";
 441                 usbdrd_dwc3_0: dwc3@fe800000 {
 442                         compatible = "snps,dwc3";
 443                         reg = <0x0 0xfe800000 0x0 0x100000>;
 444                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 445                         dr_mode = "otg";
 446                         snps,dis_enblslpm_quirk;
 447                         snps,phyif_utmi_16_bits;
 448                         snps,dis_u2_freeclk_exists_quirk;
 449                         snps,dis_del_phy_power_chg_quirk;
 450                         snps,xhci_slow_suspend_quirk;
 451                         status = "disabled";
 452                 };
 453         };
 454
 455         usbdrd3_1: usb@fe900000 {
 456                 compatible = "rockchip,dwc3";
 457                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 458                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 459                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 460                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 461                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 462                               "aclk_usb3", "aclk_usb3_grf";
 463                 #address-cells = <2>;
 464                 #size-cells = <2>;
 465                 ranges;
 466                 status = "disabled";
 467                 usbdrd_dwc3_1: dwc3@fe900000 {
 468                         compatible = "snps,dwc3";
 469                         reg = <0x0 0xfe900000 0x0 0x100000>;
 470                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 471                         dr_mode = "otg";
 472                         snps,dis_enblslpm_quirk;
 473                         snps,phyif_utmi_16_bits;
 474                         snps,dis_u2_freeclk_exists_quirk;
 475                         snps,dis_del_phy_power_chg_quirk;
 476                         snps,xhci_slow_suspend_quirk;
 477                         status = "disabled";
 478                 };
 479         };
 480
 481         gic: interrupt-controller@fee00000 {
 482                 compatible = "arm,gic-v3";
 483                 #interrupt-cells = <3>;
 484                 #address-cells = <2>;
 485                 #size-cells = <2>;
 486                 ranges;
 487                 interrupt-controller;
 488
 489                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 490                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 491                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 492                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 493                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 494                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 495                 its: interrupt-controller@fee20000 {
 496                         compatible = "arm,gic-v3-its";
 497                         msi-controller;
 498                         reg = <0x0 0xfee20000 0x0 0x20000>;
 499                 };
 500         };
 501
 502         saradc: saradc@ff100000 {
 503                 compatible = "rockchip,rk3399-saradc";
 504                 reg = <0x0 0xff100000 0x0 0x100>;
 505                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 506                 #io-channel-cells = <1>;
 507                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 508                 clock-names = "saradc", "apb_pclk";
 509                 status = "disabled";
 510         };
 511
 512         i2c0: i2c@ff3c0000 {
 513                 compatible = "rockchip,rk3399-i2c";
 514                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 515                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 516                 clock-names = "i2c", "pclk";
 517                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 518                 pinctrl-names = "default";
 519                 pinctrl-0 = <&i2c0_xfer>;
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 status = "disabled";
 523         };
 524
 525         i2c1: i2c@ff110000 {
 526                 compatible = "rockchip,rk3399-i2c";
 527                 reg = <0x0 0xff110000 0x0 0x1000>;
 528                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 529                 clock-names = "i2c", "pclk";
 530                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 531                 pinctrl-names = "default";
 532                 pinctrl-0 = <&i2c1_xfer>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 status = "disabled";
 536         };
 537
 538         i2c2: i2c@ff120000 {
 539                 compatible = "rockchip,rk3399-i2c";
 540                 reg = <0x0 0xff120000 0x0 0x1000>;
 541                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 542                 clock-names = "i2c", "pclk";
 543                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 544                 pinctrl-names = "default";
 545                 pinctrl-0 = <&i2c2_xfer>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 status = "disabled";
 549         };
 550
 551         i2c3: i2c@ff130000 {
 552                 compatible = "rockchip,rk3399-i2c";
 553                 reg = <0x0 0xff130000 0x0 0x1000>;
 554                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 555                 clock-names = "i2c", "pclk";
 556                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&i2c3_xfer>;
 559                 #address-cells = <1>;
 560                 #size-cells = <0>;
 561                 status = "disabled";
 562         };
 563
 564         i2c5: i2c@ff140000 {
 565                 compatible = "rockchip,rk3399-i2c";
 566                 reg = <0x0 0xff140000 0x0 0x1000>;
 567                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 568                 clock-names = "i2c", "pclk";
 569                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 570                 pinctrl-names = "default";
 571                 pinctrl-0 = <&i2c5_xfer>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 status = "disabled";
 575         };
 576
 577         i2c6: i2c@ff150000 {
 578                 compatible = "rockchip,rk3399-i2c";
 579                 reg = <0x0 0xff150000 0x0 0x1000>;
 580                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 581                 clock-names = "i2c", "pclk";
 582                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 583                 pinctrl-names = "default";
 584                 pinctrl-0 = <&i2c6_xfer>;
 585                 #address-cells = <1>;
 586                 #size-cells = <0>;
 587                 status = "disabled";
 588         };
 589
 590         i2c7: i2c@ff160000 {
 591                 compatible = "rockchip,rk3399-i2c";
 592                 reg = <0x0 0xff160000 0x0 0x1000>;
 593                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 594                 clock-names = "i2c", "pclk";
 595                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 596                 pinctrl-names = "default";
 597                 pinctrl-0 = <&i2c7_xfer>;
 598                 #address-cells = <1>;
 599                 #size-cells = <0>;
 600                 status = "disabled";
 601         };
 602
 603         uart0: serial@ff180000 {
 604                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 605                 reg = <0x0 0xff180000 0x0 0x100>;
 606                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 607                 clock-names = "baudclk", "apb_pclk";
 608                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 609                 reg-shift = <2>;
 610                 reg-io-width = <4>;
 611                 pinctrl-names = "default";
 612                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 613                 status = "disabled";
 614         };
 615
 616         uart1: serial@ff190000 {
 617                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 618                 reg = <0x0 0xff190000 0x0 0x100>;
 619                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 620                 clock-names = "baudclk", "apb_pclk";
 621                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 622                 reg-shift = <2>;
 623                 reg-io-width = <4>;
 624                 pinctrl-names = "default";
 625                 pinctrl-0 = <&uart1_xfer>;
 626                 status = "disabled";
 627         };
 628
 629         uart2: serial@ff1a0000 {
 630                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 631                 reg = <0x0 0xff1a0000 0x0 0x100>;
 632                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 633                 clock-names = "baudclk", "apb_pclk";
 634                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 635                 reg-shift = <2>;
 636                 reg-io-width = <4>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&uart2c_xfer>;
 639                 status = "disabled";
 640         };
 641
 642         uart3: serial@ff1b0000 {
 643                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 644                 reg = <0x0 0xff1b0000 0x0 0x100>;
 645                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 646                 clock-names = "baudclk", "apb_pclk";
 647                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 648                 reg-shift = <2>;
 649                 reg-io-width = <4>;
 650                 pinctrl-names = "default";
 651                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 652                 status = "disabled";
 653         };
 654
 655         spi0: spi@ff1c0000 {
 656                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 657                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 658                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 659                 clock-names = "spiclk", "apb_pclk";
 660                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 661                 pinctrl-names = "default";
 662                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 663                 #address-cells = <1>;
 664                 #size-cells = <0>;
 665                 status = "disabled";
 666         };
 667
 668         spi1: spi@ff1d0000 {
 669                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 670                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 671                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 672                 clock-names = "spiclk", "apb_pclk";
 673                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 674                 pinctrl-names = "default";
 675                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 676                 #address-cells = <1>;
 677                 #size-cells = <0>;
 678                 status = "disabled";
 679         };
 680
 681         spi2: spi@ff1e0000 {
 682                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 683                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 684                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 685                 clock-names = "spiclk", "apb_pclk";
 686                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 687                 pinctrl-names = "default";
 688                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 689                 #address-cells = <1>;
 690                 #size-cells = <0>;
 691                 status = "disabled";
 692         };
 693
 694         spi4: spi@ff1f0000 {
 695                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 696                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 697                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 698                 clock-names = "spiclk", "apb_pclk";
 699                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 700                 pinctrl-names = "default";
 701                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 702                 #address-cells = <1>;
 703                 #size-cells = <0>;
 704                 status = "disabled";
 705         };
 706
 707         spi5: spi@ff200000 {
 708                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 709                 reg = <0x0 0xff200000 0x0 0x1000>;
 710                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 711                 clock-names = "spiclk", "apb_pclk";
 712                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 713                 pinctrl-names = "default";
 714                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 715                 #address-cells = <1>;
 716                 #size-cells = <0>;
 717                 status = "disabled";
 718         };
 719
 720         thermal-zones {
 721                 soc_thermal: soc-thermal {
 722                         polling-delay-passive = <100>; /* milliseconds */
 723                         polling-delay = <1000>; /* milliseconds */
 724                         sustainable-power = <2600>; /* milliwatts */
 725
 726                         thermal-sensors = <&tsadc 0>;
 727
 728                         trips {
 729                                 threshold: trip-point@0 {
 730                                         temperature = <70000>; /* millicelsius */
 731                                         hysteresis = <2000>; /* millicelsius */
 732                                         type = "passive";
 733                                 };
 734                                 target: trip-point@1 {
 735                                         temperature = <85000>; /* millicelsius */
 736                                         hysteresis = <2000>; /* millicelsius */
 737                                         type = "passive";
 738                                 };
 739                                 soc_crit: soc-crit {
 740                                         temperature = <95000>; /* millicelsius */
 741                                         hysteresis = <2000>; /* millicelsius */
 742                                         type = "critical";
 743                                 };
 744                         };
 745
 746                         cooling-maps {
 747                                 map0 {
 748                                         trip = <&target>;
 749                                         cooling-device =
 750                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 751                                 };
 752                                 map1 {
 753                                         trip = <&target>;
 754                                         cooling-device =
 755                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 756                                 };
 757                                 map2 {
 758                                         trip = <&target>;
 759                                         cooling-device =
 760                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 761                                 };
 762                         };
 763                 };
 764
 765                 gpu_thermal: gpu-thermal {
 766                         polling-delay-passive = <100>; /* milliseconds */
 767                         polling-delay = <1000>; /* milliseconds */
 768
 769                         thermal-sensors = <&tsadc 1>;
 770                 };
 771         };
 772
 773         tsadc: tsadc@ff260000 {
 774                 compatible = "rockchip,rk3399-tsadc";
 775                 reg = <0x0 0xff260000 0x0 0x100>;
 776                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 777                 rockchip,grf = <&grf>;
 778                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 779                 clock-names = "tsadc", "apb_pclk";
 780                 assigned-clocks = <&cru SCLK_TSADC>;
 781                 assigned-clock-rates = <750000>;
 782                 resets = <&cru SRST_TSADC>;
 783                 reset-names = "tsadc-apb";
 784                 pinctrl-names = "init", "default", "sleep";
 785                 pinctrl-0 = <&otp_gpio>;
 786                 pinctrl-1 = <&otp_out>;
 787                 pinctrl-2 = <&otp_gpio>;
 788                 #thermal-sensor-cells = <1>;
 789                 rockchip,hw-tshut-temp = <95000>;
 790                 status = "disabled";
 791         };
 792
 793         qos_gpu: qos_gpu@0xffae0000 {
 794                 compatible ="syscon";
 795                 reg = <0x0 0xffae0000 0x0 0x20>;
 796         };
 797         qos_video_m0: qos_video_m0@0xffab8000 {
 798                 compatible ="syscon";
 799                 reg = <0x0 0xffab8000 0x0 0x20>;
 800         };
 801         qos_video_m1_r: qos_video_m1_r@0xffac0000 {
 802                 compatible ="syscon";
 803                 reg = <0x0 0xffac0000 0x0 0x20>;
 804         };
 805         qos_video_m1_w: qos_video_m1_w@0xffac0080 {
 806                 compatible ="syscon";
 807                 reg = <0x0 0xffac0080 0x0 0x20>;
 808         };
 809         qos_rga_r: qos_rga_r@0xffab0000 {
 810                 compatible ="syscon";
 811                 reg = <0x0 0xffab0000 0x0 0x20>;
 812         };
 813         qos_rga_w: qos_rga_w@0xffab0080 {
 814                 compatible ="syscon";
 815                 reg = <0x0 0xffab0000 0x0 0x20>;
 816         };
 817         qos_iep: qos_iep@0xffa98000 {
 818                 compatible ="syscon";
 819                 reg = <0x0 0xffa98000 0x0 0x20>;
 820         };
 821         qos_vop_big_r: qos_vop_big_r@0xffac8000 {
 822                 compatible ="syscon";
 823                 reg = <0x0 0xffac8000 0x0 0x20>;
 824         };
 825         qos_vop_big_w: qos_vop_big_w@0xffac8080 {
 826                 compatible ="syscon";
 827                 reg = <0x0 0xffac8080 0x0 0x20>;
 828         };
 829         qos_vop_little: qos_vop_little@0xffad0000 {
 830                 compatible ="syscon";
 831                 reg = <0x0 0xffad0000 0x0 0x20>;
 832         };
 833         qos_isp0_m0: qos_isp0_m0@0xffaa0000 {
 834                 compatible ="syscon";
 835                 reg = <0x0 0xffaa0000 0x0 0x20>;
 836         };
 837         qos_isp0_m1: qos_isp0_m1@0xffaa0080 {
 838                 compatible ="syscon";
 839                 reg = <0x0 0xffaa0080 0x0 0x20>;
 840         };
 841         qos_isp1_m0: qos_isp1_m0@0xffaa8000 {
 842                 compatible ="syscon";
 843                 reg = <0x0 0xffaa8000 0x0 0x20>;
 844         };
 845         qos_isp1_m1: qos_isp1_m1@0xffaa8080 {
 846                 compatible ="syscon";
 847                 reg = <0x0 0xffaa8080 0x0 0x20>;
 848         };
 849         qos_hdcp: qos_hdcp@0xffa90000 {
 850                 compatible ="syscon";
 851                 reg = <0x0 0xffa90000 0x0 0x20>;
 852         };
 853
 854         pmu: power-management@ff310000 {
 855                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 856                 reg = <0x0 0xff310000 0x0 0x1000>;
 857
 858                 power: power-controller {
 859                         status = "okay";
 860                         compatible = "rockchip,rk3399-power-controller";
 861                         #power-domain-cells = <1>;
 862                         #address-cells = <1>;
 863                         #size-cells = <0>;
 864
 865
 866                         pd_vdu {
 867                                 reg = <RK3399_PD_VDU>;
 868                                 pm_qos = <&qos_video_m1_r>,
 869                                          <&qos_video_m1_w>;
 870                         };
 871                         pd_vcodec {
 872                                 reg = <RK3399_PD_VCODEC>;
 873                                 pm_qos = <&qos_video_m0>;
 874                         };
 875                         pd_iep {
 876                                 reg = <RK3399_PD_IEP>;
 877                                 pm_qos = <&qos_iep>;
 878                         };
 879                         pd_rga {
 880                                 reg = <RK3399_PD_RGA>;
 881                                 pm_qos = <&qos_rga_r>,
 882                                          <&qos_rga_w>;
 883                         };
 884                         pd_vio {
 885                                 reg = <RK3399_PD_VIO>;
 886                                 #address-cells = <1>;
 887                                 #size-cells = <0>;
 888
 889                                 pd_isp0 {
 890                                         reg = <RK3399_PD_ISP0>;
 891                                         pm_qos = <&qos_isp0_m0>,
 892                                                  <&qos_isp0_m1>;
 893                                 };
 894                                 pd_isp1 {
 895                                         reg = <RK3399_PD_ISP1>;
 896                                         pm_qos = <&qos_isp1_m0>,
 897                                                  <&qos_isp1_m1>;
 898                                 };
 899                                 pd_hdcp {
 900                                         reg = <RK3399_PD_HDCP>;
 901                                         pm_qos = <&qos_hdcp>;
 902                                 };
 903                                 pd_vo {
 904                                         reg = <RK3399_PD_VO>;
 905                                         #address-cells = <1>;
 906                                         #size-cells = <0>;
 907
 908                                         pd_vopb {
 909                                                 reg = <RK3399_PD_VOPB>;
 910                                                 pm_qos = <&qos_vop_big_r>,
 911                                                          <&qos_vop_big_w>;
 912                                         };
 913                                         pd_vopl {
 914                                                 reg = <RK3399_PD_VOPL>;
 915                                                 pm_qos = <&qos_vop_little>;
 916                                         };
 917                                 };
 918                         };
 919                         pd_gpu {
 920                                 reg = <RK3399_PD_GPU>;
 921                                 pm_qos = <&qos_gpu>;
 922                         };
 923                 };
 924         };
 925
 926         pmugrf: syscon@ff320000 {
 927                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 928                 reg = <0x0 0xff320000 0x0 0x1000>;
 929
 930                 reboot-mode {
 931                         compatible = "syscon-reboot-mode";
 932                         offset = <0x300>;
 933                         mode-normal = <BOOT_NORMAL>;
 934                         mode-recovery = <BOOT_RECOVERY>;
 935                         mode-bootloader = <BOOT_FASTBOOT>;
 936                         mode-loader = <BOOT_LOADER>;
 937                 };
 938         };
 939
 940         spi3: spi@ff350000 {
 941                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 942                 reg = <0x0 0xff350000 0x0 0x1000>;
 943                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 944                 clock-names = "spiclk", "apb_pclk";
 945                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 946                 pinctrl-names = "default";
 947                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 948                 #address-cells = <1>;
 949                 #size-cells = <0>;
 950                 status = "disabled";
 951         };
 952
 953         uart4: serial@ff370000 {
 954                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 955                 reg = <0x0 0xff370000 0x0 0x100>;
 956                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 957                 clock-names = "baudclk", "apb_pclk";
 958                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 959                 reg-shift = <2>;
 960                 reg-io-width = <4>;
 961                 pinctrl-names = "default";
 962                 pinctrl-0 = <&uart4_xfer>;
 963                 status = "disabled";
 964         };
 965
 966         i2c4: i2c@ff3d0000 {
 967                 compatible = "rockchip,rk3399-i2c";
 968                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 969                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 970                 clock-names = "i2c", "pclk";
 971                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 972                 pinctrl-names = "default";
 973                 pinctrl-0 = <&i2c4_xfer>;
 974                 #address-cells = <1>;
 975                 #size-cells = <0>;
 976                 status = "disabled";
 977         };
 978
 979         i2c8: i2c@ff3e0000 {
 980                 compatible = "rockchip,rk3399-i2c";
 981                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 982                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 983                 clock-names = "i2c", "pclk";
 984                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 985                 pinctrl-names = "default";
 986                 pinctrl-0 = <&i2c8_xfer>;
 987                 #address-cells = <1>;
 988                 #size-cells = <0>;
 989                 status = "disabled";
 990         };
 991
 992         pcie0: pcie@f8000000 {
 993                 compatible = "rockchip,rk3399-pcie";
 994                 #address-cells = <3>;
 995                 #size-cells = <2>;
 996                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 997                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
 998                 clock-names = "aclk_pcie", "aclk_perf_pcie",
 999                               "hclk_pcie", "clk_pciephy_ref";
1000                 bus-range = <0x0 0x1>;
1001                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1002                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1003                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1004                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1005                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1006                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1007                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1008                       < 0x0 0xfd000000 0x0 0x1000000 >;
1009                 reg-name = "axi-base", "apb-base";
1010                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1011                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1012                          <&cru SRST_PCIE_PIPE>;
1013                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1014                               "mgmt-sticky-rst", "pipe-rst";
1015                 rockchip,grf = <&grf>;
1016                 pcie-conf = <0xe220>;
1017                 pcie-status = <0xe2a4>;
1018                 pcie-laneoff = <0xe214>;
1019                 msi-parent = <&its>;
1020                 #interrupt-cells = <1>;
1021                 interrupt-map-mask = <0 0 0 7>;
1022                 interrupt-map = <0 0 0 1 &pcie0 1>,
1023                                 <0 0 0 2 &pcie0 2>,
1024                                 <0 0 0 3 &pcie0 3>,
1025                                 <0 0 0 4 &pcie0 4>;
1026                 status = "disabled";
1027                 pcie_intc: interrupt-controller {
1028                         interrupt-controller;
1029                         #address-cells = <0>;
1030                         #interrupt-cells = <1>;
1031                 };
1032         };
1033
1034         pwm0: pwm@ff420000 {
1035                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1036                 reg = <0x0 0xff420000 0x0 0x10>;
1037                 #pwm-cells = <3>;
1038                 pinctrl-names = "default";
1039                 pinctrl-0 = <&pwm0_pin>;
1040                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1041                 clock-names = "pwm";
1042                 status = "disabled";
1043         };
1044
1045         pwm1: pwm@ff420010 {
1046                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1047                 reg = <0x0 0xff420010 0x0 0x10>;
1048                 #pwm-cells = <3>;
1049                 pinctrl-names = "default";
1050                 pinctrl-0 = <&pwm1_pin>;
1051                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1052                 clock-names = "pwm";
1053                 status = "disabled";
1054         };
1055
1056         pwm2: pwm@ff420020 {
1057                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1058                 reg = <0x0 0xff420020 0x0 0x10>;
1059                 #pwm-cells = <3>;
1060                 pinctrl-names = "default";
1061                 pinctrl-0 = <&pwm2_pin>;
1062                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1063                 clock-names = "pwm";
1064                 status = "disabled";
1065         };
1066
1067         pwm3: pwm@ff420030 {
1068                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1069                 reg = <0x0 0xff420030 0x0 0x10>;
1070                 #pwm-cells = <3>;
1071                 pinctrl-names = "default";
1072                 pinctrl-0 = <&pwm3a_pin>;
1073                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1074                 clock-names = "pwm";
1075                 status = "disabled";
1076         };
1077
1078         rga: rga@ff680000 {
1079                 compatible = "rockchip,rk3399-rga";
1080                 reg = <0x0 0xff680000 0x0 0x10000>;
1081                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1082                 interrupt-names = "rga";
1083                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1084                 clock-names = "aclk", "hclk", "sclk";
1085                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1086                 reset-names = "core", "axi", "ahb";
1087                 status = "disabled";
1088         };
1089
1090         pmucru: pmu-clock-controller@ff750000 {
1091                 compatible = "rockchip,rk3399-pmucru";
1092                 reg = <0x0 0xff750000 0x0 0x1000>;
1093                 #clock-cells = <1>;
1094                 #reset-cells = <1>;
1095                 assigned-clocks = <&pmucru PLL_PPLL>;
1096                 assigned-clock-rates = <676000000>;
1097         };
1098
1099         cru: clock-controller@ff760000 {
1100                 compatible = "rockchip,rk3399-cru";
1101                 reg = <0x0 0xff760000 0x0 0x1000>;
1102                 #clock-cells = <1>;
1103                 #reset-cells = <1>;
1104                 assigned-clocks =
1105                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1106                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1107                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1108                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1109                         <&cru PLL_NPLL>,
1110                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1111                         <&cru PCLK_PERIHP>,
1112                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1113                         <&cru PCLK_PERILP0>,
1114                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1115                 assigned-clock-rates =
1116                          <400000000>,  <200000000>,
1117                          <400000000>,  <200000000>,
1118                          <816000000>, <816000000>,
1119                          <594000000>,  <800000000>,
1120                         <1000000000>,
1121                          <150000000>,   <75000000>,
1122                           <37500000>,
1123                          <100000000>,  <100000000>,
1124                           <50000000>,
1125                          <100000000>,   <50000000>;
1126         };
1127
1128         grf: syscon@ff770000 {
1129                 compatible = "rockchip,rk3399-grf", "syscon";
1130                 reg = <0x0 0xff770000 0x0 0x10000>;
1131         };
1132
1133         watchdog@ff840000 {
1134                 compatible = "snps,dw-wdt";
1135                 reg = <0x0 0xff840000 0x0 0x100>;
1136                 clocks = <&cru PCLK_WDT>;
1137                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1138         };
1139
1140         rktimer: rktimer@ff850000 {
1141                 compatible = "rockchip,rk3399-timer";
1142                 reg = <0x0 0xff850000 0x0 0x1000>;
1143                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1144                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1145                 clock-names = "pclk", "timer";
1146         };
1147
1148         spdif: spdif@ff870000 {
1149                 compatible = "rockchip,rk3399-spdif";
1150                 reg = <0x0 0xff870000 0x0 0x1000>;
1151                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1152                 dmas = <&dmac_bus 7>;
1153                 dma-names = "tx";
1154                 clock-names = "mclk", "hclk";
1155                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1156                 pinctrl-names = "default";
1157                 pinctrl-0 = <&spdif_bus>;
1158                 status = "disabled";
1159         };
1160
1161         i2s0: i2s@ff880000 {
1162                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1163                 reg = <0x0 0xff880000 0x0 0x1000>;
1164                 rockchip,grf = <&grf>;
1165                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1166                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1167                 dma-names = "tx", "rx";
1168                 clock-names = "i2s_clk", "i2s_hclk";
1169                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1170                 pinctrl-names = "default";
1171                 pinctrl-0 = <&i2s0_8ch_bus>;
1172                 status = "disabled";
1173         };
1174
1175         i2s1: i2s@ff890000 {
1176                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1177                 reg = <0x0 0xff890000 0x0 0x1000>;
1178                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1179                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1180                 dma-names = "tx", "rx";
1181                 clock-names = "i2s_clk", "i2s_hclk";
1182                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1183                 pinctrl-names = "default";
1184                 pinctrl-0 = <&i2s1_2ch_bus>;
1185                 status = "disabled";
1186         };
1187
1188         i2s2: i2s@ff8a0000 {
1189                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1190                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1191                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1192                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1193                 dma-names = "tx", "rx";
1194                 clock-names = "i2s_clk", "i2s_hclk";
1195                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1196                 status = "disabled";
1197         };
1198
1199         gpu: gpu@ff9a0000 {
1200                 compatible = "arm,malit860",
1201                              "arm,malit86x",
1202                              "arm,malit8xx",
1203                              "arm,mali-midgard";
1204
1205                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1206
1207                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1208                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1209                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1210                 interrupt-names = "GPU", "JOB", "MMU";
1211
1212                 clocks = <&cru ACLK_GPU>;
1213                 clock-names = "clk_mali";
1214                 #cooling-cells = <2>; /* min followed by max */
1215                 operating-points-v2 = <&gpu_opp_table>;
1216                 power-domains = <&power RK3399_PD_GPU>;
1217                 status = "disabled";
1218
1219                 power_model {
1220                         compatible = "arm,mali-simple-power-model";
1221                         voltage = <900>;
1222                         frequency = <500>;
1223                         static-power = <300>;
1224                         dynamic-power = <1780>;
1225                         ts = <32000 4700 (-80) 2>;
1226                         thermal-zone = "gpu-thermal";
1227                 };
1228         };
1229
1230         gpu_opp_table: gpu_opp_table {
1231                 compatible = "operating-points-v2";
1232                 opp-shared;
1233
1234                 opp00 {
1235                         opp-hz = /bits/ 64 <200000000>;
1236                         opp-microvolt = <900000>;
1237                 };
1238                 opp01 {
1239                         opp-hz = /bits/ 64 <300000000>;
1240                         opp-microvolt = <900000>;
1241                 };
1242                 opp02 {
1243                         opp-hz = /bits/ 64 <400000000>;
1244                         opp-microvolt = <900000>;
1245                 };
1246
1247         };
1248
1249         vopl: vop@ff8f0000 {
1250                 compatible = "rockchip,rk3399-vop-lit";
1251                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1252                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1253                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1254                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1255                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1256                 reset-names = "axi", "ahb", "dclk";
1257                 iommus = <&vopl_mmu>;
1258                 status = "disabled";
1259
1260                 vopl_out: port {
1261                         #address-cells = <1>;
1262                         #size-cells = <0>;
1263
1264                         vopl_out_mipi: endpoint@0 {
1265                                 reg = <0>;
1266                                 remote-endpoint = <&mipi_in_vopl>;
1267                         };
1268
1269                         vopl_out_edp: endpoint@1 {
1270                                 reg = <1>;
1271                                 remote-endpoint = <&edp_in_vopl>;
1272                         };
1273                 };
1274         };
1275
1276         vopl_mmu: iommu@ff8f3f00 {
1277                 compatible = "rockchip,iommu";
1278                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1279                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1280                 interrupt-names = "vopl_mmu";
1281                 #iommu-cells = <0>;
1282                 status = "disabled";
1283         };
1284
1285         vopb: vop@ff900000 {
1286                 compatible = "rockchip,rk3399-vop-big";
1287                 reg = <0x0 0xff900000 0x0 0x3efc>;
1288                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1289                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1290                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1291                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1292                 reset-names = "axi", "ahb", "dclk";
1293                 iommus = <&vopb_mmu>;
1294                 status = "disabled";
1295
1296                 vopb_out: port {
1297                         #address-cells = <1>;
1298                         #size-cells = <0>;
1299
1300                         vopb_out_edp: endpoint@0 {
1301                                 reg = <0>;
1302                                 remote-endpoint = <&edp_in_vopb>;
1303                         };
1304
1305                         vopb_out_mipi: endpoint@1 {
1306                                 reg = <1>;
1307                                 remote-endpoint = <&mipi_in_vopb>;
1308                         };
1309                 };
1310         };
1311
1312         vopb_mmu: iommu@ff903f00 {
1313                 compatible = "rockchip,iommu";
1314                 reg = <0x0 0xff903f00 0x0 0x100>;
1315                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1316                 interrupt-names = "vopb_mmu";
1317                 #iommu-cells = <0>;
1318                 status = "disabled";
1319         };
1320
1321         mipi_dsi: mipi@ff960000 {
1322                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1323                 reg = <0x0 0xff960000 0x0 0x8000>;
1324                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1325                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1326                          <&cru SCLK_DPHY_TX0_CFG>;
1327                 clock-names = "ref", "pclk", "phy_cfg";
1328                 rockchip,grf = <&grf>;
1329                 #address-cells = <1>;
1330                 #size-cells = <0>;
1331                 status = "disabled";
1332
1333                 ports {
1334                         #address-cells = <1>;
1335                         #size-cells = <0>;
1336                         reg = <1>;
1337
1338                         mipi_in: port {
1339                                 #address-cells = <1>;
1340                                 #size-cells = <0>;
1341
1342                                 mipi_in_vopb: endpoint@0 {
1343                                         reg = <0>;
1344                                         remote-endpoint = <&vopb_out_mipi>;
1345                                 };
1346                                 mipi_in_vopl: endpoint@1 {
1347                                         reg = <1>;
1348                                         remote-endpoint = <&vopl_out_mipi>;
1349                                 };
1350                         };
1351                 };
1352         };
1353
1354         edp: edp@ff970000 {
1355                 compatible = "rockchip,rk3399-edp";
1356                 reg = <0x0 0xff970000 0x0 0x8000>;
1357                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1358                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1359                 clock-names = "dp", "pclk";
1360                 resets = <&cru SRST_P_EDP_CTRL>;
1361                 reset-names = "dp";
1362                 rockchip,grf = <&grf>;
1363                 status = "disabled";
1364                 pinctrl-names = "default";
1365                 pinctrl-0 = <&edp_hpd>;
1366
1367                 ports {
1368                         #address-cells = <1>;
1369                         #size-cells = <0>;
1370
1371                         edp_in: port@0 {
1372                                 reg = <0>;
1373                                 #address-cells = <1>;
1374                                 #size-cells = <0>;
1375
1376                                 edp_in_vopb: endpoint@0 {
1377                                         reg = <0>;
1378                                         remote-endpoint = <&vopb_out_edp>;
1379                                 };
1380
1381                                 edp_in_vopl: endpoint@1 {
1382                                         reg = <1>;
1383                                         remote-endpoint = <&vopl_out_edp>;
1384                                 };
1385                         };
1386                 };
1387         };
1388
1389         display_subsystem: display-subsystem {
1390                 compatible = "rockchip,display-subsystem";
1391                 ports = <&vopl_out>, <&vopb_out>;
1392                 status = "disabled";
1393         };
1394
1395         pinctrl: pinctrl {
1396                 compatible = "rockchip,rk3399-pinctrl";
1397                 rockchip,grf = <&grf>;
1398                 rockchip,pmu = <&pmugrf>;
1399                 #address-cells = <0x2>;
1400                 #size-cells = <0x2>;
1401                 ranges;
1402
1403                 gpio0: gpio0@ff720000 {
1404                         compatible = "rockchip,gpio-bank";
1405                         reg = <0x0 0xff720000 0x0 0x100>;
1406                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1407                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1408
1409                         gpio-controller;
1410                         #gpio-cells = <0x2>;
1411
1412                         interrupt-controller;
1413                         #interrupt-cells = <0x2>;
1414                 };
1415
1416                 gpio1: gpio1@ff730000 {
1417                         compatible = "rockchip,gpio-bank";
1418                         reg = <0x0 0xff730000 0x0 0x100>;
1419                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1420                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1421
1422                         gpio-controller;
1423                         #gpio-cells = <0x2>;
1424
1425                         interrupt-controller;
1426                         #interrupt-cells = <0x2>;
1427                 };
1428
1429                 gpio2: gpio2@ff780000 {
1430                         compatible = "rockchip,gpio-bank";
1431                         reg = <0x0 0xff780000 0x0 0x100>;
1432                         clocks = <&cru PCLK_GPIO2>;
1433                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1434
1435                         gpio-controller;
1436                         #gpio-cells = <0x2>;
1437
1438                         interrupt-controller;
1439                         #interrupt-cells = <0x2>;
1440                 };
1441
1442                 gpio3: gpio3@ff788000 {
1443                         compatible = "rockchip,gpio-bank";
1444                         reg = <0x0 0xff788000 0x0 0x100>;
1445                         clocks = <&cru PCLK_GPIO3>;
1446                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1447
1448                         gpio-controller;
1449                         #gpio-cells = <0x2>;
1450
1451                         interrupt-controller;
1452                         #interrupt-cells = <0x2>;
1453                 };
1454
1455                 gpio4: gpio4@ff790000 {
1456                         compatible = "rockchip,gpio-bank";
1457                         reg = <0x0 0xff790000 0x0 0x100>;
1458                         clocks = <&cru PCLK_GPIO4>;
1459                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1460
1461                         gpio-controller;
1462                         #gpio-cells = <0x2>;
1463
1464                         interrupt-controller;
1465                         #interrupt-cells = <0x2>;
1466                 };
1467
1468                 pcfg_pull_up: pcfg-pull-up {
1469                         bias-pull-up;
1470                 };
1471
1472                 pcfg_pull_down: pcfg-pull-down {
1473                         bias-pull-down;
1474                 };
1475
1476                 pcfg_pull_none: pcfg-pull-none {
1477                         bias-disable;
1478                 };
1479
1480                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1481                         bias-disable;
1482                         drive-strength = <12>;
1483                 };
1484
1485                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1486                         bias-pull-up;
1487                         drive-strength = <8>;
1488                 };
1489
1490                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1491                         bias-pull-down;
1492                         drive-strength = <4>;
1493                 };
1494
1495                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1496                         bias-pull-up;
1497                         drive-strength = <2>;
1498                 };
1499
1500                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1501                         bias-pull-down;
1502                         drive-strength = <12>;
1503                 };
1504
1505                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1506                         bias-disable;
1507                         drive-strength = <13>;
1508                 };
1509
1510                 emmc {
1511                         emmc_pwr: emmc-pwr {
1512                                 rockchip,pins =
1513                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1514                         };
1515                 };
1516
1517                 gmac {
1518                         rgmii_pins: rgmii-pins {
1519                                 rockchip,pins =
1520                                         /* mac_txclk */
1521                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1522                                         /* mac_rxclk */
1523                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1524                                         /* mac_mdio */
1525                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1526                                         /* mac_txen */
1527                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1528                                         /* mac_clk */
1529                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1530                                         /* mac_rxdv */
1531                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1532                                         /* mac_mdc */
1533                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1534                                         /* mac_rxd1 */
1535                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1536                                         /* mac_rxd0 */
1537                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1538                                         /* mac_txd1 */
1539                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1540                                         /* mac_txd0 */
1541                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1542                                         /* mac_rxd3 */
1543                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1544                                         /* mac_rxd2 */
1545                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1546                                         /* mac_txd3 */
1547                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1548                                         /* mac_txd2 */
1549                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1550                         };
1551
1552                         rmii_pins: rmii-pins {
1553                                 rockchip,pins =
1554                                         /* mac_mdio */
1555                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1556                                         /* mac_txen */
1557                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1558                                         /* mac_clk */
1559                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1560                                         /* mac_rxer */
1561                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1562                                         /* mac_rxdv */
1563                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1564                                         /* mac_mdc */
1565                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1566                                         /* mac_rxd1 */
1567                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1568                                         /* mac_rxd0 */
1569                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1570                                         /* mac_txd1 */
1571                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1572                                         /* mac_txd0 */
1573                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1574                         };
1575                 };
1576
1577                 i2c0 {
1578                         i2c0_xfer: i2c0-xfer {
1579                                 rockchip,pins =
1580                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1581                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1582                         };
1583                 };
1584
1585                 i2c1 {
1586                         i2c1_xfer: i2c1-xfer {
1587                                 rockchip,pins =
1588                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1589                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1590                         };
1591                 };
1592
1593                 i2c2 {
1594                         i2c2_xfer: i2c2-xfer {
1595                                 rockchip,pins =
1596                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1597                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1598                         };
1599                 };
1600
1601                 i2c3 {
1602                         i2c3_xfer: i2c3-xfer {
1603                                 rockchip,pins =
1604                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1605                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1606                         };
1607
1608                         i2c3_gpio: i2c3_gpio {
1609                                 rockchip,pins =
1610                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1611                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1612                         };
1613
1614                 };
1615
1616                 i2c4 {
1617                         i2c4_xfer: i2c4-xfer {
1618                                 rockchip,pins =
1619                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1620                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1621                         };
1622                 };
1623
1624                 i2c5 {
1625                         i2c5_xfer: i2c5-xfer {
1626                                 rockchip,pins =
1627                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1628                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1629                         };
1630                 };
1631
1632                 i2c6 {
1633                         i2c6_xfer: i2c6-xfer {
1634                                 rockchip,pins =
1635                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1636                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1637                         };
1638                 };
1639
1640                 i2c7 {
1641                         i2c7_xfer: i2c7-xfer {
1642                                 rockchip,pins =
1643                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1644                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1645                         };
1646                 };
1647
1648                 i2c8 {
1649                         i2c8_xfer: i2c8-xfer {
1650                                 rockchip,pins =
1651                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1652                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1653                         };
1654                 };
1655
1656                 i2s0 {
1657                         i2s0_8ch_bus: i2s0-8ch-bus {
1658                                 rockchip,pins =
1659                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1660                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1661                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1662                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1663                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1664                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1665                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1666                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1667                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1668                         };
1669                 };
1670
1671                 i2s1 {
1672                         i2s1_2ch_bus: i2s1-2ch-bus {
1673                                 rockchip,pins =
1674                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1675                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1676                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1677                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1678                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1679                         };
1680                 };
1681
1682                 sdio0 {
1683                         sdio0_bus1: sdio0-bus1 {
1684                                 rockchip,pins =
1685                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1686                         };
1687
1688                         sdio0_bus4: sdio0-bus4 {
1689                                 rockchip,pins =
1690                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1691                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1692                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1693                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1694                         };
1695
1696                         sdio0_cmd: sdio0-cmd {
1697                                 rockchip,pins =
1698                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1699                         };
1700
1701                         sdio0_clk: sdio0-clk {
1702                                 rockchip,pins =
1703                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1704                         };
1705
1706                         sdio0_cd: sdio0-cd {
1707                                 rockchip,pins =
1708                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1709                         };
1710
1711                         sdio0_pwr: sdio0-pwr {
1712                                 rockchip,pins =
1713                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1714                         };
1715
1716                         sdio0_bkpwr: sdio0-bkpwr {
1717                                 rockchip,pins =
1718                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1719                         };
1720
1721                         sdio0_wp: sdio0-wp {
1722                                 rockchip,pins =
1723                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1724                         };
1725
1726                         sdio0_int: sdio0-int {
1727                                 rockchip,pins =
1728                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1729                         };
1730                 };
1731
1732                 sdmmc {
1733                         sdmmc_bus1: sdmmc-bus1 {
1734                                 rockchip,pins =
1735                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1736                         };
1737
1738                         sdmmc_bus4: sdmmc-bus4 {
1739                                 rockchip,pins =
1740                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1741                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1742                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1743                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1744                         };
1745
1746                         sdmmc_clk: sdmmc-clk {
1747                                 rockchip,pins =
1748                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1749                         };
1750
1751                         sdmmc_cmd: sdmmc-cmd {
1752                                 rockchip,pins =
1753                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1754                         };
1755
1756                         sdmmc_cd: sdmcc-cd {
1757                                 rockchip,pins =
1758                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1759                         };
1760
1761                         sdmmc_wp: sdmmc-wp {
1762                                 rockchip,pins =
1763                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1764                         };
1765                 };
1766
1767                 spdif {
1768                         spdif_bus: spdif-bus {
1769                                 rockchip,pins =
1770                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1771                         };
1772                 };
1773
1774                 spi0 {
1775                         spi0_clk: spi0-clk {
1776                                 rockchip,pins =
1777                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1778                         };
1779                         spi0_cs0: spi0-cs0 {
1780                                 rockchip,pins =
1781                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1782                         };
1783                         spi0_cs1: spi0-cs1 {
1784                                 rockchip,pins =
1785                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1786                         };
1787                         spi0_tx: spi0-tx {
1788                                 rockchip,pins =
1789                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1790                         };
1791                         spi0_rx: spi0-rx {
1792                                 rockchip,pins =
1793                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1794                         };
1795                 };
1796
1797                 spi1 {
1798                         spi1_clk: spi1-clk {
1799                                 rockchip,pins =
1800                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1801                         };
1802                         spi1_cs0: spi1-cs0 {
1803                                 rockchip,pins =
1804                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1805                         };
1806                         spi1_rx: spi1-rx {
1807                                 rockchip,pins =
1808                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1809                         };
1810                         spi1_tx: spi1-tx {
1811                                 rockchip,pins =
1812                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1813                         };
1814                 };
1815
1816                 spi2 {
1817                         spi2_clk: spi2-clk {
1818                                 rockchip,pins =
1819                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1820                         };
1821                         spi2_cs0: spi2-cs0 {
1822                                 rockchip,pins =
1823                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1824                         };
1825                         spi2_rx: spi2-rx {
1826                                 rockchip,pins =
1827                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1828                         };
1829                         spi2_tx: spi2-tx {
1830                                 rockchip,pins =
1831                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1832                         };
1833                 };
1834
1835                 spi3 {
1836                         spi3_clk: spi3-clk {
1837                                 rockchip,pins =
1838                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1839                         };
1840                         spi3_cs0: spi3-cs0 {
1841                                 rockchip,pins =
1842                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1843                         };
1844                         spi3_rx: spi3-rx {
1845                                 rockchip,pins =
1846                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1847                         };
1848                         spi3_tx: spi3-tx {
1849                                 rockchip,pins =
1850                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1851                         };
1852                 };
1853
1854                 spi4 {
1855                         spi4_clk: spi4-clk {
1856                                 rockchip,pins =
1857                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1858                         };
1859                         spi4_cs0: spi4-cs0 {
1860                                 rockchip,pins =
1861                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1862                         };
1863                         spi4_rx: spi4-rx {
1864                                 rockchip,pins =
1865                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1866                         };
1867                         spi4_tx: spi4-tx {
1868                                 rockchip,pins =
1869                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1870                         };
1871                 };
1872
1873                 spi5 {
1874                         spi5_clk: spi5-clk {
1875                                 rockchip,pins =
1876                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1877                         };
1878                         spi5_cs0: spi5-cs0 {
1879                                 rockchip,pins =
1880                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1881                         };
1882                         spi5_rx: spi5-rx {
1883                                 rockchip,pins =
1884                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1885                         };
1886                         spi5_tx: spi5-tx {
1887                                 rockchip,pins =
1888                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1889                         };
1890                 };
1891
1892                 tsadc {
1893                         otp_gpio: otp-gpio {
1894                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1895                         };
1896
1897                         otp_out: otp-out {
1898                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1899                         };
1900                 };
1901
1902                 uart0 {
1903                         uart0_xfer: uart0-xfer {
1904                                 rockchip,pins =
1905                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1906                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1907                         };
1908
1909                         uart0_cts: uart0-cts {
1910                                 rockchip,pins =
1911                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1912                         };
1913
1914                         uart0_rts: uart0-rts {
1915                                 rockchip,pins =
1916                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1917                         };
1918                 };
1919
1920                 uart1 {
1921                         uart1_xfer: uart1-xfer {
1922                                 rockchip,pins =
1923                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1924                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1925                         };
1926                 };
1927
1928                 uart2a {
1929                         uart2a_xfer: uart2a-xfer {
1930                                 rockchip,pins =
1931                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1932                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1933                         };
1934                 };
1935
1936                 uart2b {
1937                         uart2b_xfer: uart2b-xfer {
1938                                 rockchip,pins =
1939                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1940                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1941                         };
1942                 };
1943
1944                 uart2c {
1945                         uart2c_xfer: uart2c-xfer {
1946                                 rockchip,pins =
1947                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1948                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1949                         };
1950                 };
1951
1952                 uart3 {
1953                         uart3_xfer: uart3-xfer {
1954                                 rockchip,pins =
1955                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1956                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1957                         };
1958
1959                         uart3_cts: uart3-cts {
1960                                 rockchip,pins =
1961                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1962                         };
1963
1964                         uart3_rts: uart3-rts {
1965                                 rockchip,pins =
1966                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1967                         };
1968                 };
1969
1970                 uart4 {
1971                         uart4_xfer: uart4-xfer {
1972                                 rockchip,pins =
1973                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1974                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1975                         };
1976                 };
1977
1978                 uarthdcp {
1979                         uarthdcp_xfer: uarthdcp-xfer {
1980                                 rockchip,pins =
1981                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1982                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1983                         };
1984                 };
1985
1986                 pwm0 {
1987                         pwm0_pin: pwm0-pin {
1988                                 rockchip,pins =
1989                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1990                         };
1991
1992                         vop0_pwm_pin: vop0-pwm-pin {
1993                                 rockchip,pins =
1994                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1995                         };
1996                 };
1997
1998                 pwm1 {
1999                         pwm1_pin: pwm1-pin {
2000                                 rockchip,pins =
2001                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2002                         };
2003
2004                         vop1_pwm_pin: vop1-pwm-pin {
2005                                 rockchip,pins =
2006                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2007                         };
2008                 };
2009
2010                 pwm2 {
2011                         pwm2_pin: pwm2-pin {
2012                                 rockchip,pins =
2013                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2014                         };
2015                 };
2016
2017                 pwm3a {
2018                         pwm3a_pin: pwm3a-pin {
2019                                 rockchip,pins =
2020                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2021                         };
2022                 };
2023
2024                 pwm3b {
2025                         pwm3b_pin: pwm3b-pin {
2026                                 rockchip,pins =
2027                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2028                         };
2029                 };
2030
2031                 edp {
2032                         edp_hpd: edp-hpd {
2033                                 rockchip,pins =
2034                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2035                         };
2036                 };
2037
2038                 hdmi {
2039                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2040                                 rockchip,pins =
2041                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2042                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2043                         };
2044
2045                         hdmi_cec: hdmi-cec {
2046                                 rockchip,pins =
2047                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2048                         };
2049                 };
2050
2051                 pcie {
2052                         pcie_clkreqn: pci-clkreqn {
2053                                 rockchip,pins =
2054                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2055                         };
2056
2057                         pcie_clkreqnb: pci-clkreqnb {
2058                                 rockchip,pins =
2059                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2060                         };
2061                 };
2062         };
2063 };