1 /* static struct idle_state idle_states_cluster_a53[] = { */
2 /* { .power = 56 }, /\* arch_cpu_idle() (active idle) = WFI *\/ */
3 /* { .power = 56 }, /\* WFI *\/ */
4 /* { .power = 56 }, /\* cpu-sleep-0 *\/ */
7 /* static struct idle_state idle_states_cluster_a72[] = { */
8 /* { .power = 65 }, /\* arch_cpu_idle() (active idle) = WFI *\/ */
9 /* { .power = 65 }, /\* WFI *\/ */
10 /* { .power = 65 }, /\* cpu-sleep-0 *\/ */
13 /* static struct capacity_state cap_states_cluster_a53[] = { */
14 /* /\* Power per cluster *\/ */
15 /* { .cap = 121, .power = 26, }, /\* 408 MHz *\/ */
16 /* { .cap = 179, .power = 30, }, /\* 600 MHz *\/ */
17 /* { .cap = 243, .power = 39, }, /\* 816 MHz *\/ */
18 /* { .cap = 300, .power = 47, }, /\* 1008 MHz *\/ */
19 /* { .cap = 357, .power = 57, }, /\* 1200 Mhz *\/ */
20 /* { .cap = 421, .power = 67, }, /\* 1416 Mhz *\/ */
23 /* static struct capacity_state cap_states_cluster_a72[] = { */
24 /* /\* Power per cluster *\/ */
25 /* { .cap = 232, .power = 24, }, /\* 408 MHz *\/ */
26 /* { .cap = 341, .power = 32, }, /\* 600 MHz *\/ */
27 /* { .cap = 464, .power = 43, }, /\* 816 MHz *\/ */
28 /* { .cap = 573, .power = 49, }, /\* 1008 MHz *\/ */
29 /* { .cap = 683, .power = 64, }, /\* 1200 MHz *\/ */
30 /* { .cap = 805, .power = 74, }, /\* 1416 MHz *\/ */
31 /* { .cap = 915, .power = 84, }, /\* 1608 MHz *\/ */
32 /* { .cap = 1024, .power = 94, }, /\* 1800 MHz *\/ */
35 /* static struct sched_group_energy energy_cluster_a53 = { */
36 /* .nr_idle_states = ARRAY_SIZE(idle_states_cluster_a53), */
37 /* .idle_states = idle_states_cluster_a53, */
38 /* .nr_cap_states = ARRAY_SIZE(cap_states_cluster_a53), */
39 /* .cap_states = cap_states_cluster_a53, */
42 /* static struct sched_group_energy energy_cluster_a57 = { */
43 /* .nr_idle_states = ARRAY_SIZE(idle_states_cluster_a72), */
44 /* .idle_states = idle_states_cluster_a72, */
45 /* .nr_cap_states = ARRAY_SIZE(cap_states_cluster_a72), */
46 /* .cap_states = cap_states_cluster_a72, */
49 /* static struct idle_state idle_states_core_a53[] = { */
50 /* { .power = 6 }, /\* arch_cpu_idle() (active idle) = WFI *\/ */
51 /* { .power = 6 }, /\* WFI *\/ */
52 /* { .power = 0 }, /\* cpu-sleep-0 *\/ */
55 /* static struct idle_state idle_states_core_a72[] = { */
56 /* { .power = 15 }, /\* arch_cpu_idle() (active idle) = WFI *\/ */
57 /* { .power = 15 }, /\* WFI *\/ */
58 /* { .power = 0 }, /\* cpu-sleep-0 *\/ */
61 /* static struct capacity_state cap_states_core_a53[] = { */
62 /* /\* Power per cpu *\/ */
63 /* { .cap = 121, .power = 40, }, /\* 408 MHz *\/ */
64 /* { .cap = 179, .power = 62, }, /\* 600 MHz *\/ */
65 /* { .cap = 243, .power = 90, }, /\* 816 MHz *\/ */
66 /* { .cap = 300, .power = 126, }, /\* 1008 MHz *\/ */
67 /* { .cap = 357, .power = 196, }, /\* 1200 Mhz *\/ */
68 /* { .cap = 421, .power = 246, }, /\* 1416 Mhz *\/ */
71 /* static struct capacity_state cap_states_core_a72[] = { */
72 /* /\* Power per cpu *\/ */
73 /* { .cap = 232, .power = 349, }, /\* 408 MHz *\/ */
74 /* { .cap = 341, .power = 547, }, /\* 600 MHz *\/ */
75 /* { .cap = 464, .power = 794, }, /\* 816 MHz *\/ */
76 /* { .cap = 573, .power = 1141, }, /\* 1008 MHz *\/ */
77 /* { .cap = 683, .power = 1850, }, /\* 1200 MHz *\/ */
78 /* { .cap = 805, .power = 2499, }, /\* 1416 MHz *\/ */
79 /* { .cap = 915, .power = 2922, }, /\* 1608 MHz *\/ */
80 /* { .cap = 1024, .power = 3416, }, /\* 1800 MHz *\/ */
84 CPU_COST_A72: core-cost0 {
89 573 1141 /* 1008MHz */
90 683 1850 /* 1200MHz */
91 // 805 2499 /* 1416MHz */
92 // 915 2922 /* 1608MHz */
93 // 1024 3416 /* 1800MHz */
101 CPU_COST_A53: core-cost1 {
109 // 449 263 /* 1512M */
117 CLUSTER_COST_A72: cluster-cost0 {
122 573 1141 /* 1008MHz */
123 683 1850 /* 1200MHz */
124 // 805 2499 /* 1416MHz */
125 // 915 2922 /* 1608MHz */
126 // 1024 3416 /* 1800MHz */
134 CLUSTER_COST_A53: cluster-cost1 {
142 // 449 263 /* 1512M */