arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "dt-bindings/pwm/pwm.h"
  44 #include "rk3399.dtsi"
  45
  46 / {
  47         compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
  48
  49         backlight: backlight {
  50                 status = "disabled";
  51                 compatible = "pwm-backlight";
  52                 pwms = <&pwm0 0 25000 0>;
  53                 brightness-levels = <
  54                           0   1   2   3   4   5   6   7
  55                           8   9  10  11  12  13  14  15
  56                          16  17  18  19  20  21  22  23
  57                          24  25  26  27  28  29  30  31
  58                          32  33  34  35  36  37  38  39
  59                          40  41  42  43  44  45  46  47
  60                          48  49  50  51  52  53  54  55
  61                          56  57  58  59  60  61  62  63
  62                          64  65  66  67  68  69  70  71
  63                          72  73  74  75  76  77  78  79
  64                          80  81  82  83  84  85  86  87
  65                          88  89  90  91  92  93  94  95
  66                          96  97  98  99 100 101 102 103
  67                         104 105 106 107 108 109 110 111
  68                         112 113 114 115 116 117 118 119
  69                         120 121 122 123 124 125 126 127
  70                         128 129 130 131 132 133 134 135
  71                         136 137 138 139 140 141 142 143
  72                         144 145 146 147 148 149 150 151
  73                         152 153 154 155 156 157 158 159
  74                         160 161 162 163 164 165 166 167
  75                         168 169 170 171 172 173 174 175
  76                         176 177 178 179 180 181 182 183
  77                         184 185 186 187 188 189 190 191
  78                         192 193 194 195 196 197 198 199
  79                         200 201 202 203 204 205 206 207
  80                         208 209 210 211 212 213 214 215
  81                         216 217 218 219 220 221 222 223
  82                         224 225 226 227 228 229 230 231
  83                         232 233 234 235 236 237 238 239
  84                         240 241 242 243 244 245 246 247
  85                         248 249 250 251 252 253 254 255>;
  86                 default-brightness-level = <200>;
  87         };
  88
  89         clkin_gmac: external-gmac-clock {
  90                 compatible = "fixed-clock";
  91                 clock-frequency = <125000000>;
  92                 clock-output-names = "clkin_gmac";
  93                 #clock-cells = <0>;
  94         };
  95
  96         dw_hdmi_audio: dw-hdmi-audio {
  97                 status = "disabled";
  98                 compatible = "rockchip,dw-hdmi-audio";
  99                 #sound-dai-cells = <0>;
 100         };
 101
 102         hdmi_sound: hdmi-sound {
 103                 status = "disabled";
 104                 compatible = "simple-audio-card";
 105                 simple-audio-card,format = "i2s";
 106                 simple-audio-card,mclk-fs = <256>;
 107                 simple-audio-card,name = "rockchip,hdmi";
 108
 109                 simple-audio-card,cpu {
 110                         sound-dai = <&i2s2>;
 111                 };
 112                 simple-audio-card,codec {
 113                         sound-dai = <&dw_hdmi_audio>;
 114                 };
 115         };
 116
 117         io-domains {
 118                 compatible = "rockchip,rk3399-io-voltage-domain";
 119                 rockchip,grf = <&grf>;
 120
 121                 bt656-supply = <&vcc_3v0>;              /* bt656_gpio2ab_ms */
 122                 audio-supply = <&vcca1v8_codec>;        /* audio_gpio3d4a_ms */
 123                 sdmmc-supply = <&vcc_sd>;               /* sdmmc_gpio4b_ms */
 124                 gpio1830-supply = <&vcc_3v0>;           /* gpio1833_gpio4cd_ms */
 125         };
 126
 127         pmu-io-domains {
 128                 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 129                 rockchip,grf = <&pmugrf>;
 130                 pmu1830-supply = <&vcc_3v0>;
 131         };
 132
 133         sdio_pwrseq: sdio-pwrseq {
 134                 compatible = "mmc-pwrseq-simple";
 135                 clocks = <&rk808 1>;
 136                 clock-names = "ext_clock";
 137                 pinctrl-names = "default";
 138                 pinctrl-0 = <&wifi_enable_h>;
 139
 140                 /*
 141                  * On the module itself this is one of these (depending
 142                  * on the actual card populated):
 143                  * - SDIO_RESET_L_WL_REG_ON
 144                  * - PDN (power down when low)
 145                  */
 146                 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
 147         };
 148
 149         vcc3v3_sys: vcc3v3-sys {
 150                 compatible = "regulator-fixed";
 151                 regulator-name = "vcc3v3_sys";
 152                 regulator-always-on;
 153                 regulator-boot-on;
 154                 regulator-min-microvolt = <3300000>;
 155                 regulator-max-microvolt = <3300000>;
 156         };
 157
 158         vcc5v0_host: vcc5v0-host-regulator {
 159                 compatible = "regulator-fixed";
 160                 enable-active-high;
 161                 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 162                 pinctrl-names = "default";
 163                 pinctrl-0 = <&host_vbus_drv>;
 164                 regulator-name = "vcc5v0_host";
 165         };
 166
 167         vcc5v0_sys: vcc5v0-sys {
 168                 compatible = "regulator-fixed";
 169                 regulator-name = "vcc5v0_sys";
 170                 regulator-always-on;
 171                 regulator-boot-on;
 172                 regulator-min-microvolt = <5000000>;
 173                 regulator-max-microvolt = <5000000>;
 174         };
 175
 176         vcc_phy: vcc-phy-regulator {
 177                 compatible = "regulator-fixed";
 178                 regulator-name = "vcc_phy";
 179                 regulator-always-on;
 180                 regulator-boot-on;
 181         };
 182
 183         vdd_log: vdd-log {
 184                 compatible = "pwm-regulator";
 185                 pwms = <&pwm2 0 25000 0>;
 186                 regulator-name = "vdd_log";
 187                 regulator-min-microvolt = <800000>;
 188                 regulator-max-microvolt = <1400000>;
 189                 regulator-always-on;
 190                 regulator-boot-on;
 191
 192                 /* for rockchip boot on */
 193                 rockchip,pwm_id= <2>;
 194                 rockchip,pwm_voltage = <1000000>;
 195         };
 196 };
 197
 198 &cpu_l0 {
 199         cpu-supply = <&vdd_cpu_l>;
 200 };
 201
 202 &cpu_l1 {
 203         cpu-supply = <&vdd_cpu_l>;
 204 };
 205
 206 &cpu_l2 {
 207         cpu-supply = <&vdd_cpu_l>;
 208 };
 209
 210 &cpu_l3 {
 211         cpu-supply = <&vdd_cpu_l>;
 212 };
 213
 214 &cpu_b0 {
 215         cpu-supply = <&vdd_cpu_b>;
 216 };
 217
 218 &cpu_b1 {
 219         cpu-supply = <&vdd_cpu_b>;
 220 };
 221
 222 &emmc_phy {
 223         freq-sel = <200000000>;
 224         dr-sel = <50>;
 225         opdelay = <4>;
 226         status = "okay";
 227 };
 228
 229 &gmac {
 230         phy-supply = <&vcc_phy>;
 231         phy-mode = "rgmii";
 232         clock_in_out = "input";
 233         snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
 234         snps,reset-active-low;
 235         snps,reset-delays-us = <0 10000 50000>;
 236         assigned-clocks = <&cru SCLK_RMII_SRC>;
 237         assigned-clock-parents = <&clkin_gmac>;
 238         pinctrl-names = "default";
 239         pinctrl-0 = <&rgmii_pins>;
 240         tx_delay = <0x28>;
 241         rx_delay = <0x11>;
 242         status = "okay";
 243 };
 244
 245 &gpu {
 246         status = "okay";
 247         mali-supply = <&vdd_gpu>;
 248 };
 249
 250 &i2c0 {
 251         status = "okay";
 252         i2c-scl-rising-time-ns = <168>;
 253         i2c-scl-falling-time-ns = <4>;
 254         clock-frequency = <400000>;
 255
 256         vdd_cpu_b: syr827@40 {
 257                 compatible = "silergy,syr827";
 258                 reg = <0x40>;
 259                 vin-supply = <&vcc5v0_sys>;
 260                 regulator-compatible = "fan53555-reg";
 261                 regulator-name = "vdd_cpu_b";
 262                 regulator-min-microvolt = <712500>;
 263                 regulator-max-microvolt = <1500000>;
 264                 regulator-ramp-delay = <1000>;
 265                 fcs,suspend-voltage-selector = <1>;
 266                 regulator-always-on;
 267                 regulator-boot-on;
 268                 regulator-initial-state = <3>;
 269                         regulator-state-mem {
 270                         regulator-off-in-suspend;
 271                 };
 272         };
 273
 274         vdd_gpu: syr828@41 {
 275                 compatible = "silergy,syr828";
 276                 reg = <0x41>;
 277                 vin-supply = <&vcc5v0_sys>;
 278                 regulator-compatible = "fan53555-reg";
 279                 regulator-name = "vdd_gpu";
 280                 regulator-min-microvolt = <712500>;
 281                 regulator-max-microvolt = <1500000>;
 282                 regulator-ramp-delay = <1000>;
 283                 fcs,suspend-voltage-selector = <1>;
 284                 regulator-always-on;
 285                 regulator-boot-on;
 286                 regulator-initial-state = <3>;
 287                         regulator-state-mem {
 288                         regulator-off-in-suspend;
 289                 };
 290         };
 291
 292         rk808: pmic@1b {
 293                 compatible = "rockchip,rk808";
 294                 reg = <0x1b>;
 295                 interrupt-parent = <&gpio1>;
 296                 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
 297                 pinctrl-names = "default";
 298                 pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
 299                 rockchip,system-power-controller;
 300                 wakeup-source;
 301                 #clock-cells = <1>;
 302                 clock-output-names = "xin32k", "rk808-clkout2";
 303
 304                 vcc1-supply = <&vcc3v3_sys>;
 305                 vcc2-supply = <&vcc3v3_sys>;
 306                 vcc3-supply = <&vcc3v3_sys>;
 307                 vcc4-supply = <&vcc3v3_sys>;
 308                 vcc6-supply = <&vcc3v3_sys>;
 309                 vcc7-supply = <&vcc3v3_sys>;
 310                 vcc8-supply = <&vcc3v3_sys>;
 311                 vcc9-supply = <&vcc3v3_sys>;
 312                 vcc10-supply = <&vcc3v3_sys>;
 313                 vcc11-supply = <&vcc3v3_sys>;
 314                 vcc12-supply = <&vcc3v3_sys>;
 315                 vddio-supply = <&vcc1v8_pmu>;
 316
 317                 regulators {
 318                         vdd_center: DCDC_REG1 {
 319                                 regulator-always-on;
 320                                 regulator-boot-on;
 321                                 regulator-min-microvolt = <750000>;
 322                                 regulator-max-microvolt = <1350000>;
 323                                 regulator-name = "vdd_center";
 324                                 regulator-state-mem {
 325                                         regulator-off-in-suspend;
 326                                 };
 327                         };
 328
 329                         vdd_cpu_l: DCDC_REG2 {
 330                                 regulator-always-on;
 331                                 regulator-boot-on;
 332                                 regulator-min-microvolt = <750000>;
 333                                 regulator-max-microvolt = <1350000>;
 334                                 regulator-name = "vdd_cpu_l";
 335                                 regulator-state-mem {
 336                                         regulator-off-in-suspend;
 337                                 };
 338                         };
 339
 340                         vcc_ddr: DCDC_REG3 {
 341                                 regulator-always-on;
 342                                 regulator-boot-on;
 343                                 regulator-name = "vcc_ddr";
 344                                 regulator-state-mem {
 345                                         regulator-on-in-suspend;
 346                                 };
 347                         };
 348
 349                         vcc_1v8: DCDC_REG4 {
 350                                 regulator-always-on;
 351                                 regulator-boot-on;
 352                                 regulator-min-microvolt = <1800000>;
 353                                 regulator-max-microvolt = <1800000>;
 354                                 regulator-name = "vcc_1v8";
 355                                 regulator-state-mem {
 356                                         regulator-on-in-suspend;
 357                                         regulator-suspend-microvolt = <1800000>;
 358                                 };
 359                         };
 360
 361                         vcc1v8_dvp: LDO_REG1 {
 362                                 regulator-always-on;
 363                                 regulator-boot-on;
 364                                 regulator-min-microvolt = <1800000>;
 365                                 regulator-max-microvolt = <1800000>;
 366                                 regulator-name = "vcc1v8_dvp";
 367                                 regulator-state-mem {
 368                                         regulator-off-in-suspend;
 369                                 };
 370                         };
 371
 372                         vcc3v0_tp: LDO_REG2 {
 373                                 regulator-always-on;
 374                                 regulator-boot-on;
 375                                 regulator-min-microvolt = <3000000>;
 376                                 regulator-max-microvolt = <3000000>;
 377                                 regulator-name = "vcc3v0_tp";
 378                                 regulator-state-mem {
 379                                         regulator-off-in-suspend;
 380                                 };
 381                         };
 382
 383                         vcc1v8_pmu: LDO_REG3 {
 384                                 regulator-always-on;
 385                                 regulator-boot-on;
 386                                 regulator-min-microvolt = <1800000>;
 387                                 regulator-max-microvolt = <1800000>;
 388                                 regulator-name = "vcc1v8_pmu";
 389                                 regulator-state-mem {
 390                                         regulator-on-in-suspend;
 391                                         regulator-suspend-microvolt = <1800000>;
 392                                 };
 393                         };
 394
 395                         vcc_sd: LDO_REG4 {
 396                                 regulator-always-on;
 397                                 regulator-boot-on;
 398                                 regulator-min-microvolt = <1800000>;
 399                                 regulator-max-microvolt = <3300000>;
 400                                 regulator-name = "vcc_sd";
 401                                 regulator-state-mem {
 402                                         regulator-on-in-suspend;
 403                                         regulator-suspend-microvolt = <3300000>;
 404                                 };
 405                         };
 406
 407                         vcca3v0_codec: LDO_REG5 {
 408                                 regulator-always-on;
 409                                 regulator-boot-on;
 410                                 regulator-min-microvolt = <3000000>;
 411                                 regulator-max-microvolt = <3000000>;
 412                                 regulator-name = "vcca3v0_codec";
 413                                 regulator-state-mem {
 414                                         regulator-off-in-suspend;
 415                                 };
 416                         };
 417
 418                         vcc_1v5: LDO_REG6 {
 419                                 regulator-always-on;
 420                                 regulator-boot-on;
 421                                 regulator-min-microvolt = <1500000>;
 422                                 regulator-max-microvolt = <1500000>;
 423                                 regulator-name = "vcc_1v5";
 424                                 regulator-state-mem {
 425                                         regulator-on-in-suspend;
 426                                         regulator-suspend-microvolt = <1500000>;
 427                                 };
 428                         };
 429
 430                         vcca1v8_codec: LDO_REG7 {
 431                                 regulator-always-on;
 432                                 regulator-boot-on;
 433                                 regulator-min-microvolt = <1800000>;
 434                                 regulator-max-microvolt = <1800000>;
 435                                 regulator-name = "vcca1v8_codec";
 436                                 regulator-state-mem {
 437                                         regulator-off-in-suspend;
 438                                 };
 439                         };
 440
 441                         vcc_3v0: LDO_REG8 {
 442                                 regulator-always-on;
 443                                 regulator-boot-on;
 444                                 regulator-min-microvolt = <3000000>;
 445                                 regulator-max-microvolt = <3000000>;
 446                                 regulator-name = "vcc_3v0";
 447                                 regulator-state-mem {
 448                                         regulator-on-in-suspend;
 449                                         regulator-suspend-microvolt = <3000000>;
 450                                 };
 451                         };
 452
 453                         vcc3v3_s3: SWITCH_REG1 {
 454                                 regulator-always-on;
 455                                 regulator-boot-on;
 456                                 regulator-name = "vcc3v3_s3";
 457                                 regulator-state-mem {
 458                                         regulator-off-in-suspend;
 459                                 };
 460                         };
 461
 462                         vcc3v3_s0: SWITCH_REG2 {
 463                                 regulator-always-on;
 464                                 regulator-boot-on;
 465                                 regulator-name = "vcc3v3_s0";
 466                                 regulator-state-mem {
 467                                         regulator-off-in-suspend;
 468                                 };
 469                         };
 470                 };
 471         };
 472 };
 473
 474 &i2c4 {
 475         status = "okay";
 476         i2c-scl-rising-time-ns = <475>;
 477         i2c-scl-falling-time-ns = <26>;
 478
 479         fusb0: fusb30x@22 {
 480                 compatible = "fairchild,fusb302";
 481                 reg = <0x22>;
 482                 pinctrl-names = "default";
 483                 pinctrl-0 = <&fusb0_int>;
 484                 int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 485                 status = "okay";
 486         };
 487 };
 488
 489 &i2s0 {
 490         status = "okay";
 491         rockchip,i2s-broken-burst-len;
 492         rockchip,playback-channels = <8>;
 493         rockchip,capture-channels = <8>;
 494         #sound-dai-cells = <0>;
 495 };
 496
 497 &i2s2 {
 498         #sound-dai-cells = <0>;
 499         status = "okay";
 500 };
 501
 502 &pcie0 {
 503         assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
 504         assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
 505         assigned-clock-rates = <100000000>;
 506         ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 507         num-lanes = <4>;
 508         pinctrl-names = "default";
 509         pinctrl-0 = <&pcie_clkreqn>;
 510         status = "okay";
 511 };
 512
 513 &pwm0 {
 514         status = "okay";
 515 };
 516
 517 &pwm2 {
 518         status = "okay";
 519 };
 520
 521 &sdhci {
 522         bus-width = <8>;
 523         mmc-hs400-1_8v;
 524         supports-emmc;
 525         non-removable;
 526         keep-power-in-suspend;
 527         mmc-hs400-enhanced-strobe;
 528         status = "okay";
 529 };
 530
 531 &sdio0 {
 532         clock-frequency = <50000000>;
 533         clock-freq-min-max = <200000 50000000>;
 534         supports-sdio;
 535         bus-width = <4>;
 536         disable-wp;
 537         cap-sd-highspeed;
 538         cap-sdio-irq;
 539         keep-power-in-suspend;
 540         mmc-pwrseq = <&sdio_pwrseq>;
 541         non-removable;
 542         num-slots = <1>;
 543         pinctrl-names = "default";
 544         pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
 545         sd-uhs-sdr104;
 546         status = "okay";
 547 };
 548
 549 &sdmmc {
 550         clock-frequency = <150000000>;
 551         clock-freq-min-max = <100000 150000000>;
 552         supports-sd;
 553         bus-width = <4>;
 554         cap-mmc-highspeed;
 555         cap-sd-highspeed;
 556         disable-wp;
 557         num-slots = <1>;
 558         //sd-uhs-sdr104;
 559         vqmmc-supply = <&vcc_sd>;
 560         pinctrl-names = "default";
 561         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
 562         status = "okay";
 563 };
 564
 565 &saradc {
 566         status = "okay";
 567 };
 568
 569 &tcphy0 {
 570         extcon = <&fusb0>;
 571         status = "okay";
 572 };
 573
 574 &tcphy1 {
 575         status = "okay";
 576 };
 577
 578 &tsadc {
 579         /* tshut mode 0:CRU 1:GPIO */
 580         rockchip,hw-tshut-mode = <1>;
 581         /* tshut polarity 0:LOW 1:HIGH */
 582         rockchip,hw-tshut-polarity = <1>;
 583         status = "okay";
 584 };
 585
 586 &u2phy0 {
 587         status = "okay";
 588         extcon = <&fusb0>;
 589
 590         u2phy0_otg: otg-port {
 591                 status = "okay";
 592         };
 593
 594         u2phy0_host: host-port {
 595                 phy-supply = <&vcc5v0_host>;
 596                 status = "okay";
 597         };
 598 };
 599
 600 &u2phy1 {
 601         status = "okay";
 602
 603         u2phy1_otg: otg-port {
 604                 status = "okay";
 605         };
 606
 607         u2phy1_host: host-port {
 608                 phy-supply = <&vcc5v0_host>;
 609                 status = "okay";
 610         };
 611 };
 612
 613 &uart2 {
 614         status = "okay";
 615 };
 616
 617 &usbdrd3_0 {
 618         status = "okay";
 619         extcon = <&fusb0>;
 620 };
 621
 622 &usbdrd3_1 {
 623         status = "okay";
 624 };
 625
 626 &usbdrd_dwc3_0 {
 627         status = "okay";
 628 };
 629
 630 &usbdrd_dwc3_1 {
 631         status = "okay";
 632         dr_mode = "host";
 633 };
 634
 635 &usb_host0_ehci {
 636         status = "okay";
 637 };
 638
 639 &usb_host0_ohci {
 640         status = "okay";
 641 };
 642
 643 &usb_host1_ehci {
 644         status = "okay";
 645 };
 646
 647 &usb_host1_ohci {
 648         status = "okay";
 649 };
 650
 651 &cluster0_opp {
 652         opp@408000000 {
 653                 opp-hz = /bits/ 64 <408000000>;
 654                 opp-microvolt = <800000>;
 655                 clock-latency-ns = <40000>;
 656         };
 657         opp@600000000 {
 658                 opp-hz = /bits/ 64 <600000000>;
 659                 opp-microvolt = <800000>;
 660         };
 661         opp@816000000 {
 662                 opp-hz = /bits/ 64 <816000000>;
 663                 opp-microvolt = <800000>;
 664         };
 665         opp@1008000000 {
 666                 opp-hz = /bits/ 64 <1008000000>;
 667                 opp-microvolt = <875000>;
 668         };
 669         opp@1200000000 {
 670                 opp-hz = /bits/ 64 <1200000000>;
 671                 opp-microvolt = <925000>;
 672         };
 673         opp@1416000000 {
 674                 opp-hz = /bits/ 64 <1416000000>;
 675                 opp-microvolt = <1050000>;
 676         };
 677         opp@1512000000 {
 678                 opp-hz = /bits/ 64 <1512000000>;
 679                 opp-microvolt = <1075000>;
 680         };
 681 };
 682
 683 &cluster1_opp {
 684         opp@408000000 {
 685                 opp-hz = /bits/ 64 <408000000>;
 686                 opp-microvolt = <800000>;
 687                 clock-latency-ns = <40000>;
 688         };
 689         opp@600000000 {
 690                 opp-hz = /bits/ 64 <600000000>;
 691                 opp-microvolt = <800000>;
 692         };
 693         opp@816000000 {
 694                 opp-hz = /bits/ 64 <816000000>;
 695                 opp-microvolt = <825000>;
 696         };
 697         opp@1008000000 {
 698                 opp-hz = /bits/ 64 <1008000000>;
 699                 opp-microvolt = <875000>;
 700         };
 701         opp@1200000000 {
 702                 opp-hz = /bits/ 64 <1200000000>;
 703                 opp-microvolt = <950000>;
 704         };
 705         opp@1416000000 {
 706                 opp-hz = /bits/ 64 <1416000000>;
 707                 opp-microvolt = <1025000>;
 708         };
 709         opp@1608000000 {
 710                 opp-hz = /bits/ 64 <1608000000>;
 711                 opp-microvolt = <1100000>;
 712         };
 713         opp@1800000000 {
 714                 opp-hz = /bits/ 64 <1800000000>;
 715                 opp-microvolt = <1175000>;
 716         };
 717         opp@1992000000 {
 718                 opp-hz = /bits/ 64 <1992000000>;
 719                 opp-microvolt = <1250000>;
 720         };
 721 };
 722
 723 &CPU_COST_A72 {
 724         busy-cost-data = <
 725                 210   129       /*  408MHz */
 726                 308   184       /*  600MHz */
 727                 419   246       /*  816MHz */
 728                 518   335       /* 1008MHz */
 729                 617   428       /* 1200MHz */
 730                 728   573       /* 1416MHz */
 731                 827   724       /* 1608MHz */
 732                 925   900       /* 1800MHz */
 733                 1024  1108      /* 1992MHz */
 734         >;
 735         idle-cost-data = <
 736                 15
 737                 15
 738                 0
 739         >;
 740 };
 741
 742 &CPU_COST_A53 {
 743         busy-cost-data = <
 744                 108    46       /*  408M */
 745                 159    67       /*  600M */
 746                 216    90       /*  816M */
 747                 267    120      /* 1008M */
 748                 318    153      /* 1200M */
 749                 375    198      /* 1416M */
 750                 401    222      /* 1512M */
 751         >;
 752         idle-cost-data = <
 753                 6
 754                 6
 755                 0
 756         >;
 757 };
 758
 759 &CLUSTER_COST_A72 {
 760         busy-cost-data = <
 761                 210   129       /*  408MHz */
 762                 308   184       /*  600MHz */
 763                 419   246       /*  816MHz */
 764                 518   335       /* 1008MHz */
 765                 617   428       /* 1200MHz */
 766                 728   573       /* 1416MHz */
 767                 827   724       /* 1608MHz */
 768                 925   900       /* 1800MHz */
 769                 1024  1108      /* 1992MHz */
 770         >;
 771         idle-cost-data = <
 772                 65
 773                 65
 774                 65
 775         >;
 776 };
 777
 778 &CLUSTER_COST_A53 {
 779         busy-cost-data = <
 780                 108    46       /*  408M */
 781                 159    67       /*  600M */
 782                 216    90       /*  816M */
 783                 267    120      /* 1008M */
 784                 318    153      /* 1200M */
 785                 375    198      /* 1416M */
 786                 401    222      /* 1512M */
 787         >;
 788         idle-cost-data = <
 789                 56
 790                 56
 791                 56
 792         >;
 793 };
 794
 795 &gpu_opp_table {
 796         opp@200000000 {
 797                 opp-hz = /bits/ 64 <200000000>;
 798                 opp-microvolt = <800000>;
 799         };
 800         opp@300000000 {
 801                 opp-hz = /bits/ 64 <300000000>;
 802                 opp-microvolt = <800000>;
 803         };
 804         opp@400000000 {
 805                 opp-hz = /bits/ 64 <400000000>;
 806                 opp-microvolt = <800000>;
 807         };
 808         opp@500000000 {
 809                 opp-hz = /bits/ 64 <500000000>;
 810                 opp-microvolt = <900000>;
 811         };
 812         opp@600000000 {
 813                 opp-hz = /bits/ 64 <600000000>;
 814                 opp-microvolt = <900000>;
 815         };
 816         opp@800000000 {
 817                 opp-hz = /bits/ 64 <800000000>;
 818                 opp-microvolt = <1000000>;
 819         };
 820 };
 821
 822 &pinctrl {
 823         pmic {
 824                 pmic_int_l: pmic-int-l {
 825                         rockchip,pins =
 826                                 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
 827                 };
 828
 829                 pmic_dvs2: pmic-dvs2 {
 830                         rockchip,pins =
 831                                 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
 832                 };
 833         };
 834
 835         usb2 {
 836                 host_vbus_drv: host-vbus-drv {
 837                         rockchip,pins =
 838                                 <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
 839                 };
 840         };
 841
 842         fusb30x {
 843                 fusb0_int: fusb0-int {
 844                         rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
 845                 };
 846         };
 847 };