2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "dt-bindings/pwm/pwm.h"
44 #include "rk3399.dtsi"
45 #include "rk3399-opp.dtsi"
48 compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
50 backlight: backlight {
52 compatible = "pwm-backlight";
53 pwms = <&pwm0 0 25000 0>;
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85 240 241 242 243 244 245 246 247
86 248 249 250 251 252 253 254 255>;
87 default-brightness-level = <200>;
90 clkin_gmac: external-gmac-clock {
91 compatible = "fixed-clock";
92 clock-frequency = <125000000>;
93 clock-output-names = "clkin_gmac";
97 dw_hdmi_audio: dw-hdmi-audio {
99 compatible = "rockchip,dw-hdmi-audio";
100 #sound-dai-cells = <0>;
103 hdmi_sound: hdmi-sound {
105 compatible = "simple-audio-card";
106 simple-audio-card,format = "i2s";
107 simple-audio-card,mclk-fs = <256>;
108 simple-audio-card,name = "rockchip,hdmi";
110 simple-audio-card,cpu {
113 simple-audio-card,codec {
114 sound-dai = <&dw_hdmi_audio>;
119 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
120 rockchip,grf = <&pmugrf>;
121 pmu1830-supply = <&vcc_3v0>;
124 sdio_pwrseq: sdio-pwrseq {
125 compatible = "mmc-pwrseq-simple";
127 clock-names = "ext_clock";
128 pinctrl-names = "default";
129 pinctrl-0 = <&wifi_enable_h>;
132 * On the module itself this is one of these (depending
133 * on the actual card populated):
134 * - SDIO_RESET_L_WL_REG_ON
135 * - PDN (power down when low)
137 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
140 vcc3v3_sys: vcc3v3-sys {
141 compatible = "regulator-fixed";
142 regulator-name = "vcc3v3_sys";
145 regulator-min-microvolt = <3300000>;
146 regulator-max-microvolt = <3300000>;
149 vcc5v0_host: vcc5v0-host-regulator {
150 compatible = "regulator-fixed";
152 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&host_vbus_drv>;
155 regulator-name = "vcc5v0_host";
158 vcc5v0_sys: vcc5v0-sys {
159 compatible = "regulator-fixed";
160 regulator-name = "vcc5v0_sys";
163 regulator-min-microvolt = <5000000>;
164 regulator-max-microvolt = <5000000>;
167 vcc_phy: vcc-phy-regulator {
168 compatible = "regulator-fixed";
169 regulator-name = "vcc_phy";
175 compatible = "pwm-regulator";
176 pwms = <&pwm2 0 25000 0>;
177 regulator-name = "vdd_log";
178 regulator-min-microvolt = <800000>;
179 regulator-max-microvolt = <1400000>;
183 /* for rockchip boot on */
184 rockchip,pwm_id= <2>;
185 rockchip,pwm_voltage = <1000000>;
190 cpu-supply = <&vdd_cpu_l>;
194 cpu-supply = <&vdd_cpu_l>;
198 cpu-supply = <&vdd_cpu_l>;
202 cpu-supply = <&vdd_cpu_l>;
206 cpu-supply = <&vdd_cpu_b>;
210 cpu-supply = <&vdd_cpu_b>;
214 freq-sel = <200000000>;
221 phy-supply = <&vcc_phy>;
223 clock_in_out = "input";
224 snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
225 snps,reset-active-low;
226 snps,reset-delays-us = <0 10000 50000>;
227 assigned-clocks = <&cru SCLK_RMII_SRC>;
228 assigned-clock-parents = <&clkin_gmac>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&rgmii_pins>;
238 mali-supply = <&vdd_gpu>;
243 i2c-scl-rising-time-ns = <168>;
244 i2c-scl-falling-time-ns = <4>;
245 clock-frequency = <400000>;
247 vdd_cpu_b: syr827@40 {
248 compatible = "silergy,syr827";
250 vin-supply = <&vcc5v0_sys>;
251 regulator-compatible = "fan53555-reg";
252 regulator-name = "vdd_cpu_b";
253 regulator-min-microvolt = <712500>;
254 regulator-max-microvolt = <1500000>;
255 regulator-ramp-delay = <1000>;
256 fcs,suspend-voltage-selector = <1>;
259 regulator-initial-state = <3>;
260 regulator-state-mem {
261 regulator-off-in-suspend;
266 compatible = "silergy,syr828";
268 vin-supply = <&vcc5v0_sys>;
269 regulator-compatible = "fan53555-reg";
270 regulator-name = "vdd_gpu";
271 regulator-min-microvolt = <712500>;
272 regulator-max-microvolt = <1500000>;
273 regulator-ramp-delay = <1000>;
274 fcs,suspend-voltage-selector = <1>;
277 regulator-initial-state = <3>;
278 regulator-state-mem {
279 regulator-off-in-suspend;
284 compatible = "rockchip,rk808";
286 interrupt-parent = <&gpio1>;
287 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
290 rockchip,system-power-controller;
293 clock-output-names = "xin32k", "rk808-clkout2";
295 vcc1-supply = <&vcc3v3_sys>;
296 vcc2-supply = <&vcc3v3_sys>;
297 vcc3-supply = <&vcc3v3_sys>;
298 vcc4-supply = <&vcc3v3_sys>;
299 vcc6-supply = <&vcc3v3_sys>;
300 vcc7-supply = <&vcc3v3_sys>;
301 vcc8-supply = <&vcc3v3_sys>;
302 vcc9-supply = <&vcc3v3_sys>;
303 vcc10-supply = <&vcc3v3_sys>;
304 vcc11-supply = <&vcc3v3_sys>;
305 vcc12-supply = <&vcc3v3_sys>;
306 vddio-supply = <&vcc1v8_pmu>;
309 vdd_center: DCDC_REG1 {
312 regulator-min-microvolt = <750000>;
313 regulator-max-microvolt = <1350000>;
314 regulator-ramp-delay = <6001>;
315 regulator-name = "vdd_center";
316 regulator-state-mem {
317 regulator-off-in-suspend;
321 vdd_cpu_l: DCDC_REG2 {
324 regulator-min-microvolt = <750000>;
325 regulator-max-microvolt = <1350000>;
326 regulator-ramp-delay = <6001>;
327 regulator-name = "vdd_cpu_l";
328 regulator-state-mem {
329 regulator-off-in-suspend;
336 regulator-name = "vcc_ddr";
337 regulator-state-mem {
338 regulator-on-in-suspend;
345 regulator-min-microvolt = <1800000>;
346 regulator-max-microvolt = <1800000>;
347 regulator-name = "vcc_1v8";
348 regulator-state-mem {
349 regulator-on-in-suspend;
350 regulator-suspend-microvolt = <1800000>;
354 vcc1v8_dvp: LDO_REG1 {
357 regulator-min-microvolt = <1800000>;
358 regulator-max-microvolt = <1800000>;
359 regulator-name = "vcc1v8_dvp";
360 regulator-state-mem {
361 regulator-off-in-suspend;
365 vcc3v0_tp: LDO_REG2 {
368 regulator-min-microvolt = <3000000>;
369 regulator-max-microvolt = <3000000>;
370 regulator-name = "vcc3v0_tp";
371 regulator-state-mem {
372 regulator-off-in-suspend;
376 vcc1v8_pmu: LDO_REG3 {
379 regulator-min-microvolt = <1800000>;
380 regulator-max-microvolt = <1800000>;
381 regulator-name = "vcc1v8_pmu";
382 regulator-state-mem {
383 regulator-on-in-suspend;
384 regulator-suspend-microvolt = <1800000>;
391 regulator-min-microvolt = <1800000>;
392 regulator-max-microvolt = <3300000>;
393 regulator-name = "vcc_sd";
394 regulator-state-mem {
395 regulator-on-in-suspend;
396 regulator-suspend-microvolt = <3300000>;
400 vcca3v0_codec: LDO_REG5 {
403 regulator-min-microvolt = <3000000>;
404 regulator-max-microvolt = <3000000>;
405 regulator-name = "vcca3v0_codec";
406 regulator-state-mem {
407 regulator-off-in-suspend;
414 regulator-min-microvolt = <1500000>;
415 regulator-max-microvolt = <1500000>;
416 regulator-name = "vcc_1v5";
417 regulator-state-mem {
418 regulator-on-in-suspend;
419 regulator-suspend-microvolt = <1500000>;
423 vcca1v8_codec: LDO_REG7 {
426 regulator-min-microvolt = <1800000>;
427 regulator-max-microvolt = <1800000>;
428 regulator-name = "vcca1v8_codec";
429 regulator-state-mem {
430 regulator-off-in-suspend;
437 regulator-min-microvolt = <3000000>;
438 regulator-max-microvolt = <3000000>;
439 regulator-name = "vcc_3v0";
440 regulator-state-mem {
441 regulator-on-in-suspend;
442 regulator-suspend-microvolt = <3000000>;
446 vcc3v3_s3: SWITCH_REG1 {
449 regulator-name = "vcc3v3_s3";
450 regulator-state-mem {
451 regulator-off-in-suspend;
455 vcc3v3_s0: SWITCH_REG2 {
458 regulator-name = "vcc3v3_s0";
459 regulator-state-mem {
460 regulator-off-in-suspend;
469 i2c-scl-rising-time-ns = <475>;
470 i2c-scl-falling-time-ns = <26>;
473 compatible = "fairchild,fusb302";
475 pinctrl-names = "default";
476 pinctrl-0 = <&fusb0_int>;
477 int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
484 rockchip,i2s-broken-burst-len;
485 rockchip,playback-channels = <8>;
486 rockchip,capture-channels = <8>;
487 #sound-dai-cells = <0>;
491 #sound-dai-cells = <0>;
498 bt656-supply = <&vcc_3v0>; /* bt656_gpio2ab_ms */
499 audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */
500 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
501 gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
505 assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
506 assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
507 assigned-clock-rates = <100000000>;
508 ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&pcie_clkreqn>;
528 keep-power-in-suspend;
529 mmc-hs400-enhanced-strobe;
534 clock-frequency = <50000000>;
535 clock-freq-min-max = <200000 50000000>;
541 keep-power-in-suspend;
542 mmc-pwrseq = <&sdio_pwrseq>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
552 clock-frequency = <150000000>;
553 clock-freq-min-max = <100000 150000000>;
561 vqmmc-supply = <&vcc_sd>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
581 /* tshut mode 0:CRU 1:GPIO */
582 rockchip,hw-tshut-mode = <1>;
583 /* tshut polarity 0:LOW 1:HIGH */
584 rockchip,hw-tshut-polarity = <1>;
592 u2phy0_otg: otg-port {
596 u2phy0_host: host-port {
597 phy-supply = <&vcc5v0_host>;
605 u2phy1_otg: otg-port {
609 u2phy1_host: host-port {
610 phy-supply = <&vcc5v0_host>;
655 pmic_int_l: pmic-int-l {
657 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
660 pmic_dvs2: pmic-dvs2 {
662 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
667 host_vbus_drv: host-vbus-drv {
669 <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
674 fusb0_int: fusb0-int {
675 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;