arch/arm64/boot/dts/rockchip/rk3399-android.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42 #include <dt-bindings/display/rk_fb.h>
  43 #include <dt-bindings/display/mipi_dsi.h>
  44
  45 / {
  46         compatible = "rockchip,android", "rockchip,rk3399";
  47
  48         aliases {
  49                 lcdc0 = &vopb_rk_fb;
  50                 lcdc1 = &vopl_rk_fb;
  51         };
  52
  53         chosen {
  54                 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
  55         };
  56
  57         ramoops_mem: ramoops_mem {
  58                 reg = <0x0 0x100000 0x0 0x100000>;
  59                 reg-names = "ramoops_mem";
  60         };
  61
  62         ramoops {
  63                 compatible = "ramoops";
  64                 record-size = <0x0 0x20000>;
  65                 console-size = <0x0 0x80000>;
  66                 ftrace-size = <0x0 0x10000>;
  67                 pmsg-size = <0x0 0x50000>;
  68                 memory-region = <&ramoops_mem>;
  69         };
  70
  71         fiq_debugger: fiq-debugger {
  72                 compatible = "rockchip,fiq-debugger";
  73                 rockchip,serial-id = <2>;
  74                 rockchip,signal-irq = <182>;
  75                 rockchip,wake-irq = <0>;
  76                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
  77                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
  78                 pinctrl-names = "default";
  79                 pinctrl-0 = <&uart2c_xfer>;
  80         };
  81
  82         reserved-memory {
  83                 #address-cells = <2>;
  84                 #size-cells = <2>;
  85                 ranges;
  86
  87                 /* global autoconfigured region for contiguous allocations */
  88                 linux,cma {
  89                         compatible = "shared-dma-pool";
  90                         reusable;
  91                         size = <0x0 0x8000000>;
  92                         linux,cma-default;
  93                 };
  94                 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
  95                 rockchip_logo: rockchip-logo@00000000 {
  96                         compatible = "rockchip,fb-logo";
  97                         reg = <0x0 0x0 0x0 0x0>;
  98                 };
  99         };
 100
 101         ion {
 102                 compatible = "rockchip,ion";
 103                 #address-cells = <1>;
 104                 #size-cells = <0>;
 105
 106                 cma-heap {
 107                         reg = <0x00000000 0x02000000>;
 108                 };
 109
 110                 system-heap {
 111                 };
 112         };
 113
 114         rk_key: rockchip-key {
 115                 compatible = "rockchip,key";
 116                 status = "okay";
 117
 118                 io-channels = <&saradc 1>;
 119
 120                 vol-up-key {
 121                         linux,code = <115>;
 122                         label = "volume up";
 123                         rockchip,adc_value = <1>;
 124                 };
 125
 126                 vol-down-key {
 127                         linux,code = <114>;
 128                         label = "volume down";
 129                         rockchip,adc_value = <170>;
 130                 };
 131
 132                 power-key {
 133                         gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 134                         linux,code = <116>;
 135                         label = "power";
 136                         gpio-key,wakeup;
 137                 };
 138
 139                 menu-key {
 140                         linux,code = <59>;
 141                         label = "menu";
 142                         rockchip,adc_value = <746>;
 143                 };
 144
 145                 home-key {
 146                         linux,code = <102>;
 147                         label = "home";
 148                         rockchip,adc_value = <355>;
 149                 };
 150
 151                 back-key {
 152                         linux,code = <158>;
 153                         label = "back";
 154                         rockchip,adc_value = <560>;
 155                 };
 156
 157                 camera-key {
 158                         linux,code = <212>;
 159                         label = "camera";
 160                         rockchip,adc_value = <450>;
 161                 };
 162         };
 163
 164         cdn_dp_fb: dp-fb@fec00000 {
 165                 status = "disabled";
 166                 compatible = "rockchip,rk3399-cdn-dp-fb";
 167                 reg = <0x0 0xfec00000 0x0 0x100000>;
 168                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 169                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 170                          <&cru SCLK_SPDIF_REC_DPTX>;
 171                 clock-names = "core-clk", "pclk", "spdif";
 172                 assigned-clocks = <&cru SCLK_DP_CORE>;
 173                 assigned-clock-rates = <100000000>;
 174                 power-domains = <&power RK3399_PD_HDCP>;
 175                 phys = <&tcphy0 0>, <&tcphy1 0>;
 176                 resets = <&cru SRST_DPTX_SPDIF_REC>;
 177                 reset-names = "spdif";
 178                 rockchip,grf = <&grf>;
 179                 #address-cells = <1>;
 180                 #size-cells = <0>;
 181                 #sound-dai-cells = <1>;
 182         };
 183
 184         cdn_dp_sound: cdn-dp-sound {
 185                 status = "disabled";
 186                 compatible = "simple-audio-card";
 187                 simple-audio-card,name = "rockchip,cdn-dp-fb";
 188                 simple-audio-card,widgets = "Headphone", "Out Jack",
 189                                             "Line", "In Jack";
 190
 191                 simple-audio-card,dai-link@0 {
 192                         format = "i2s";
 193                         mclk-fs = <256>;
 194
 195                         cpu {
 196                                 sound-dai = <&i2s2>;
 197                         };
 198
 199                         codec {
 200                                 sound-dai = <&cdn_dp_fb 0>;
 201                         };
 202                 };
 203
 204                 simple-audio-card,dai-link@1 {
 205                         format = "spdif";
 206                         cpu {
 207                                 sound-dai = <&spdif>;
 208                         };
 209
 210                         codec {
 211                                 sound-dai = <&cdn_dp_fb 1>;
 212                         };
 213                 };
 214         };
 215
 216         vpu: vpu_service@ff650000 {
 217                 compatible = "rockchip,vpu_service";
 218                 rockchip,grf = <&grf>;
 219                 iommu_enabled = <1>;
 220                 reg = <0x0 0xff650000 0x0 0x800>;
 221                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
 222                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
 223                 interrupt-names = "irq_dec", "irq_enc";
 224                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 225                 clock-names = "aclk_vcodec", "hclk_vcodec";
 226                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
 227                 reset-names = "video_h", "video_a";
 228                 power-domains = <&power RK3399_PD_VCODEC>;
 229                 name = "vpu_service";
 230                 dev_mode = <0>;
 231         };
 232
 233         vpu_mmu: vpu_mmu {
 234                 dbgname = "vpu";
 235                 compatible = "rockchip,vpu_mmu";
 236                 reg = <0x0 0xff650800 0x0 0x40>;
 237                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
 238                 interrupt-names = "vpu_mmu";
 239         };
 240
 241         rkvdec: rkvdec@ff660000 {
 242                 compatible = "rockchip,rkvdec";
 243                 rockchip,grf = <&grf>;
 244                 iommu_enabled = <1>;
 245                 reg = <0x0 0xff660000 0x0 0x400>;
 246                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
 247                 interrupt-names = "irq_dec";
 248                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
 249                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
 250                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
 251                 reset-names = "video_h", "video_a";
 252                 power-domains = <&power RK3399_PD_VDU>;
 253                 dev_mode = <2>;
 254                 name = "rkvdec";
 255         };
 256
 257         vdec_mmu: vdec_mmu {
 258                 dbgname = "vdec";
 259                 compatible = "rockchip,vdec_mmu";
 260                 reg = <0x0 0xff660480 0x0 0x40>,
 261                       <0x0 0xff6604c0 0x0 0x40>;
 262                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
 263                 interrupt-names = "vdec_mmu";
 264         };
 265
 266         iep: iep@ff670000 {
 267                 compatible = "rockchip,iep";
 268                 iommu_enabled = <1>;
 269                 reg = <0x0 0xff670000 0x0 0x800>;
 270                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
 271                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 272                 clock-names = "aclk_iep", "hclk_iep";
 273                 power-domains = <&power RK3399_PD_IEP>;
 274                 version = <2>;
 275         };
 276
 277         iep_mmu: iep-mmu {
 278                 dbgname = "iep";
 279                 compatible = "rockchip,iep_mmu";
 280                 reg = <0x0 0xff670800 0x0 0x40>;
 281                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
 282                 interrupt-names = "iep_mmu";
 283         };
 284
 285         rga: rga@ff680000 {
 286                 compatible = "rockchip,rga2";
 287                 dev_mode = <1>;
 288                 reg = <0x0 0xff680000 0x0 0x1000>;
 289                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
 290                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
 291                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 292                 power-domains = <&power RK3399_PD_RGA>;
 293                 status = "okay";
 294         };
 295
 296         fb: fb {
 297                 status = "okay";
 298                 compatible = "rockchip,rk-fb";
 299                 rockchip,disp-mode = <DUAL>;
 300                 rockchip,uboot-logo-on = <1>;
 301                 memory-region = <&rockchip_logo>;
 302         };
 303
 304         rk_screen: screen {
 305                 status = "okay";
 306                 compatible = "rockchip,screen";
 307         };
 308
 309         vopb_rk_fb: vop-rk-fb@ff900000 {
 310                 status = "disabled";
 311                 compatible = "rockchip,rk3399-lcdc";
 312                 rockchip,prop = <PRMRY>;
 313                 reg = <0x0 0xff900000 0x0 0x3efc>;
 314                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
 315                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 316                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 317                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
 318                 reset-names = "axi", "ahb", "dclk";
 319                 rockchip,grf = <&grf>;
 320                 rockchip,pwr18 = <0>;
 321                 rockchip,iommu-enabled = <1>;
 322                 power-domains = <&power RK3399_PD_VOPB>;
 323         };
 324
 325         vopb_mmu_rk_fb: vopb-mmu {
 326                 status = "okay";
 327                 dbgname = "vop";
 328                 compatible = "rockchip,vopb_mmu";
 329                 reg = <0x0 0xff903f00 0x0 0x100>;
 330                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
 331                 interrupt-names = "vopb_mmu";
 332         };
 333
 334         vopl_rk_fb: vop-rk-fb@ff8f0000 {
 335                 status = "disabled";
 336                 compatible = "rockchip,rk3399-lcdc";
 337                 rockchip,prop = <EXTEND>;
 338                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
 339                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
 340                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 341                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 342                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
 343                 reset-names = "axi", "ahb", "dclk";
 344                 rockchip,grf = <&grf>;
 345                 rockchip,pwr18 = <0>;
 346                 rockchip,iommu-enabled = <1>;
 347                 power-domains = <&power RK3399_PD_VOPL>;
 348         };
 349
 350         vopl_mmu_rk_fb: vopl-mmu {
 351                 status = "okay";
 352                 dbgname = "vop";
 353                 compatible = "rockchip,vopl_mmu";
 354                 reg = <0x0 0xff8f3f00 0x0 0x100>;
 355                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
 356                 interrupt-names = "vopl_mmu";
 357         };
 358
 359         isp0: isp@ff910000 {
 360                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
 361                 reg = <0x0 0xff910000 0x0 0x10000>;
 362                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
 363                 clocks =
 364                         <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
 365                         <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
 366                         <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
 367                         <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
 368                         <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
 369                 clock-names =
 370                         "clk_cif_out", "clk_cif_pll",
 371                         "pclk_dphytxrx", "pclk_dphy_ref",
 372                         "aclk_isp0_noc", "aclk_isp0_wrapper",
 373                         "hclk_isp0_noc", "hclk_isp0_wrapper",
 374                         "clk_isp0", "pclk_dphyrx";
 375                 pinctrl-names =
 376                         "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
 377                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 378                         "isp_flash_as_trigger_out";
 379                 pinctrl-0 = <&cif_clkout>;
 380                 pinctrl-1 = <&isp_dvp_d0d7>;
 381                 pinctrl-2 = <&cif_clkout>;
 382                 pinctrl-3 = <&isp_prelight>;
 383                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
 384                 pinctrl-5 = <&isp_flash_trigger>;
 385                 rockchip,isp,mipiphy = <2>;
 386                 rockchip,isp,cifphy = <1>;
 387                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
 388                 rockchip,grf = <&grf>;
 389                 rockchip,cru = <&cru>;
 390                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 391                 rockchip,isp,iommu-enable = <1>;
 392                 power-domains = <&power RK3399_PD_ISP0>;
 393                 status = "disabled";
 394         };
 395
 396         isp0_mmu {
 397                 dbgname = "isp0";
 398                 compatible = "rockchip,isp0_mmu";
 399                 reg = <0x0 0xff914000 0x0  0x100>,
 400                       <0x0 0xff915000 0x0  0x100>;
 401                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
 402                 interrupt-names = "isp0_mmu";
 403         };
 404
 405         isp1: isp@ff920000 {
 406                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
 407                 reg = <0x0 0xff920000 0x0 0x10000>;
 408                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
 409                 clocks =
 410                         <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
 411                         <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
 412                         <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
 413                         <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
 414                         <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
 415                         <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
 416                         <&cru SCLK_MIPIDPHY_CFG>;
 417                 clock-names =
 418                         "aclk_isp1_noc", "aclk_isp1_wrapper",
 419                         "hclk_isp1_noc", "hclk_isp1_wrapper",
 420                         "clk_isp1", "clk_cif_out",
 421                         "clk_cif_pll", "pclk_dphytxrx",
 422                         "pclk_dphy_ref", "pclk_isp1",
 423                         "pclk_dphyrx", "pclk_mipi_dsi",
 424                         "mipi_dphy_cfg";
 425                 pinctrl-names =
 426                         "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
 427                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 428                         "isp_flash_as_trigger_out";
 429                 pinctrl-0 = <&cif_clkout>;
 430                 pinctrl-1 = <&isp_dvp_d0d7>;
 431                 pinctrl-2 = <&cif_clkout>;
 432                 pinctrl-3 = <&isp_prelight>;
 433                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
 434                 pinctrl-5 = <&isp_flash_trigger>;
 435                 rockchip,isp,mipiphy = <2>;
 436                 rockchip,isp,cifphy = <1>;
 437                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
 438                 rockchip,grf = <&grf>;
 439                 rockchip,cru = <&cru>;
 440                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 441                 rockchip,isp,iommu-enable = <1>;
 442                 power-domains = <&power RK3399_PD_ISP1>;
 443                 status = "disabled";
 444         };
 445
 446         isp1_mmu {
 447                 dbgname = "isp1";
 448                 compatible = "rockchip,isp1_mmu";
 449                 reg = <0x0 0xff924000 0x0  0x100>,
 450                       <0x0 0xff925000 0x0  0x100>;
 451                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
 452                 interrupt-names = "isp1_mmu";
 453         };
 454
 455         hdmi_rk_fb: hdmi-rk-fb@ff940000 {
 456                 status = "disabled";
 457                 compatible = "rockchip,rk3399-hdmi";
 458                 reg = <0x0 0xff940000 0x0 0x20000>;
 459                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
 460                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>;
 461                 clocks = <&cru PCLK_HDMI_CTRL>,
 462                          <&cru HCLK_HDCP>,
 463                          <&cru SCLK_HDMI_CEC>,
 464                          <&cru PLL_VPLL>,
 465                          <&cru SCLK_HDMI_SFR>;
 466                 clock-names = "pclk_hdmi",
 467                               "hdcp_clk_hdmi",
 468                               "cec_clk_hdmi",
 469                               "dclk_hdmi_phy",
 470                               "sclk_hdmi_sfr";
 471                 resets = <&cru SRST_HDMI_CTRL>;
 472                 reset-names = "hdmi";
 473                 pinctrl-names = "default", "gpio";
 474                 pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
 475                 pinctrl-1 = <&i2c3_gpio>;
 476                 rockchip,grf = <&grf>;
 477                 power-domains = <&power RK3399_PD_HDCP>;
 478         };
 479
 480         mipi0_rk_fb: mipi-rk-fb@ff960000 {
 481                 compatible = "rockchip,rk3399-dsi";
 482                 rockchip,prop = <0>;
 483                 rockchip,grf = <&grf>;
 484                 reg = <0x0 0xff960000 0x0 0x8000>;
 485                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
 486                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
 487                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
 488                 power-domains = <&power RK3399_PD_VIO>;
 489                 status = "disabled";
 490         };
 491
 492         mipi1_rk_fb: mipi-rk-fb@ff968000 {
 493                 compatible = "rockchip,rk3399-dsi";
 494                 rockchip,prop = <1>;
 495                 rockchip,grf = <&grf>;
 496                 reg = <0x0 0xff968000 0x0 0x8000>;
 497                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
 498                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
 499                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
 500                 power-domains = <&power RK3399_PD_VIO>;
 501                 status = "disabled";
 502         };
 503
 504         edp_rk_fb: edp-rk-fb@ff970000 {
 505                 compatible = "rockchip,rk3399-edp-fb";
 506                 reg = <0x0 0xff970000 0x0 0x8000>;
 507                 rockchip,grf = <&grf>;
 508                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
 509                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
 510                 clock-names = "clk_edp", "pclk_edp";
 511                 resets = <&cru SRST_P_EDP_CTRL>;
 512                 reset-names = "edp_apb";
 513                 status = "disabled";
 514         };
 515 };
 516
 517 &pinctrl {
 518         isp {
 519                 cif_clkout: cif-clkout {
 520                         rockchip,pins =
 521                         /*cif_clkout*/
 522                         <2 11 RK_FUNC_3 &pcfg_pull_none>;
 523                 };
 524
 525                 isp_dvp_d0d7: isp-dvp-d0d7 {
 526                         rockchip,pins =
 527                         /*cif_data0*/
 528                         <2 0 RK_FUNC_3 &pcfg_pull_none>,
 529                         /*cif_data1*/
 530                         <2 1 RK_FUNC_3 &pcfg_pull_none>,
 531                         /*cif_data2*/
 532                         <2 2 RK_FUNC_3 &pcfg_pull_none>,
 533                         /*cif_data3*/
 534                         <2 3 RK_FUNC_3 &pcfg_pull_none>,
 535                         /*cif_data4*/
 536                         <2 4 RK_FUNC_3 &pcfg_pull_none>,
 537                         /*cif_data5*/
 538                         <2 5 RK_FUNC_3 &pcfg_pull_none>,
 539                         /*cif_data6*/
 540                         <2 6 RK_FUNC_3 &pcfg_pull_none>,
 541                         /*cif_data7*/
 542                         <2 7 RK_FUNC_3 &pcfg_pull_none>,
 543                         /*cif_sync*/
 544                         <2 8 RK_FUNC_3 &pcfg_pull_none>,
 545                         /*cif_href*/
 546                         <2 9 RK_FUNC_3 &pcfg_pull_none>,
 547                         /*cif_clkin*/
 548                         <2 10 RK_FUNC_3 &pcfg_pull_none>;
 549                 };
 550
 551                 isp_shutter: isp-shutter {
 552                         rockchip,pins =
 553                         /*SHUTTEREN*/
 554                         <1 1 RK_FUNC_1 &pcfg_pull_none>,
 555                         /*SHUTTERTRIG*/
 556                         <1 0 RK_FUNC_1 &pcfg_pull_none>;
 557                 };
 558
 559                 isp_flash_trigger: isp-flash-trigger {
 560                         /*ISP_FLASHTRIGOU*/
 561                         rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
 562                 };
 563
 564                 isp_prelight: isp-prelight {
 565                         /*ISP_PRELIGHTTRIG*/
 566                         rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
 567                 };
 568
 569                 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
 570                         /*ISP_FLASHTRIGOU*/
 571                         rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
 572                 };
 573         };
 574 };