arch/arm64/boot/dts/rockchip/rk3399-android.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42 #include <dt-bindings/display/rk_fb.h>
  43 #include <dt-bindings/display/mipi_dsi.h>
  44
  45 / {
  46         compatible = "rockchip,android", "rockchip,rk3399";
  47
  48         chosen {
  49                 bootargs = "console=uart,mmio32,0xff1a0000";
  50         };
  51
  52         ramoops_mem: ramoops_mem {
  53                 reg = <0x0 0x100000 0x0 0x100000>;
  54                 reg-names = "ramoops_mem";
  55         };
  56
  57         ramoops {
  58                 compatible = "ramoops";
  59                 record-size = <0x0 0x20000>;
  60                 console-size = <0x0 0x80000>;
  61                 ftrace-size = <0x0 0x10000>;
  62                 pmsg-size = <0x0 0x50000>;
  63                 memory-region = <&ramoops_mem>;
  64         };
  65
  66         reserved-memory {
  67                 #address-cells = <2>;
  68                 #size-cells = <2>;
  69                 ranges;
  70
  71                 /* global autoconfigured region for contiguous allocations */
  72                 linux,cma {
  73                         compatible = "shared-dma-pool";
  74                         reusable;
  75                         size = <0x0 0x8000000>;
  76                         linux,cma-default;
  77                 };
  78         };
  79
  80         ion {
  81                 compatible = "rockchip,ion";
  82                 #address-cells = <1>;
  83                 #size-cells = <0>;
  84
  85                 cma-heap {
  86                         reg = <0x00000000 0x02000000>;
  87                 };
  88
  89                 system-heap {
  90                 };
  91         };
  92
  93         rk_key: rockchip-key {
  94                 compatible = "rockchip,key";
  95                 status = "okay";
  96
  97                 io-channels = <&saradc 1>;
  98
  99                 vol-up-key {
 100                         linux,code = <115>;
 101                         label = "volume up";
 102                         rockchip,adc_value = <1>;
 103                 };
 104
 105                 vol-down-key {
 106                         linux,code = <114>;
 107                         label = "volume down";
 108                         rockchip,adc_value = <170>;
 109                 };
 110
 111                 power-key {
 112                         gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 113                         linux,code = <116>;
 114                         label = "power";
 115                         gpio-key,wakeup;
 116                 };
 117
 118                 menu-key {
 119                         linux,code = <59>;
 120                         label = "menu";
 121                         rockchip,adc_value = <746>;
 122                 };
 123
 124                 home-key {
 125                         linux,code = <102>;
 126                         label = "home";
 127                         rockchip,adc_value = <355>;
 128                 };
 129
 130                 back-key {
 131                         linux,code = <158>;
 132                         label = "back";
 133                         rockchip,adc_value = <560>;
 134                 };
 135
 136                 camera-key {
 137                         linux,code = <212>;
 138                         label = "camera";
 139                         rockchip,adc_value = <450>;
 140                 };
 141         };
 142
 143         vpu: vpu_service@ff650000 {
 144                 compatible = "rockchip,vpu_service";
 145                 rockchip,grf = <&grf>;
 146                 iommu_enabled = <1>;
 147                 reg = <0x0 0xff650000 0x0 0x800>;
 148                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 149                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 150                 interrupt-names = "irq_dec", "irq_enc";
 151                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 152                 clock-names = "aclk_vcodec", "hclk_vcodec";
 153                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
 154                 reset-names = "video_h", "video_a";
 155                 power-domains = <&power RK3399_PD_VCODEC>;
 156                 name = "vpu_service";
 157                 dev_mode = <0>;
 158         };
 159
 160         vpu_mmu: vpu_mmu {
 161                 dbgname = "vpu";
 162                 compatible = "rockchip,vpu_mmu";
 163                 reg = <0x0 0xff650800 0x0 0x40>;
 164                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 165                 interrupt-names = "vpu_mmu";
 166         };
 167
 168         rkvdec: rkvdec@ff660000 {
 169                 compatible = "rockchip,rkvdec";
 170                 rockchip,grf = <&grf>;
 171                 iommu_enabled = <1>;
 172                 reg = <0x0 0xff660000 0x0 0x400>;
 173                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 174                 interrupt-names = "irq_dec";
 175                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
 176                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
 177                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
 178                 reset-names = "video_h", "video_a";
 179                 power-domains = <&power RK3399_PD_VDU>;
 180                 dev_mode = <2>;
 181                 name = "rkvdec";
 182         };
 183
 184         vdec_mmu: vdec_mmu {
 185                 dbgname = "vdec";
 186                 compatible = "rockchip,vdec_mmu";
 187                 reg = <0x0 0xff660480 0x0 0x40>,
 188                       <0x0 0xff6604c0 0x0 0x40>;
 189                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 190                 interrupt-names = "vdec_mmu";
 191         };
 192
 193         iep: iep@ff670000 {
 194                 compatible = "rockchip,iep";
 195                 iommu_enabled = <1>;
 196                 reg = <0x0 0xff670000 0x0 0x800>;
 197                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 198                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 199                 clock-names = "aclk_iep", "hclk_iep";
 200                 version = <2>;
 201         };
 202
 203         iep_mmu: iep-mmu {
 204                 dbgname = "iep";
 205                 compatible = "rockchip,iep_mmu";
 206                 reg = <0x0 0xff670800 0x0 0x40>;
 207                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 208                 interrupt-names = "iep_mmu";
 209         };
 210
 211         rga: rga@ff680000 {
 212                 compatible = "rockchip,rga2";
 213                 dev_mode = <1>;
 214                 reg = <0x0 0xff680000 0x0 0x1000>;
 215                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 216                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
 217                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 218                 power-domains = <&power RK3399_PD_RGA>;
 219                 status = "okay";
 220         };
 221
 222         fb: fb {
 223                 compatible = "rockchip,rk-fb";
 224                 rockchip,disp-mode = <DUAL>;
 225         };
 226
 227         rk_screen: screen {
 228                 compatible = "rockchip,screen";
 229                 #include <dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi>
 230         };
 231
 232         vopb_rk_fb: vop-rk-fb@ff900000 {
 233                 compatible = "rockchip,rk3399-lcdc";
 234                 rockchip,prop = <PRMRY>;
 235                 reg = <0x0 0xff900000 0x0 0x3efc>;
 236                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 237                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 238                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 239                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
 240                 reset-names = "axi", "ahb", "dclk";
 241                 rockchip,grf = <&grf>;
 242                 rockchip,pwr18 = <0>;
 243                 rockchip,iommu-enabled = <1>;
 244                 power-domains = <&power RK3399_PD_VOPB>;
 245                 power_ctr: power_ctr {
 246                 /*rockchip,debug = <0>;
 247                 lcd_en: lcd-en {
 248                         rockchip,power_type = <GPIO>;
 249                         gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;//GPIO_C6 = 22
 250                         rockchip,delay = <10>;
 251                 };
 252                 */
 253
 254                 /*lcd_cs: lcd-cs {
 255                         rockchip,power_type = <GPIO>;
 256                         gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;//GPIO_C5 = 21
 257                         rockchip,delay = <10>;
 258                 };*/
 259
 260                 /*lcd_rst: lcd-rst {
 261                         rockchip,power_type = <GPIO>;
 262                         gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
 263                         rockchip,delay = <5>;
 264                 };*/
 265                 };
 266         };
 267
 268         vopb_mmu_rk_fb: vopb-mmu {
 269                 dbgname = "vop";
 270                 compatible = "rockchip,vopb_mmu";
 271                 reg = <0x0 0xff903f00 0x0 0x100>;
 272                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 273                 interrupt-names = "vopb_mmu";
 274         };
 275
 276         vopl_rk_fb: vop-rk-fb@ff8f0000 {
 277                 compatible = "rockchip,rk3399-lcdc";
 278                 rockchip,prop = <EXTEND>;
 279                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
 280                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 281                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 282                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 283                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
 284                 reset-names = "axi", "ahb", "dclk";
 285                 rockchip,grf = <&grf>;
 286                 rockchip,pwr18 = <0>;
 287                 rockchip,iommu-enabled = <1>;
 288                 power-domains = <&power RK3399_PD_VOPL>;
 289         };
 290
 291         vopl_mmu_rk_fb: vopl-mmu {
 292                 dbgname = "vop";
 293                 compatible = "rockchip,vopl_mmu";
 294                 reg = <0x0 0xff8f3f00 0x0 0x100>;
 295                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 296                 interrupt-names = "vopl_mmu";
 297         };
 298
 299         hdmi_rk_fb: hdmi-rk-fb@ff940000 {
 300                 compatible = "rockchip,rk3399-hdmi";
 301                 reg = <0x0 0xff940000 0x0 0x20000>;
 302                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&cru PCLK_HDMI_CTRL>,
 305                          <&cru SCLK_HDMI_SFR>,
 306                          <&cru SCLK_HDMI_CEC>,
 307                          <&cru PLL_VPLL>;
 308                 clock-names = "pclk_hdmi",
 309                               "hdcp_clk_hdmi",
 310                               "cec_clk_hdmi",
 311                               "dclk_hdmi_phy";
 312                 resets = <&cru SRST_HDMI_CTRL>;
 313                 reset-names = "hdmi";
 314                 pinctrl-names = "default", "gpio";
 315                 pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
 316                 pinctrl-1 = <&i2c3_gpio>;
 317                 rockchip,grf = <&grf>;
 318                 power-domains = <&power RK3399_PD_HDCP>;
 319         };
 320
 321         mipi0_rk_fb: mipi-rk-fb@ff960000 {
 322                 compatible = "rockchip,rk3399-dsi";
 323                 rockchip,prop = <0>;
 324                 rockchip,grf = <&grf>;
 325                 reg = <0x0 0xff960000 0x0 0x8000>;
 326                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
 328                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
 329                 power-domains = <&power RK3399_PD_VIO>;
 330         };
 331
 332         mipi1_rk_fb: mipi-rk-fb@ff968000 {
 333                 compatible = "rockchip,rk3399-dsi";
 334                 rockchip,prop = <1>;
 335                 rockchip,grf = <&grf>;
 336                 reg = <0x0 0xff968000 0x0 0x8000>;
 337                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 338                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
 339                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
 340                 power-domains = <&power RK3399_PD_VIO>;
 341         };
 342
 343         hdmi-sound {
 344                 compatible = "simple-audio-card";
 345                 simple-audio-card,format = "i2s";
 346                 simple-audio-card,mclk-fs = <256>;
 347                 simple-audio-card,name = "rockchip,hdmi";
 348                 simple-audio-card,cpu {
 349                         sound-dai = <&i2s2>;
 350                 };
 351                 simple-audio-card,codec {
 352                         sound-dai = <&dw_hdmi_audio>;
 353                 };
 354         };
 355
 356         dw_hdmi_audio: dw-hdmi-audio {
 357                 compatible = "rockchip,dw-hdmi-audio";
 358                 #sound-dai-cells = <0>;
 359         };
 360 };
 361
 362 &i2s2 {
 363         status = "okay";
 364         #sound-dai-cells = <0>;
 365 };
 366
 367 &usbdrd_dwc3_0 {
 368         dr_mode = "peripheral";
 369 };