arch/arm64/boot/dts/rockchip/rk3399-android.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42 #include <dt-bindings/display/rk_fb.h>
  43 #include <dt-bindings/display/mipi_dsi.h>
  44
  45 / {
  46         compatible = "rockchip,android", "rockchip,rk3399";
  47
  48         aliases {
  49                 lcdc0 = &vopb_rk_fb;
  50                 lcdc1 = &vopl_rk_fb;
  51         };
  52
  53         chosen {
  54                 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
  55         };
  56
  57         ramoops_mem: ramoops_mem {
  58                 reg = <0x0 0x110000 0x0 0xf0000>;
  59                 reg-names = "ramoops_mem";
  60         };
  61
  62         ramoops {
  63                 compatible = "ramoops";
  64                 record-size = <0x0 0x20000>;
  65                 console-size = <0x0 0x80000>;
  66                 ftrace-size = <0x0 0x00000>;
  67                 pmsg-size = <0x0 0x50000>;
  68                 memory-region = <&ramoops_mem>;
  69         };
  70
  71         fiq_debugger: fiq-debugger {
  72                 compatible = "rockchip,fiq-debugger";
  73                 rockchip,serial-id = <2>;
  74                 rockchip,signal-irq = <182>;
  75                 rockchip,wake-irq = <0>;
  76                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
  77                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
  78                 pinctrl-names = "default";
  79                 pinctrl-0 = <&uart2c_xfer>;
  80         };
  81
  82         reserved-memory {
  83                 #address-cells = <2>;
  84                 #size-cells = <2>;
  85                 ranges;
  86
  87                 /* global autoconfigured region for contiguous allocations */
  88                 linux,cma {
  89                         compatible = "shared-dma-pool";
  90                         reusable;
  91                         size = <0x0 0x8000000>;
  92                         linux,cma-default;
  93                 };
  94                 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
  95                 rockchip_logo: rockchip-logo@00000000 {
  96                         compatible = "rockchip,fb-logo";
  97                         reg = <0x0 0x0 0x0 0x0>;
  98                 };
  99         };
 100
 101         ion {
 102                 compatible = "rockchip,ion";
 103                 #address-cells = <1>;
 104                 #size-cells = <0>;
 105
 106                 cma-heap {
 107                         reg = <0x00000000 0x02000000>;
 108                 };
 109
 110                 system-heap {
 111                 };
 112         };
 113
 114         rk_key: rockchip-key {
 115                 compatible = "rockchip,key";
 116                 status = "okay";
 117
 118                 io-channels = <&saradc 1>;
 119
 120                 vol-up-key {
 121                         linux,code = <115>;
 122                         label = "volume up";
 123                         rockchip,adc_value = <1>;
 124                 };
 125
 126                 vol-down-key {
 127                         linux,code = <114>;
 128                         label = "volume down";
 129                         rockchip,adc_value = <170>;
 130                 };
 131
 132                 power-key {
 133                         gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 134                         linux,code = <116>;
 135                         label = "power";
 136                         gpio-key,wakeup;
 137                 };
 138
 139                 menu-key {
 140                         linux,code = <59>;
 141                         label = "menu";
 142                         rockchip,adc_value = <746>;
 143                 };
 144
 145                 home-key {
 146                         linux,code = <102>;
 147                         label = "home";
 148                         rockchip,adc_value = <355>;
 149                 };
 150
 151                 back-key {
 152                         linux,code = <158>;
 153                         label = "back";
 154                         rockchip,adc_value = <560>;
 155                 };
 156
 157                 camera-key {
 158                         linux,code = <212>;
 159                         label = "camera";
 160                         rockchip,adc_value = <450>;
 161                 };
 162         };
 163
 164         cdn_dp_fb: dp-fb@fec00000 {
 165                 status = "disabled";
 166                 compatible = "rockchip,rk3399-cdn-dp-fb";
 167                 reg = <0x0 0xfec00000 0x0 0x100000>;
 168                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 169                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 170                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 171                 clock-names = "core-clk", "pclk", "spdif", "grf";
 172                 assigned-clocks = <&cru SCLK_DP_CORE>;
 173                 assigned-clock-rates = <100000000>;
 174                 power-domains = <&power RK3399_PD_HDCP>;
 175                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 176                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 177                          <&cru SRST_P_UPHY0_APB>;
 178                 reset-names = "spdif", "dptx", "apb";
 179                 rockchip,grf = <&grf>;
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 #sound-dai-cells = <1>;
 183         };
 184
 185         cdn_dp_sound: cdn-dp-sound {
 186                 status = "disabled";
 187                 compatible = "simple-audio-card";
 188                 simple-audio-card,name = "rockchip,cdn-dp-fb";
 189                 simple-audio-card,widgets = "Headphone", "Out Jack",
 190                                             "Line", "In Jack";
 191
 192                 simple-audio-card,dai-link@0 {
 193                         format = "i2s";
 194                         mclk-fs = <256>;
 195
 196                         cpu {
 197                                 sound-dai = <&i2s2>;
 198                         };
 199
 200                         codec {
 201                                 sound-dai = <&cdn_dp_fb 0>;
 202                         };
 203                 };
 204         };
 205
 206         vpu: vpu_service@ff650000 {
 207                 compatible = "rockchip,vpu_service";
 208                 rockchip,grf = <&grf>;
 209                 iommu_enabled = <1>;
 210                 reg = <0x0 0xff650000 0x0 0x800>;
 211                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
 212                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
 213                 interrupt-names = "irq_dec", "irq_enc";
 214                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 215                 clock-names = "aclk_vcodec", "hclk_vcodec";
 216                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
 217                 reset-names = "video_h", "video_a";
 218                 power-domains = <&power RK3399_PD_VCODEC>;
 219                 name = "vpu_service";
 220                 dev_mode = <0>;
 221                 /* 0 means ion, 1 means drm */
 222                 allocator = <0>;
 223         };
 224
 225         vpu_mmu: vpu_mmu {
 226                 dbgname = "vpu";
 227                 compatible = "rockchip,vpu_mmu";
 228                 reg = <0x0 0xff650800 0x0 0x40>;
 229                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
 230                 interrupt-names = "vpu_mmu";
 231         };
 232
 233         rkvdec: rkvdec@ff660000 {
 234                 compatible = "rockchip,rkvdec";
 235                 rockchip,grf = <&grf>;
 236                 iommu_enabled = <1>;
 237                 reg = <0x0 0xff660000 0x0 0x400>;
 238                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
 239                 interrupt-names = "irq_dec";
 240                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
 241                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
 242                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
 243                 reset-names = "video_h", "video_a";
 244                 power-domains = <&power RK3399_PD_VDU>;
 245                 dev_mode = <2>;
 246                 name = "rkvdec";
 247                 /* 0 means ion, 1 means drm */
 248                 allocator = <0>;
 249         };
 250
 251         vdec_mmu: vdec_mmu {
 252                 dbgname = "vdec";
 253                 compatible = "rockchip,vdec_mmu";
 254                 reg = <0x0 0xff660480 0x0 0x40>,
 255                       <0x0 0xff6604c0 0x0 0x40>;
 256                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
 257                 interrupt-names = "vdec_mmu";
 258         };
 259
 260         iep: iep@ff670000 {
 261                 compatible = "rockchip,iep";
 262                 iommu_enabled = <1>;
 263                 reg = <0x0 0xff670000 0x0 0x800>;
 264                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
 265                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 266                 clock-names = "aclk_iep", "hclk_iep";
 267                 power-domains = <&power RK3399_PD_IEP>;
 268                 version = <2>;
 269         };
 270
 271         iep_mmu: iep-mmu {
 272                 dbgname = "iep";
 273                 compatible = "rockchip,iep_mmu";
 274                 reg = <0x0 0xff670800 0x0 0x40>;
 275                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
 276                 interrupt-names = "iep_mmu";
 277         };
 278
 279         rga: rga@ff680000 {
 280                 compatible = "rockchip,rga2";
 281                 dev_mode = <1>;
 282                 reg = <0x0 0xff680000 0x0 0x1000>;
 283                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
 284                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
 285                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 286                 power-domains = <&power RK3399_PD_RGA>;
 287                 status = "okay";
 288         };
 289
 290         fb: fb {
 291                 status = "okay";
 292                 compatible = "rockchip,rk-fb";
 293                 rockchip,disp-mode = <DUAL>;
 294                 rockchip,uboot-logo-on = <1>;
 295                 memory-region = <&rockchip_logo>;
 296         };
 297
 298         rk_screen: screen {
 299                 status = "okay";
 300                 compatible = "rockchip,screen";
 301         };
 302
 303         vopb_rk_fb: vop-rk-fb@ff900000 {
 304                 status = "disabled";
 305                 compatible = "rockchip,rk3399-lcdc";
 306                 rockchip,prop = <PRMRY>;
 307                 reg = <0x0 0xff900000 0x0 0x3efc>;
 308                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
 309                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 310                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 311                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
 312                 reset-names = "axi", "ahb", "dclk";
 313                 rockchip,grf = <&grf>;
 314                 rockchip,pwr18 = <0>;
 315                 rockchip,iommu-enabled = <1>;
 316                 power-domains = <&power RK3399_PD_VOPB>;
 317                 devfreq = <&dmc>;
 318         };
 319
 320         vopb_mmu_rk_fb: vopb-mmu {
 321                 status = "okay";
 322                 dbgname = "vop";
 323                 compatible = "rockchip,vopb_mmu";
 324                 reg = <0x0 0xff903f00 0x0 0x100>;
 325                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
 326                 interrupt-names = "vopb_mmu";
 327         };
 328
 329         vopl_rk_fb: vop-rk-fb@ff8f0000 {
 330                 status = "disabled";
 331                 compatible = "rockchip,rk3399-lcdc";
 332                 rockchip,prop = <EXTEND>;
 333                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
 334                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
 335                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 336                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 337                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
 338                 reset-names = "axi", "ahb", "dclk";
 339                 rockchip,grf = <&grf>;
 340                 rockchip,pwr18 = <0>;
 341                 rockchip,iommu-enabled = <1>;
 342                 power-domains = <&power RK3399_PD_VOPL>;
 343                 devfreq = <&dmc>;
 344         };
 345
 346         vopl_mmu_rk_fb: vopl-mmu {
 347                 status = "okay";
 348                 dbgname = "vop";
 349                 compatible = "rockchip,vopl_mmu";
 350                 reg = <0x0 0xff8f3f00 0x0 0x100>;
 351                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
 352                 interrupt-names = "vopl_mmu";
 353         };
 354
 355         cif_isp0: cif_isp@ff910000 {
 356                 compatible = "rockchip,rk3399-cif-isp";
 357                 rockchip,grf = <&grf>;
 358                 reg = <0x0 0xff910000 0x0 0x10000>, <0x0 0xff968000 0x0 0x8000>;
 359                 reg-names = "register", "dsihost-register";
 360                 clocks =
 361                         <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
 362                         <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
 363                         <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
 364                         <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
 365                         <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
 366                 clock-names =
 367                         "clk_cif_out", "clk_cif_pll",
 368                         "pclk_dphytxrx", "pclk_dphy_ref",
 369                         "aclk_isp0_noc", "aclk_isp0_wrapper",
 370                         "hclk_isp0_noc", "hclk_isp0_wrapper",
 371                         "clk_isp0", "pclk_dphyrx";
 372                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
 373                 interrupt-names = "cif_isp10_irq";
 374                 power-domains = <&power RK3399_PD_ISP0>;
 375                 status = "disabled";
 376         };
 377
 378         isp0: isp@ff910000 {
 379                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
 380                 reg = <0x0 0xff910000 0x0 0x10000>;
 381                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
 382                 clocks =
 383                         <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
 384                         <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
 385                         <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
 386                         <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
 387                         <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
 388                 clock-names =
 389                         "clk_cif_out", "clk_cif_pll",
 390                         "pclk_dphytxrx", "pclk_dphy_ref",
 391                         "aclk_isp0_noc", "aclk_isp0_wrapper",
 392                         "hclk_isp0_noc", "hclk_isp0_wrapper",
 393                         "clk_isp0", "pclk_dphyrx";
 394                 pinctrl-names =
 395                         "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
 396                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 397                         "isp_flash_as_trigger_out";
 398                 pinctrl-0 = <&cif_clkout>;
 399                 pinctrl-1 = <&isp_dvp_d0d7>;
 400                 pinctrl-2 = <&cif_clkout>;
 401                 pinctrl-3 = <&isp_prelight>;
 402                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
 403                 pinctrl-5 = <&isp_flash_trigger>;
 404                 rockchip,isp,mipiphy = <2>;
 405                 rockchip,isp,cifphy = <1>;
 406                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
 407                 rockchip,grf = <&grf>;
 408                 rockchip,cru = <&cru>;
 409                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 410                 rockchip,isp,iommu-enable = <1>;
 411                 power-domains = <&power RK3399_PD_ISP0>;
 412                 status = "disabled";
 413         };
 414
 415         isp0_mmu {
 416                 dbgname = "isp0";
 417                 compatible = "rockchip,isp0_mmu";
 418                 reg = <0x0 0xff914000 0x0  0x100>,
 419                       <0x0 0xff915000 0x0  0x100>;
 420                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
 421                 interrupt-names = "isp0_mmu";
 422         };
 423
 424         isp1: isp@ff920000 {
 425                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
 426                 reg = <0x0 0xff920000 0x0 0x10000>;
 427                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
 428                 clocks =
 429                         <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
 430                         <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
 431                         <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
 432                         <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
 433                         <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
 434                         <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
 435                         <&cru SCLK_MIPIDPHY_CFG>;
 436                 clock-names =
 437                         "aclk_isp1_noc", "aclk_isp1_wrapper",
 438                         "hclk_isp1_noc", "hclk_isp1_wrapper",
 439                         "clk_isp1", "clk_cif_out",
 440                         "clk_cif_pll", "pclk_dphytxrx",
 441                         "pclk_dphy_ref", "pclk_isp1",
 442                         "pclk_dphyrx", "pclk_mipi_dsi",
 443                         "mipi_dphy_cfg";
 444                 pinctrl-names =
 445                         "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
 446                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 447                         "isp_flash_as_trigger_out";
 448                 pinctrl-0 = <&cif_clkout>;
 449                 pinctrl-1 = <&isp_dvp_d0d7>;
 450                 pinctrl-2 = <&cif_clkout>;
 451                 pinctrl-3 = <&isp_prelight>;
 452                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
 453                 pinctrl-5 = <&isp_flash_trigger>;
 454                 rockchip,isp,mipiphy = <2>;
 455                 rockchip,isp,cifphy = <1>;
 456                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
 457                 rockchip,grf = <&grf>;
 458                 rockchip,cru = <&cru>;
 459                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 460                 rockchip,isp,iommu-enable = <1>;
 461                 power-domains = <&power RK3399_PD_ISP1>;
 462                 status = "disabled";
 463         };
 464
 465         isp1_mmu {
 466                 dbgname = "isp1";
 467                 compatible = "rockchip,isp1_mmu";
 468                 reg = <0x0 0xff924000 0x0  0x100>,
 469                       <0x0 0xff925000 0x0  0x100>;
 470                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
 471                 interrupt-names = "isp1_mmu";
 472         };
 473
 474         hdmi_rk_fb: hdmi-rk-fb@ff940000 {
 475                 status = "disabled";
 476                 compatible = "rockchip,rk3399-hdmi";
 477                 reg = <0x0 0xff940000 0x0 0x20000>;
 478                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
 479                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>;
 480                 clocks = <&cru PCLK_HDMI_CTRL>,
 481                          <&cru HCLK_HDCP>,
 482                          <&cru SCLK_HDMI_CEC>,
 483                          <&cru PLL_VPLL>,
 484                          <&cru SCLK_HDMI_SFR>;
 485                 clock-names = "pclk_hdmi",
 486                               "hdcp_clk_hdmi",
 487                               "cec_clk_hdmi",
 488                               "dclk_hdmi_phy",
 489                               "sclk_hdmi_sfr";
 490                 resets = <&cru SRST_HDMI_CTRL>;
 491                 reset-names = "hdmi";
 492                 pinctrl-names = "default", "gpio";
 493                 pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
 494                 pinctrl-1 = <&i2c3_gpio>;
 495                 rockchip,grf = <&grf>;
 496                 power-domains = <&power RK3399_PD_HDCP>;
 497         };
 498
 499         mipi0_rk_fb: mipi-rk-fb@ff960000 {
 500                 compatible = "rockchip,rk3399-dsi";
 501                 rockchip,prop = <0>;
 502                 rockchip,grf = <&grf>;
 503                 reg = <0x0 0xff960000 0x0 0x8000>;
 504                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
 505                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
 506                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
 507                 power-domains = <&power RK3399_PD_VIO>;
 508                 status = "disabled";
 509         };
 510
 511         mipi1_rk_fb: mipi-rk-fb@ff968000 {
 512                 compatible = "rockchip,rk3399-dsi";
 513                 rockchip,prop = <1>;
 514                 rockchip,grf = <&grf>;
 515                 reg = <0x0 0xff968000 0x0 0x8000>;
 516                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
 517                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
 518                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
 519                 power-domains = <&power RK3399_PD_VIO>;
 520                 status = "disabled";
 521         };
 522
 523         edp_rk_fb: edp-rk-fb@ff970000 {
 524                 compatible = "rockchip,rk3399-edp-fb";
 525                 reg = <0x0 0xff970000 0x0 0x8000>;
 526                 rockchip,grf = <&grf>;
 527                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
 528                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
 529                 clock-names = "clk_edp", "pclk_edp", "clk_grf";
 530                 resets = <&cru SRST_P_EDP_CTRL>;
 531                 reset-names = "edp_apb";
 532                 status = "disabled";
 533                 power-domains = <&power RK3399_PD_EDP>;
 534         };
 535 };
 536
 537 &pinctrl {
 538         isp {
 539                 cif_clkout: cif-clkout {
 540                         rockchip,pins =
 541                         /*cif_clkout*/
 542                         <2 11 RK_FUNC_3 &pcfg_pull_none>;
 543                 };
 544
 545                 isp_dvp_d0d7: isp-dvp-d0d7 {
 546                         rockchip,pins =
 547                         /*cif_data0*/
 548                         <2 0 RK_FUNC_3 &pcfg_pull_none>,
 549                         /*cif_data1*/
 550                         <2 1 RK_FUNC_3 &pcfg_pull_none>,
 551                         /*cif_data2*/
 552                         <2 2 RK_FUNC_3 &pcfg_pull_none>,
 553                         /*cif_data3*/
 554                         <2 3 RK_FUNC_3 &pcfg_pull_none>,
 555                         /*cif_data4*/
 556                         <2 4 RK_FUNC_3 &pcfg_pull_none>,
 557                         /*cif_data5*/
 558                         <2 5 RK_FUNC_3 &pcfg_pull_none>,
 559                         /*cif_data6*/
 560                         <2 6 RK_FUNC_3 &pcfg_pull_none>,
 561                         /*cif_data7*/
 562                         <2 7 RK_FUNC_3 &pcfg_pull_none>,
 563                         /*cif_sync*/
 564                         <2 8 RK_FUNC_3 &pcfg_pull_none>,
 565                         /*cif_href*/
 566                         <2 9 RK_FUNC_3 &pcfg_pull_none>,
 567                         /*cif_clkin*/
 568                         <2 10 RK_FUNC_3 &pcfg_pull_none>;
 569                 };
 570
 571                 isp_shutter: isp-shutter {
 572                         rockchip,pins =
 573                         /*SHUTTEREN*/
 574                         <1 1 RK_FUNC_1 &pcfg_pull_none>,
 575                         /*SHUTTERTRIG*/
 576                         <1 0 RK_FUNC_1 &pcfg_pull_none>;
 577                 };
 578
 579                 isp_flash_trigger: isp-flash-trigger {
 580                         /*ISP_FLASHTRIGOU*/
 581                         rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
 582                 };
 583
 584                 isp_prelight: isp-prelight {
 585                         /*ISP_PRELIGHTTRIG*/
 586                         rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
 587                 };
 588
 589                 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
 590                         /*ISP_FLASHTRIGOU*/
 591                         rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
 592                 };
 593         };
 594
 595         cam_pins {
 596                 cam0_default_pins: cam0-default-pins {
 597                         rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>,
 598                                         <2 11 RK_FUNC_3 &pcfg_pull_none>;
 599                 };
 600                 cam0_sleep_pins: cam0-sleep-pins {
 601                         rockchip,pins = <4 27 RK_FUNC_3 &pcfg_pull_none>,
 602                                         <2 11 RK_FUNC_GPIO &pcfg_pull_none>;
 603                 };
 604         };
 605 };