arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49
  50 / {
  51         compatible = "rockchip,rk3368";
  52         interrupt-parent = <&gic>;
  53         #address-cells = <2>;
  54         #size-cells = <2>;
  55
  56         aliases {
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 serial0 = &uart0;
  64                 serial1 = &uart1;
  65                 serial2 = &uart2;
  66                 serial3 = &uart3;
  67                 serial4 = &uart4;
  68                 spi0 = &spi0;
  69                 spi1 = &spi1;
  70                 spi2 = &spi2;
  71                 lcdc = &lcdc;
  72         };
  73
  74         cpus {
  75                 #address-cells = <0x2>;
  76                 #size-cells = <0x0>;
  77
  78                 cpu-map {
  79                         cluster0 {
  80                                 core0 {
  81                                         cpu = <&cpu_b0>;
  82                                 };
  83                                 core1 {
  84                                         cpu = <&cpu_b1>;
  85                                 };
  86                                 core2 {
  87                                         cpu = <&cpu_b2>;
  88                                 };
  89                                 core3 {
  90                                         cpu = <&cpu_b3>;
  91                                 };
  92                         };
  93
  94                         cluster1 {
  95                                 core0 {
  96                                         cpu = <&cpu_l0>;
  97                                 };
  98                                 core1 {
  99                                         cpu = <&cpu_l1>;
 100                                 };
 101                                 core2 {
 102                                         cpu = <&cpu_l2>;
 103                                 };
 104                                 core3 {
 105                                         cpu = <&cpu_l3>;
 106                                 };
 107                         };
 108                 };
 109
 110                 idle-states {
 111                         entry-method = "psci";
 112
 113                         cpu_sleep: cpu-sleep-0 {
 114                                 compatible = "arm,idle-state";
 115                                 arm,psci-suspend-param = <0x1010000>;
 116                                 entry-latency-us = <0x3fffffff>;
 117                                 exit-latency-us = <0x40000000>;
 118                                 min-residency-us = <0xffffffff>;
 119                         };
 120                 };
 121
 122                 cpu_l0: cpu@0 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x0>;
 126                         cpu-idle-states = <&cpu_sleep>;
 127                         enable-method = "psci";
 128                 };
 129
 130                 cpu_l1: cpu@1 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a53", "arm,armv8";
 133                         reg = <0x0 0x1>;
 134                         cpu-idle-states = <&cpu_sleep>;
 135                         enable-method = "psci";
 136                 };
 137
 138                 cpu_l2: cpu@2 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a53", "arm,armv8";
 141                         reg = <0x0 0x2>;
 142                         cpu-idle-states = <&cpu_sleep>;
 143                         enable-method = "psci";
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         cpu-idle-states = <&cpu_sleep>;
 151                         enable-method = "psci";
 152                 };
 153
 154                 cpu_b0: cpu@100 {
 155                         device_type = "cpu";
 156                         compatible = "arm,cortex-a53", "arm,armv8";
 157                         reg = <0x0 0x100>;
 158                         cpu-idle-states = <&cpu_sleep>;
 159                         enable-method = "psci";
 160                 };
 161
 162                 cpu_b1: cpu@101 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-a53", "arm,armv8";
 165                         reg = <0x0 0x101>;
 166                         cpu-idle-states = <&cpu_sleep>;
 167                         enable-method = "psci";
 168                 };
 169
 170                 cpu_b2: cpu@102 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a53", "arm,armv8";
 173                         reg = <0x0 0x102>;
 174                         cpu-idle-states = <&cpu_sleep>;
 175                         enable-method = "psci";
 176                 };
 177
 178                 cpu_b3: cpu@103 {
 179                         device_type = "cpu";
 180                         compatible = "arm,cortex-a53", "arm,armv8";
 181                         reg = <0x0 0x103>;
 182                         cpu-idle-states = <&cpu_sleep>;
 183                         enable-method = "psci";
 184                 };
 185         };
 186
 187         arm-pmu {
 188                 compatible = "arm,armv8-pmuv3";
 189                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 197                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 198                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 199                                      <&cpu_b2>, <&cpu_b3>;
 200         };
 201
 202         amba {
 203                 compatible = "arm,amba-bus";
 204                 #address-cells = <2>;
 205                 #size-cells = <2>;
 206                 ranges;
 207
 208                 dmac_peri: dma-controller@ff250000 {
 209                         compatible = "arm,pl330", "arm,primecell";
 210                         reg = <0x0 0xff250000 0x0 0x4000>;
 211                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 212                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 213                         #dma-cells = <1>;
 214                         clocks = <&cru ACLK_DMAC_PERI>;
 215                         clock-names = "apb_pclk";
 216                 };
 217
 218                 dmac_bus: dma-controller@ff600000 {
 219                         compatible = "arm,pl330", "arm,primecell";
 220                         reg = <0x0 0xff600000 0x0 0x4000>;
 221                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 223                         #dma-cells = <1>;
 224                         clocks = <&cru ACLK_DMAC_BUS>;
 225                         clock-names = "apb_pclk";
 226                 };
 227         };
 228
 229         psci {
 230                 compatible = "arm,psci-0.2";
 231                 method = "smc";
 232         };
 233
 234         timer {
 235                 compatible = "arm,armv8-timer";
 236                 interrupts = <GIC_PPI 13
 237                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 238                              <GIC_PPI 14
 239                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 240                              <GIC_PPI 11
 241                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 242                              <GIC_PPI 10
 243                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 244         };
 245
 246         xin24m: oscillator {
 247                 compatible = "fixed-clock";
 248                 clock-frequency = <24000000>;
 249                 clock-output-names = "xin24m";
 250                 #clock-cells = <0>;
 251         };
 252
 253         sdmmc: rksdmmc@ff0c0000 {
 254                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 255                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 256                 clock-freq-min-max = <400000 150000000>;
 257                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 258                 clock-names = "biu", "ciu";
 259                 fifo-depth = <0x100>;
 260                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 261                 status = "disabled";
 262         };
 263
 264         sdio0: dwmmc@ff0d0000 {
 265                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 266                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 267                 clock-freq-min-max = <400000 150000000>;
 268                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 269                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 270                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 271                 fifo-depth = <0x100>;
 272                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 273                 status = "disabled";
 274         };
 275
 276         emmc: rksdmmc@ff0f0000 {
 277                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 278                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 279                 clock-freq-min-max = <400000 150000000>;
 280                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 281                 clock-names = "biu", "ciu";
 282                 fifo-depth = <0x100>;
 283                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 284                 status = "disabled";
 285         };
 286
 287         saradc: saradc@ff100000 {
 288                 compatible = "rockchip,saradc";
 289                 reg = <0x0 0xff100000 0x0 0x100>;
 290                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 291                 #io-channel-cells = <1>;
 292                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 293                 clock-names = "saradc", "apb_pclk";
 294                 status = "disabled";
 295         };
 296
 297         spi0: spi@ff110000 {
 298                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 299                 reg = <0x0 0xff110000 0x0 0x1000>;
 300                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 301                 clock-names = "spiclk", "apb_pclk";
 302                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 305                 #address-cells = <1>;
 306                 #size-cells = <0>;
 307                 status = "disabled";
 308         };
 309
 310         spi1: spi@ff120000 {
 311                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 312                 reg = <0x0 0xff120000 0x0 0x1000>;
 313                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 314                 clock-names = "spiclk", "apb_pclk";
 315                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 316                 pinctrl-names = "default";
 317                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 318                 #address-cells = <1>;
 319                 #size-cells = <0>;
 320                 status = "disabled";
 321         };
 322
 323         spi2: spi@ff130000 {
 324                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 325                 reg = <0x0 0xff130000 0x0 0x1000>;
 326                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 327                 clock-names = "spiclk", "apb_pclk";
 328                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 status = "disabled";
 334         };
 335
 336         i2c1: i2c@ff140000 {
 337                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 338                 reg = <0x0 0xff140000 0x0 0x1000>;
 339                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 clock-names = "i2c";
 343                 clocks = <&cru PCLK_I2C1>;
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&i2c1_xfer>;
 346                 status = "disabled";
 347         };
 348
 349         i2c3: i2c@ff150000 {
 350                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 351                 reg = <0x0 0xff150000 0x0 0x1000>;
 352                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 clock-names = "i2c";
 356                 clocks = <&cru PCLK_I2C3>;
 357                 pinctrl-names = "default";
 358                 pinctrl-0 = <&i2c3_xfer>;
 359                 status = "disabled";
 360         };
 361
 362         i2c4: i2c@ff160000 {
 363                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 364                 reg = <0x0 0xff160000 0x0 0x1000>;
 365                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 clock-names = "i2c";
 369                 clocks = <&cru PCLK_I2C4>;
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&i2c4_xfer>;
 372                 status = "disabled";
 373         };
 374
 375         i2c5: i2c@ff170000 {
 376                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 377                 reg = <0x0 0xff170000 0x0 0x1000>;
 378                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 clock-names = "i2c";
 382                 clocks = <&cru PCLK_I2C5>;
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&i2c5_xfer>;
 385                 status = "disabled";
 386         };
 387
 388         uart0: serial@ff180000 {
 389                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 390                 reg = <0x0 0xff180000 0x0 0x100>;
 391                 clock-frequency = <24000000>;
 392                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 393                 clock-names = "baudclk", "apb_pclk";
 394                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 395                 reg-shift = <2>;
 396                 reg-io-width = <4>;
 397                 status = "disabled";
 398         };
 399
 400         uart1: serial@ff190000 {
 401                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 402                 reg = <0x0 0xff190000 0x0 0x100>;
 403                 clock-frequency = <24000000>;
 404                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 405                 clock-names = "baudclk", "apb_pclk";
 406                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 407                 reg-shift = <2>;
 408                 reg-io-width = <4>;
 409                 status = "disabled";
 410         };
 411
 412         uart3: serial@ff1b0000 {
 413                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 414                 reg = <0x0 0xff1b0000 0x0 0x100>;
 415                 clock-frequency = <24000000>;
 416                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 417                 clock-names = "baudclk", "apb_pclk";
 418                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 419                 reg-shift = <2>;
 420                 reg-io-width = <4>;
 421                 status = "disabled";
 422         };
 423
 424         uart4: serial@ff1c0000 {
 425                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 426                 reg = <0x0 0xff1c0000 0x0 0x100>;
 427                 clock-frequency = <24000000>;
 428                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 429                 clock-names = "baudclk", "apb_pclk";
 430                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 431                 reg-shift = <2>;
 432                 reg-io-width = <4>;
 433                 status = "disabled";
 434         };
 435
 436         gmac: ethernet@ff290000 {
 437                 compatible = "rockchip,rk3368-gmac";
 438                 reg = <0x0 0xff290000 0x0 0x10000>;
 439                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 440                 interrupt-names = "macirq";
 441                 rockchip,grf = <&grf>;
 442                 clocks = <&cru SCLK_MAC>,
 443                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 444                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 445                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 446                 clock-names = "stmmaceth",
 447                         "mac_clk_rx", "mac_clk_tx",
 448                         "clk_mac_ref", "clk_mac_refout",
 449                         "aclk_mac", "pclk_mac";
 450                 status = "disabled";
 451         };
 452
 453         usb_host0_ehci: usb@ff500000 {
 454                 compatible = "generic-ehci";
 455                 reg = <0x0 0xff500000 0x0 0x100>;
 456                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 457                 clocks = <&cru HCLK_HOST0>;
 458                 clock-names = "usbhost";
 459                 status = "disabled";
 460         };
 461
 462         usb_otg: usb@ff580000 {
 463                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 464                                 "snps,dwc2";
 465                 reg = <0x0 0xff580000 0x0 0x40000>;
 466                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 467                 clocks = <&cru HCLK_OTG0>;
 468                 clock-names = "otg";
 469                 dr_mode = "otg";
 470                 g-np-tx-fifo-size = <16>;
 471                 g-rx-fifo-size = <275>;
 472                 g-tx-fifo-size = <256 128 128 64 64 32>;
 473                 g-use-dma;
 474                 status = "disabled";
 475         };
 476
 477         ddrpctl: syscon@ff610000 {
 478                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 479                 reg = <0x0 0xff610000 0x0 0x400>;
 480         };
 481
 482         i2c0: i2c@ff650000 {
 483                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 484                 reg = <0x0 0xff650000 0x0 0x1000>;
 485                 clocks = <&cru PCLK_I2C0>;
 486                 clock-names = "i2c";
 487                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&i2c0_xfer>;
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 status = "disabled";
 493         };
 494
 495         i2c2: i2c@ff660000 {
 496                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 497                 reg = <0x0 0xff660000 0x0 0x1000>;
 498                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 clock-names = "i2c";
 502                 clocks = <&cru PCLK_I2C2>;
 503                 pinctrl-names = "default";
 504                 pinctrl-0 = <&i2c2_xfer>;
 505                 status = "disabled";
 506         };
 507
 508         pwm0: pwm@ff680000 {
 509                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 510                 reg = <0x0 0xff680000 0x0 0x10>;
 511                 #pwm-cells = <3>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&pwm0_pin>;
 514                 clocks = <&cru PCLK_PWM1>;
 515                 clock-names = "pwm";
 516                 status = "disabled";
 517         };
 518
 519         pwm1: pwm@ff680010 {
 520                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 521                 reg = <0x0 0xff680010 0x0 0x10>;
 522                 #pwm-cells = <3>;
 523                 pinctrl-names = "default";
 524                 pinctrl-0 = <&pwm1_pin>;
 525                 clocks = <&cru PCLK_PWM1>;
 526                 clock-names = "pwm";
 527                 status = "disabled";
 528         };
 529
 530         pwm2: pwm@ff680020 {
 531                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 532                 reg = <0x0 0xff680020 0x0 0x10>;
 533                 #pwm-cells = <3>;
 534                 clocks = <&cru PCLK_PWM1>;
 535                 clock-names = "pwm";
 536                 status = "disabled";
 537         };
 538
 539         pwm3: pwm@ff680030 {
 540                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 541                 reg = <0x0 0xff680030 0x0 0x10>;
 542                 #pwm-cells = <3>;
 543                 pinctrl-names = "default";
 544                 pinctrl-0 = <&pwm3_pin>;
 545                 clocks = <&cru PCLK_PWM1>;
 546                 clock-names = "pwm";
 547                 status = "disabled";
 548         };
 549
 550         uart2: serial@ff690000 {
 551                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 552                 reg = <0x0 0xff690000 0x0 0x100>;
 553                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 554                 clock-names = "baudclk", "apb_pclk";
 555                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 556                 pinctrl-names = "default";
 557                 pinctrl-0 = <&uart2_xfer>;
 558                 reg-shift = <2>;
 559                 reg-io-width = <4>;
 560                 status = "disabled";
 561         };
 562
 563         pmu: power-management@ff730000 {
 564                 compatible = "rockchip,rk3368-pmu", "syscon";
 565                 reg = <0x0 0xff730000 0x0 0x1000>;
 566         };
 567
 568         pmugrf: syscon@ff738000 {
 569                 compatible = "rockchip,rk3368-pmugrf", "syscon";
 570                 reg = <0x0 0xff738000 0x0 0x1000>;
 571         };
 572
 573         cru: clock-controller@ff760000 {
 574                 compatible = "rockchip,rk3368-cru";
 575                 reg = <0x0 0xff760000 0x0 0x1000>;
 576                 rockchip,grf = <&grf>;
 577                 #clock-cells = <1>;
 578                 #reset-cells = <1>;
 579         };
 580
 581         grf: syscon@ff770000 {
 582                 compatible = "rockchip,rk3368-grf", "syscon";
 583                 reg = <0x0 0xff770000 0x0 0x1000>;
 584         };
 585
 586         wdt: watchdog@ff800000 {
 587                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 588                 reg = <0x0 0xff800000 0x0 0x100>;
 589                 clocks = <&cru PCLK_WDT>;
 590                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 591                 status = "disabled";
 592         };
 593
 594         gic: interrupt-controller@ffb71000 {
 595                 compatible = "arm,gic-400";
 596                 interrupt-controller;
 597                 #interrupt-cells = <3>;
 598                 #address-cells = <0>;
 599
 600                 reg = <0x0 0xffb71000 0x0 0x1000>,
 601                       <0x0 0xffb72000 0x0 0x1000>,
 602                       <0x0 0xffb74000 0x0 0x2000>,
 603                       <0x0 0xffb76000 0x0 0x2000>;
 604                 interrupts = <GIC_PPI 9
 605                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 606         };
 607
 608         gpu: rogue-g6110@ffa30000 {
 609                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
 610                 reg = <0x0 0xffa30000 0x0 0x10000>;
 611                 clocks =
 612                         <&cru SCLK_GPU_CORE>,
 613                         <&cru ACLK_GPU_MEM>,
 614                         <&cru ACLK_GPU_CFG>;
 615                 clock-names =
 616                         "clk_gpu",
 617                         "aclk_gpu_mem",
 618                         "aclk_gpu_cfg";
 619                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 620                 interrupt-names = "rogue-g6110-irq";
 621         };
 622
 623         i2s_2ch: i2s-2ch@ff890000 {
 624                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 625                 reg = <0x0 0xff898000 0x0 0x1000>;
 626                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 627                 #address-cells = <2>;
 628                 #size-cells = <0>;
 629                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 630                 dma-names = "tx", "rx";
 631                 clock-names = "i2s_hclk", "i2s_clk";
 632                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 633                 status = "disabled";
 634         };
 635
 636         i2s_8ch: i2s-8ch@ff898000 {
 637                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 638                 reg = <0x0 0xff898000 0x0 0x1000>;
 639                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 640                 #address-cells = <1>;
 641                 #size-cells = <0>;
 642                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 643                 dma-names = "tx", "rx";
 644                 clock-names = "i2s_hclk", "i2s_clk";
 645                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 646                 pinctrl-names = "default";
 647                 pinctrl-0 = <&i2s_8ch_bus>;
 648                 status = "disabled";
 649         };
 650
 651         pinctrl: pinctrl {
 652                 compatible = "rockchip,rk3368-pinctrl";
 653                 rockchip,grf = <&grf>;
 654                 rockchip,pmu = <&pmugrf>;
 655                 #address-cells = <0x2>;
 656                 #size-cells = <0x2>;
 657                 ranges;
 658
 659                 gpio0: gpio0@ff750000 {
 660                         compatible = "rockchip,gpio-bank";
 661                         reg = <0x0 0xff750000 0x0 0x100>;
 662                         clocks = <&cru PCLK_GPIO0>;
 663                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 664
 665                         gpio-controller;
 666                         #gpio-cells = <0x2>;
 667
 668                         interrupt-controller;
 669                         #interrupt-cells = <0x2>;
 670                 };
 671
 672                 gpio1: gpio1@ff780000 {
 673                         compatible = "rockchip,gpio-bank";
 674                         reg = <0x0 0xff780000 0x0 0x100>;
 675                         clocks = <&cru PCLK_GPIO1>;
 676                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 677
 678                         gpio-controller;
 679                         #gpio-cells = <0x2>;
 680
 681                         interrupt-controller;
 682                         #interrupt-cells = <0x2>;
 683                 };
 684
 685                 gpio2: gpio2@ff790000 {
 686                         compatible = "rockchip,gpio-bank";
 687                         reg = <0x0 0xff790000 0x0 0x100>;
 688                         clocks = <&cru PCLK_GPIO2>;
 689                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
 690
 691                         gpio-controller;
 692                         #gpio-cells = <0x2>;
 693
 694                         interrupt-controller;
 695                         #interrupt-cells = <0x2>;
 696                 };
 697
 698                 gpio3: gpio3@ff7a0000 {
 699                         compatible = "rockchip,gpio-bank";
 700                         reg = <0x0 0xff7a0000 0x0 0x100>;
 701                         clocks = <&cru PCLK_GPIO3>;
 702                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
 703
 704                         gpio-controller;
 705                         #gpio-cells = <0x2>;
 706
 707                         interrupt-controller;
 708                         #interrupt-cells = <0x2>;
 709                 };
 710
 711                 pcfg_pull_up: pcfg-pull-up {
 712                         bias-pull-up;
 713                 };
 714
 715                 pcfg_pull_down: pcfg-pull-down {
 716                         bias-pull-down;
 717                 };
 718
 719                 pcfg_pull_none: pcfg-pull-none {
 720                         bias-disable;
 721                 };
 722
 723                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 724                         bias-disable;
 725                         drive-strength = <12>;
 726                 };
 727
 728                 emmc {
 729                         emmc_clk: emmc-clk {
 730                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 731                         };
 732
 733                         emmc_cmd: emmc-cmd {
 734                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
 735                         };
 736
 737                         emmc_pwr: emmc-pwr {
 738                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
 739                         };
 740
 741                         emmc_bus1: emmc-bus1 {
 742                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
 743                         };
 744
 745                         emmc_bus4: emmc-bus4 {
 746                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 747                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 748                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 749                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
 750                         };
 751
 752                         emmc_bus8: emmc-bus8 {
 753                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 754                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 755                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 756                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
 757                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
 758                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
 759                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
 760                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
 761                         };
 762                 };
 763
 764                 gmac {
 765                         rgmii_pins: rgmii-pins {
 766                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 767                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 768                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 769                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 770                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 771                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
 772                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
 773                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
 774                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 775                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 776                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 777                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
 778                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
 779                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
 780                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
 781                         };
 782
 783                         rmii_pins: rmii-pins {
 784                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 785                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 786                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 787                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 788                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 789                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 790                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 791                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 792                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
 793                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
 794                         };
 795                 };
 796
 797                 i2c0 {
 798                         i2c0_xfer: i2c0-xfer {
 799                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 800                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 801                         };
 802                 };
 803
 804                 i2c1 {
 805                         i2c1_xfer: i2c1-xfer {
 806                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
 807                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
 808                         };
 809                 };
 810
 811                 i2c2 {
 812                         i2c2_xfer: i2c2-xfer {
 813                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
 814                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
 815                         };
 816                 };
 817
 818                 i2c3 {
 819                         i2c3_xfer: i2c3-xfer {
 820                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
 821                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
 822                         };
 823                 };
 824
 825                 i2c4 {
 826                         i2c4_xfer: i2c4-xfer {
 827                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
 828                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
 829                         };
 830                 };
 831
 832                 i2c5 {
 833                         i2c5_xfer: i2c5-xfer {
 834                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
 835                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
 836                         };
 837                 };
 838
 839                 i2s {
 840                         i2s_8ch_bus: i2s-8ch-bus {
 841                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
 842                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
 843                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
 844                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
 845                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
 846                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
 847                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
 848                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
 849                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
 850                         };
 851                 };
 852
 853                 sdio0 {
 854                         sdio0_bus1: sdio0-bus1 {
 855                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
 856                         };
 857
 858                         sdio0_bus4: sdio0-bus4 {
 859                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
 860                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
 861                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
 862                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
 863                         };
 864
 865                         sdio0_cmd: sdio0-cmd {
 866                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
 867                         };
 868
 869                         sdio0_clk: sdio0-clk {
 870                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
 871                         };
 872
 873                         sdio0_cd: sdio0-cd {
 874                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
 875                         };
 876
 877                         sdio0_wp: sdio0-wp {
 878                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
 879                         };
 880
 881                         sdio0_pwr: sdio0-pwr {
 882                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
 883                         };
 884
 885                         sdio0_bkpwr: sdio0-bkpwr {
 886                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
 887                         };
 888
 889                         sdio0_int: sdio0-int {
 890                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
 891                         };
 892                 };
 893
 894                 sdmmc {
 895                         sdmmc_clk: sdmmc-clk {
 896                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
 897                         };
 898
 899                         sdmmc_cmd: sdmmc-cmd {
 900                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
 901                         };
 902
 903                         sdmmc_cd: sdmcc-cd {
 904                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
 905                         };
 906
 907                         sdmmc_bus1: sdmmc-bus1 {
 908                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
 909                         };
 910
 911                         sdmmc_bus4: sdmmc-bus4 {
 912                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
 913                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
 914                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
 915                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
 916                         };
 917                 };
 918
 919                 spi0 {
 920                         spi0_clk: spi0-clk {
 921                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
 922                         };
 923                         spi0_cs0: spi0-cs0 {
 924                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
 925                         };
 926                         spi0_cs1: spi0-cs1 {
 927                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
 928                         };
 929                         spi0_tx: spi0-tx {
 930                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
 931                         };
 932                         spi0_rx: spi0-rx {
 933                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
 934                         };
 935                 };
 936
 937                 spi1 {
 938                         spi1_clk: spi1-clk {
 939                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
 940                         };
 941                         spi1_cs0: spi1-cs0 {
 942                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
 943                         };
 944                         spi1_cs1: spi1-cs1 {
 945                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
 946                         };
 947                         spi1_rx: spi1-rx {
 948                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
 949                         };
 950                         spi1_tx: spi1-tx {
 951                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
 952                         };
 953                 };
 954
 955                 spi2 {
 956                         spi2_clk: spi2-clk {
 957                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
 958                         };
 959                         spi2_cs0: spi2-cs0 {
 960                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
 961                         };
 962                         spi2_rx: spi2-rx {
 963                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
 964                         };
 965                         spi2_tx: spi2-tx {
 966                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
 967                         };
 968                 };
 969
 970                 uart0 {
 971                         uart0_xfer: uart0-xfer {
 972                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
 973                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
 974                         };
 975
 976                         uart0_cts: uart0-cts {
 977                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
 978                         };
 979
 980                         uart0_rts: uart0-rts {
 981                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
 982                         };
 983                 };
 984
 985                 uart1 {
 986                         uart1_xfer: uart1-xfer {
 987                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
 988                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
 989                         };
 990
 991                         uart1_cts: uart1-cts {
 992                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
 993                         };
 994
 995                         uart1_rts: uart1-rts {
 996                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
 997                         };
 998                 };
 999
1000                 uart2 {
1001                         uart2_xfer: uart2-xfer {
1002                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1003                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1004                         };
1005                         /* no rts / cts for uart2 */
1006                 };
1007
1008                 uart3 {
1009                         uart3_xfer: uart3-xfer {
1010                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1011                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1012                         };
1013
1014                         uart3_cts: uart3-cts {
1015                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1016                         };
1017
1018                         uart3_rts: uart3-rts {
1019                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1020                         };
1021                 };
1022
1023                 uart4 {
1024                         uart4_xfer: uart4-xfer {
1025                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1026                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1027                         };
1028
1029                         uart4_cts: uart4-cts {
1030                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1031                         };
1032
1033                         uart4_rts: uart4-rts {
1034                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1035                         };
1036                 };
1037
1038                 pwm0 {
1039                         pwm0_pin: pwm0-pin {
1040                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1041                         };
1042
1043                         vop_pwm_pin: vop-pwm {
1044                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1045                         };
1046                 };
1047
1048                 pwm1 {
1049                         pwm1_pin: pwm1-pin {
1050                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1051                         };
1052                 };
1053
1054                 pwm3 {
1055                         pwm3_pin: pwm3-pin {
1056                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1057                         };
1058                 };
1059
1060                 lcdc {
1061                         lcdc_lcdc: lcdc-lcdc {
1062                                 rockchip,pins =
1063                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1064                                                 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1065                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1066                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1067                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1068                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1069                                                 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1070                                                 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1071                                                 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1072                                                 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1073                                                 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1074                                                 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1075                                                 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1076                                                 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1077                                                 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1078                                                 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1079                                                 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1080                                                 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1081                         };
1082
1083                         lcdc_gpio: lcdc-gpio {
1084                                 rockchip,pins =
1085                                                 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1086                                                 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1087                                                 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1088                                                 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1089                                                 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1090                                                 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1091                                                 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1092                                                 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1093                                                 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1094                                                 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1095                                                 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1096                                                 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1097                                                 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1098                                                 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1099                                                 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1100                                                 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1101                                                 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1102                                                 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1103                         };
1104                 };
1105         };
1106
1107         fb: fb {
1108                 compatible = "rockchip,rk-fb";
1109                 rockchip,disp-mode = <NO_DUAL>;
1110                 status = "disabled";
1111         };
1112
1113         rk_screen: screen {
1114                 compatible = "rockchip,screen";
1115                 status = "disabled";
1116         };
1117
1118         lcdc: lcdc@ff930000 {
1119                 compatible = "rockchip,rk3368-lcdc";
1120                 rockchip,grf = <&grf>;
1121                 rockchip,pmugrf = <&pmugrf>;
1122                 rockchip,cru = <&cru>;
1123                 rockchip,prop = <PRMRY>;
1124                 rockchip,pwr18 = <0>;
1125                 rockchip,iommu-enabled = <1>;
1126                 reg = <0x0 0xff930000 0x0 0x10000>;
1127                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1128                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1129                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1130                 /*power-domains = <&power PD_VIO>;*/
1131                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1132                 reset-names = "axi", "ahb", "dclk";
1133                 status = "disabled";
1134         };
1135
1136         mipi: mipi@ff960000 {
1137                 compatible = "rockchip,rk3368-dsi";
1138                 rockchip,prop = <0>;
1139                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1140                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1141                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1142                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1143                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1144                 /*power-domains = <&power PD_VIO>;*/
1145                 status = "disabled";
1146         };
1147
1148         lvds: lvds@ff968000 {
1149                 compatible = "rockchip,rk3368-lvds";
1150                 rockchip,grf = <&grf>;
1151                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1152                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1153                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1154                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1155                 /*power-domains = <&power PD_VIO>;*/
1156                 status = "disabled";
1157         };
1158
1159         edp: edp@ff970000 {
1160                 compatible = "rockchip,rk32-edp";
1161                 reg = <0x0 0xff970000 0x0 0x4000>;
1162                 rockchip,grf = <&grf>;
1163                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1164                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1165                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1166                 /*power-domains = <&power PD_VIO>;*/
1167                 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1168                 reset-names = "edp_24m", "edp_apb";
1169                 status = "disabled";
1170         };
1171
1172         iep_mmu: iep-mmu {
1173                 dbgname = "iep";
1174                 compatible = "rockchip,iep_mmu";
1175                 reg = <0x0 0xff900800 0x0 0x100>;
1176                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1177                 interrupt-names = "iep_mmu";
1178                 status = "disabled";
1179         };
1180
1181         vip_mmu: vip-mmu {
1182                 dbgname = "vip";
1183                 compatible = "rockchip,vip_mmu";
1184                 reg = <0x0 0xff950800 0x0 0x100>;
1185                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1186                 interrupt-names = "vip_mmu";
1187                 status = "disabled";
1188         };
1189
1190         vopb_mmu: vopb-mmu {
1191                 dbgname = "vop";
1192                 compatible = "rockchip,vopb_mmu";
1193                 reg = <0x0 0xff930300 0x0 0x100>;
1194                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1195                 interrupt-names = "vop_mmu";
1196                 status = "disabled";
1197         };
1198
1199         isp_mmu: isp-mmu {
1200                 dbgname = "isp_mmu";
1201                 compatible = "rockchip,isp_mmu";
1202                 reg = <0x0 0xff914000 0x0 0x100>,
1203                       <0x0 0xff915000 0x0 0x100>;
1204                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1205                 interrupt-names = "isp_mmu";
1206                 status = "disabled";
1207         };
1208
1209         hdcp_mmu: hdcp-mmu {
1210                  dbgname = "hdcp_mmu";
1211                  compatible = "rockchip,hdcp_mmu";
1212                  reg = <0x0 0xff940000 0x0 0x100>;
1213                  interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1214                  interrupt-names = "hdcp_mmu";
1215                 status = "disabled";
1216         };
1217
1218         hevc_mmu: hevc-mmu {
1219                 dbgname = "hevc";
1220                 compatible = "rockchip,hevc_mmu";
1221                 reg = <0x0 0xff9a0440 0x0 0x40>,
1222                       <0x0 0xff9a0480 0x0 0x40>;
1223                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1224                 interrupt-names = "hevc_mmu";
1225                 status = "disabled";
1226         };
1227
1228         vpu_mmu: vpu-mmu {
1229                 dbgname = "vpu";
1230                 compatible = "rockchip,vpu_mmu";
1231                 reg = <0x0 0xff9a0800 0x0 0x100>;
1232                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1233                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1234                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1235                 status = "disabled";
1236         };
1237 };