2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/display/mipi_dsi.h>
50 #include <dt-bindings/power/rk3368-power.h>
51 #include <dt-bindings/soc/rockchip,boot-mode.h>
52 #include <dt-bindings/thermal/thermal.h>
55 compatible = "rockchip,rk3368";
56 interrupt-parent = <&gic>;
80 #address-cells = <0x2>;
116 entry-method = "psci";
118 cpu_sleep: cpu-sleep-0 {
119 compatible = "arm,idle-state";
120 arm,psci-suspend-param = <0x1010000>;
121 entry-latency-us = <0x3fffffff>;
122 exit-latency-us = <0x40000000>;
123 min-residency-us = <0xffffffff>;
129 compatible = "arm,cortex-a53", "arm,armv8";
131 cpu-idle-states = <&cpu_sleep>;
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster1_opp>;
136 #cooling-cells = <2>; /* min followed by max */
141 compatible = "arm,cortex-a53", "arm,armv8";
143 cpu-idle-states = <&cpu_sleep>;
144 enable-method = "psci";
145 clocks = <&cru ARMCLKL>;
146 operating-points-v2 = <&cluster1_opp>;
151 compatible = "arm,cortex-a53", "arm,armv8";
153 cpu-idle-states = <&cpu_sleep>;
154 enable-method = "psci";
155 clocks = <&cru ARMCLKL>;
156 operating-points-v2 = <&cluster1_opp>;
161 compatible = "arm,cortex-a53", "arm,armv8";
163 cpu-idle-states = <&cpu_sleep>;
164 enable-method = "psci";
165 clocks = <&cru ARMCLKL>;
166 operating-points-v2 = <&cluster1_opp>;
171 compatible = "arm,cortex-a53", "arm,armv8";
173 cpu-idle-states = <&cpu_sleep>;
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 operating-points-v2 = <&cluster0_opp>;
178 #cooling-cells = <2>; /* min followed by max */
183 compatible = "arm,cortex-a53", "arm,armv8";
185 cpu-idle-states = <&cpu_sleep>;
186 enable-method = "psci";
187 clocks = <&cru ARMCLKB>;
188 operating-points-v2 = <&cluster0_opp>;
193 compatible = "arm,cortex-a53", "arm,armv8";
195 cpu-idle-states = <&cpu_sleep>;
196 enable-method = "psci";
197 clocks = <&cru ARMCLKB>;
198 operating-points-v2 = <&cluster0_opp>;
203 compatible = "arm,cortex-a53", "arm,armv8";
205 cpu-idle-states = <&cpu_sleep>;
206 enable-method = "psci";
207 clocks = <&cru ARMCLKB>;
208 operating-points-v2 = <&cluster0_opp>;
212 cluster0_opp: opp_table0 {
213 compatible = "operating-points-v2";
217 opp-hz = /bits/ 64 <408000000>;
218 opp-microvolt = <1200000>;
219 clock-latency-ns = <40000>;
223 opp-hz = /bits/ 64 <600000000>;
224 opp-microvolt = <1200000>;
227 opp-hz = /bits/ 64 <816000000>;
228 opp-microvolt = <1200000>;
231 opp-hz = /bits/ 64 <1008000000>;
232 opp-microvolt = <1200000>;
235 opp-hz = /bits/ 64 <1200000000>;
236 opp-microvolt = <1200000>;
240 cluster1_opp: opp_table1 {
241 compatible = "operating-points-v2";
245 opp-hz = /bits/ 64 <408000000>;
246 opp-microvolt = <1200000>;
247 clock-latency-ns = <40000>;
251 opp-hz = /bits/ 64 <600000000>;
252 opp-microvolt = <1200000>;
255 opp-hz = /bits/ 64 <816000000>;
256 opp-microvolt = <1200000>;
259 opp-hz = /bits/ 64 <1008000000>;
260 opp-microvolt = <1200000>;
265 compatible = "arm,armv8-pmuv3";
266 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
274 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
275 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
276 <&cpu_b2>, <&cpu_b3>;
280 compatible = "arm,amba-bus";
281 #address-cells = <2>;
285 dmac_peri: dma-controller@ff250000 {
286 compatible = "arm,pl330", "arm,primecell";
287 reg = <0x0 0xff250000 0x0 0x4000>;
288 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&cru ACLK_DMAC_PERI>;
292 clock-names = "apb_pclk";
293 arm,pl330-broken-no-flushp;
294 peripherals-req-type-burst;
297 dmac_bus: dma-controller@ff600000 {
298 compatible = "arm,pl330", "arm,primecell";
299 reg = <0x0 0xff600000 0x0 0x4000>;
300 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&cru ACLK_DMAC_BUS>;
304 clock-names = "apb_pclk";
305 arm,pl330-broken-no-flushp;
306 peripherals-req-type-burst;
311 compatible = "arm,psci-0.2";
316 compatible = "arm,armv8-timer";
317 interrupts = <GIC_PPI 13
318 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
320 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
322 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
324 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
328 compatible = "fixed-clock";
329 clock-frequency = <24000000>;
330 clock-output-names = "xin24m";
334 sdmmc: rksdmmc@ff0c0000 {
335 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
336 reg = <0x0 0xff0c0000 0x0 0x4000>;
337 clock-freq-min-max = <400000 150000000>;
338 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
339 clock-names = "biu", "ciu";
340 fifo-depth = <0x100>;
341 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
345 sdio0: dwmmc@ff0d0000 {
346 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
347 reg = <0x0 0xff0d0000 0x0 0x4000>;
348 clock-freq-min-max = <400000 150000000>;
349 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
350 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
351 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
352 fifo-depth = <0x100>;
353 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
357 emmc: rksdmmc@ff0f0000 {
358 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
359 reg = <0x0 0xff0f0000 0x0 0x4000>;
360 clock-freq-min-max = <400000 150000000>;
361 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
362 clock-names = "biu", "ciu";
363 fifo-depth = <0x100>;
364 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
368 saradc: saradc@ff100000 {
369 compatible = "rockchip,saradc";
370 reg = <0x0 0xff100000 0x0 0x100>;
371 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
372 #io-channel-cells = <1>;
373 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
374 clock-names = "saradc", "apb_pclk";
375 resets = <&cru SRST_SARADC>;
376 reset-names = "saradc-apb";
381 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
382 reg = <0x0 0xff110000 0x0 0x1000>;
383 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
384 clock-names = "spiclk", "apb_pclk";
385 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
388 #address-cells = <1>;
394 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
395 reg = <0x0 0xff120000 0x0 0x1000>;
396 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
397 clock-names = "spiclk", "apb_pclk";
398 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
401 #address-cells = <1>;
407 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
408 reg = <0x0 0xff130000 0x0 0x1000>;
409 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
410 clock-names = "spiclk", "apb_pclk";
411 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
414 #address-cells = <1>;
420 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
421 reg = <0x0 0xff650000 0x0 0x1000>;
422 clocks = <&cru PCLK_I2C0>;
424 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&i2c0_xfer>;
427 #address-cells = <1>;
433 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
434 reg = <0x0 0xff140000 0x0 0x1000>;
435 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
436 #address-cells = <1>;
439 clocks = <&cru PCLK_I2C2>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&i2c2_xfer>;
446 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
447 reg = <0x0 0xff150000 0x0 0x1000>;
448 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
449 #address-cells = <1>;
452 clocks = <&cru PCLK_I2C3>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&i2c3_xfer>;
459 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
460 reg = <0x0 0xff160000 0x0 0x1000>;
461 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
462 #address-cells = <1>;
465 clocks = <&cru PCLK_I2C4>;
466 pinctrl-names = "default";
467 pinctrl-0 = <&i2c4_xfer>;
472 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
473 reg = <0x0 0xff170000 0x0 0x1000>;
474 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
475 #address-cells = <1>;
478 clocks = <&cru PCLK_I2C5>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&i2c5_xfer>;
484 uart0: serial@ff180000 {
485 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
486 reg = <0x0 0xff180000 0x0 0x100>;
487 clock-frequency = <24000000>;
488 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
489 clock-names = "baudclk", "apb_pclk";
490 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
496 uart1: serial@ff190000 {
497 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
498 reg = <0x0 0xff190000 0x0 0x100>;
499 clock-frequency = <24000000>;
500 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
501 clock-names = "baudclk", "apb_pclk";
502 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
508 uart3: serial@ff1b0000 {
509 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
510 reg = <0x0 0xff1b0000 0x0 0x100>;
511 clock-frequency = <24000000>;
512 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
513 clock-names = "baudclk", "apb_pclk";
514 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
520 uart4: serial@ff1c0000 {
521 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
522 reg = <0x0 0xff1c0000 0x0 0x100>;
523 clock-frequency = <24000000>;
524 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
525 clock-names = "baudclk", "apb_pclk";
526 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
533 #include "rk3368-thermal.dtsi"
536 tsadc: tsadc@ff280000 {
537 compatible = "rockchip,rk3368-tsadc";
538 reg = <0x0 0xff280000 0x0 0x100>;
539 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
541 clock-names = "tsadc", "apb_pclk";
542 resets = <&cru SRST_TSADC>;
543 reset-names = "tsadc-apb";
544 pinctrl-names = "init", "default", "sleep";
545 pinctrl-0 = <&otp_gpio>;
546 pinctrl-1 = <&otp_out>;
547 pinctrl-2 = <&otp_gpio>;
548 #thermal-sensor-cells = <1>;
549 rockchip,hw-tshut-temp = <95000>;
553 gmac: ethernet@ff290000 {
554 compatible = "rockchip,rk3368-gmac";
555 reg = <0x0 0xff290000 0x0 0x10000>;
556 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-names = "macirq";
558 rockchip,grf = <&grf>;
559 clocks = <&cru SCLK_MAC>,
560 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
561 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
562 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
563 clock-names = "stmmaceth",
564 "mac_clk_rx", "mac_clk_tx",
565 "clk_mac_ref", "clk_mac_refout",
566 "aclk_mac", "pclk_mac";
570 nandc0: nandc@ff400000 {
571 compatible = "rockchip,rk-nandc";
572 reg = <0x0 0xff400000 0x0 0x4000>;
573 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
576 clock-names = "clk_nandc", "hclk_nandc";
580 usb_host0_ehci: usb@ff500000 {
581 compatible = "generic-ehci";
582 reg = <0x0 0xff500000 0x0 0x100>;
583 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cru HCLK_HOST0>;
585 clock-names = "usbhost";
589 usb_otg: usb@ff580000 {
590 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
592 reg = <0x0 0xff580000 0x0 0x40000>;
593 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&cru HCLK_OTG0>;
597 g-np-tx-fifo-size = <16>;
598 g-rx-fifo-size = <275>;
599 g-tx-fifo-size = <256 128 128 64 64 32>;
604 ddrpctl: syscon@ff610000 {
605 compatible = "rockchip,rk3368-ddrpctl", "syscon";
606 reg = <0x0 0xff610000 0x0 0x400>;
610 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
611 reg = <0x0 0xff660000 0x0 0x1000>;
612 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
613 #address-cells = <1>;
616 clocks = <&cru PCLK_I2C1>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&i2c1_xfer>;
623 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
624 reg = <0x0 0xff680000 0x0 0x10>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&pwm0_pin>;
628 clocks = <&cru PCLK_PWM1>;
634 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
635 reg = <0x0 0xff680010 0x0 0x10>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&pwm1_pin>;
639 clocks = <&cru PCLK_PWM1>;
645 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
646 reg = <0x0 0xff680020 0x0 0x10>;
648 clocks = <&cru PCLK_PWM1>;
654 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
655 reg = <0x0 0xff680030 0x0 0x10>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&pwm3_pin>;
659 clocks = <&cru PCLK_PWM1>;
664 uart2: serial@ff690000 {
665 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
666 reg = <0x0 0xff690000 0x0 0x100>;
667 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
668 clock-names = "baudclk", "apb_pclk";
669 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&uart2_xfer>;
677 pmu: power-management@ff730000 {
678 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
679 reg = <0x0 0xff730000 0x0 0x1000>;
681 power: power-controller {
683 compatible = "rockchip,rk3368-power-controller";
684 #power-domain-cells = <1>;
685 #address-cells = <1>;
689 * Note: Although SCLK_* are the working clocks
690 * of device without including on the NOC, needed for
693 * The clocks on the which NOC:
694 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
695 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
696 * ACLK_RGA is on ACLK_RGA_NIU.
697 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
699 * Which clock are device clocks:
701 * *_IEP IEP:Image Enhancement Processor
702 * *_ISP ISP:Image Signal Processing
703 * *_VIP VIP:Video Input Processor
704 * *_VOP* VOP:Visual Output Processor
712 reg = <RK3368_PD_VIO>;
713 clocks = <&cru ACLK_IEP>,
725 <&cru HCLK_VIO_HDCPMMU>,
726 <&cru PCLK_EDP_CTRL>,
727 <&cru PCLK_HDMI_CTRL>,
733 <&cru PCLK_MIPI_CSI>,
734 <&cru PCLK_MIPI_DSI0>,
735 <&cru SCLK_VOP0_PWM>,
741 <&cru SCLK_HDMI_CEC>,
742 <&cru SCLK_HDMI_HDCP>;
745 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
746 * (video endecoder & decoder) clocks that on the
747 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
750 reg = <RK3368_PD_VIDEO>;
751 clocks = <&cru ACLK_VIDEO>,
753 <&cru SCLK_HEVC_CABAC>,
754 <&cru SCLK_HEVC_CORE>;
757 * Note: ACLK_GPU is the GPU clock,
758 * and on the ACLK_GPU_NIU (NOC).
761 reg = <RK3368_PD_GPU_1>;
762 clocks = <&cru ACLK_GPU_CFG>,
764 <&cru SCLK_GPU_CORE>;
769 pmugrf: syscon@ff738000 {
770 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
771 reg = <0x0 0xff738000 0x0 0x1000>;
774 compatible = "syscon-reboot-mode";
776 mode-normal = <BOOT_NORMAL>;
777 mode-recovery = <BOOT_RECOVERY>;
778 mode-bootloader = <BOOT_FASTBOOT>;
779 mode-loader = <BOOT_BL_DOWNLOAD>;
784 cru: clock-controller@ff760000 {
785 compatible = "rockchip,rk3368-cru";
786 reg = <0x0 0xff760000 0x0 0x1000>;
787 rockchip,grf = <&grf>;
791 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
793 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
794 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
795 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
796 assigned-clock-rates =
797 <576000000>, <400000000>,
799 <300000000>, <300000000>,
800 <150000000>, <150000000>,
801 <75000000>, <75000000>;
804 grf: syscon@ff770000 {
805 compatible = "rockchip,rk3368-grf", "syscon";
806 reg = <0x0 0xff770000 0x0 0x1000>;
809 wdt: watchdog@ff800000 {
810 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
811 reg = <0x0 0xff800000 0x0 0x100>;
812 clocks = <&cru PCLK_WDT>;
813 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
817 gic: interrupt-controller@ffb71000 {
818 compatible = "arm,gic-400";
819 interrupt-controller;
820 #interrupt-cells = <3>;
821 #address-cells = <0>;
823 reg = <0x0 0xffb71000 0x0 0x1000>,
824 <0x0 0xffb72000 0x0 0x2000>,
825 <0x0 0xffb74000 0x0 0x2000>,
826 <0x0 0xffb76000 0x0 0x2000>;
827 interrupts = <GIC_PPI 9
828 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
831 gpu: rogue-g6110@ffa30000 {
832 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
833 reg = <0x0 0xffa30000 0x0 0x10000>;
835 <&cru SCLK_GPU_CORE>,
849 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
850 interrupt-names = "rogue-g6110-irq";
853 i2s_2ch: i2s-2ch@ff890000 {
854 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
855 reg = <0x0 0xff890000 0x0 0x1000>;
856 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
857 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
858 dma-names = "tx", "rx";
859 clock-names = "i2s_clk", "i2s_hclk";
860 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
864 i2s_8ch: i2s-8ch@ff898000 {
865 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
866 reg = <0x0 0xff898000 0x0 0x1000>;
867 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
868 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
869 dma-names = "tx", "rx";
870 clock-names = "i2s_clk", "i2s_hclk";
871 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
872 pinctrl-names = "default";
873 pinctrl-0 = <&i2s_8ch_bus>;
878 compatible = "rockchip,rk3368-isp", "rockchip,isp";
879 reg = <0x0 0xff910000 0x0 0x10000>;
880 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
881 /*power-domains = <&power PD_VIO>;*/
883 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
884 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
885 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
886 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
888 "aclk_isp", "hclk_isp", "clk_isp",
889 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
890 "clk_cif_pll", "hclk_mipiphy1",
891 "pclk_dphyrx", "clk_vio0_noc";
893 "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
894 "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
895 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
896 "isp_flash_as_trigger_out";
897 pinctrl-0 = <&cif_clkout>;
898 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
899 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
900 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
901 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
902 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
903 pinctrl-6 = <&cif_clkout>;
904 pinctrl-7 = <&cif_clkout &isp_prelight>;
905 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
906 pinctrl-9 = <&isp_flash_trigger>;
907 rockchip,isp,mipiphy = <2>;
908 rockchip,isp,cifphy = <1>;
909 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
910 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
911 rockchip,grf = <&grf>;
912 rockchip,cru = <&cru>;
913 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
914 rockchip,isp,iommu_enable = <1>;
919 compatible = "rockchip,rga2";
921 reg = <0x0 0xff920000 0x0 0x1000>;
922 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
924 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
929 compatible = "rockchip,rk3368-pinctrl";
930 rockchip,grf = <&grf>;
931 rockchip,pmu = <&pmugrf>;
932 #address-cells = <0x2>;
936 gpio0: gpio0@ff750000 {
937 compatible = "rockchip,gpio-bank";
938 reg = <0x0 0xff750000 0x0 0x100>;
939 clocks = <&cru PCLK_GPIO0>;
940 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
945 interrupt-controller;
946 #interrupt-cells = <0x2>;
949 gpio1: gpio1@ff780000 {
950 compatible = "rockchip,gpio-bank";
951 reg = <0x0 0xff780000 0x0 0x100>;
952 clocks = <&cru PCLK_GPIO1>;
953 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
958 interrupt-controller;
959 #interrupt-cells = <0x2>;
962 gpio2: gpio2@ff790000 {
963 compatible = "rockchip,gpio-bank";
964 reg = <0x0 0xff790000 0x0 0x100>;
965 clocks = <&cru PCLK_GPIO2>;
966 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-controller;
972 #interrupt-cells = <0x2>;
975 gpio3: gpio3@ff7a0000 {
976 compatible = "rockchip,gpio-bank";
977 reg = <0x0 0xff7a0000 0x0 0x100>;
978 clocks = <&cru PCLK_GPIO3>;
979 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
984 interrupt-controller;
985 #interrupt-cells = <0x2>;
988 pcfg_pull_up: pcfg-pull-up {
992 pcfg_pull_down: pcfg-pull-down {
996 pcfg_pull_none: pcfg-pull-none {
1000 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1002 drive-strength = <12>;
1006 emmc_clk: emmc-clk {
1007 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1010 emmc_cmd: emmc-cmd {
1011 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1014 emmc_pwr: emmc-pwr {
1015 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1018 emmc_bus1: emmc-bus1 {
1019 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1022 emmc_bus4: emmc-bus4 {
1023 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1024 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1025 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1026 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1029 emmc_bus8: emmc-bus8 {
1030 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1031 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1032 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1033 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1034 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1035 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1036 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1037 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1042 rgmii_pins: rgmii-pins {
1043 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1044 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1045 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1046 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1047 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1048 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1049 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1050 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1051 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1052 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1053 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1054 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1055 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1056 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1057 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1060 rmii_pins: rmii-pins {
1061 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1062 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1063 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1064 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1065 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1066 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1067 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1068 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1069 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1070 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1075 hdmii2c_xfer: hdmii2c-xfer {
1076 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1077 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1082 hdmi_cec: hdmi-cec {
1083 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1088 i2c0_xfer: i2c0-xfer {
1089 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1090 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1095 i2c1_xfer: i2c1-xfer {
1096 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1097 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1102 i2c2_xfer: i2c2-xfer {
1103 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1104 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1109 i2c3_xfer: i2c3-xfer {
1110 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1111 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1116 i2c4_xfer: i2c4-xfer {
1117 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1118 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1123 i2c5_xfer: i2c5-xfer {
1124 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1125 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1127 i2c5_gpio: i2c5-gpio {
1128 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
1129 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
1134 i2s_8ch_bus: i2s-8ch-bus {
1135 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1136 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1137 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1138 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1139 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1140 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1141 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1142 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1143 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1148 sdio0_bus1: sdio0-bus1 {
1149 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1152 sdio0_bus4: sdio0-bus4 {
1153 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1154 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1155 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1156 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1159 sdio0_cmd: sdio0-cmd {
1160 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1163 sdio0_clk: sdio0-clk {
1164 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1167 sdio0_cd: sdio0-cd {
1168 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1171 sdio0_wp: sdio0-wp {
1172 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1175 sdio0_pwr: sdio0-pwr {
1176 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1179 sdio0_bkpwr: sdio0-bkpwr {
1180 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1183 sdio0_int: sdio0-int {
1184 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1189 sdmmc_clk: sdmmc-clk {
1190 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1193 sdmmc_cmd: sdmmc-cmd {
1194 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1197 sdmmc_cd: sdmcc-cd {
1198 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1201 sdmmc_bus1: sdmmc-bus1 {
1202 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1205 sdmmc_bus4: sdmmc-bus4 {
1206 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1207 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1208 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1209 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1214 spi0_clk: spi0-clk {
1215 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1217 spi0_cs0: spi0-cs0 {
1218 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1220 spi0_cs1: spi0-cs1 {
1221 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1224 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1227 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1232 spi1_clk: spi1-clk {
1233 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1235 spi1_cs0: spi1-cs0 {
1236 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1238 spi1_cs1: spi1-cs1 {
1239 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1242 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1245 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1250 spi2_clk: spi2-clk {
1251 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1253 spi2_cs0: spi2-cs0 {
1254 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1257 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1260 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1265 otp_gpio: otp-gpio {
1266 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1270 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1275 uart0_xfer: uart0-xfer {
1276 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1277 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1280 uart0_cts: uart0-cts {
1281 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1284 uart0_rts: uart0-rts {
1285 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1290 uart1_xfer: uart1-xfer {
1291 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1292 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1295 uart1_cts: uart1-cts {
1296 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1299 uart1_rts: uart1-rts {
1300 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1305 uart2_xfer: uart2-xfer {
1306 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1307 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1309 /* no rts / cts for uart2 */
1313 uart3_xfer: uart3-xfer {
1314 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1315 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1318 uart3_cts: uart3-cts {
1319 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1322 uart3_rts: uart3-rts {
1323 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1328 uart4_xfer: uart4-xfer {
1329 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1330 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1333 uart4_cts: uart4-cts {
1334 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1337 uart4_rts: uart4-rts {
1338 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1343 pwm0_pin: pwm0-pin {
1344 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1347 vop_pwm_pin: vop-pwm {
1348 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1353 pwm1_pin: pwm1-pin {
1354 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1359 pwm3_pin: pwm3-pin {
1360 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1365 lcdc_lcdc: lcdc-lcdc {
1367 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1368 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1369 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1370 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1371 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1372 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1373 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1374 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1375 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1376 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1377 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1378 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1379 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1380 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1381 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1382 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1383 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1384 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1387 lcdc_gpio: lcdc-gpio {
1389 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1390 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1391 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1392 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1393 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1394 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1395 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1396 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1397 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1398 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1399 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1400 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1401 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1402 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1403 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1404 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1405 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1406 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1411 cif_clkout: cif-clkout {
1412 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1415 isp_dvp_d2d9: isp-dvp-d2d9 {
1417 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1418 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1419 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1420 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1421 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1422 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1423 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1424 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1425 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1426 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1427 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1428 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1431 isp_dvp_d0d1: isp-dvp-d0d1 {
1433 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1434 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1437 isp_dvp_d10d11:isp_d10d11 {
1439 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1440 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1443 isp_dvp_d0d7: isp-dvp-d0d7 {
1445 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1446 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1447 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1448 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1449 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1450 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1451 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1452 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1455 isp_dvp_d4d11: isp-dvp-d4d11 {
1457 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1458 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1459 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1460 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1461 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1462 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1463 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1464 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1467 isp_shutter: isp-shutter {
1469 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1470 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1473 isp_flash_trigger: isp-flash-trigger {
1474 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1477 isp_prelight: isp-prelight {
1478 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1481 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1482 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1488 compatible = "rockchip,rk-fb";
1489 rockchip,disp-mode = <NO_DUAL>;
1490 status = "disabled";
1494 compatible = "rockchip,screen";
1495 status = "disabled";
1498 lcdc: lcdc@ff930000 {
1499 compatible = "rockchip,rk3368-lcdc";
1500 rockchip,grf = <&grf>;
1501 rockchip,pmugrf = <&pmugrf>;
1502 rockchip,cru = <&cru>;
1503 rockchip,prop = <PRMRY>;
1504 rockchip,pwr18 = <0>;
1505 rockchip,iommu-enabled = <1>;
1506 reg = <0x0 0xff930000 0x0 0x10000>;
1507 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1508 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1509 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1510 /*power-domains = <&power PD_VIO>;*/
1511 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1512 reset-names = "axi", "ahb", "dclk";
1513 status = "disabled";
1516 mipi: mipi@ff960000 {
1517 compatible = "rockchip,rk3368-dsi";
1518 rockchip,prop = <0>;
1519 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1520 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1521 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1522 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1523 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1524 /*power-domains = <&power PD_VIO>;*/
1525 status = "disabled";
1528 lvds: lvds@ff968000 {
1529 compatible = "rockchip,rk3368-lvds";
1530 rockchip,grf = <&grf>;
1531 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1532 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1533 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1534 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1535 /*power-domains = <&power PD_VIO>;*/
1536 status = "disabled";
1540 compatible = "rockchip,rk32-edp";
1541 reg = <0x0 0xff970000 0x0 0x4000>;
1542 rockchip,grf = <&grf>;
1543 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1544 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1545 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1546 /*power-domains = <&power PD_VIO>;*/
1547 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1548 reset-names = "edp_24m", "edp_apb";
1549 status = "disabled";
1552 hdmi: hdmi@ff980000 {
1553 compatible = "rockchip,rk3368-hdmi";
1554 reg = <0x0 0xff980000 0x0 0x20000>;
1555 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1556 clocks = <&cru PCLK_HDMI_CTRL>,
1557 <&cru SCLK_HDMI_HDCP>,
1558 <&cru SCLK_HDMI_CEC>;
1559 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
1560 /*power-domains = <&power PD_VIO>;*/
1561 resets = <&cru SRST_HDMI>;
1562 reset-names = "hdmi";
1563 pinctrl-names = "default", "gpio";
1564 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1565 pinctrl-1 = <&i2c5_gpio>;
1566 status = "disabled";
1571 compatible = "rockchip,iep_mmu";
1572 reg = <0x0 0xff900800 0x0 0x100>;
1573 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1574 interrupt-names = "iep_mmu";
1575 status = "disabled";
1580 compatible = "rockchip,vip_mmu";
1581 reg = <0x0 0xff950800 0x0 0x100>;
1582 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1583 interrupt-names = "vip_mmu";
1584 status = "disabled";
1587 vopb_mmu: vopb-mmu {
1589 compatible = "rockchip,vopb_mmu";
1590 reg = <0x0 0xff930300 0x0 0x100>;
1591 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1592 interrupt-names = "vop_mmu";
1593 status = "disabled";
1597 dbgname = "isp_mmu";
1598 compatible = "rockchip,isp_mmu";
1599 reg = <0x0 0xff914000 0x0 0x100>,
1600 <0x0 0xff915000 0x0 0x100>;
1601 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1602 interrupt-names = "isp_mmu";
1603 status = "disabled";
1606 hdcp_mmu: hdcp-mmu {
1607 dbgname = "hdcp_mmu";
1608 compatible = "rockchip,hdcp_mmu";
1609 reg = <0x0 0xff940000 0x0 0x100>;
1610 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1611 interrupt-names = "hdcp_mmu";
1612 status = "disabled";
1615 hevc_mmu: hevc-mmu {
1617 compatible = "rockchip,hevc_mmu";
1618 reg = <0x0 0xff9a0440 0x0 0x40>,
1619 <0x0 0xff9a0480 0x0 0x40>;
1620 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1621 interrupt-names = "hevc_mmu";
1622 status = "disabled";
1627 compatible = "rockchip,vpu_mmu";
1628 reg = <0x0 0xff9a0800 0x0 0x100>;
1629 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1630 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1631 interrupt-names = "vepu_mmu", "vdpu_mmu";
1632 status = "disabled";