arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48
  49 / {
  50         compatible = "rockchip,rk3368";
  51         interrupt-parent = <&gic>;
  52         #address-cells = <2>;
  53         #size-cells = <2>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 serial0 = &uart0;
  63                 serial1 = &uart1;
  64                 serial2 = &uart2;
  65                 serial3 = &uart3;
  66                 serial4 = &uart4;
  67                 spi0 = &spi0;
  68                 spi1 = &spi1;
  69                 spi2 = &spi2;
  70         };
  71
  72         cpus {
  73                 #address-cells = <0x2>;
  74                 #size-cells = <0x0>;
  75
  76                 cpu-map {
  77                         cluster0 {
  78                                 core0 {
  79                                         cpu = <&cpu_b0>;
  80                                 };
  81                                 core1 {
  82                                         cpu = <&cpu_b1>;
  83                                 };
  84                                 core2 {
  85                                         cpu = <&cpu_b2>;
  86                                 };
  87                                 core3 {
  88                                         cpu = <&cpu_b3>;
  89                                 };
  90                         };
  91
  92                         cluster1 {
  93                                 core0 {
  94                                         cpu = <&cpu_l0>;
  95                                 };
  96                                 core1 {
  97                                         cpu = <&cpu_l1>;
  98                                 };
  99                                 core2 {
 100                                         cpu = <&cpu_l2>;
 101                                 };
 102                                 core3 {
 103                                         cpu = <&cpu_l3>;
 104                                 };
 105                         };
 106                 };
 107
 108                 idle-states {
 109                         entry-method = "psci";
 110
 111                         cpu_sleep: cpu-sleep-0 {
 112                                 compatible = "arm,idle-state";
 113                                 arm,psci-suspend-param = <0x1010000>;
 114                                 entry-latency-us = <0x3fffffff>;
 115                                 exit-latency-us = <0x40000000>;
 116                                 min-residency-us = <0xffffffff>;
 117                         };
 118                 };
 119
 120                 cpu_l0: cpu@0 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53", "arm,armv8";
 123                         reg = <0x0 0x0>;
 124                         cpu-idle-states = <&cpu_sleep>;
 125                         enable-method = "psci";
 126                 };
 127
 128                 cpu_l1: cpu@1 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x1>;
 132                         cpu-idle-states = <&cpu_sleep>;
 133                         enable-method = "psci";
 134                 };
 135
 136                 cpu_l2: cpu@2 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53", "arm,armv8";
 139                         reg = <0x0 0x2>;
 140                         cpu-idle-states = <&cpu_sleep>;
 141                         enable-method = "psci";
 142                 };
 143
 144                 cpu_l3: cpu@3 {
 145                         device_type = "cpu";
 146                         compatible = "arm,cortex-a53", "arm,armv8";
 147                         reg = <0x0 0x3>;
 148                         cpu-idle-states = <&cpu_sleep>;
 149                         enable-method = "psci";
 150                 };
 151
 152                 cpu_b0: cpu@100 {
 153                         device_type = "cpu";
 154                         compatible = "arm,cortex-a53", "arm,armv8";
 155                         reg = <0x0 0x100>;
 156                         cpu-idle-states = <&cpu_sleep>;
 157                         enable-method = "psci";
 158                 };
 159
 160                 cpu_b1: cpu@101 {
 161                         device_type = "cpu";
 162                         compatible = "arm,cortex-a53", "arm,armv8";
 163                         reg = <0x0 0x101>;
 164                         cpu-idle-states = <&cpu_sleep>;
 165                         enable-method = "psci";
 166                 };
 167
 168                 cpu_b2: cpu@102 {
 169                         device_type = "cpu";
 170                         compatible = "arm,cortex-a53", "arm,armv8";
 171                         reg = <0x0 0x102>;
 172                         cpu-idle-states = <&cpu_sleep>;
 173                         enable-method = "psci";
 174                 };
 175
 176                 cpu_b3: cpu@103 {
 177                         device_type = "cpu";
 178                         compatible = "arm,cortex-a53", "arm,armv8";
 179                         reg = <0x0 0x103>;
 180                         cpu-idle-states = <&cpu_sleep>;
 181                         enable-method = "psci";
 182                 };
 183         };
 184
 185         arm-pmu {
 186                 compatible = "arm,armv8-pmuv3";
 187                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 195                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 196                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 197                                      <&cpu_b2>, <&cpu_b3>;
 198         };
 199
 200         amba {
 201                 compatible = "arm,amba-bus";
 202                 #address-cells = <2>;
 203                 #size-cells = <2>;
 204                 ranges;
 205
 206                 dmac_peri: dma-controller@ff250000 {
 207                         compatible = "arm,pl330", "arm,primecell";
 208                         reg = <0x0 0xff250000 0x0 0x4000>;
 209                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 210                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 211                         #dma-cells = <1>;
 212                         clocks = <&cru ACLK_DMAC_PERI>;
 213                         clock-names = "apb_pclk";
 214                 };
 215
 216                 dmac_bus: dma-controller@ff600000 {
 217                         compatible = "arm,pl330", "arm,primecell";
 218                         reg = <0x0 0xff600000 0x0 0x4000>;
 219                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 220                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 221                         #dma-cells = <1>;
 222                         clocks = <&cru ACLK_DMAC_BUS>;
 223                         clock-names = "apb_pclk";
 224                 };
 225         };
 226
 227         psci {
 228                 compatible = "arm,psci-0.2";
 229                 method = "smc";
 230         };
 231
 232         timer {
 233                 compatible = "arm,armv8-timer";
 234                 interrupts = <GIC_PPI 13
 235                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 236                              <GIC_PPI 14
 237                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 238                              <GIC_PPI 11
 239                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 240                              <GIC_PPI 10
 241                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 242         };
 243
 244         xin24m: oscillator {
 245                 compatible = "fixed-clock";
 246                 clock-frequency = <24000000>;
 247                 clock-output-names = "xin24m";
 248                 #clock-cells = <0>;
 249         };
 250
 251         sdmmc: rksdmmc@ff0c0000 {
 252                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 253                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 254                 clock-freq-min-max = <400000 150000000>;
 255                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 256                 clock-names = "biu", "ciu";
 257                 fifo-depth = <0x100>;
 258                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 259                 status = "disabled";
 260         };
 261
 262         sdio0: dwmmc@ff0d0000 {
 263                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 264                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 265                 clock-freq-min-max = <400000 150000000>;
 266                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 267                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 268                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 269                 fifo-depth = <0x100>;
 270                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 271                 status = "disabled";
 272         };
 273
 274         emmc: rksdmmc@ff0f0000 {
 275                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 276                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 277                 clock-freq-min-max = <400000 150000000>;
 278                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 279                 clock-names = "biu", "ciu";
 280                 fifo-depth = <0x100>;
 281                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 282                 status = "disabled";
 283         };
 284
 285         saradc: saradc@ff100000 {
 286                 compatible = "rockchip,saradc";
 287                 reg = <0x0 0xff100000 0x0 0x100>;
 288                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 289                 #io-channel-cells = <1>;
 290                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 291                 clock-names = "saradc", "apb_pclk";
 292                 status = "disabled";
 293         };
 294
 295         spi0: spi@ff110000 {
 296                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 297                 reg = <0x0 0xff110000 0x0 0x1000>;
 298                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 299                 clock-names = "spiclk", "apb_pclk";
 300                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 301                 pinctrl-names = "default";
 302                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 status = "disabled";
 306         };
 307
 308         spi1: spi@ff120000 {
 309                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 310                 reg = <0x0 0xff120000 0x0 0x1000>;
 311                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 312                 clock-names = "spiclk", "apb_pclk";
 313                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 314                 pinctrl-names = "default";
 315                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 status = "disabled";
 319         };
 320
 321         spi2: spi@ff130000 {
 322                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 323                 reg = <0x0 0xff130000 0x0 0x1000>;
 324                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 325                 clock-names = "spiclk", "apb_pclk";
 326                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331                 status = "disabled";
 332         };
 333
 334         i2c1: i2c@ff140000 {
 335                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 336                 reg = <0x0 0xff140000 0x0 0x1000>;
 337                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 clock-names = "i2c";
 341                 clocks = <&cru PCLK_I2C1>;
 342                 pinctrl-names = "default";
 343                 pinctrl-0 = <&i2c1_xfer>;
 344                 status = "disabled";
 345         };
 346
 347         i2c3: i2c@ff150000 {
 348                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 349                 reg = <0x0 0xff150000 0x0 0x1000>;
 350                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 351                 #address-cells = <1>;
 352                 #size-cells = <0>;
 353                 clock-names = "i2c";
 354                 clocks = <&cru PCLK_I2C3>;
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&i2c3_xfer>;
 357                 status = "disabled";
 358         };
 359
 360         i2c4: i2c@ff160000 {
 361                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 362                 reg = <0x0 0xff160000 0x0 0x1000>;
 363                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 clock-names = "i2c";
 367                 clocks = <&cru PCLK_I2C4>;
 368                 pinctrl-names = "default";
 369                 pinctrl-0 = <&i2c4_xfer>;
 370                 status = "disabled";
 371         };
 372
 373         i2c5: i2c@ff170000 {
 374                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 375                 reg = <0x0 0xff170000 0x0 0x1000>;
 376                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379                 clock-names = "i2c";
 380                 clocks = <&cru PCLK_I2C5>;
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&i2c5_xfer>;
 383                 status = "disabled";
 384         };
 385
 386         uart0: serial@ff180000 {
 387                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 388                 reg = <0x0 0xff180000 0x0 0x100>;
 389                 clock-frequency = <24000000>;
 390                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 391                 clock-names = "baudclk", "apb_pclk";
 392                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 393                 reg-shift = <2>;
 394                 reg-io-width = <4>;
 395                 status = "disabled";
 396         };
 397
 398         uart1: serial@ff190000 {
 399                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 400                 reg = <0x0 0xff190000 0x0 0x100>;
 401                 clock-frequency = <24000000>;
 402                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 403                 clock-names = "baudclk", "apb_pclk";
 404                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 405                 reg-shift = <2>;
 406                 reg-io-width = <4>;
 407                 status = "disabled";
 408         };
 409
 410         uart3: serial@ff1b0000 {
 411                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 412                 reg = <0x0 0xff1b0000 0x0 0x100>;
 413                 clock-frequency = <24000000>;
 414                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 415                 clock-names = "baudclk", "apb_pclk";
 416                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 417                 reg-shift = <2>;
 418                 reg-io-width = <4>;
 419                 status = "disabled";
 420         };
 421
 422         uart4: serial@ff1c0000 {
 423                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 424                 reg = <0x0 0xff1c0000 0x0 0x100>;
 425                 clock-frequency = <24000000>;
 426                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 427                 clock-names = "baudclk", "apb_pclk";
 428                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 429                 reg-shift = <2>;
 430                 reg-io-width = <4>;
 431                 status = "disabled";
 432         };
 433
 434         gmac: ethernet@ff290000 {
 435                 compatible = "rockchip,rk3368-gmac";
 436                 reg = <0x0 0xff290000 0x0 0x10000>;
 437                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 438                 interrupt-names = "macirq";
 439                 rockchip,grf = <&grf>;
 440                 clocks = <&cru SCLK_MAC>,
 441                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 442                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 443                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 444                 clock-names = "stmmaceth",
 445                         "mac_clk_rx", "mac_clk_tx",
 446                         "clk_mac_ref", "clk_mac_refout",
 447                         "aclk_mac", "pclk_mac";
 448                 status = "disabled";
 449         };
 450
 451         usb_host0_ehci: usb@ff500000 {
 452                 compatible = "generic-ehci";
 453                 reg = <0x0 0xff500000 0x0 0x100>;
 454                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 455                 clocks = <&cru HCLK_HOST0>;
 456                 clock-names = "usbhost";
 457                 status = "disabled";
 458         };
 459
 460         usb_otg: usb@ff580000 {
 461                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 462                                 "snps,dwc2";
 463                 reg = <0x0 0xff580000 0x0 0x40000>;
 464                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 465                 clocks = <&cru HCLK_OTG0>;
 466                 clock-names = "otg";
 467                 dr_mode = "otg";
 468                 g-np-tx-fifo-size = <16>;
 469                 g-rx-fifo-size = <275>;
 470                 g-tx-fifo-size = <256 128 128 64 64 32>;
 471                 g-use-dma;
 472                 status = "disabled";
 473         };
 474
 475         ddrpctl: syscon@ff610000 {
 476                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 477                 reg = <0x0 0xff610000 0x0 0x400>;
 478         };
 479
 480         i2c0: i2c@ff650000 {
 481                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 482                 reg = <0x0 0xff650000 0x0 0x1000>;
 483                 clocks = <&cru PCLK_I2C0>;
 484                 clock-names = "i2c";
 485                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&i2c0_xfer>;
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 status = "disabled";
 491         };
 492
 493         i2c2: i2c@ff660000 {
 494                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 495                 reg = <0x0 0xff660000 0x0 0x1000>;
 496                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499                 clock-names = "i2c";
 500                 clocks = <&cru PCLK_I2C2>;
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&i2c2_xfer>;
 503                 status = "disabled";
 504         };
 505
 506         pwm0: pwm@ff680000 {
 507                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 508                 reg = <0x0 0xff680000 0x0 0x10>;
 509                 #pwm-cells = <3>;
 510                 pinctrl-names = "default";
 511                 pinctrl-0 = <&pwm0_pin>;
 512                 clocks = <&cru PCLK_PWM1>;
 513                 clock-names = "pwm";
 514                 status = "disabled";
 515         };
 516
 517         pwm1: pwm@ff680010 {
 518                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 519                 reg = <0x0 0xff680010 0x0 0x10>;
 520                 #pwm-cells = <3>;
 521                 pinctrl-names = "default";
 522                 pinctrl-0 = <&pwm1_pin>;
 523                 clocks = <&cru PCLK_PWM1>;
 524                 clock-names = "pwm";
 525                 status = "disabled";
 526         };
 527
 528         pwm2: pwm@ff680020 {
 529                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 530                 reg = <0x0 0xff680020 0x0 0x10>;
 531                 #pwm-cells = <3>;
 532                 clocks = <&cru PCLK_PWM1>;
 533                 clock-names = "pwm";
 534                 status = "disabled";
 535         };
 536
 537         pwm3: pwm@ff680030 {
 538                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 539                 reg = <0x0 0xff680030 0x0 0x10>;
 540                 #pwm-cells = <3>;
 541                 pinctrl-names = "default";
 542                 pinctrl-0 = <&pwm3_pin>;
 543                 clocks = <&cru PCLK_PWM1>;
 544                 clock-names = "pwm";
 545                 status = "disabled";
 546         };
 547
 548         uart2: serial@ff690000 {
 549                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 550                 reg = <0x0 0xff690000 0x0 0x100>;
 551                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 552                 clock-names = "baudclk", "apb_pclk";
 553                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 554                 pinctrl-names = "default";
 555                 pinctrl-0 = <&uart2_xfer>;
 556                 reg-shift = <2>;
 557                 reg-io-width = <4>;
 558                 status = "disabled";
 559         };
 560
 561         pmu: power-management@ff730000 {
 562                 compatible = "rockchip,rk3368-pmu", "syscon";
 563                 reg = <0x0 0xff730000 0x0 0x1000>;
 564         };
 565
 566         pmugrf: syscon@ff738000 {
 567                 compatible = "rockchip,rk3368-pmugrf", "syscon";
 568                 reg = <0x0 0xff738000 0x0 0x1000>;
 569         };
 570
 571         cru: clock-controller@ff760000 {
 572                 compatible = "rockchip,rk3368-cru";
 573                 reg = <0x0 0xff760000 0x0 0x1000>;
 574                 rockchip,grf = <&grf>;
 575                 #clock-cells = <1>;
 576                 #reset-cells = <1>;
 577         };
 578
 579         grf: syscon@ff770000 {
 580                 compatible = "rockchip,rk3368-grf", "syscon";
 581                 reg = <0x0 0xff770000 0x0 0x1000>;
 582         };
 583
 584         wdt: watchdog@ff800000 {
 585                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 586                 reg = <0x0 0xff800000 0x0 0x100>;
 587                 clocks = <&cru PCLK_WDT>;
 588                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 589                 status = "disabled";
 590         };
 591
 592         gic: interrupt-controller@ffb71000 {
 593                 compatible = "arm,gic-400";
 594                 interrupt-controller;
 595                 #interrupt-cells = <3>;
 596                 #address-cells = <0>;
 597
 598                 reg = <0x0 0xffb71000 0x0 0x1000>,
 599                       <0x0 0xffb72000 0x0 0x1000>,
 600                       <0x0 0xffb74000 0x0 0x2000>,
 601                       <0x0 0xffb76000 0x0 0x2000>;
 602                 interrupts = <GIC_PPI 9
 603                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 604         };
 605
 606         i2s_2ch: i2s-2ch@ff890000 {
 607                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 608                 reg = <0x0 0xff898000 0x0 0x1000>;
 609                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 610                 #address-cells = <2>;
 611                 #size-cells = <0>;
 612                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 613                 dma-names = "tx", "rx";
 614                 clock-names = "i2s_hclk", "i2s_clk";
 615                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 616                 status = "disabled";
 617         };
 618
 619         i2s_8ch: i2s-8ch@ff898000 {
 620                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 621                 reg = <0x0 0xff898000 0x0 0x1000>;
 622                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 623                 #address-cells = <1>;
 624                 #size-cells = <0>;
 625                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 626                 dma-names = "tx", "rx";
 627                 clock-names = "i2s_hclk", "i2s_clk";
 628                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 629                 pinctrl-names = "default";
 630                 pinctrl-0 = <&i2s_8ch_bus>;
 631                 status = "disabled";
 632         };
 633
 634         pinctrl: pinctrl {
 635                 compatible = "rockchip,rk3368-pinctrl";
 636                 rockchip,grf = <&grf>;
 637                 rockchip,pmu = <&pmugrf>;
 638                 #address-cells = <0x2>;
 639                 #size-cells = <0x2>;
 640                 ranges;
 641
 642                 gpio0: gpio0@ff750000 {
 643                         compatible = "rockchip,gpio-bank";
 644                         reg = <0x0 0xff750000 0x0 0x100>;
 645                         clocks = <&cru PCLK_GPIO0>;
 646                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 647
 648                         gpio-controller;
 649                         #gpio-cells = <0x2>;
 650
 651                         interrupt-controller;
 652                         #interrupt-cells = <0x2>;
 653                 };
 654
 655                 gpio1: gpio1@ff780000 {
 656                         compatible = "rockchip,gpio-bank";
 657                         reg = <0x0 0xff780000 0x0 0x100>;
 658                         clocks = <&cru PCLK_GPIO1>;
 659                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 660
 661                         gpio-controller;
 662                         #gpio-cells = <0x2>;
 663
 664                         interrupt-controller;
 665                         #interrupt-cells = <0x2>;
 666                 };
 667
 668                 gpio2: gpio2@ff790000 {
 669                         compatible = "rockchip,gpio-bank";
 670                         reg = <0x0 0xff790000 0x0 0x100>;
 671                         clocks = <&cru PCLK_GPIO2>;
 672                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
 673
 674                         gpio-controller;
 675                         #gpio-cells = <0x2>;
 676
 677                         interrupt-controller;
 678                         #interrupt-cells = <0x2>;
 679                 };
 680
 681                 gpio3: gpio3@ff7a0000 {
 682                         compatible = "rockchip,gpio-bank";
 683                         reg = <0x0 0xff7a0000 0x0 0x100>;
 684                         clocks = <&cru PCLK_GPIO3>;
 685                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
 686
 687                         gpio-controller;
 688                         #gpio-cells = <0x2>;
 689
 690                         interrupt-controller;
 691                         #interrupt-cells = <0x2>;
 692                 };
 693
 694                 pcfg_pull_up: pcfg-pull-up {
 695                         bias-pull-up;
 696                 };
 697
 698                 pcfg_pull_down: pcfg-pull-down {
 699                         bias-pull-down;
 700                 };
 701
 702                 pcfg_pull_none: pcfg-pull-none {
 703                         bias-disable;
 704                 };
 705
 706                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 707                         bias-disable;
 708                         drive-strength = <12>;
 709                 };
 710
 711                 emmc {
 712                         emmc_clk: emmc-clk {
 713                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 714                         };
 715
 716                         emmc_cmd: emmc-cmd {
 717                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
 718                         };
 719
 720                         emmc_pwr: emmc-pwr {
 721                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
 722                         };
 723
 724                         emmc_bus1: emmc-bus1 {
 725                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
 726                         };
 727
 728                         emmc_bus4: emmc-bus4 {
 729                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 730                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 731                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 732                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
 733                         };
 734
 735                         emmc_bus8: emmc-bus8 {
 736                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 737                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 738                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 739                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
 740                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
 741                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
 742                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
 743                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
 744                         };
 745                 };
 746
 747                 gmac {
 748                         rgmii_pins: rgmii-pins {
 749                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 750                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 751                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 752                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 753                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 754                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
 755                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
 756                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
 757                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 758                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 759                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 760                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
 761                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
 762                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
 763                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
 764                         };
 765
 766                         rmii_pins: rmii-pins {
 767                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 768                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 769                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 770                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 771                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 772                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 773                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 774                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 775                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
 776                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
 777                         };
 778                 };
 779
 780                 i2c0 {
 781                         i2c0_xfer: i2c0-xfer {
 782                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 783                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 784                         };
 785                 };
 786
 787                 i2c1 {
 788                         i2c1_xfer: i2c1-xfer {
 789                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
 790                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
 791                         };
 792                 };
 793
 794                 i2c2 {
 795                         i2c2_xfer: i2c2-xfer {
 796                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
 797                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
 798                         };
 799                 };
 800
 801                 i2c3 {
 802                         i2c3_xfer: i2c3-xfer {
 803                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
 804                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
 805                         };
 806                 };
 807
 808                 i2c4 {
 809                         i2c4_xfer: i2c4-xfer {
 810                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
 811                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
 812                         };
 813                 };
 814
 815                 i2c5 {
 816                         i2c5_xfer: i2c5-xfer {
 817                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
 818                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
 819                         };
 820                 };
 821
 822                 i2s {
 823                         i2s_8ch_bus: i2s-8ch-bus {
 824                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
 825                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
 826                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
 827                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
 828                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
 829                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
 830                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
 831                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
 832                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
 833                         };
 834                 };
 835
 836                 sdio0 {
 837                         sdio0_bus1: sdio0-bus1 {
 838                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
 839                         };
 840
 841                         sdio0_bus4: sdio0-bus4 {
 842                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
 843                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
 844                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
 845                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
 846                         };
 847
 848                         sdio0_cmd: sdio0-cmd {
 849                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
 850                         };
 851
 852                         sdio0_clk: sdio0-clk {
 853                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
 854                         };
 855
 856                         sdio0_cd: sdio0-cd {
 857                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
 858                         };
 859
 860                         sdio0_wp: sdio0-wp {
 861                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
 862                         };
 863
 864                         sdio0_pwr: sdio0-pwr {
 865                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
 866                         };
 867
 868                         sdio0_bkpwr: sdio0-bkpwr {
 869                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
 870                         };
 871
 872                         sdio0_int: sdio0-int {
 873                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
 874                         };
 875                 };
 876
 877                 sdmmc {
 878                         sdmmc_clk: sdmmc-clk {
 879                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
 880                         };
 881
 882                         sdmmc_cmd: sdmmc-cmd {
 883                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
 884                         };
 885
 886                         sdmmc_cd: sdmcc-cd {
 887                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
 888                         };
 889
 890                         sdmmc_bus1: sdmmc-bus1 {
 891                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
 892                         };
 893
 894                         sdmmc_bus4: sdmmc-bus4 {
 895                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
 896                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
 897                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
 898                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
 899                         };
 900                 };
 901
 902                 spi0 {
 903                         spi0_clk: spi0-clk {
 904                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
 905                         };
 906                         spi0_cs0: spi0-cs0 {
 907                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
 908                         };
 909                         spi0_cs1: spi0-cs1 {
 910                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
 911                         };
 912                         spi0_tx: spi0-tx {
 913                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
 914                         };
 915                         spi0_rx: spi0-rx {
 916                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
 917                         };
 918                 };
 919
 920                 spi1 {
 921                         spi1_clk: spi1-clk {
 922                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
 923                         };
 924                         spi1_cs0: spi1-cs0 {
 925                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
 926                         };
 927                         spi1_cs1: spi1-cs1 {
 928                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
 929                         };
 930                         spi1_rx: spi1-rx {
 931                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
 932                         };
 933                         spi1_tx: spi1-tx {
 934                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
 935                         };
 936                 };
 937
 938                 spi2 {
 939                         spi2_clk: spi2-clk {
 940                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
 941                         };
 942                         spi2_cs0: spi2-cs0 {
 943                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
 944                         };
 945                         spi2_rx: spi2-rx {
 946                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
 947                         };
 948                         spi2_tx: spi2-tx {
 949                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
 950                         };
 951                 };
 952
 953                 uart0 {
 954                         uart0_xfer: uart0-xfer {
 955                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
 956                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
 957                         };
 958
 959                         uart0_cts: uart0-cts {
 960                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
 961                         };
 962
 963                         uart0_rts: uart0-rts {
 964                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
 965                         };
 966                 };
 967
 968                 uart1 {
 969                         uart1_xfer: uart1-xfer {
 970                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
 971                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
 972                         };
 973
 974                         uart1_cts: uart1-cts {
 975                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
 976                         };
 977
 978                         uart1_rts: uart1-rts {
 979                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
 980                         };
 981                 };
 982
 983                 uart2 {
 984                         uart2_xfer: uart2-xfer {
 985                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
 986                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
 987                         };
 988                         /* no rts / cts for uart2 */
 989                 };
 990
 991                 uart3 {
 992                         uart3_xfer: uart3-xfer {
 993                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
 994                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
 995                         };
 996
 997                         uart3_cts: uart3-cts {
 998                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
 999                         };
1000
1001                         uart3_rts: uart3-rts {
1002                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1003                         };
1004                 };
1005
1006                 uart4 {
1007                         uart4_xfer: uart4-xfer {
1008                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1009                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1010                         };
1011
1012                         uart4_cts: uart4-cts {
1013                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1014                         };
1015
1016                         uart4_rts: uart4-rts {
1017                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1018                         };
1019                 };
1020
1021                 pwm0 {
1022                         pwm0_pin: pwm0-pin {
1023                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1024                         };
1025
1026                         vop_pwm_pin: vop-pwm {
1027                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1028                         };
1029                 };
1030
1031                 pwm1 {
1032                         pwm1_pin: pwm1-pin {
1033                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1034                         };
1035                 };
1036
1037                 pwm3 {
1038                         pwm3_pin: pwm3-pin {
1039                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1040                         };
1041                 };
1042         };
1043
1044         iep_mmu {
1045                 dbgname = "iep";
1046                 compatible = "rockchip,iep_mmu";
1047                 reg = <0x0 0xff900800 0x0 0x100>;
1048                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1049                 interrupt-names = "iep_mmu";
1050         };
1051
1052         vip_mmu {
1053                 dbgname = "vip";
1054                 compatible = "rockchip,vip_mmu";
1055                 reg = <0x0 0xff950800 0x0 0x100>;
1056                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1057                 interrupt-names = "vip_mmu";
1058         };
1059
1060         vop_mmu {
1061                 dbgname = "vop";
1062                 compatible = "rockchip,vopb_mmu";
1063                 reg = <0x0 0xff930300 0x0 0x100>;
1064                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1065                 interrupt-names = "vop_mmu";
1066         };
1067
1068         isp_mmu {
1069                 dbgname = "isp_mmu";
1070                 compatible = "rockchip,isp_mmu";
1071                 reg = <0x0 0xff914000 0x0 0x100>,
1072                       <0x0 0xff915000 0x0 0x100>;
1073                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1074                 interrupt-names = "isp_mmu";
1075         };
1076
1077         hdcp_mmu {
1078                  dbgname = "hdcp_mmu";
1079                  compatible = "rockchip,hdcp_mmu";
1080                  reg = <0x0 0xff940000 0x0 0x100>;
1081                  interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1082                  interrupt-names = "hdcp_mmu";
1083         };
1084
1085         hevc_mmu {
1086                 dbgname = "hevc";
1087                 compatible = "rockchip,hevc_mmu";
1088                 reg = <0x0 0xff9a0440 0x0 0x40>,
1089                       <0x0 0xff9a0480 0x0 0x40>;
1090                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1091                 interrupt-names = "hevc_mmu";
1092         };
1093
1094         vpu_mmu {
1095                 dbgname = "vpu";
1096                 compatible = "rockchip,vpu_mmu";
1097                 reg = <0x0 0xff9a0800 0x0 0x100>;
1098                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1099                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1100                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1101         };
1102 };