arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3368";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 ethernet0 = &gmac;
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74         };
  75
  76         cpus {
  77                 #address-cells = <0x2>;
  78                 #size-cells = <0x0>;
  79
  80                 cpu-map {
  81                         cluster0 {
  82                                 core0 {
  83                                         cpu = <&cpu_l0>;
  84                                 };
  85                                 core1 {
  86                                         cpu = <&cpu_l1>;
  87                                 };
  88                                 core2 {
  89                                         cpu = <&cpu_l2>;
  90                                 };
  91                                 core3 {
  92                                         cpu = <&cpu_l3>;
  93                                 };
  94                         };
  95
  96                         cluster1 {
  97                                 core0 {
  98                                         cpu = <&cpu_b0>;
  99                                 };
 100                                 core1 {
 101                                         cpu = <&cpu_b1>;
 102                                 };
 103                                 core2 {
 104                                         cpu = <&cpu_b2>;
 105                                 };
 106                                 core3 {
 107                                         cpu = <&cpu_b3>;
 108                                 };
 109                         };
 110                 };
 111
 112                 idle-states {
 113                         entry-method = "psci";
 114
 115                         cpu_sleep: cpu-sleep-0 {
 116                                 compatible = "arm,idle-state";
 117                                 arm,psci-suspend-param = <0x1010000>;
 118                                 entry-latency-us = <0x3fffffff>;
 119                                 exit-latency-us = <0x40000000>;
 120                                 min-residency-us = <0xffffffff>;
 121                         };
 122                 };
 123
 124                 cpu_l0: cpu@0 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x0>;
 128                         cpu-idle-states = <&cpu_sleep>;
 129                         enable-method = "psci";
 130                         clocks = <&cru ARMCLKL>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132
 133                         #cooling-cells = <2>; /* min followed by max */
 134                 };
 135
 136                 cpu_l1: cpu@1 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53", "arm,armv8";
 139                         reg = <0x0 0x1>;
 140                         cpu-idle-states = <&cpu_sleep>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu_l2: cpu@2 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x2>;
 150                         cpu-idle-states = <&cpu_sleep>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKL>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                 };
 155
 156                 cpu_l3: cpu@3 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a53", "arm,armv8";
 159                         reg = <0x0 0x3>;
 160                         cpu-idle-states = <&cpu_sleep>;
 161                         enable-method = "psci";
 162                         clocks = <&cru ARMCLKL>;
 163                         operating-points-v2 = <&cluster0_opp>;
 164                 };
 165
 166                 cpu_b0: cpu@100 {
 167                         device_type = "cpu";
 168                         compatible = "arm,cortex-a53", "arm,armv8";
 169                         reg = <0x0 0x100>;
 170                         cpu-idle-states = <&cpu_sleep>;
 171                         enable-method = "psci";
 172                         clocks = <&cru ARMCLKB>;
 173                         operating-points-v2 = <&cluster1_opp>;
 174
 175                         #cooling-cells = <2>; /* min followed by max */
 176                 };
 177
 178                 cpu_b1: cpu@101 {
 179                         device_type = "cpu";
 180                         compatible = "arm,cortex-a53", "arm,armv8";
 181                         reg = <0x0 0x101>;
 182                         cpu-idle-states = <&cpu_sleep>;
 183                         enable-method = "psci";
 184                         clocks = <&cru ARMCLKB>;
 185                         operating-points-v2 = <&cluster1_opp>;
 186                 };
 187
 188                 cpu_b2: cpu@102 {
 189                         device_type = "cpu";
 190                         compatible = "arm,cortex-a53", "arm,armv8";
 191                         reg = <0x0 0x102>;
 192                         cpu-idle-states = <&cpu_sleep>;
 193                         enable-method = "psci";
 194                         clocks = <&cru ARMCLKB>;
 195                         operating-points-v2 = <&cluster1_opp>;
 196                 };
 197
 198                 cpu_b3: cpu@103 {
 199                         device_type = "cpu";
 200                         compatible = "arm,cortex-a53", "arm,armv8";
 201                         reg = <0x0 0x103>;
 202                         cpu-idle-states = <&cpu_sleep>;
 203                         enable-method = "psci";
 204                         clocks = <&cru ARMCLKB>;
 205                         operating-points-v2 = <&cluster1_opp>;
 206                 };
 207         };
 208
 209         cluster0_opp: opp_table0 {
 210                 compatible = "operating-points-v2";
 211                 opp-shared;
 212
 213                 opp@216000000 {
 214                         opp-hz = /bits/ 64 <216000000>;
 215                         opp-microvolt = <950000 950000 1350000>;
 216                         clock-latency-ns = <40000>;
 217                         opp-suspend;
 218                 };
 219                 opp@408000000 {
 220                         opp-hz = /bits/ 64 <408000000>;
 221                         opp-microvolt = <950000 950000 1350000>;
 222                         clock-latency-ns = <40000>;
 223                 };
 224                 opp@600000000 {
 225                         opp-hz = /bits/ 64 <600000000>;
 226                         opp-microvolt = <950000 950000 1350000>;
 227                         clock-latency-ns = <40000>;
 228                 };
 229                 opp@816000000 {
 230                         opp-hz = /bits/ 64 <816000000>;
 231                         opp-microvolt = <1025000 1025000 1350000>;
 232                         clock-latency-ns = <40000>;
 233                 };
 234                 opp@1008000000 {
 235                         opp-hz = /bits/ 64 <1008000000>;
 236                         opp-microvolt = <1125000 1125000 1350000>;
 237                         clock-latency-ns = <40000>;
 238                 };
 239                 opp@1200000000 {
 240                         opp-hz = /bits/ 64 <1200000000>;
 241                         opp-microvolt = <1225000 1225000 1350000>;
 242                         clock-latency-ns = <40000>;
 243                 };
 244         };
 245
 246         cluster1_opp: opp_table1 {
 247                 compatible = "operating-points-v2";
 248                 opp-shared;
 249
 250                 opp@216000000 {
 251                         opp-hz = /bits/ 64 <216000000>;
 252                         opp-microvolt = <950000 950000 1350000>;
 253                         clock-latency-ns = <40000>;
 254                         opp-suspend;
 255                 };
 256                 opp@408000000 {
 257                         opp-hz = /bits/ 64 <408000000>;
 258                         opp-microvolt = <950000 950000 1350000>;
 259                         clock-latency-ns = <40000>;
 260                 };
 261                 opp@600000000 {
 262                         opp-hz = /bits/ 64 <600000000>;
 263                         opp-microvolt = <950000 950000 1350000>;
 264                         clock-latency-ns = <40000>;
 265                 };
 266                 opp@816000000 {
 267                         opp-hz = /bits/ 64 <816000000>;
 268                         opp-microvolt = <975000 975000 1350000>;
 269                         clock-latency-ns = <40000>;
 270                 };
 271                 opp@1008000000 {
 272                         opp-hz = /bits/ 64 <1008000000>;
 273                         opp-microvolt = <1050000 1050000 1350000>;
 274                         clock-latency-ns = <40000>;
 275                 };
 276                 opp@1200000000 {
 277                         opp-hz = /bits/ 64 <1200000000>;
 278                         opp-microvolt = <1150000 1150000 1350000>;
 279                         clock-latency-ns = <40000>;
 280                 };
 281                 opp@1296000000 {
 282                         opp-hz = /bits/ 64 <1296000000>;
 283                         opp-microvolt = <1225000 1225000 1350000>;
 284                         clock-latency-ns = <40000>;
 285                 };
 286                 opp@1416000000 {
 287                         opp-hz = /bits/ 64 <1416000000>;
 288                         opp-microvolt = <1300000 1300000 1350000>;
 289                         clock-latency-ns = <40000>;
 290                 };
 291                 opp@1512000000 {
 292                         opp-hz = /bits/ 64 <1512000000>;
 293                         opp-microvolt = <1350000 1350000 1350000>;
 294                         clock-latency-ns = <40000>;
 295                 };
 296         };
 297
 298         cpu_avs: cpu-avs {
 299                 cluster0-avs {
 300                         cluster-id = <0>;
 301                         min-volt = <950000>; /* uV */
 302                         min-freq = <216000>; /* KHz */
 303                         leakage-adjust-volt = <
 304                         /*  mA        mA         uV */
 305                             0         254        0
 306                         >;
 307                         nvmem-cells = <&cpu_leakage>;
 308                         nvmem-cell-names = "cpu_leakage";
 309                 };
 310                 cluster1-avs {
 311                         cluster-id = <1>;
 312                         min-volt = <950000>; /* uV */
 313                         min-freq = <216000>; /* KHz */
 314                         leakage-adjust-volt = <
 315                         /*  mA        mA         uV */
 316                             0         254        0
 317                         >;
 318                         nvmem-cells = <&cpu_leakage>;
 319                         nvmem-cell-names = "cpu_leakage";
 320                 };
 321         };
 322
 323         arm-pmu {
 324                 compatible = "arm,armv8-pmuv3";
 325                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 326                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 327                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 328                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 329                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 330                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 331                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 332                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 333                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 334                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 335                                      <&cpu_b2>, <&cpu_b3>;
 336         };
 337
 338         amba {
 339                 compatible = "arm,amba-bus";
 340                 #address-cells = <2>;
 341                 #size-cells = <2>;
 342                 ranges;
 343
 344                 dmac_peri: dma-controller@ff250000 {
 345                         compatible = "arm,pl330", "arm,primecell";
 346                         reg = <0x0 0xff250000 0x0 0x4000>;
 347                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 348                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 349                         #dma-cells = <1>;
 350                         clocks = <&cru ACLK_DMAC_PERI>;
 351                         clock-names = "apb_pclk";
 352                         arm,pl330-broken-no-flushp;
 353                         peripherals-req-type-burst;
 354                 };
 355
 356                 dmac_bus: dma-controller@ff600000 {
 357                         compatible = "arm,pl330", "arm,primecell";
 358                         reg = <0x0 0xff600000 0x0 0x4000>;
 359                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 360                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 361                         #dma-cells = <1>;
 362                         clocks = <&cru ACLK_DMAC_BUS>;
 363                         clock-names = "apb_pclk";
 364                         arm,pl330-broken-no-flushp;
 365                         peripherals-req-type-burst;
 366                 };
 367         };
 368
 369         psci {
 370                 compatible = "arm,psci-0.2";
 371                 method = "smc";
 372         };
 373
 374         timer {
 375                 compatible = "arm,armv8-timer";
 376                 interrupts = <GIC_PPI 13
 377                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 378                              <GIC_PPI 14
 379                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 380                              <GIC_PPI 11
 381                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 382                              <GIC_PPI 10
 383                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 384         };
 385
 386         xin24m: oscillator {
 387                 compatible = "fixed-clock";
 388                 clock-frequency = <24000000>;
 389                 clock-output-names = "xin24m";
 390                 #clock-cells = <0>;
 391         };
 392
 393         sdmmc: rksdmmc@ff0c0000 {
 394                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 395                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 396                 clock-freq-min-max = <400000 150000000>;
 397                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 398                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 399                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 400                 fifo-depth = <0x100>;
 401                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 402                 status = "disabled";
 403         };
 404
 405         sdio0: dwmmc@ff0d0000 {
 406                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 407                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 408                 clock-freq-min-max = <400000 150000000>;
 409                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 410                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 411                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 412                 fifo-depth = <0x100>;
 413                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 414                 status = "disabled";
 415         };
 416
 417         emmc: rksdmmc@ff0f0000 {
 418                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 419                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 420                 clock-freq-min-max = <400000 150000000>;
 421                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 422                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 423                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 424                 fifo-depth = <0x100>;
 425                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 426                 status = "disabled";
 427         };
 428
 429         saradc: saradc@ff100000 {
 430                 compatible = "rockchip,saradc";
 431                 reg = <0x0 0xff100000 0x0 0x100>;
 432                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 433                 #io-channel-cells = <1>;
 434                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 435                 clock-names = "saradc", "apb_pclk";
 436                 resets = <&cru SRST_SARADC>;
 437                 reset-names = "saradc-apb";
 438                 status = "disabled";
 439         };
 440
 441         spi0: spi@ff110000 {
 442                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 443                 reg = <0x0 0xff110000 0x0 0x1000>;
 444                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 445                 clock-names = "spiclk", "apb_pclk";
 446                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 status = "disabled";
 452         };
 453
 454         spi1: spi@ff120000 {
 455                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 456                 reg = <0x0 0xff120000 0x0 0x1000>;
 457                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 458                 clock-names = "spiclk", "apb_pclk";
 459                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 status = "disabled";
 465         };
 466
 467         spi2: spi@ff130000 {
 468                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 469                 reg = <0x0 0xff130000 0x0 0x1000>;
 470                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 471                 clock-names = "spiclk", "apb_pclk";
 472                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 status = "disabled";
 478         };
 479
 480         i2c0: i2c@ff650000 {
 481                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 482                 reg = <0x0 0xff650000 0x0 0x1000>;
 483                 clocks = <&cru PCLK_I2C0>;
 484                 clock-names = "i2c";
 485                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&i2c0_xfer>;
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 status = "disabled";
 491         };
 492
 493         i2c2: i2c@ff140000 {
 494                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 495                 reg = <0x0 0xff140000 0x0 0x1000>;
 496                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499                 clock-names = "i2c";
 500                 clocks = <&cru PCLK_I2C2>;
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&i2c2_xfer>;
 503                 status = "disabled";
 504         };
 505
 506         i2c3: i2c@ff150000 {
 507                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 508                 reg = <0x0 0xff150000 0x0 0x1000>;
 509                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 510                 #address-cells = <1>;
 511                 #size-cells = <0>;
 512                 clock-names = "i2c";
 513                 clocks = <&cru PCLK_I2C3>;
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&i2c3_xfer>;
 516                 status = "disabled";
 517         };
 518
 519         i2c4: i2c@ff160000 {
 520                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 521                 reg = <0x0 0xff160000 0x0 0x1000>;
 522                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 523                 #address-cells = <1>;
 524                 #size-cells = <0>;
 525                 clock-names = "i2c";
 526                 clocks = <&cru PCLK_I2C4>;
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&i2c4_xfer>;
 529                 status = "disabled";
 530         };
 531
 532         i2c5: i2c@ff170000 {
 533                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 534                 reg = <0x0 0xff170000 0x0 0x1000>;
 535                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 536                 #address-cells = <1>;
 537                 #size-cells = <0>;
 538                 clock-names = "i2c";
 539                 clocks = <&cru PCLK_I2C5>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&i2c5_xfer>;
 542                 status = "disabled";
 543         };
 544
 545         uart0: serial@ff180000 {
 546                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 547                 reg = <0x0 0xff180000 0x0 0x100>;
 548                 clock-frequency = <24000000>;
 549                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 550                 clock-names = "baudclk", "apb_pclk";
 551                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 552                 reg-shift = <2>;
 553                 reg-io-width = <4>;
 554                 status = "disabled";
 555         };
 556
 557         uart1: serial@ff190000 {
 558                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 559                 reg = <0x0 0xff190000 0x0 0x100>;
 560                 clock-frequency = <24000000>;
 561                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 562                 clock-names = "baudclk", "apb_pclk";
 563                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 564                 reg-shift = <2>;
 565                 reg-io-width = <4>;
 566                 status = "disabled";
 567         };
 568
 569         uart3: serial@ff1b0000 {
 570                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 571                 reg = <0x0 0xff1b0000 0x0 0x100>;
 572                 clock-frequency = <24000000>;
 573                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 574                 clock-names = "baudclk", "apb_pclk";
 575                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 576                 reg-shift = <2>;
 577                 reg-io-width = <4>;
 578                 status = "disabled";
 579         };
 580
 581         uart4: serial@ff1c0000 {
 582                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 583                 reg = <0x0 0xff1c0000 0x0 0x100>;
 584                 clock-frequency = <24000000>;
 585                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 586                 clock-names = "baudclk", "apb_pclk";
 587                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 588                 reg-shift = <2>;
 589                 reg-io-width = <4>;
 590                 status = "disabled";
 591         };
 592
 593         thermal-zones {
 594                 cpu {
 595                         polling-delay-passive = <100>; /* milliseconds */
 596                         polling-delay = <5000>; /* milliseconds */
 597
 598                         thermal-sensors = <&tsadc 0>;
 599
 600                         trips {
 601                                 cpu_alert0: cpu_alert0 {
 602                                         temperature = <75000>; /* millicelsius */
 603                                         hysteresis = <2000>; /* millicelsius */
 604                                         type = "passive";
 605                                 };
 606                                 cpu_alert1: cpu_alert1 {
 607                                         temperature = <80000>; /* millicelsius */
 608                                         hysteresis = <2000>; /* millicelsius */
 609                                         type = "passive";
 610                                 };
 611                                 cpu_crit: cpu_crit {
 612                                         temperature = <95000>; /* millicelsius */
 613                                         hysteresis = <2000>; /* millicelsius */
 614                                         type = "critical";
 615                                 };
 616                         };
 617
 618                         cooling-maps {
 619                                 map0 {
 620                                         trip = <&cpu_alert0>;
 621                                         cooling-device =
 622                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 623                                 };
 624                                 map1 {
 625                                         trip = <&cpu_alert1>;
 626                                         cooling-device =
 627                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 628                                 };
 629                         };
 630                 };
 631
 632                 gpu {
 633                         polling-delay-passive = <100>; /* milliseconds */
 634                         polling-delay = <5000>; /* milliseconds */
 635
 636                         thermal-sensors = <&tsadc 1>;
 637
 638                         trips {
 639                                 gpu_alert0: gpu_alert0 {
 640                                         temperature = <80000>; /* millicelsius */
 641                                         hysteresis = <2000>; /* millicelsius */
 642                                         type = "passive";
 643                                 };
 644                                 gpu_crit: gpu_crit {
 645                                         temperature = <115000>; /* millicelsius */
 646                                         hysteresis = <2000>; /* millicelsius */
 647                                         type = "critical";
 648                                 };
 649                         };
 650
 651                         cooling-maps {
 652                                 map0 {
 653                                         trip = <&gpu_alert0>;
 654                                         cooling-device =
 655                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 656                                 };
 657                         };
 658                 };
 659         };
 660
 661         tsadc: tsadc@ff280000 {
 662                 compatible = "rockchip,rk3368-tsadc";
 663                 reg = <0x0 0xff280000 0x0 0x100>;
 664                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 665                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 666                 clock-names = "tsadc", "apb_pclk";
 667                 resets = <&cru SRST_TSADC>;
 668                 reset-names = "tsadc-apb";
 669                 pinctrl-names = "init", "default", "sleep";
 670                 pinctrl-0 = <&otp_gpio>;
 671                 pinctrl-1 = <&otp_out>;
 672                 pinctrl-2 = <&otp_gpio>;
 673                 #thermal-sensor-cells = <1>;
 674                 rockchip,hw-tshut-temp = <95000>;
 675                 status = "disabled";
 676         };
 677
 678         gmac: ethernet@ff290000 {
 679                 compatible = "rockchip,rk3368-gmac";
 680                 reg = <0x0 0xff290000 0x0 0x10000>;
 681                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 682                 interrupt-names = "macirq";
 683                 rockchip,grf = <&grf>;
 684                 clocks = <&cru SCLK_MAC>,
 685                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 686                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 687                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 688                 clock-names = "stmmaceth",
 689                         "mac_clk_rx", "mac_clk_tx",
 690                         "clk_mac_ref", "clk_mac_refout",
 691                         "aclk_mac", "pclk_mac";
 692                 status = "disabled";
 693         };
 694
 695         nandc0: nandc@ff400000 {
 696                 compatible = "rockchip,rk-nandc";
 697                 reg = <0x0 0xff400000 0x0 0x4000>;
 698                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 699                 nandc_id = <0>;
 700                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 701                 clock-names = "clk_nandc", "hclk_nandc";
 702                 status = "disabled";
 703         };
 704
 705         usb_host0_ehci: usb@ff500000 {
 706                 compatible = "generic-ehci";
 707                 reg = <0x0 0xff500000 0x0 0x20000>;
 708                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 709                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 710                 clock-names = "usbhost", "utmi";
 711                 phys = <&u2phy_host>;
 712                 phy-names = "usb";
 713                 status = "disabled";
 714         };
 715
 716         usb_host0_ohci: usb@ff520000 {
 717                 compatible = "generic-ohci";
 718                 reg = <0x0 0xff520000 0x0 0x20000>;
 719                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 720                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 721                 clock-names = "usbhost", "utmi";
 722                 phys = <&u2phy_host>;
 723                 phy-names = "usb";
 724                 status = "disabled";
 725         };
 726
 727         usb_otg: usb@ff580000 {
 728                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 729                                 "snps,dwc2";
 730                 reg = <0x0 0xff580000 0x0 0x40000>;
 731                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 732                 clocks = <&cru HCLK_OTG0>;
 733                 clock-names = "otg";
 734                 dr_mode = "otg";
 735                 g-np-tx-fifo-size = <16>;
 736                 g-rx-fifo-size = <275>;
 737                 g-tx-fifo-size = <256 128 128 64 64 32>;
 738                 g-use-dma;
 739                 status = "disabled";
 740         };
 741
 742         ddrpctl: syscon@ff610000 {
 743                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 744                 reg = <0x0 0xff610000 0x0 0x400>;
 745         };
 746
 747         i2c1: i2c@ff660000 {
 748                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 749                 reg = <0x0 0xff660000 0x0 0x1000>;
 750                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 751                 #address-cells = <1>;
 752                 #size-cells = <0>;
 753                 clock-names = "i2c";
 754                 clocks = <&cru PCLK_I2C1>;
 755                 pinctrl-names = "default";
 756                 pinctrl-0 = <&i2c1_xfer>;
 757                 status = "disabled";
 758         };
 759
 760         pwm0: pwm@ff680000 {
 761                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 762                 reg = <0x0 0xff680000 0x0 0x10>;
 763                 #pwm-cells = <3>;
 764                 pinctrl-names = "default";
 765                 pinctrl-0 = <&pwm0_pin>;
 766                 clocks = <&cru PCLK_PWM1>;
 767                 clock-names = "pwm";
 768                 status = "disabled";
 769         };
 770
 771         pwm1: pwm@ff680010 {
 772                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 773                 reg = <0x0 0xff680010 0x0 0x10>;
 774                 #pwm-cells = <3>;
 775                 pinctrl-names = "default";
 776                 pinctrl-0 = <&pwm1_pin>;
 777                 clocks = <&cru PCLK_PWM1>;
 778                 clock-names = "pwm";
 779                 status = "disabled";
 780         };
 781
 782         pwm2: pwm@ff680020 {
 783                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 784                 reg = <0x0 0xff680020 0x0 0x10>;
 785                 #pwm-cells = <3>;
 786                 clocks = <&cru PCLK_PWM1>;
 787                 clock-names = "pwm";
 788                 status = "disabled";
 789         };
 790
 791         pwm3: pwm@ff680030 {
 792                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 793                 reg = <0x0 0xff680030 0x0 0x10>;
 794                 #pwm-cells = <3>;
 795                 pinctrl-names = "default";
 796                 pinctrl-0 = <&pwm3_pin>;
 797                 clocks = <&cru PCLK_PWM1>;
 798                 clock-names = "pwm";
 799                 status = "disabled";
 800         };
 801
 802         uart2: serial@ff690000 {
 803                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 804                 reg = <0x0 0xff690000 0x0 0x100>;
 805                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 806                 clock-names = "baudclk", "apb_pclk";
 807                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 808                 pinctrl-names = "default";
 809                 pinctrl-0 = <&uart2_xfer>;
 810                 reg-shift = <2>;
 811                 reg-io-width = <4>;
 812                 status = "disabled";
 813         };
 814
 815         mbox: mbox@ff6b0000 {
 816                 compatible = "rockchip,rk3368-mailbox";
 817                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 818                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 819                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 820                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 821                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 822                 clocks = <&cru PCLK_MAILBOX>;
 823                 clock-names = "pclk_mailbox";
 824                 #mbox-cells = <1>;
 825                 status = "disabled";
 826         };
 827
 828         mailbox: mailbox@ff6b0000 {
 829                 compatible = "rockchip,rk3368-mbox-legacy";
 830                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 831                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 832                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 833                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 834                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 835                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 836                 clocks = <&cru PCLK_MAILBOX>;
 837                 clock-names = "pclk_mailbox";
 838                 #mbox-cells = <1>;
 839                 status = "disabled";
 840         };
 841
 842         mailbox_scpi: mailbox-scpi {
 843                 compatible = "rockchip,rk3368-scpi-legacy";
 844                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 845                 chan-nums = <3>;
 846                 status = "disabled";
 847         };
 848
 849         qos_iep: qos@ffad0000 {
 850                 compatible = "syscon";
 851                 reg = <0x0 0xffad0000 0x0 0x20>;
 852         };
 853
 854         qos_isp_r0: qos@ffad0080 {
 855                 compatible = "syscon";
 856                 reg = <0x0 0xffad0080 0x0 0x20>;
 857         };
 858
 859         qos_isp_r1: qos@ffad0100 {
 860                 compatible = "syscon";
 861                 reg = <0x0 0xffad0100 0x0 0x20>;
 862         };
 863
 864         qos_isp_w0: qos@ffad0180 {
 865                 compatible = "syscon";
 866                 reg = <0x0 0xffad0180 0x0 0x20>;
 867         };
 868
 869         qos_isp_w1: qos@ffad0200 {
 870                 compatible = "syscon";
 871                 reg = <0x0 0xffad0200 0x0 0x20>;
 872         };
 873
 874         qos_vip: qos@ffad0280 {
 875                 compatible = "syscon";
 876                 reg = <0x0 0xffad0280 0x0 0x20>;
 877         };
 878
 879         qos_vop: qos@ffad0300 {
 880                 compatible = "syscon";
 881                 reg = <0x0 0xffad0300 0x0 0x20>;
 882         };
 883
 884         qos_rga_r: qos@ffad0380 {
 885                 compatible = "syscon";
 886                 reg = <0x0 0xffad0380 0x0 0x20>;
 887         };
 888
 889         qos_rga_w: qos@ffad0400 {
 890                 compatible = "syscon";
 891                 reg = <0x0 0xffad0400 0x0 0x20>;
 892         };
 893
 894         qos_hevc_r: qos@ffae0000 {
 895                 compatible = "syscon";
 896                 reg = <0x0 0xffae0000 0x0 0x20>;
 897         };
 898
 899         qos_vpu_r: qos@ffae0100 {
 900                 compatible = "syscon";
 901                 reg = <0x0 0xffae0100 0x0 0x20>;
 902         };
 903
 904         qos_vpu_w: qos@ffae0180 {
 905                 compatible = "syscon";
 906                 reg = <0x0 0xffae0180 0x0 0x20>;
 907         };
 908
 909         qos_gpu: qos@ffaf0000 {
 910                 compatible = "syscon";
 911                 reg = <0x0 0xffaf0000 0x0 0x20>;
 912         };
 913
 914         pmu: power-management@ff730000 {
 915                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 916                 reg = <0x0 0xff730000 0x0 0x1000>;
 917
 918                 power: power-controller {
 919                         status = "disabled";
 920                         compatible = "rockchip,rk3368-power-controller";
 921                         #power-domain-cells = <1>;
 922                         #address-cells = <1>;
 923                         #size-cells = <0>;
 924
 925                         /*
 926                          * Note: Although SCLK_* are the working clocks
 927                          * of device without including on the NOC, needed for
 928                          * synchronous reset.
 929                          *
 930                          * The clocks on the which NOC:
 931                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 932                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 933                          * ACLK_RGA is on ACLK_RGA_NIU.
 934                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 935                          *
 936                          * Which clock are device clocks:
 937                          *      clocks          devices
 938                          *      *_IEP           IEP:Image Enhancement Processor
 939                          *      *_ISP           ISP:Image Signal Processing
 940                          *      *_VIP           VIP:Video Input Processor
 941                          *      *_VOP*          VOP:Visual Output Processor
 942                          *      *_RGA           RGA
 943                          *      *_EDP*          EDP
 944                          *      *_DPHY*         LVDS
 945                          *      *_HDMI          HDMI
 946                          *      *_MIPI_*        MIPI
 947                          */
 948                         pd_vio {
 949                                 reg = <RK3368_PD_VIO>;
 950                                 clocks = <&cru ACLK_IEP>,
 951                                          <&cru ACLK_ISP>,
 952                                          <&cru ACLK_VIP>,
 953                                          <&cru ACLK_RGA>,
 954                                          <&cru ACLK_VOP>,
 955                                          <&cru ACLK_VOP_IEP>,
 956                                          <&cru DCLK_VOP>,
 957                                          <&cru HCLK_IEP>,
 958                                          <&cru HCLK_ISP>,
 959                                          <&cru HCLK_RGA>,
 960                                          <&cru HCLK_VIP>,
 961                                          <&cru HCLK_VOP>,
 962                                          <&cru HCLK_VIO_HDCPMMU>,
 963                                          <&cru PCLK_EDP_CTRL>,
 964                                          <&cru PCLK_HDMI_CTRL>,
 965                                          <&cru PCLK_HDCP>,
 966                                          <&cru PCLK_ISP>,
 967                                          <&cru PCLK_VIP>,
 968                                          <&cru PCLK_DPHYRX>,
 969                                          <&cru PCLK_DPHYTX0>,
 970                                          <&cru PCLK_MIPI_CSI>,
 971                                          <&cru PCLK_MIPI_DSI0>,
 972                                          <&cru SCLK_VOP0_PWM>,
 973                                          <&cru SCLK_EDP_24M>,
 974                                          <&cru SCLK_EDP>,
 975                                          <&cru SCLK_HDCP>,
 976                                          <&cru SCLK_ISP>,
 977                                          <&cru SCLK_RGA>,
 978                                          <&cru SCLK_HDMI_CEC>,
 979                                          <&cru SCLK_HDMI_HDCP>;
 980                                 pm_qos = <&qos_iep>,
 981                                          <&qos_isp_r0>,
 982                                          <&qos_isp_r1>,
 983                                          <&qos_isp_w0>,
 984                                          <&qos_isp_w1>,
 985                                          <&qos_vip>,
 986                                          <&qos_vop>,
 987                                          <&qos_rga_r>,
 988                                          <&qos_rga_w>;
 989                         };
 990                         /*
 991                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 992                          * (video endecoder & decoder) clocks that on the
 993                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 994                          */
 995                         pd_video {
 996                                 reg = <RK3368_PD_VIDEO>;
 997                                 clocks = <&cru ACLK_VIDEO>,
 998                                          <&cru HCLK_VIDEO>,
 999                                          <&cru SCLK_HEVC_CABAC>,
1000                                          <&cru SCLK_HEVC_CORE>;
1001                                 pm_qos = <&qos_hevc_r>,
1002                                          <&qos_vpu_r>,
1003                                          <&qos_vpu_w>;
1004                         };
1005                         /*
1006                          * Note: ACLK_GPU is the GPU clock,
1007                          * and on the ACLK_GPU_NIU (NOC).
1008                          */
1009                         pd_gpu_1 {
1010                                 reg = <RK3368_PD_GPU_1>;
1011                                 clocks = <&cru ACLK_GPU_CFG>,
1012                                          <&cru ACLK_GPU_MEM>,
1013                                          <&cru SCLK_GPU_CORE>;
1014                                 pm_qos = <&qos_gpu>;
1015                         };
1016                 };
1017         };
1018
1019         pmugrf: syscon@ff738000 {
1020                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1021                 reg = <0x0 0xff738000 0x0 0x1000>;
1022
1023                 pmu_io_domains: io-domains {
1024                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1025                         status = "disabled";
1026                 };
1027
1028                 reboot-mode {
1029                         compatible = "syscon-reboot-mode";
1030                         offset = <0x200>;
1031                         mode-normal = <BOOT_NORMAL>;
1032                         mode-recovery = <BOOT_RECOVERY>;
1033                         mode-bootloader = <BOOT_FASTBOOT>;
1034                         mode-loader = <BOOT_BL_DOWNLOAD>;
1035                 };
1036         };
1037
1038         cru: clock-controller@ff760000 {
1039                 compatible = "rockchip,rk3368-cru";
1040                 reg = <0x0 0xff760000 0x0 0x1000>;
1041                 rockchip,grf = <&grf>;
1042                 #clock-cells = <1>;
1043                 #reset-cells = <1>;
1044                 assigned-clocks =
1045                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1046                         <&cru PLL_NPLL>,
1047                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1048                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1049                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
1050                 assigned-clock-rates =
1051                         <576000000>, <400000000>,
1052                         <1188000000>,
1053                         <300000000>, <300000000>,
1054                         <150000000>, <150000000>,
1055                         <75000000>, <75000000>;
1056         };
1057
1058         grf: syscon@ff770000 {
1059                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1060                 reg = <0x0 0xff770000 0x0 0x1000>;
1061                 #address-cells = <1>;
1062                 #size-cells = <1>;
1063
1064                 io_domains: io-domains {
1065                         compatible = "rockchip,rk3368-io-voltage-domain";
1066                         status = "disabled";
1067                 };
1068
1069                 u2phy: usb2-phy@700 {
1070                         compatible = "rockchip,rk3368-usb2phy";
1071                         reg = <0x700 0x2c>;
1072                         clocks = <&cru SCLK_OTGPHY0>;
1073                         clock-names = "phyclk";
1074                         #clock-cells = <0>;
1075                         clock-output-names = "usbotg_out";
1076                         assigned-clocks = <&cru SCLK_USBPHY480M>;
1077                         assigned-clock-parents = <&u2phy>;
1078                         status = "disabled";
1079
1080                         u2phy_host: host-port {
1081                                 #phy-cells = <0>;
1082                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1083                                 interrupt-names = "linestate";
1084                                 status = "disabled";
1085                         };
1086                 };
1087         };
1088
1089         wdt: watchdog@ff800000 {
1090                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1091                 reg = <0x0 0xff800000 0x0 0x100>;
1092                 clocks = <&cru PCLK_WDT>;
1093                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1094                 status = "disabled";
1095         };
1096
1097         timer@ff810000 {
1098                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1099                 reg = <0x0 0xff810000 0x0 0x20>;
1100                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1101         };
1102
1103         i2s_2ch: i2s-2ch@ff890000 {
1104                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1105                 reg = <0x0 0xff890000 0x0 0x1000>;
1106                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1107                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1108                 dma-names = "tx", "rx";
1109                 clock-names = "i2s_clk", "i2s_hclk";
1110                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1111                 status = "disabled";
1112         };
1113
1114         i2s_8ch: i2s-8ch@ff898000 {
1115                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1116                 reg = <0x0 0xff898000 0x0 0x1000>;
1117                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1118                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1119                 dma-names = "tx", "rx";
1120                 clock-names = "i2s_clk", "i2s_hclk";
1121                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1122                 pinctrl-names = "default";
1123                 pinctrl-0 = <&i2s_8ch_bus>;
1124                 status = "disabled";
1125         };
1126
1127         isp_mmu: iommu@ff914000 {
1128                 compatible = "rockchip,iommu";
1129                 reg = <0x0 0xff914000 0x0 0x100>,
1130                       <0x0 0xff915000 0x0 0x100>;
1131                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1132                 interrupt-names = "isp_mmu";
1133                 #iommu-cells = <0>;
1134                 status = "disabled";
1135         };
1136
1137         vop: vop@ff930000 {
1138                 compatible = "rockchip,rk3368-vop";
1139                 reg = <0x0 0xff930000 0x0 0x2fc>;
1140                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1141                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1142                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1143                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1144                 reset-names = "axi", "ahb", "dclk";
1145                 power-domains = <&power RK3368_PD_VIO>;
1146                 iommus = <&vop_mmu>;
1147                 status = "disabled";
1148
1149                 vop_out: port {
1150                         #address-cells = <1>;
1151                         #size-cells = <0>;
1152                 };
1153         };
1154
1155         display_subsystem: display-subsystem {
1156                 compatible = "rockchip,display-subsystem";
1157                 ports = <&vop_out>;
1158                 status = "disabled";
1159         };
1160
1161         vop_mmu: iommu@ff930300 {
1162                 compatible = "rockchip,iommu";
1163                 reg = <0x0 0xff930300 0x0 0x100>;
1164                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1165                 interrupt-names = "vop_mmu";
1166                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1167                 clock-names = "aclk", "hclk";
1168                 power-domains = <&power RK3368_PD_VIO>;
1169                 #iommu-cells = <0>;
1170                 status = "disabled";
1171         };
1172
1173         hevc_mmu: iommu@ff9a0440 {
1174                 compatible = "rockchip,iommu";
1175                 reg = <0x0 0xff9a0440 0x0 0x100>,
1176                       <0x0 0xff9a0480 0x0 0x100>;
1177                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1178                 interrupt-names = "hevc_mmu";
1179                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1180                 clock-names = "aclk", "hclk";
1181                 power-domains = <&power RK3368_PD_VIDEO>;
1182                 #iommu-cells = <0>;
1183                 status = "disabled";
1184         };
1185
1186         vpu_mmu: iommu@ff9a0800 {
1187                 compatible = "rockchip,iommu";
1188                 reg = <0x0 0xff9a0800 0x0 0x100>;
1189                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1190                 interrupt-names = "vpu_mmu";
1191                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1192                 clock-names = "aclk", "hclk";
1193                 power-domains = <&power RK3368_PD_VIDEO>;
1194                 #iommu-cells = <0>;
1195                 status = "disabled";
1196         };
1197
1198         gic: interrupt-controller@ffb71000 {
1199                 compatible = "arm,gic-400";
1200                 interrupt-controller;
1201                 #interrupt-cells = <3>;
1202                 #address-cells = <0>;
1203
1204                 reg = <0x0 0xffb71000 0x0 0x1000>,
1205                       <0x0 0xffb72000 0x0 0x2000>,
1206                       <0x0 0xffb74000 0x0 0x2000>,
1207                       <0x0 0xffb76000 0x0 0x2000>;
1208                 interrupts = <GIC_PPI 9
1209                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1210         };
1211
1212         gpu: rogue-g6110@ffa30000 {
1213                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1214                 reg = <0x0 0xffa30000 0x0 0x10000>;
1215                 clocks =
1216                         <&cru SCLK_GPU_CORE>,
1217                         <&cru ACLK_GPU_MEM>,
1218                         <&cru ACLK_GPU_CFG>;
1219                 clock-names =
1220                         "sclk_gpu_core",
1221                         "aclk_gpu_mem",
1222                         "aclk_gpu_cfg";
1223                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1224                 interrupt-names = "rogue-g6110-irq";
1225                 operating-points-v2 = <&gpu_opp_table>;
1226         };
1227
1228         gpu_opp_table: gpu_opp_table {
1229                 compatible = "operating-points-v2";
1230                 opp-shared;
1231
1232                 opp@200000000 {
1233                         opp-hz = /bits/ 64 <200000000>;
1234                         opp-microvolt = <1100000>;
1235                 };
1236                 opp@288000000 {
1237                         opp-hz = /bits/ 64 <288000000>;
1238                         opp-microvolt = <1100000>;
1239                 };
1240                 opp@400000000 {
1241                         opp-hz = /bits/ 64 <400000000>;
1242                         opp-microvolt = <1100000>;
1243                 };
1244                 opp@576000000 {
1245                         opp-hz = /bits/ 64 <576000000>;
1246                         opp-microvolt = <1200000>;
1247                 };
1248         };
1249
1250         efuse: efuse@ffb00000 {
1251                 compatible = "rockchip,rk3368-efuse";
1252                 reg = <0x0 0xffb00000 0x0 0x20>;
1253                 #address-cells = <1>;
1254                 #size-cells = <1>;
1255                 clocks = <&cru PCLK_EFUSE256>;
1256                 clock-names = "pclk_efuse";
1257
1258                 /* Data cells */
1259                 cpu_leakage: cpu-leakage@17 {
1260                         reg = <0x17 0x1>;
1261                 };
1262                 temp_adjust: temp-adjust@1f {
1263                         reg = <0x1f 0x1>;
1264                 };
1265         };
1266
1267         pinctrl: pinctrl {
1268                 compatible = "rockchip,rk3368-pinctrl";
1269                 rockchip,grf = <&grf>;
1270                 rockchip,pmu = <&pmugrf>;
1271                 #address-cells = <0x2>;
1272                 #size-cells = <0x2>;
1273                 ranges;
1274
1275                 gpio0: gpio0@ff750000 {
1276                         compatible = "rockchip,gpio-bank";
1277                         reg = <0x0 0xff750000 0x0 0x100>;
1278                         clocks = <&cru PCLK_GPIO0>;
1279                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1280
1281                         gpio-controller;
1282                         #gpio-cells = <0x2>;
1283
1284                         interrupt-controller;
1285                         #interrupt-cells = <0x2>;
1286                 };
1287
1288                 gpio1: gpio1@ff780000 {
1289                         compatible = "rockchip,gpio-bank";
1290                         reg = <0x0 0xff780000 0x0 0x100>;
1291                         clocks = <&cru PCLK_GPIO1>;
1292                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1293
1294                         gpio-controller;
1295                         #gpio-cells = <0x2>;
1296
1297                         interrupt-controller;
1298                         #interrupt-cells = <0x2>;
1299                 };
1300
1301                 gpio2: gpio2@ff790000 {
1302                         compatible = "rockchip,gpio-bank";
1303                         reg = <0x0 0xff790000 0x0 0x100>;
1304                         clocks = <&cru PCLK_GPIO2>;
1305                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1306
1307                         gpio-controller;
1308                         #gpio-cells = <0x2>;
1309
1310                         interrupt-controller;
1311                         #interrupt-cells = <0x2>;
1312                 };
1313
1314                 gpio3: gpio3@ff7a0000 {
1315                         compatible = "rockchip,gpio-bank";
1316                         reg = <0x0 0xff7a0000 0x0 0x100>;
1317                         clocks = <&cru PCLK_GPIO3>;
1318                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1319
1320                         gpio-controller;
1321                         #gpio-cells = <0x2>;
1322
1323                         interrupt-controller;
1324                         #interrupt-cells = <0x2>;
1325                 };
1326
1327                 pcfg_pull_up: pcfg-pull-up {
1328                         bias-pull-up;
1329                 };
1330
1331                 pcfg_pull_down: pcfg-pull-down {
1332                         bias-pull-down;
1333                 };
1334
1335                 pcfg_pull_none: pcfg-pull-none {
1336                         bias-disable;
1337                 };
1338
1339                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1340                         bias-disable;
1341                         drive-strength = <12>;
1342                 };
1343
1344                 emmc {
1345                         emmc_clk: emmc-clk {
1346                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1347                         };
1348
1349                         emmc_cmd: emmc-cmd {
1350                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1351                         };
1352
1353                         emmc_pwr: emmc-pwr {
1354                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1355                         };
1356
1357                         emmc_bus1: emmc-bus1 {
1358                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1359                         };
1360
1361                         emmc_bus4: emmc-bus4 {
1362                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1363                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1364                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1365                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1366                         };
1367
1368                         emmc_bus8: emmc-bus8 {
1369                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1370                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1371                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1372                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1373                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1374                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1375                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1376                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1377                         };
1378                 };
1379
1380                 gmac {
1381                         rgmii_pins: rgmii-pins {
1382                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1383                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1384                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1385                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1386                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1387                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1388                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1389                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1390                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1391                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1392                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1393                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1394                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1395                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1396                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1397                         };
1398
1399                         rmii_pins: rmii-pins {
1400                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1401                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1402                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1403                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1404                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1405                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1406                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1407                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1408                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1409                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1410                         };
1411                 };
1412
1413                 i2c0 {
1414                         i2c0_xfer: i2c0-xfer {
1415                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1416                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1417                         };
1418                 };
1419
1420                 i2c1 {
1421                         i2c1_xfer: i2c1-xfer {
1422                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1423                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1424                         };
1425                 };
1426
1427                 i2c2 {
1428                         i2c2_xfer: i2c2-xfer {
1429                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1430                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1431                         };
1432                 };
1433
1434                 i2c3 {
1435                         i2c3_xfer: i2c3-xfer {
1436                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1437                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1438                         };
1439                 };
1440
1441                 i2c4 {
1442                         i2c4_xfer: i2c4-xfer {
1443                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1444                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1445                         };
1446                 };
1447
1448                 i2c5 {
1449                         i2c5_xfer: i2c5-xfer {
1450                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1451                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1452                         };
1453                 };
1454
1455                 i2s {
1456                         i2s_8ch_bus: i2s-8ch-bus {
1457                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1458                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1459                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1460                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1461                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1462                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1463                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1464                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1465                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1466                         };
1467                 };
1468
1469                 pwm0 {
1470                         pwm0_pin: pwm0-pin {
1471                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1472                         };
1473
1474                         vop_pwm_pin: vop-pwm {
1475                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1476                         };
1477                 };
1478
1479                 pwm1 {
1480                         pwm1_pin: pwm1-pin {
1481                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1482                         };
1483                 };
1484
1485                 pwm3 {
1486                         pwm3_pin: pwm3-pin {
1487                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1488                         };
1489                 };
1490
1491                 sdio0 {
1492                         sdio0_bus1: sdio0-bus1 {
1493                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1494                         };
1495
1496                         sdio0_bus4: sdio0-bus4 {
1497                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1498                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1499                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1500                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1501                         };
1502
1503                         sdio0_cmd: sdio0-cmd {
1504                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1505                         };
1506
1507                         sdio0_clk: sdio0-clk {
1508                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1509                         };
1510
1511                         sdio0_cd: sdio0-cd {
1512                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1513                         };
1514
1515                         sdio0_wp: sdio0-wp {
1516                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1517                         };
1518
1519                         sdio0_pwr: sdio0-pwr {
1520                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1521                         };
1522
1523                         sdio0_bkpwr: sdio0-bkpwr {
1524                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1525                         };
1526
1527                         sdio0_int: sdio0-int {
1528                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1529                         };
1530                 };
1531
1532                 sdmmc {
1533                         sdmmc_clk: sdmmc-clk {
1534                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1535                         };
1536
1537                         sdmmc_cmd: sdmmc-cmd {
1538                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1539                         };
1540
1541                         sdmmc_cd: sdmmc-cd {
1542                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1543                         };
1544
1545                         sdmmc_bus1: sdmmc-bus1 {
1546                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1547                         };
1548
1549                         sdmmc_bus4: sdmmc-bus4 {
1550                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1551                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1552                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1553                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1554                         };
1555                 };
1556
1557                 spi0 {
1558                         spi0_clk: spi0-clk {
1559                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1560                         };
1561                         spi0_cs0: spi0-cs0 {
1562                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1563                         };
1564                         spi0_cs1: spi0-cs1 {
1565                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1566                         };
1567                         spi0_tx: spi0-tx {
1568                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1569                         };
1570                         spi0_rx: spi0-rx {
1571                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1572                         };
1573                 };
1574
1575                 spi1 {
1576                         spi1_clk: spi1-clk {
1577                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1578                         };
1579                         spi1_cs0: spi1-cs0 {
1580                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1581                         };
1582                         spi1_cs1: spi1-cs1 {
1583                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1584                         };
1585                         spi1_rx: spi1-rx {
1586                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1587                         };
1588                         spi1_tx: spi1-tx {
1589                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1590                         };
1591                 };
1592
1593                 spi2 {
1594                         spi2_clk: spi2-clk {
1595                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1596                         };
1597                         spi2_cs0: spi2-cs0 {
1598                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1599                         };
1600                         spi2_rx: spi2-rx {
1601                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1602                         };
1603                         spi2_tx: spi2-tx {
1604                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1605                         };
1606                 };
1607
1608                 tsadc {
1609                         otp_gpio: otp-gpio {
1610                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1611                         };
1612
1613                         otp_out: otp-out {
1614                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1615                         };
1616                 };
1617
1618                 uart0 {
1619                         uart0_xfer: uart0-xfer {
1620                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1621                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1622                         };
1623
1624                         uart0_cts: uart0-cts {
1625                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1626                         };
1627
1628                         uart0_rts: uart0-rts {
1629                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1630                         };
1631                 };
1632
1633                 uart1 {
1634                         uart1_xfer: uart1-xfer {
1635                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1636                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1637                         };
1638
1639                         uart1_cts: uart1-cts {
1640                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1641                         };
1642
1643                         uart1_rts: uart1-rts {
1644                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1645                         };
1646                 };
1647
1648                 uart2 {
1649                         uart2_xfer: uart2-xfer {
1650                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1651                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1652                         };
1653                         /* no rts / cts for uart2 */
1654                 };
1655
1656                 uart3 {
1657                         uart3_xfer: uart3-xfer {
1658                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1659                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1660                         };
1661
1662                         uart3_cts: uart3-cts {
1663                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1664                         };
1665
1666                         uart3_rts: uart3-rts {
1667                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1668                         };
1669                 };
1670
1671                 uart4 {
1672                         uart4_xfer: uart4-xfer {
1673                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1674                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1675                         };
1676
1677                         uart4_cts: uart4-cts {
1678                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1679                         };
1680
1681                         uart4_rts: uart4-rts {
1682                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1683                         };
1684                 };
1685         };
1686 };