arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/display/mipi_dsi.h>
  50 #include <dt-bindings/power/rk3368-power.h>
  51 #include <dt-bindings/soc/rockchip_boot-mode.h>
  52
  53 / {
  54         compatible = "rockchip,rk3368";
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74                 lcdc = &lcdc;
  75         };
  76
  77         cpus {
  78                 #address-cells = <0x2>;
  79                 #size-cells = <0x0>;
  80
  81                 cpu-map {
  82                         cluster0 {
  83                                 core0 {
  84                                         cpu = <&cpu_b0>;
  85                                 };
  86                                 core1 {
  87                                         cpu = <&cpu_b1>;
  88                                 };
  89                                 core2 {
  90                                         cpu = <&cpu_b2>;
  91                                 };
  92                                 core3 {
  93                                         cpu = <&cpu_b3>;
  94                                 };
  95                         };
  96
  97                         cluster1 {
  98                                 core0 {
  99                                         cpu = <&cpu_l0>;
 100                                 };
 101                                 core1 {
 102                                         cpu = <&cpu_l1>;
 103                                 };
 104                                 core2 {
 105                                         cpu = <&cpu_l2>;
 106                                 };
 107                                 core3 {
 108                                         cpu = <&cpu_l3>;
 109                                 };
 110                         };
 111                 };
 112
 113                 idle-states {
 114                         entry-method = "psci";
 115
 116                         cpu_sleep: cpu-sleep-0 {
 117                                 compatible = "arm,idle-state";
 118                                 arm,psci-suspend-param = <0x1010000>;
 119                                 entry-latency-us = <0x3fffffff>;
 120                                 exit-latency-us = <0x40000000>;
 121                                 min-residency-us = <0xffffffff>;
 122                         };
 123                 };
 124
 125                 cpu_l0: cpu@0 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a53", "arm,armv8";
 128                         reg = <0x0 0x0>;
 129                         cpu-idle-states = <&cpu_sleep>;
 130                         enable-method = "psci";
 131                         clocks = <&cru ARMCLKL>;
 132                         operating-points-v2 = <&cluster1_opp>;
 133                 };
 134
 135                 cpu_l1: cpu@1 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x1>;
 139                         cpu-idle-states = <&cpu_sleep>;
 140                         enable-method = "psci";
 141                         clocks = <&cru ARMCLKL>;
 142                         operating-points-v2 = <&cluster1_opp>;
 143                 };
 144
 145                 cpu_l2: cpu@2 {
 146                         device_type = "cpu";
 147                         compatible = "arm,cortex-a53", "arm,armv8";
 148                         reg = <0x0 0x2>;
 149                         cpu-idle-states = <&cpu_sleep>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         operating-points-v2 = <&cluster1_opp>;
 153                 };
 154
 155                 cpu_l3: cpu@3 {
 156                         device_type = "cpu";
 157                         compatible = "arm,cortex-a53", "arm,armv8";
 158                         reg = <0x0 0x3>;
 159                         cpu-idle-states = <&cpu_sleep>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKL>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164
 165                 cpu_b0: cpu@100 {
 166                         device_type = "cpu";
 167                         compatible = "arm,cortex-a53", "arm,armv8";
 168                         reg = <0x0 0x100>;
 169                         cpu-idle-states = <&cpu_sleep>;
 170                         enable-method = "psci";
 171                         clocks = <&cru ARMCLKB>;
 172                         operating-points-v2 = <&cluster0_opp>;
 173                 };
 174
 175                 cpu_b1: cpu@101 {
 176                         device_type = "cpu";
 177                         compatible = "arm,cortex-a53", "arm,armv8";
 178                         reg = <0x0 0x101>;
 179                         cpu-idle-states = <&cpu_sleep>;
 180                         enable-method = "psci";
 181                         clocks = <&cru ARMCLKB>;
 182                         operating-points-v2 = <&cluster0_opp>;
 183                 };
 184
 185                 cpu_b2: cpu@102 {
 186                         device_type = "cpu";
 187                         compatible = "arm,cortex-a53", "arm,armv8";
 188                         reg = <0x0 0x102>;
 189                         cpu-idle-states = <&cpu_sleep>;
 190                         enable-method = "psci";
 191                         clocks = <&cru ARMCLKB>;
 192                         operating-points-v2 = <&cluster0_opp>;
 193                 };
 194
 195                 cpu_b3: cpu@103 {
 196                         device_type = "cpu";
 197                         compatible = "arm,cortex-a53", "arm,armv8";
 198                         reg = <0x0 0x103>;
 199                         cpu-idle-states = <&cpu_sleep>;
 200                         enable-method = "psci";
 201                         clocks = <&cru ARMCLKB>;
 202                         operating-points-v2 = <&cluster0_opp>;
 203                 };
 204         };
 205
 206         cluster0_opp: opp_table0 {
 207                 compatible = "operating-points-v2";
 208                 opp-shared;
 209
 210                 opp00 {
 211                         opp-hz = /bits/ 64 <408000000>;
 212                         opp-microvolt = <1200000>;
 213                         clock-latency-ns = <40000>;
 214                         opp-suspend;
 215                 };
 216                 opp01 {
 217                         opp-hz = /bits/ 64 <600000000>;
 218                         opp-microvolt = <1200000>;
 219                 };
 220                 opp02 {
 221                         opp-hz = /bits/ 64 <816000000>;
 222                         opp-microvolt = <1200000>;
 223                 };
 224                 opp03 {
 225                         opp-hz = /bits/ 64 <1008000000>;
 226                         opp-microvolt = <1200000>;
 227                 };
 228                 opp04 {
 229                         opp-hz = /bits/ 64 <1200000000>;
 230                         opp-microvolt = <1200000>;
 231                 };
 232         };
 233
 234         cluster1_opp: opp_table1 {
 235                 compatible = "operating-points-v2";
 236                 opp-shared;
 237
 238                 opp00 {
 239                         opp-hz = /bits/ 64 <408000000>;
 240                         opp-microvolt = <1200000>;
 241                         clock-latency-ns = <40000>;
 242                         opp-suspend;
 243                 };
 244                 opp01 {
 245                         opp-hz = /bits/ 64 <600000000>;
 246                         opp-microvolt = <1200000>;
 247                 };
 248                 opp02 {
 249                         opp-hz = /bits/ 64 <816000000>;
 250                         opp-microvolt = <1200000>;
 251                 };
 252                 opp03 {
 253                         opp-hz = /bits/ 64 <1008000000>;
 254                         opp-microvolt = <1200000>;
 255                 };
 256         };
 257
 258         arm-pmu {
 259                 compatible = "arm,armv8-pmuv3";
 260                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 268                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 269                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 270                                      <&cpu_b2>, <&cpu_b3>;
 271         };
 272
 273         amba {
 274                 compatible = "arm,amba-bus";
 275                 #address-cells = <2>;
 276                 #size-cells = <2>;
 277                 ranges;
 278
 279                 dmac_peri: dma-controller@ff250000 {
 280                         compatible = "arm,pl330", "arm,primecell";
 281                         reg = <0x0 0xff250000 0x0 0x4000>;
 282                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 283                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 284                         #dma-cells = <1>;
 285                         clocks = <&cru ACLK_DMAC_PERI>;
 286                         clock-names = "apb_pclk";
 287                 };
 288
 289                 dmac_bus: dma-controller@ff600000 {
 290                         compatible = "arm,pl330", "arm,primecell";
 291                         reg = <0x0 0xff600000 0x0 0x4000>;
 292                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 293                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 294                         #dma-cells = <1>;
 295                         clocks = <&cru ACLK_DMAC_BUS>;
 296                         clock-names = "apb_pclk";
 297                 };
 298         };
 299
 300         psci {
 301                 compatible = "arm,psci-0.2";
 302                 method = "smc";
 303         };
 304
 305         timer {
 306                 compatible = "arm,armv8-timer";
 307                 interrupts = <GIC_PPI 13
 308                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 309                              <GIC_PPI 14
 310                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 311                              <GIC_PPI 11
 312                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 313                              <GIC_PPI 10
 314                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 315         };
 316
 317         xin24m: oscillator {
 318                 compatible = "fixed-clock";
 319                 clock-frequency = <24000000>;
 320                 clock-output-names = "xin24m";
 321                 #clock-cells = <0>;
 322         };
 323
 324         sdmmc: rksdmmc@ff0c0000 {
 325                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 326                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 327                 clock-freq-min-max = <400000 150000000>;
 328                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 329                 clock-names = "biu", "ciu";
 330                 fifo-depth = <0x100>;
 331                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 332                 status = "disabled";
 333         };
 334
 335         sdio0: dwmmc@ff0d0000 {
 336                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 337                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 338                 clock-freq-min-max = <400000 150000000>;
 339                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 340                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 341                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 342                 fifo-depth = <0x100>;
 343                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 344                 status = "disabled";
 345         };
 346
 347         emmc: rksdmmc@ff0f0000 {
 348                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 349                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 350                 clock-freq-min-max = <400000 150000000>;
 351                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 352                 clock-names = "biu", "ciu";
 353                 fifo-depth = <0x100>;
 354                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 355                 status = "disabled";
 356         };
 357
 358         saradc: saradc@ff100000 {
 359                 compatible = "rockchip,saradc";
 360                 reg = <0x0 0xff100000 0x0 0x100>;
 361                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 362                 #io-channel-cells = <1>;
 363                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 364                 clock-names = "saradc", "apb_pclk";
 365                 status = "disabled";
 366         };
 367
 368         spi0: spi@ff110000 {
 369                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 370                 reg = <0x0 0xff110000 0x0 0x1000>;
 371                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 372                 clock-names = "spiclk", "apb_pclk";
 373                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 status = "disabled";
 379         };
 380
 381         spi1: spi@ff120000 {
 382                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 383                 reg = <0x0 0xff120000 0x0 0x1000>;
 384                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 385                 clock-names = "spiclk", "apb_pclk";
 386                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 389                 #address-cells = <1>;
 390                 #size-cells = <0>;
 391                 status = "disabled";
 392         };
 393
 394         spi2: spi@ff130000 {
 395                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 396                 reg = <0x0 0xff130000 0x0 0x1000>;
 397                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 398                 clock-names = "spiclk", "apb_pclk";
 399                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 status = "disabled";
 405         };
 406
 407         i2c0: i2c@ff650000 {
 408                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 409                 reg = <0x0 0xff650000 0x0 0x1000>;
 410                 clocks = <&cru PCLK_I2C0>;
 411                 clock-names = "i2c";
 412                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&i2c0_xfer>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 status = "disabled";
 418         };
 419
 420         i2c2: i2c@ff140000 {
 421                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 422                 reg = <0x0 0xff140000 0x0 0x1000>;
 423                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426                 clock-names = "i2c";
 427                 clocks = <&cru PCLK_I2C2>;
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&i2c2_xfer>;
 430                 status = "disabled";
 431         };
 432
 433         i2c3: i2c@ff150000 {
 434                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 435                 reg = <0x0 0xff150000 0x0 0x1000>;
 436                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 clock-names = "i2c";
 440                 clocks = <&cru PCLK_I2C3>;
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&i2c3_xfer>;
 443                 status = "disabled";
 444         };
 445
 446         i2c4: i2c@ff160000 {
 447                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 448                 reg = <0x0 0xff160000 0x0 0x1000>;
 449                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 450                 #address-cells = <1>;
 451                 #size-cells = <0>;
 452                 clock-names = "i2c";
 453                 clocks = <&cru PCLK_I2C4>;
 454                 pinctrl-names = "default";
 455                 pinctrl-0 = <&i2c4_xfer>;
 456                 status = "disabled";
 457         };
 458
 459         i2c5: i2c@ff170000 {
 460                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 461                 reg = <0x0 0xff170000 0x0 0x1000>;
 462                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 463                 #address-cells = <1>;
 464                 #size-cells = <0>;
 465                 clock-names = "i2c";
 466                 clocks = <&cru PCLK_I2C5>;
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&i2c5_xfer>;
 469                 status = "disabled";
 470         };
 471
 472         uart0: serial@ff180000 {
 473                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 474                 reg = <0x0 0xff180000 0x0 0x100>;
 475                 clock-frequency = <24000000>;
 476                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 477                 clock-names = "baudclk", "apb_pclk";
 478                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 479                 reg-shift = <2>;
 480                 reg-io-width = <4>;
 481                 status = "disabled";
 482         };
 483
 484         uart1: serial@ff190000 {
 485                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 486                 reg = <0x0 0xff190000 0x0 0x100>;
 487                 clock-frequency = <24000000>;
 488                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 489                 clock-names = "baudclk", "apb_pclk";
 490                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 491                 reg-shift = <2>;
 492                 reg-io-width = <4>;
 493                 status = "disabled";
 494         };
 495
 496         uart3: serial@ff1b0000 {
 497                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 498                 reg = <0x0 0xff1b0000 0x0 0x100>;
 499                 clock-frequency = <24000000>;
 500                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 501                 clock-names = "baudclk", "apb_pclk";
 502                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 503                 reg-shift = <2>;
 504                 reg-io-width = <4>;
 505                 status = "disabled";
 506         };
 507
 508         uart4: serial@ff1c0000 {
 509                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 510                 reg = <0x0 0xff1c0000 0x0 0x100>;
 511                 clock-frequency = <24000000>;
 512                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 513                 clock-names = "baudclk", "apb_pclk";
 514                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 515                 reg-shift = <2>;
 516                 reg-io-width = <4>;
 517                 status = "disabled";
 518         };
 519
 520         gmac: ethernet@ff290000 {
 521                 compatible = "rockchip,rk3368-gmac";
 522                 reg = <0x0 0xff290000 0x0 0x10000>;
 523                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 524                 interrupt-names = "macirq";
 525                 rockchip,grf = <&grf>;
 526                 clocks = <&cru SCLK_MAC>,
 527                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 528                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 529                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 530                 clock-names = "stmmaceth",
 531                         "mac_clk_rx", "mac_clk_tx",
 532                         "clk_mac_ref", "clk_mac_refout",
 533                         "aclk_mac", "pclk_mac";
 534                 status = "disabled";
 535         };
 536
 537         nandc0: nandc@ff400000 {
 538                 compatible = "rockchip,rk-nandc";
 539                 reg = <0x0 0xff400000 0x0 0x4000>;
 540                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 541                 nandc_id = <0>;
 542                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 543                 clock-names = "clk_nandc", "hclk_nandc";
 544                 status = "disabled";
 545         };
 546
 547         usb_host0_ehci: usb@ff500000 {
 548                 compatible = "generic-ehci";
 549                 reg = <0x0 0xff500000 0x0 0x100>;
 550                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 551                 clocks = <&cru HCLK_HOST0>;
 552                 clock-names = "usbhost";
 553                 status = "disabled";
 554         };
 555
 556         usb_otg: usb@ff580000 {
 557                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 558                                 "snps,dwc2";
 559                 reg = <0x0 0xff580000 0x0 0x40000>;
 560                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 561                 clocks = <&cru HCLK_OTG0>;
 562                 clock-names = "otg";
 563                 dr_mode = "otg";
 564                 g-np-tx-fifo-size = <16>;
 565                 g-rx-fifo-size = <275>;
 566                 g-tx-fifo-size = <256 128 128 64 64 32>;
 567                 g-use-dma;
 568                 status = "disabled";
 569         };
 570
 571         ddrpctl: syscon@ff610000 {
 572                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 573                 reg = <0x0 0xff610000 0x0 0x400>;
 574         };
 575
 576         i2c1: i2c@ff660000 {
 577                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 578                 reg = <0x0 0xff660000 0x0 0x1000>;
 579                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 580                 #address-cells = <1>;
 581                 #size-cells = <0>;
 582                 clock-names = "i2c";
 583                 clocks = <&cru PCLK_I2C1>;
 584                 pinctrl-names = "default";
 585                 pinctrl-0 = <&i2c1_xfer>;
 586                 status = "disabled";
 587         };
 588
 589         pwm0: pwm@ff680000 {
 590                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 591                 reg = <0x0 0xff680000 0x0 0x10>;
 592                 #pwm-cells = <3>;
 593                 pinctrl-names = "default";
 594                 pinctrl-0 = <&pwm0_pin>;
 595                 clocks = <&cru PCLK_PWM1>;
 596                 clock-names = "pwm";
 597                 status = "disabled";
 598         };
 599
 600         pwm1: pwm@ff680010 {
 601                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 602                 reg = <0x0 0xff680010 0x0 0x10>;
 603                 #pwm-cells = <3>;
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&pwm1_pin>;
 606                 clocks = <&cru PCLK_PWM1>;
 607                 clock-names = "pwm";
 608                 status = "disabled";
 609         };
 610
 611         pwm2: pwm@ff680020 {
 612                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 613                 reg = <0x0 0xff680020 0x0 0x10>;
 614                 #pwm-cells = <3>;
 615                 clocks = <&cru PCLK_PWM1>;
 616                 clock-names = "pwm";
 617                 status = "disabled";
 618         };
 619
 620         pwm3: pwm@ff680030 {
 621                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 622                 reg = <0x0 0xff680030 0x0 0x10>;
 623                 #pwm-cells = <3>;
 624                 pinctrl-names = "default";
 625                 pinctrl-0 = <&pwm3_pin>;
 626                 clocks = <&cru PCLK_PWM1>;
 627                 clock-names = "pwm";
 628                 status = "disabled";
 629         };
 630
 631         uart2: serial@ff690000 {
 632                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 633                 reg = <0x0 0xff690000 0x0 0x100>;
 634                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 635                 clock-names = "baudclk", "apb_pclk";
 636                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&uart2_xfer>;
 639                 reg-shift = <2>;
 640                 reg-io-width = <4>;
 641                 status = "disabled";
 642         };
 643
 644         pmu: power-management@ff730000 {
 645                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 646                 reg = <0x0 0xff730000 0x0 0x1000>;
 647
 648                 power: power-controller {
 649                         status = "disabled";
 650                         compatible = "rockchip,rk3368-power-controller";
 651                         #power-domain-cells = <1>;
 652                         #address-cells = <1>;
 653                         #size-cells = <0>;
 654
 655                         /*
 656                          * Note: Although SCLK_* are the working clocks
 657                          * of device without including on the NOC, needed for
 658                          * synchronous reset.
 659                          *
 660                          * The clocks on the which NOC:
 661                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 662                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 663                          * ACLK_RGA is on ACLK_RGA_NIU.
 664                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 665                          *
 666                          * Which clock are device clocks:
 667                          *      clocks          devices
 668                          *      *_IEP           IEP:Image Enhancement Processor
 669                          *      *_ISP           ISP:Image Signal Processing
 670                          *      *_VIP           VIP:Video Input Processor
 671                          *      *_VOP*          VOP:Visual Output Processor
 672                          *      *_RGA           RGA
 673                          *      *_EDP*          EDP
 674                          *      *_DPHY*         LVDS
 675                          *      *_HDMI          HDMI
 676                          *      *_MIPI_*        MIPI
 677                          */
 678                         pd_vio {
 679                                 reg = <RK3368_PD_VIO>;
 680                                 clocks = <&cru ACLK_IEP>,
 681                                          <&cru ACLK_ISP>,
 682                                          <&cru ACLK_VIP>,
 683                                          <&cru ACLK_RGA>,
 684                                          <&cru ACLK_VOP>,
 685                                          <&cru ACLK_VOP_IEP>,
 686                                          <&cru DCLK_VOP>,
 687                                          <&cru HCLK_IEP>,
 688                                          <&cru HCLK_ISP>,
 689                                          <&cru HCLK_RGA>,
 690                                          <&cru HCLK_VIP>,
 691                                          <&cru HCLK_VOP>,
 692                                          <&cru HCLK_VIO_HDCPMMU>,
 693                                          <&cru PCLK_EDP_CTRL>,
 694                                          <&cru PCLK_HDMI_CTRL>,
 695                                          <&cru PCLK_HDCP>,
 696                                          <&cru PCLK_ISP>,
 697                                          <&cru PCLK_VIP>,
 698                                          <&cru PCLK_DPHYRX>,
 699                                          <&cru PCLK_DPHYTX0>,
 700                                          <&cru PCLK_MIPI_CSI>,
 701                                          <&cru PCLK_MIPI_DSI0>,
 702                                          <&cru SCLK_VOP0_PWM>,
 703                                          <&cru SCLK_EDP_24M>,
 704                                          <&cru SCLK_EDP>,
 705                                          <&cru SCLK_HDCP>,
 706                                          <&cru SCLK_ISP>,
 707                                          <&cru SCLK_RGA>,
 708                                          <&cru SCLK_HDMI_CEC>,
 709                                          <&cru SCLK_HDMI_HDCP>;
 710                         };
 711                         /*
 712                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 713                          * (video endecoder & decoder) clocks that on the
 714                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 715                          */
 716                         pd_video {
 717                                 reg = <RK3368_PD_VIDEO>;
 718                                 clocks = <&cru ACLK_VIDEO>,
 719                                          <&cru HCLK_VIDEO>,
 720                                          <&cru SCLK_HEVC_CABAC>,
 721                                          <&cru SCLK_HEVC_CORE>;
 722                         };
 723                         /*
 724                          * Note: ACLK_GPU is the GPU clock,
 725                          * and on the ACLK_GPU_NIU (NOC).
 726                          */
 727                         pd_gpu_1 {
 728                                 reg = <RK3368_PD_GPU_1>;
 729                                 clocks = <&cru ACLK_GPU_CFG>,
 730                                          <&cru ACLK_GPU_MEM>,
 731                                          <&cru SCLK_GPU_CORE>;
 732                         };
 733                 };
 734         };
 735
 736         pmugrf: syscon@ff738000 {
 737                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 738                 reg = <0x0 0xff738000 0x0 0x1000>;
 739
 740                 reboot-mode {
 741                         compatible = "syscon-reboot-mode";
 742                         offset = <0x200>;
 743                         mode-normal = <BOOT_NORMAL>;
 744                         mode-recovery = <BOOT_RECOVERY>;
 745                         mode-bootloader = <BOOT_FASTBOOT>;
 746                         mode-loader = <BOOT_LOADER>;
 747
 748                 };
 749         };
 750
 751         cru: clock-controller@ff760000 {
 752                 compatible = "rockchip,rk3368-cru";
 753                 reg = <0x0 0xff760000 0x0 0x1000>;
 754                 rockchip,grf = <&grf>;
 755                 #clock-cells = <1>;
 756                 #reset-cells = <1>;
 757                 assigned-clocks =
 758                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 759                         <&cru PLL_NPLL>,
 760                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
 761                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
 762                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
 763                 assigned-clock-rates =
 764                         <576000000>, <400000000>,
 765                         <1188000000>,
 766                         <300000000>, <300000000>,
 767                         <150000000>, <150000000>,
 768                         <75000000>, <75000000>;
 769         };
 770
 771         grf: syscon@ff770000 {
 772                 compatible = "rockchip,rk3368-grf", "syscon";
 773                 reg = <0x0 0xff770000 0x0 0x1000>;
 774         };
 775
 776         wdt: watchdog@ff800000 {
 777                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 778                 reg = <0x0 0xff800000 0x0 0x100>;
 779                 clocks = <&cru PCLK_WDT>;
 780                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 781                 status = "disabled";
 782         };
 783
 784         gic: interrupt-controller@ffb71000 {
 785                 compatible = "arm,gic-400";
 786                 interrupt-controller;
 787                 #interrupt-cells = <3>;
 788                 #address-cells = <0>;
 789
 790                 reg = <0x0 0xffb71000 0x0 0x1000>,
 791                       <0x0 0xffb72000 0x0 0x1000>,
 792                       <0x0 0xffb74000 0x0 0x2000>,
 793                       <0x0 0xffb76000 0x0 0x2000>;
 794                 interrupts = <GIC_PPI 9
 795                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 796         };
 797
 798         gpu: rogue-g6110@ffa30000 {
 799                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
 800                 reg = <0x0 0xffa30000 0x0 0x10000>;
 801                 clocks =
 802                         <&cru SCLK_GPU_CORE>,
 803                         <&cru ACLK_GPU_MEM>,
 804                         <&cru ACLK_GPU_CFG>;
 805                 clock-names =
 806                         "sclk_gpu_core",
 807                         "aclk_gpu_mem",
 808                         "aclk_gpu_cfg";
 809                 operating-points = <
 810                         /* KHz uV */
 811                         200000 1100000
 812                         288000 1100000
 813                         400000 1150000
 814                         576000 1200000
 815                 >;
 816                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 817                 interrupt-names = "rogue-g6110-irq";
 818         };
 819
 820         i2s_2ch: i2s-2ch@ff890000 {
 821                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 822                 reg = <0x0 0xff890000 0x0 0x1000>;
 823                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 824                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 825                 dma-names = "tx", "rx";
 826                 clock-names = "i2s_clk", "i2s_hclk";
 827                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 828                 status = "disabled";
 829         };
 830
 831         i2s_8ch: i2s-8ch@ff898000 {
 832                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 833                 reg = <0x0 0xff898000 0x0 0x1000>;
 834                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 835                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 836                 dma-names = "tx", "rx";
 837                 clock-names = "i2s_clk", "i2s_hclk";
 838                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 839                 pinctrl-names = "default";
 840                 pinctrl-0 = <&i2s_8ch_bus>;
 841                 status = "disabled";
 842         };
 843
 844         isp: isp@ff910000 {
 845                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
 846                 reg = <0x0 0xff910000 0x0 0x10000>;
 847                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 848                 /*power-domains = <&power PD_VIO>;*/
 849                 clocks =
 850                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
 851                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
 852                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
 853                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
 854                 clock-names =
 855                         "aclk_isp", "hclk_isp", "clk_isp",
 856                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
 857                         "clk_cif_pll", "hclk_mipiphy1",
 858                         "pclk_dphyrx", "clk_vio0_noc";
 859                 pinctrl-names =
 860                         "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
 861                         "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
 862                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 863                         "isp_flash_as_trigger_out";
 864                 pinctrl-0 = <&cif_clkout>;
 865                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
 866                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
 867                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
 868                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
 869                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
 870                 pinctrl-6 = <&cif_clkout>;
 871                 pinctrl-7 = <&cif_clkout &isp_prelight>;
 872                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
 873                 pinctrl-9 = <&isp_flash_trigger>;
 874                 rockchip,isp,mipiphy = <2>;
 875                 rockchip,isp,cifphy = <1>;
 876                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
 877                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
 878                 rockchip,grf = <&grf>;
 879                 rockchip,cru = <&cru>;
 880                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 881                 rockchip,isp,iommu_enable = <1>;
 882                 status = "disabled";
 883         };
 884
 885         rga: rga@ff920000 {
 886                 compatible = "rockchip,rga2";
 887                 dev_mode = <1>;
 888                 reg = <0x0 0xff920000 0x0 0x1000>;
 889                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 890                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 891                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 892                 status = "disabled";
 893         };
 894
 895         pinctrl: pinctrl {
 896                 compatible = "rockchip,rk3368-pinctrl";
 897                 rockchip,grf = <&grf>;
 898                 rockchip,pmu = <&pmugrf>;
 899                 #address-cells = <0x2>;
 900                 #size-cells = <0x2>;
 901                 ranges;
 902
 903                 gpio0: gpio0@ff750000 {
 904                         compatible = "rockchip,gpio-bank";
 905                         reg = <0x0 0xff750000 0x0 0x100>;
 906                         clocks = <&cru PCLK_GPIO0>;
 907                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 908
 909                         gpio-controller;
 910                         #gpio-cells = <0x2>;
 911
 912                         interrupt-controller;
 913                         #interrupt-cells = <0x2>;
 914                 };
 915
 916                 gpio1: gpio1@ff780000 {
 917                         compatible = "rockchip,gpio-bank";
 918                         reg = <0x0 0xff780000 0x0 0x100>;
 919                         clocks = <&cru PCLK_GPIO1>;
 920                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 921
 922                         gpio-controller;
 923                         #gpio-cells = <0x2>;
 924
 925                         interrupt-controller;
 926                         #interrupt-cells = <0x2>;
 927                 };
 928
 929                 gpio2: gpio2@ff790000 {
 930                         compatible = "rockchip,gpio-bank";
 931                         reg = <0x0 0xff790000 0x0 0x100>;
 932                         clocks = <&cru PCLK_GPIO2>;
 933                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
 934
 935                         gpio-controller;
 936                         #gpio-cells = <0x2>;
 937
 938                         interrupt-controller;
 939                         #interrupt-cells = <0x2>;
 940                 };
 941
 942                 gpio3: gpio3@ff7a0000 {
 943                         compatible = "rockchip,gpio-bank";
 944                         reg = <0x0 0xff7a0000 0x0 0x100>;
 945                         clocks = <&cru PCLK_GPIO3>;
 946                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
 947
 948                         gpio-controller;
 949                         #gpio-cells = <0x2>;
 950
 951                         interrupt-controller;
 952                         #interrupt-cells = <0x2>;
 953                 };
 954
 955                 pcfg_pull_up: pcfg-pull-up {
 956                         bias-pull-up;
 957                 };
 958
 959                 pcfg_pull_down: pcfg-pull-down {
 960                         bias-pull-down;
 961                 };
 962
 963                 pcfg_pull_none: pcfg-pull-none {
 964                         bias-disable;
 965                 };
 966
 967                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 968                         bias-disable;
 969                         drive-strength = <12>;
 970                 };
 971
 972                 emmc {
 973                         emmc_clk: emmc-clk {
 974                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 975                         };
 976
 977                         emmc_cmd: emmc-cmd {
 978                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
 979                         };
 980
 981                         emmc_pwr: emmc-pwr {
 982                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
 983                         };
 984
 985                         emmc_bus1: emmc-bus1 {
 986                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
 987                         };
 988
 989                         emmc_bus4: emmc-bus4 {
 990                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 991                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 992                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 993                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
 994                         };
 995
 996                         emmc_bus8: emmc-bus8 {
 997                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 998                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 999                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1000                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1001                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1002                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1003                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1004                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1005                         };
1006                 };
1007
1008                 gmac {
1009                         rgmii_pins: rgmii-pins {
1010                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1011                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1012                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1013                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1014                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1015                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1016                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1017                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1018                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1019                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1020                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1021                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1022                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1023                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1024                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1025                         };
1026
1027                         rmii_pins: rmii-pins {
1028                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1029                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1030                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1031                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1032                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1033                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1034                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1035                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1036                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1037                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1038                         };
1039                 };
1040
1041                 hdmi_i2c {
1042                         hdmii2c_xfer: hdmii2c-xfer {
1043                                 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1044                                                 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1045                         };
1046                 };
1047
1048                 hdmi_pin {
1049                         hdmi_cec: hdmi-cec {
1050                                 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1051                         };
1052                 };
1053
1054                 i2c0 {
1055                         i2c0_xfer: i2c0-xfer {
1056                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1057                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1058                         };
1059                 };
1060
1061                 i2c1 {
1062                         i2c1_xfer: i2c1-xfer {
1063                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1064                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1065                         };
1066                 };
1067
1068                 i2c2 {
1069                         i2c2_xfer: i2c2-xfer {
1070                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1071                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1072                         };
1073                 };
1074
1075                 i2c3 {
1076                         i2c3_xfer: i2c3-xfer {
1077                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1078                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1079                         };
1080                 };
1081
1082                 i2c4 {
1083                         i2c4_xfer: i2c4-xfer {
1084                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1085                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1086                         };
1087                 };
1088
1089                 i2c5 {
1090                         i2c5_xfer: i2c5-xfer {
1091                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1092                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1093                         };
1094                         i2c5_gpio: i2c5-gpio {
1095                                 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
1096                                                 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
1097                         };
1098                 };
1099
1100                 i2s {
1101                         i2s_8ch_bus: i2s-8ch-bus {
1102                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1103                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1104                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1105                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1106                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1107                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1108                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1109                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1110                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1111                         };
1112                 };
1113
1114                 sdio0 {
1115                         sdio0_bus1: sdio0-bus1 {
1116                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1117                         };
1118
1119                         sdio0_bus4: sdio0-bus4 {
1120                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1121                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1122                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1123                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1124                         };
1125
1126                         sdio0_cmd: sdio0-cmd {
1127                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1128                         };
1129
1130                         sdio0_clk: sdio0-clk {
1131                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1132                         };
1133
1134                         sdio0_cd: sdio0-cd {
1135                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1136                         };
1137
1138                         sdio0_wp: sdio0-wp {
1139                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1140                         };
1141
1142                         sdio0_pwr: sdio0-pwr {
1143                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1144                         };
1145
1146                         sdio0_bkpwr: sdio0-bkpwr {
1147                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1148                         };
1149
1150                         sdio0_int: sdio0-int {
1151                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1152                         };
1153                 };
1154
1155                 sdmmc {
1156                         sdmmc_clk: sdmmc-clk {
1157                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1158                         };
1159
1160                         sdmmc_cmd: sdmmc-cmd {
1161                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1162                         };
1163
1164                         sdmmc_cd: sdmcc-cd {
1165                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1166                         };
1167
1168                         sdmmc_bus1: sdmmc-bus1 {
1169                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1170                         };
1171
1172                         sdmmc_bus4: sdmmc-bus4 {
1173                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1174                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1175                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1176                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1177                         };
1178                 };
1179
1180                 spi0 {
1181                         spi0_clk: spi0-clk {
1182                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1183                         };
1184                         spi0_cs0: spi0-cs0 {
1185                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1186                         };
1187                         spi0_cs1: spi0-cs1 {
1188                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1189                         };
1190                         spi0_tx: spi0-tx {
1191                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1192                         };
1193                         spi0_rx: spi0-rx {
1194                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1195                         };
1196                 };
1197
1198                 spi1 {
1199                         spi1_clk: spi1-clk {
1200                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1201                         };
1202                         spi1_cs0: spi1-cs0 {
1203                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1204                         };
1205                         spi1_cs1: spi1-cs1 {
1206                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1207                         };
1208                         spi1_rx: spi1-rx {
1209                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1210                         };
1211                         spi1_tx: spi1-tx {
1212                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1213                         };
1214                 };
1215
1216                 spi2 {
1217                         spi2_clk: spi2-clk {
1218                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1219                         };
1220                         spi2_cs0: spi2-cs0 {
1221                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1222                         };
1223                         spi2_rx: spi2-rx {
1224                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1225                         };
1226                         spi2_tx: spi2-tx {
1227                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1228                         };
1229                 };
1230
1231                 uart0 {
1232                         uart0_xfer: uart0-xfer {
1233                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1234                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1235                         };
1236
1237                         uart0_cts: uart0-cts {
1238                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1239                         };
1240
1241                         uart0_rts: uart0-rts {
1242                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1243                         };
1244                 };
1245
1246                 uart1 {
1247                         uart1_xfer: uart1-xfer {
1248                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1249                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1250                         };
1251
1252                         uart1_cts: uart1-cts {
1253                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1254                         };
1255
1256                         uart1_rts: uart1-rts {
1257                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1258                         };
1259                 };
1260
1261                 uart2 {
1262                         uart2_xfer: uart2-xfer {
1263                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1264                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1265                         };
1266                         /* no rts / cts for uart2 */
1267                 };
1268
1269                 uart3 {
1270                         uart3_xfer: uart3-xfer {
1271                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1272                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1273                         };
1274
1275                         uart3_cts: uart3-cts {
1276                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1277                         };
1278
1279                         uart3_rts: uart3-rts {
1280                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1281                         };
1282                 };
1283
1284                 uart4 {
1285                         uart4_xfer: uart4-xfer {
1286                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1287                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1288                         };
1289
1290                         uart4_cts: uart4-cts {
1291                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1292                         };
1293
1294                         uart4_rts: uart4-rts {
1295                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1296                         };
1297                 };
1298
1299                 pwm0 {
1300                         pwm0_pin: pwm0-pin {
1301                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1302                         };
1303
1304                         vop_pwm_pin: vop-pwm {
1305                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1306                         };
1307                 };
1308
1309                 pwm1 {
1310                         pwm1_pin: pwm1-pin {
1311                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1312                         };
1313                 };
1314
1315                 pwm3 {
1316                         pwm3_pin: pwm3-pin {
1317                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1318                         };
1319                 };
1320
1321                 lcdc {
1322                         lcdc_lcdc: lcdc-lcdc {
1323                                 rockchip,pins =
1324                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1325                                                 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1326                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1327                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1328                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1329                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1330                                                 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1331                                                 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1332                                                 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1333                                                 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1334                                                 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1335                                                 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1336                                                 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1337                                                 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1338                                                 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1339                                                 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1340                                                 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1341                                                 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1342                         };
1343
1344                         lcdc_gpio: lcdc-gpio {
1345                                 rockchip,pins =
1346                                                 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1347                                                 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1348                                                 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1349                                                 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1350                                                 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1351                                                 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1352                                                 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1353                                                 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1354                                                 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1355                                                 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1356                                                 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1357                                                 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1358                                                 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1359                                                 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1360                                                 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1361                                                 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1362                                                 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1363                                                 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1364                         };
1365                 };
1366
1367                 isp {
1368                         cif_clkout: cif-clkout {
1369                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1370                         };
1371
1372                         isp_dvp_d2d9: isp-dvp-d2d9 {
1373                                 rockchip,pins =
1374                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1375                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1376                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1377                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1378                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1379                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1380                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1381                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1382                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1383                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1384                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1385                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1386                         };
1387
1388                         isp_dvp_d0d1: isp-dvp-d0d1 {
1389                                 rockchip,pins =
1390                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1391                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1392                         };
1393
1394                         isp_dvp_d10d11:isp_d10d11 {
1395                                 rockchip,pins =
1396                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1397                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1398                         };
1399
1400                         isp_dvp_d0d7: isp-dvp-d0d7 {
1401                                 rockchip,pins =
1402                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1403                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1404                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1405                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1406                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1407                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1408                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1409                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1410                         };
1411
1412                         isp_dvp_d4d11: isp-dvp-d4d11 {
1413                                 rockchip,pins =
1414                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1415                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1416                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1417                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1418                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1419                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1420                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1421                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1422                         };
1423
1424                         isp_shutter: isp-shutter {
1425                                 rockchip,pins =
1426                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1427                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1428                         };
1429
1430                         isp_flash_trigger: isp-flash-trigger {
1431                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1432                         };
1433
1434                         isp_prelight: isp-prelight {
1435                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1436                         };
1437
1438                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1439                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1440                         };
1441                 };
1442         };
1443
1444         fb: fb {
1445                 compatible = "rockchip,rk-fb";
1446                 rockchip,disp-mode = <NO_DUAL>;
1447                 status = "disabled";
1448         };
1449
1450         rk_screen: screen {
1451                 compatible = "rockchip,screen";
1452                 status = "disabled";
1453         };
1454
1455         lcdc: lcdc@ff930000 {
1456                 compatible = "rockchip,rk3368-lcdc";
1457                 rockchip,grf = <&grf>;
1458                 rockchip,pmugrf = <&pmugrf>;
1459                 rockchip,cru = <&cru>;
1460                 rockchip,prop = <PRMRY>;
1461                 rockchip,pwr18 = <0>;
1462                 rockchip,iommu-enabled = <1>;
1463                 reg = <0x0 0xff930000 0x0 0x10000>;
1464                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1465                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1466                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1467                 /*power-domains = <&power PD_VIO>;*/
1468                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1469                 reset-names = "axi", "ahb", "dclk";
1470                 status = "disabled";
1471         };
1472
1473         mipi: mipi@ff960000 {
1474                 compatible = "rockchip,rk3368-dsi";
1475                 rockchip,prop = <0>;
1476                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1477                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1478                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1479                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1480                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1481                 /*power-domains = <&power PD_VIO>;*/
1482                 status = "disabled";
1483         };
1484
1485         lvds: lvds@ff968000 {
1486                 compatible = "rockchip,rk3368-lvds";
1487                 rockchip,grf = <&grf>;
1488                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1489                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1490                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1491                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1492                 /*power-domains = <&power PD_VIO>;*/
1493                 status = "disabled";
1494         };
1495
1496         edp: edp@ff970000 {
1497                 compatible = "rockchip,rk32-edp";
1498                 reg = <0x0 0xff970000 0x0 0x4000>;
1499                 rockchip,grf = <&grf>;
1500                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1501                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1502                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1503                 /*power-domains = <&power PD_VIO>;*/
1504                 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1505                 reset-names = "edp_24m", "edp_apb";
1506                 status = "disabled";
1507         };
1508
1509         hdmi: hdmi@ff980000 {
1510                 compatible = "rockchip,rk3368-hdmi";
1511                 reg = <0x0 0xff980000 0x0 0x20000>;
1512                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1513                 clocks = <&cru PCLK_HDMI_CTRL>,
1514                          <&cru SCLK_HDMI_HDCP>,
1515                          <&cru SCLK_HDMI_CEC>;
1516                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
1517                 /*power-domains = <&power PD_VIO>;*/
1518                 resets = <&cru SRST_HDMI>;
1519                 reset-names = "hdmi";
1520                 pinctrl-names = "default", "gpio";
1521                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1522                 pinctrl-1 = <&i2c5_gpio>;
1523                 status = "disabled";
1524         };
1525
1526         iep_mmu: iep-mmu {
1527                 dbgname = "iep";
1528                 compatible = "rockchip,iep_mmu";
1529                 reg = <0x0 0xff900800 0x0 0x100>;
1530                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1531                 interrupt-names = "iep_mmu";
1532                 status = "disabled";
1533         };
1534
1535         vip_mmu: vip-mmu {
1536                 dbgname = "vip";
1537                 compatible = "rockchip,vip_mmu";
1538                 reg = <0x0 0xff950800 0x0 0x100>;
1539                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1540                 interrupt-names = "vip_mmu";
1541                 status = "disabled";
1542         };
1543
1544         vopb_mmu: vopb-mmu {
1545                 dbgname = "vop";
1546                 compatible = "rockchip,vopb_mmu";
1547                 reg = <0x0 0xff930300 0x0 0x100>;
1548                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1549                 interrupt-names = "vop_mmu";
1550                 status = "disabled";
1551         };
1552
1553         isp_mmu: isp-mmu {
1554                 dbgname = "isp_mmu";
1555                 compatible = "rockchip,isp_mmu";
1556                 reg = <0x0 0xff914000 0x0 0x100>,
1557                       <0x0 0xff915000 0x0 0x100>;
1558                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1559                 interrupt-names = "isp_mmu";
1560                 status = "disabled";
1561         };
1562
1563         hdcp_mmu: hdcp-mmu {
1564                  dbgname = "hdcp_mmu";
1565                  compatible = "rockchip,hdcp_mmu";
1566                  reg = <0x0 0xff940000 0x0 0x100>;
1567                  interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1568                  interrupt-names = "hdcp_mmu";
1569                 status = "disabled";
1570         };
1571
1572         hevc_mmu: hevc-mmu {
1573                 dbgname = "hevc";
1574                 compatible = "rockchip,hevc_mmu";
1575                 reg = <0x0 0xff9a0440 0x0 0x40>,
1576                       <0x0 0xff9a0480 0x0 0x40>;
1577                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1578                 interrupt-names = "hevc_mmu";
1579                 status = "disabled";
1580         };
1581
1582         vpu_mmu: vpu-mmu {
1583                 dbgname = "vpu";
1584                 compatible = "rockchip,vpu_mmu";
1585                 reg = <0x0 0xff9a0800 0x0 0x100>;
1586                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1587                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1588                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1589                 status = "disabled";
1590         };
1591 };