2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/power/rk3368-power.h>
50 #include <dt-bindings/soc/rockchip_boot-mode.h>
53 compatible = "rockchip,rk3368";
54 interrupt-parent = <&gic>;
77 #address-cells = <0x2>;
113 entry-method = "psci";
115 cpu_sleep: cpu-sleep-0 {
116 compatible = "arm,idle-state";
117 arm,psci-suspend-param = <0x1010000>;
118 entry-latency-us = <0x3fffffff>;
119 exit-latency-us = <0x40000000>;
120 min-residency-us = <0xffffffff>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 cpu-idle-states = <&cpu_sleep>;
129 enable-method = "psci";
130 clocks = <&cru ARMCLKL>;
131 operating-points-v2 = <&cluster1_opp>;
136 compatible = "arm,cortex-a53", "arm,armv8";
138 cpu-idle-states = <&cpu_sleep>;
139 enable-method = "psci";
140 clocks = <&cru ARMCLKL>;
141 operating-points-v2 = <&cluster1_opp>;
146 compatible = "arm,cortex-a53", "arm,armv8";
148 cpu-idle-states = <&cpu_sleep>;
149 enable-method = "psci";
150 clocks = <&cru ARMCLKL>;
151 operating-points-v2 = <&cluster1_opp>;
156 compatible = "arm,cortex-a53", "arm,armv8";
158 cpu-idle-states = <&cpu_sleep>;
159 enable-method = "psci";
160 clocks = <&cru ARMCLKL>;
161 operating-points-v2 = <&cluster1_opp>;
166 compatible = "arm,cortex-a53", "arm,armv8";
168 cpu-idle-states = <&cpu_sleep>;
169 enable-method = "psci";
170 clocks = <&cru ARMCLKB>;
171 operating-points-v2 = <&cluster0_opp>;
176 compatible = "arm,cortex-a53", "arm,armv8";
178 cpu-idle-states = <&cpu_sleep>;
179 enable-method = "psci";
180 clocks = <&cru ARMCLKB>;
181 operating-points-v2 = <&cluster0_opp>;
186 compatible = "arm,cortex-a53", "arm,armv8";
188 cpu-idle-states = <&cpu_sleep>;
189 enable-method = "psci";
190 clocks = <&cru ARMCLKB>;
191 operating-points-v2 = <&cluster0_opp>;
196 compatible = "arm,cortex-a53", "arm,armv8";
198 cpu-idle-states = <&cpu_sleep>;
199 enable-method = "psci";
200 clocks = <&cru ARMCLKB>;
201 operating-points-v2 = <&cluster0_opp>;
205 cluster0_opp: opp_table0 {
206 compatible = "operating-points-v2";
210 opp-hz = /bits/ 64 <408000000>;
211 opp-microvolt = <1200000>;
212 clock-latency-ns = <40000>;
216 opp-hz = /bits/ 64 <600000000>;
217 opp-microvolt = <1200000>;
220 opp-hz = /bits/ 64 <816000000>;
221 opp-microvolt = <1200000>;
224 opp-hz = /bits/ 64 <1008000000>;
225 opp-microvolt = <1200000>;
228 opp-hz = /bits/ 64 <1200000000>;
229 opp-microvolt = <1200000>;
233 cluster1_opp: opp_table1 {
234 compatible = "operating-points-v2";
238 opp-hz = /bits/ 64 <408000000>;
239 opp-microvolt = <1200000>;
240 clock-latency-ns = <40000>;
244 opp-hz = /bits/ 64 <600000000>;
245 opp-microvolt = <1200000>;
248 opp-hz = /bits/ 64 <816000000>;
249 opp-microvolt = <1200000>;
252 opp-hz = /bits/ 64 <1008000000>;
253 opp-microvolt = <1200000>;
258 compatible = "arm,armv8-pmuv3";
259 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
267 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
268 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
269 <&cpu_b2>, <&cpu_b3>;
273 compatible = "arm,amba-bus";
274 #address-cells = <2>;
278 dmac_peri: dma-controller@ff250000 {
279 compatible = "arm,pl330", "arm,primecell";
280 reg = <0x0 0xff250000 0x0 0x4000>;
281 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&cru ACLK_DMAC_PERI>;
285 clock-names = "apb_pclk";
288 dmac_bus: dma-controller@ff600000 {
289 compatible = "arm,pl330", "arm,primecell";
290 reg = <0x0 0xff600000 0x0 0x4000>;
291 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&cru ACLK_DMAC_BUS>;
295 clock-names = "apb_pclk";
300 compatible = "arm,psci-0.2";
305 compatible = "arm,armv8-timer";
306 interrupts = <GIC_PPI 13
307 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
309 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
311 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
313 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
317 compatible = "fixed-clock";
318 clock-frequency = <24000000>;
319 clock-output-names = "xin24m";
323 sdmmc: rksdmmc@ff0c0000 {
324 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
325 reg = <0x0 0xff0c0000 0x0 0x4000>;
326 clock-freq-min-max = <400000 150000000>;
327 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
328 clock-names = "biu", "ciu";
329 fifo-depth = <0x100>;
330 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
334 sdio0: dwmmc@ff0d0000 {
335 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
336 reg = <0x0 0xff0d0000 0x0 0x4000>;
337 clock-freq-min-max = <400000 150000000>;
338 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
339 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
340 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
341 fifo-depth = <0x100>;
342 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
346 emmc: rksdmmc@ff0f0000 {
347 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
348 reg = <0x0 0xff0f0000 0x0 0x4000>;
349 clock-freq-min-max = <400000 150000000>;
350 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
351 clock-names = "biu", "ciu";
352 fifo-depth = <0x100>;
353 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
357 saradc: saradc@ff100000 {
358 compatible = "rockchip,saradc";
359 reg = <0x0 0xff100000 0x0 0x100>;
360 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
361 #io-channel-cells = <1>;
362 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
363 clock-names = "saradc", "apb_pclk";
368 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
369 reg = <0x0 0xff110000 0x0 0x1000>;
370 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
371 clock-names = "spiclk", "apb_pclk";
372 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
375 #address-cells = <1>;
381 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
382 reg = <0x0 0xff120000 0x0 0x1000>;
383 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
384 clock-names = "spiclk", "apb_pclk";
385 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
388 #address-cells = <1>;
394 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
395 reg = <0x0 0xff130000 0x0 0x1000>;
396 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
397 clock-names = "spiclk", "apb_pclk";
398 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
401 #address-cells = <1>;
407 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
408 reg = <0x0 0xff650000 0x0 0x1000>;
409 clocks = <&cru PCLK_I2C0>;
411 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&i2c0_xfer>;
414 #address-cells = <1>;
420 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
421 reg = <0x0 0xff140000 0x0 0x1000>;
422 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
423 #address-cells = <1>;
426 clocks = <&cru PCLK_I2C2>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&i2c2_xfer>;
433 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
434 reg = <0x0 0xff150000 0x0 0x1000>;
435 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
436 #address-cells = <1>;
439 clocks = <&cru PCLK_I2C3>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&i2c3_xfer>;
446 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
447 reg = <0x0 0xff160000 0x0 0x1000>;
448 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
449 #address-cells = <1>;
452 clocks = <&cru PCLK_I2C4>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&i2c4_xfer>;
459 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
460 reg = <0x0 0xff170000 0x0 0x1000>;
461 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
462 #address-cells = <1>;
465 clocks = <&cru PCLK_I2C5>;
466 pinctrl-names = "default";
467 pinctrl-0 = <&i2c5_xfer>;
471 uart0: serial@ff180000 {
472 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
473 reg = <0x0 0xff180000 0x0 0x100>;
474 clock-frequency = <24000000>;
475 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
476 clock-names = "baudclk", "apb_pclk";
477 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
483 uart1: serial@ff190000 {
484 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
485 reg = <0x0 0xff190000 0x0 0x100>;
486 clock-frequency = <24000000>;
487 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
488 clock-names = "baudclk", "apb_pclk";
489 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
495 uart3: serial@ff1b0000 {
496 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
497 reg = <0x0 0xff1b0000 0x0 0x100>;
498 clock-frequency = <24000000>;
499 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
500 clock-names = "baudclk", "apb_pclk";
501 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
507 uart4: serial@ff1c0000 {
508 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
509 reg = <0x0 0xff1c0000 0x0 0x100>;
510 clock-frequency = <24000000>;
511 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
512 clock-names = "baudclk", "apb_pclk";
513 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
519 gmac: ethernet@ff290000 {
520 compatible = "rockchip,rk3368-gmac";
521 reg = <0x0 0xff290000 0x0 0x10000>;
522 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
523 interrupt-names = "macirq";
524 rockchip,grf = <&grf>;
525 clocks = <&cru SCLK_MAC>,
526 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
527 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
528 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
529 clock-names = "stmmaceth",
530 "mac_clk_rx", "mac_clk_tx",
531 "clk_mac_ref", "clk_mac_refout",
532 "aclk_mac", "pclk_mac";
536 nandc0: nandc@ff400000 {
537 compatible = "rockchip,rk-nandc";
538 reg = <0x0 0xff400000 0x0 0x4000>;
539 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
542 clock-names = "clk_nandc", "hclk_nandc";
546 usb_host0_ehci: usb@ff500000 {
547 compatible = "generic-ehci";
548 reg = <0x0 0xff500000 0x0 0x100>;
549 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&cru HCLK_HOST0>;
551 clock-names = "usbhost";
555 usb_otg: usb@ff580000 {
556 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
558 reg = <0x0 0xff580000 0x0 0x40000>;
559 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&cru HCLK_OTG0>;
563 g-np-tx-fifo-size = <16>;
564 g-rx-fifo-size = <275>;
565 g-tx-fifo-size = <256 128 128 64 64 32>;
570 ddrpctl: syscon@ff610000 {
571 compatible = "rockchip,rk3368-ddrpctl", "syscon";
572 reg = <0x0 0xff610000 0x0 0x400>;
576 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
577 reg = <0x0 0xff660000 0x0 0x1000>;
578 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
579 #address-cells = <1>;
582 clocks = <&cru PCLK_I2C1>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&i2c1_xfer>;
589 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
590 reg = <0x0 0xff680000 0x0 0x10>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&pwm0_pin>;
594 clocks = <&cru PCLK_PWM1>;
600 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
601 reg = <0x0 0xff680010 0x0 0x10>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&pwm1_pin>;
605 clocks = <&cru PCLK_PWM1>;
611 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
612 reg = <0x0 0xff680020 0x0 0x10>;
614 clocks = <&cru PCLK_PWM1>;
620 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
621 reg = <0x0 0xff680030 0x0 0x10>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&pwm3_pin>;
625 clocks = <&cru PCLK_PWM1>;
630 uart2: serial@ff690000 {
631 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
632 reg = <0x0 0xff690000 0x0 0x100>;
633 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
634 clock-names = "baudclk", "apb_pclk";
635 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
636 pinctrl-names = "default";
637 pinctrl-0 = <&uart2_xfer>;
643 pmu: power-management@ff730000 {
644 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
645 reg = <0x0 0xff730000 0x0 0x1000>;
647 power: power-controller {
649 compatible = "rockchip,rk3368-power-controller";
650 #power-domain-cells = <1>;
651 #address-cells = <1>;
655 * Note: Although SCLK_* are the working clocks
656 * of device without including on the NOC, needed for
659 * The clocks on the which NOC:
660 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
661 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
662 * ACLK_RGA is on ACLK_RGA_NIU.
663 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
665 * Which clock are device clocks:
667 * *_IEP IEP:Image Enhancement Processor
668 * *_ISP ISP:Image Signal Processing
669 * *_VIP VIP:Video Input Processor
670 * *_VOP* VOP:Visual Output Processor
678 reg = <RK3368_PD_VIO>;
679 clocks = <&cru ACLK_IEP>,
691 <&cru HCLK_VIO_HDCPMMU>,
692 <&cru PCLK_EDP_CTRL>,
693 <&cru PCLK_HDMI_CTRL>,
699 <&cru PCLK_MIPI_CSI>,
700 <&cru PCLK_MIPI_DSI0>,
701 <&cru SCLK_VOP0_PWM>,
707 <&cru SCLK_HDMI_CEC>,
708 <&cru SCLK_HDMI_HDCP>;
711 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
712 * (video endecoder & decoder) clocks that on the
713 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
716 reg = <RK3368_PD_VIDEO>;
717 clocks = <&cru ACLK_VIDEO>,
719 <&cru SCLK_HEVC_CABAC>,
720 <&cru SCLK_HEVC_CORE>;
723 * Note: ACLK_GPU is the GPU clock,
724 * and on the ACLK_GPU_NIU (NOC).
727 reg = <RK3368_PD_GPU_1>;
728 clocks = <&cru ACLK_GPU_CFG>,
730 <&cru SCLK_GPU_CORE>;
735 pmugrf: syscon@ff738000 {
736 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
737 reg = <0x0 0xff738000 0x0 0x1000>;
740 compatible = "syscon-reboot-mode";
742 mode-normal = <BOOT_NORMAL>;
743 mode-recovery = <BOOT_RECOVERY>;
744 mode-bootloader = <BOOT_FASTBOOT>;
745 mode-loader = <BOOT_LOADER>;
750 cru: clock-controller@ff760000 {
751 compatible = "rockchip,rk3368-cru";
752 reg = <0x0 0xff760000 0x0 0x1000>;
753 rockchip,grf = <&grf>;
757 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
759 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
760 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
761 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
762 assigned-clock-rates =
763 <576000000>, <400000000>,
765 <300000000>, <300000000>,
766 <150000000>, <150000000>,
767 <75000000>, <75000000>;
770 grf: syscon@ff770000 {
771 compatible = "rockchip,rk3368-grf", "syscon";
772 reg = <0x0 0xff770000 0x0 0x1000>;
775 wdt: watchdog@ff800000 {
776 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
777 reg = <0x0 0xff800000 0x0 0x100>;
778 clocks = <&cru PCLK_WDT>;
779 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
783 gic: interrupt-controller@ffb71000 {
784 compatible = "arm,gic-400";
785 interrupt-controller;
786 #interrupt-cells = <3>;
787 #address-cells = <0>;
789 reg = <0x0 0xffb71000 0x0 0x1000>,
790 <0x0 0xffb72000 0x0 0x1000>,
791 <0x0 0xffb74000 0x0 0x2000>,
792 <0x0 0xffb76000 0x0 0x2000>;
793 interrupts = <GIC_PPI 9
794 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
797 gpu: rogue-g6110@ffa30000 {
798 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
799 reg = <0x0 0xffa30000 0x0 0x10000>;
801 <&cru SCLK_GPU_CORE>,
815 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
816 interrupt-names = "rogue-g6110-irq";
819 i2s_2ch: i2s-2ch@ff890000 {
820 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
821 reg = <0x0 0xff890000 0x0 0x1000>;
822 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
823 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
824 dma-names = "tx", "rx";
825 clock-names = "i2s_clk", "i2s_hclk";
826 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
830 i2s_8ch: i2s-8ch@ff898000 {
831 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
832 reg = <0x0 0xff898000 0x0 0x1000>;
833 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
834 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
835 dma-names = "tx", "rx";
836 clock-names = "i2s_clk", "i2s_hclk";
837 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
838 pinctrl-names = "default";
839 pinctrl-0 = <&i2s_8ch_bus>;
844 compatible = "rockchip,rk3368-isp", "rockchip,isp";
845 reg = <0x0 0xff910000 0x0 0x10000>;
846 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
847 /*power-domains = <&power PD_VIO>;*/
849 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
850 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
851 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
852 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
854 "aclk_isp", "hclk_isp", "clk_isp",
855 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
856 "clk_cif_pll", "hclk_mipiphy1",
857 "pclk_dphyrx", "clk_vio0_noc";
859 "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
860 "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
861 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
862 "isp_flash_as_trigger_out";
863 pinctrl-0 = <&cif_clkout>;
864 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
865 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
866 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
867 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
868 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
869 pinctrl-6 = <&cif_clkout>;
870 pinctrl-7 = <&cif_clkout &isp_prelight>;
871 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
872 pinctrl-9 = <&isp_flash_trigger>;
873 rockchip,isp,mipiphy = <2>;
874 rockchip,isp,cifphy = <1>;
875 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
876 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
877 rockchip,grf = <&grf>;
878 rockchip,cru = <&cru>;
879 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
880 rockchip,isp,iommu_enable = <1>;
885 compatible = "rockchip,rga2";
887 reg = <0x0 0xff920000 0x0 0x1000>;
888 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
890 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
895 compatible = "rockchip,rk3368-pinctrl";
896 rockchip,grf = <&grf>;
897 rockchip,pmu = <&pmugrf>;
898 #address-cells = <0x2>;
902 gpio0: gpio0@ff750000 {
903 compatible = "rockchip,gpio-bank";
904 reg = <0x0 0xff750000 0x0 0x100>;
905 clocks = <&cru PCLK_GPIO0>;
906 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
911 interrupt-controller;
912 #interrupt-cells = <0x2>;
915 gpio1: gpio1@ff780000 {
916 compatible = "rockchip,gpio-bank";
917 reg = <0x0 0xff780000 0x0 0x100>;
918 clocks = <&cru PCLK_GPIO1>;
919 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
924 interrupt-controller;
925 #interrupt-cells = <0x2>;
928 gpio2: gpio2@ff790000 {
929 compatible = "rockchip,gpio-bank";
930 reg = <0x0 0xff790000 0x0 0x100>;
931 clocks = <&cru PCLK_GPIO2>;
932 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
937 interrupt-controller;
938 #interrupt-cells = <0x2>;
941 gpio3: gpio3@ff7a0000 {
942 compatible = "rockchip,gpio-bank";
943 reg = <0x0 0xff7a0000 0x0 0x100>;
944 clocks = <&cru PCLK_GPIO3>;
945 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
950 interrupt-controller;
951 #interrupt-cells = <0x2>;
954 pcfg_pull_up: pcfg-pull-up {
958 pcfg_pull_down: pcfg-pull-down {
962 pcfg_pull_none: pcfg-pull-none {
966 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
968 drive-strength = <12>;
973 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
977 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
981 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
984 emmc_bus1: emmc-bus1 {
985 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
988 emmc_bus4: emmc-bus4 {
989 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
990 <1 19 RK_FUNC_2 &pcfg_pull_up>,
991 <1 20 RK_FUNC_2 &pcfg_pull_up>,
992 <1 21 RK_FUNC_2 &pcfg_pull_up>;
995 emmc_bus8: emmc-bus8 {
996 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
997 <1 19 RK_FUNC_2 &pcfg_pull_up>,
998 <1 20 RK_FUNC_2 &pcfg_pull_up>,
999 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1000 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1001 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1002 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1003 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1008 rgmii_pins: rgmii-pins {
1009 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1010 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1011 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1012 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1013 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1014 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1015 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1016 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1017 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1018 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1019 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1020 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1021 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1022 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1023 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1026 rmii_pins: rmii-pins {
1027 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1028 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1029 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1030 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1031 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1032 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1033 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1034 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1035 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1036 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1041 hdmii2c_xfer: hdmii2c-xfer {
1042 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1043 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1048 hdmi_cec: hdmi-cec {
1049 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1054 i2c0_xfer: i2c0-xfer {
1055 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1056 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1061 i2c1_xfer: i2c1-xfer {
1062 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1063 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1068 i2c2_xfer: i2c2-xfer {
1069 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1070 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1075 i2c3_xfer: i2c3-xfer {
1076 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1077 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1082 i2c4_xfer: i2c4-xfer {
1083 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1084 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1089 i2c5_xfer: i2c5-xfer {
1090 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1091 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1093 i2c5_gpio: i2c5-gpio {
1094 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
1095 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
1100 i2s_8ch_bus: i2s-8ch-bus {
1101 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1102 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1103 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1104 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1105 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1106 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1107 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1108 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1109 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1114 sdio0_bus1: sdio0-bus1 {
1115 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1118 sdio0_bus4: sdio0-bus4 {
1119 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1120 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1121 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1122 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1125 sdio0_cmd: sdio0-cmd {
1126 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1129 sdio0_clk: sdio0-clk {
1130 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1133 sdio0_cd: sdio0-cd {
1134 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1137 sdio0_wp: sdio0-wp {
1138 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1141 sdio0_pwr: sdio0-pwr {
1142 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1145 sdio0_bkpwr: sdio0-bkpwr {
1146 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1149 sdio0_int: sdio0-int {
1150 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1155 sdmmc_clk: sdmmc-clk {
1156 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1159 sdmmc_cmd: sdmmc-cmd {
1160 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1163 sdmmc_cd: sdmcc-cd {
1164 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1167 sdmmc_bus1: sdmmc-bus1 {
1168 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1171 sdmmc_bus4: sdmmc-bus4 {
1172 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1173 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1174 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1175 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1180 spi0_clk: spi0-clk {
1181 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1183 spi0_cs0: spi0-cs0 {
1184 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1186 spi0_cs1: spi0-cs1 {
1187 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1190 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1193 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1198 spi1_clk: spi1-clk {
1199 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1201 spi1_cs0: spi1-cs0 {
1202 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1204 spi1_cs1: spi1-cs1 {
1205 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1208 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1211 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1216 spi2_clk: spi2-clk {
1217 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1219 spi2_cs0: spi2-cs0 {
1220 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1223 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1226 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1231 uart0_xfer: uart0-xfer {
1232 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1233 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1236 uart0_cts: uart0-cts {
1237 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1240 uart0_rts: uart0-rts {
1241 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1246 uart1_xfer: uart1-xfer {
1247 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1248 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1251 uart1_cts: uart1-cts {
1252 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1255 uart1_rts: uart1-rts {
1256 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1261 uart2_xfer: uart2-xfer {
1262 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1263 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1265 /* no rts / cts for uart2 */
1269 uart3_xfer: uart3-xfer {
1270 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1271 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1274 uart3_cts: uart3-cts {
1275 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1278 uart3_rts: uart3-rts {
1279 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1284 uart4_xfer: uart4-xfer {
1285 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1286 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1289 uart4_cts: uart4-cts {
1290 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1293 uart4_rts: uart4-rts {
1294 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1299 pwm0_pin: pwm0-pin {
1300 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1303 vop_pwm_pin: vop-pwm {
1304 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1309 pwm1_pin: pwm1-pin {
1310 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1315 pwm3_pin: pwm3-pin {
1316 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1321 lcdc_lcdc: lcdc-lcdc {
1323 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1324 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1325 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1326 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1327 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1328 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1329 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1330 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1331 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1332 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1333 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1334 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1335 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1336 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1337 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1338 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1339 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1340 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1343 lcdc_gpio: lcdc-gpio {
1345 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1346 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1347 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1348 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1349 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1350 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1351 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1352 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1353 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1354 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1355 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1356 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1357 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1358 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1359 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1360 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1361 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1362 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1367 cif_clkout: cif-clkout {
1368 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1371 isp_dvp_d2d9: isp-dvp-d2d9 {
1373 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1374 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1375 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1376 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1377 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1378 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1379 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1380 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1381 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1382 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1383 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1384 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1387 isp_dvp_d0d1: isp-dvp-d0d1 {
1389 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1390 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1393 isp_dvp_d10d11:isp_d10d11 {
1395 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1396 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1399 isp_dvp_d0d7: isp-dvp-d0d7 {
1401 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1402 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1403 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1404 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1405 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1406 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1407 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1408 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1411 isp_dvp_d4d11: isp-dvp-d4d11 {
1413 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1414 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1415 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1416 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1417 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1418 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1419 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1420 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1423 isp_shutter: isp-shutter {
1425 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1426 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1429 isp_flash_trigger: isp-flash-trigger {
1430 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1433 isp_prelight: isp-prelight {
1434 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1437 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1438 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1444 compatible = "rockchip,rk-fb";
1445 rockchip,disp-mode = <NO_DUAL>;
1446 status = "disabled";
1450 compatible = "rockchip,screen";
1451 status = "disabled";
1454 lcdc: lcdc@ff930000 {
1455 compatible = "rockchip,rk3368-lcdc";
1456 rockchip,grf = <&grf>;
1457 rockchip,pmugrf = <&pmugrf>;
1458 rockchip,cru = <&cru>;
1459 rockchip,prop = <PRMRY>;
1460 rockchip,pwr18 = <0>;
1461 rockchip,iommu-enabled = <1>;
1462 reg = <0x0 0xff930000 0x0 0x10000>;
1463 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1464 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1465 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1466 /*power-domains = <&power PD_VIO>;*/
1467 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1468 reset-names = "axi", "ahb", "dclk";
1469 status = "disabled";
1472 mipi: mipi@ff960000 {
1473 compatible = "rockchip,rk3368-dsi";
1474 rockchip,prop = <0>;
1475 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1476 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1477 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1478 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1479 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1480 /*power-domains = <&power PD_VIO>;*/
1481 status = "disabled";
1484 lvds: lvds@ff968000 {
1485 compatible = "rockchip,rk3368-lvds";
1486 rockchip,grf = <&grf>;
1487 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1488 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1489 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1490 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1491 /*power-domains = <&power PD_VIO>;*/
1492 status = "disabled";
1496 compatible = "rockchip,rk32-edp";
1497 reg = <0x0 0xff970000 0x0 0x4000>;
1498 rockchip,grf = <&grf>;
1499 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1500 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1501 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1502 /*power-domains = <&power PD_VIO>;*/
1503 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1504 reset-names = "edp_24m", "edp_apb";
1505 status = "disabled";
1508 hdmi: hdmi@ff980000 {
1509 compatible = "rockchip,rk3368-hdmi";
1510 reg = <0x0 0xff980000 0x0 0x20000>;
1511 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1512 clocks = <&cru PCLK_HDMI_CTRL>,
1513 <&cru SCLK_HDMI_HDCP>,
1514 <&cru SCLK_HDMI_CEC>;
1515 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
1516 /*power-domains = <&power PD_VIO>;*/
1517 resets = <&cru SRST_HDMI>;
1518 reset-names = "hdmi";
1519 pinctrl-names = "default", "gpio";
1520 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1521 pinctrl-1 = <&i2c5_gpio>;
1522 status = "disabled";
1527 compatible = "rockchip,iep_mmu";
1528 reg = <0x0 0xff900800 0x0 0x100>;
1529 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1530 interrupt-names = "iep_mmu";
1531 status = "disabled";
1536 compatible = "rockchip,vip_mmu";
1537 reg = <0x0 0xff950800 0x0 0x100>;
1538 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1539 interrupt-names = "vip_mmu";
1540 status = "disabled";
1543 vopb_mmu: vopb-mmu {
1545 compatible = "rockchip,vopb_mmu";
1546 reg = <0x0 0xff930300 0x0 0x100>;
1547 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1548 interrupt-names = "vop_mmu";
1549 status = "disabled";
1553 dbgname = "isp_mmu";
1554 compatible = "rockchip,isp_mmu";
1555 reg = <0x0 0xff914000 0x0 0x100>,
1556 <0x0 0xff915000 0x0 0x100>;
1557 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1558 interrupt-names = "isp_mmu";
1559 status = "disabled";
1562 hdcp_mmu: hdcp-mmu {
1563 dbgname = "hdcp_mmu";
1564 compatible = "rockchip,hdcp_mmu";
1565 reg = <0x0 0xff940000 0x0 0x100>;
1566 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1567 interrupt-names = "hdcp_mmu";
1568 status = "disabled";
1571 hevc_mmu: hevc-mmu {
1573 compatible = "rockchip,hevc_mmu";
1574 reg = <0x0 0xff9a0440 0x0 0x40>,
1575 <0x0 0xff9a0480 0x0 0x40>;
1576 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1577 interrupt-names = "hevc_mmu";
1578 status = "disabled";
1583 compatible = "rockchip,vpu_mmu";
1584 reg = <0x0 0xff9a0800 0x0 0x100>;
1585 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1586 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1587 interrupt-names = "vepu_mmu", "vdpu_mmu";
1588 status = "disabled";