arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/display/mipi_dsi.h>
  50 #include <dt-bindings/power/rk3368-power.h>
  51 #include <dt-bindings/soc/rockchip,boot-mode.h>
  52 #include <dt-bindings/thermal/thermal.h>
  53
  54 / {
  55         compatible = "rockchip,rk3368";
  56         interrupt-parent = <&gic>;
  57         #address-cells = <2>;
  58         #size-cells = <2>;
  59
  60         aliases {
  61                 ethernet0 = &gmac;
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73                 spi0 = &spi0;
  74                 spi1 = &spi1;
  75                 spi2 = &spi2;
  76                 lcdc = &lcdc;
  77         };
  78
  79         cpus {
  80                 #address-cells = <0x2>;
  81                 #size-cells = <0x0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_b0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_b1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_b2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_b3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_l0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_l1>;
 105                                 };
 106                                 core2 {
 107                                         cpu = <&cpu_l2>;
 108                                 };
 109                                 core3 {
 110                                         cpu = <&cpu_l3>;
 111                                 };
 112                         };
 113                 };
 114
 115                 idle-states {
 116                         entry-method = "psci";
 117
 118                         cpu_sleep: cpu-sleep-0 {
 119                                 compatible = "arm,idle-state";
 120                                 arm,psci-suspend-param = <0x1010000>;
 121                                 entry-latency-us = <0x3fffffff>;
 122                                 exit-latency-us = <0x40000000>;
 123                                 min-residency-us = <0xffffffff>;
 124                         };
 125                 };
 126
 127                 cpu_l0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x0 0x0>;
 131                         cpu-idle-states = <&cpu_sleep>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster1_opp>;
 135
 136                         #cooling-cells = <2>; /* min followed by max */
 137                 };
 138
 139                 cpu_l1: cpu@1 {
 140                         device_type = "cpu";
 141                         compatible = "arm,cortex-a53", "arm,armv8";
 142                         reg = <0x0 0x1>;
 143                         cpu-idle-states = <&cpu_sleep>;
 144                         enable-method = "psci";
 145                         clocks = <&cru ARMCLKL>;
 146                         operating-points-v2 = <&cluster1_opp>;
 147                 };
 148
 149                 cpu_l2: cpu@2 {
 150                         device_type = "cpu";
 151                         compatible = "arm,cortex-a53", "arm,armv8";
 152                         reg = <0x0 0x2>;
 153                         cpu-idle-states = <&cpu_sleep>;
 154                         enable-method = "psci";
 155                         clocks = <&cru ARMCLKL>;
 156                         operating-points-v2 = <&cluster1_opp>;
 157                 };
 158
 159                 cpu_l3: cpu@3 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a53", "arm,armv8";
 162                         reg = <0x0 0x3>;
 163                         cpu-idle-states = <&cpu_sleep>;
 164                         enable-method = "psci";
 165                         clocks = <&cru ARMCLKL>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                 };
 168
 169                 cpu_b0: cpu@100 {
 170                         device_type = "cpu";
 171                         compatible = "arm,cortex-a53", "arm,armv8";
 172                         reg = <0x0 0x100>;
 173                         cpu-idle-states = <&cpu_sleep>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         operating-points-v2 = <&cluster0_opp>;
 177
 178                         #cooling-cells = <2>; /* min followed by max */
 179                 };
 180
 181                 cpu_b1: cpu@101 {
 182                         device_type = "cpu";
 183                         compatible = "arm,cortex-a53", "arm,armv8";
 184                         reg = <0x0 0x101>;
 185                         cpu-idle-states = <&cpu_sleep>;
 186                         enable-method = "psci";
 187                         clocks = <&cru ARMCLKB>;
 188                         operating-points-v2 = <&cluster0_opp>;
 189                 };
 190
 191                 cpu_b2: cpu@102 {
 192                         device_type = "cpu";
 193                         compatible = "arm,cortex-a53", "arm,armv8";
 194                         reg = <0x0 0x102>;
 195                         cpu-idle-states = <&cpu_sleep>;
 196                         enable-method = "psci";
 197                         clocks = <&cru ARMCLKB>;
 198                         operating-points-v2 = <&cluster0_opp>;
 199                 };
 200
 201                 cpu_b3: cpu@103 {
 202                         device_type = "cpu";
 203                         compatible = "arm,cortex-a53", "arm,armv8";
 204                         reg = <0x0 0x103>;
 205                         cpu-idle-states = <&cpu_sleep>;
 206                         enable-method = "psci";
 207                         clocks = <&cru ARMCLKB>;
 208                         operating-points-v2 = <&cluster0_opp>;
 209                 };
 210         };
 211
 212         cluster0_opp: opp_table0 {
 213                 compatible = "operating-points-v2";
 214                 opp-shared;
 215
 216                 opp@408000000 {
 217                         opp-hz = /bits/ 64 <408000000>;
 218                         opp-microvolt = <1200000>;
 219                         clock-latency-ns = <40000>;
 220                         opp-suspend;
 221                 };
 222                 opp@600000000 {
 223                         opp-hz = /bits/ 64 <600000000>;
 224                         opp-microvolt = <1200000>;
 225                 };
 226                 opp@816000000 {
 227                         opp-hz = /bits/ 64 <816000000>;
 228                         opp-microvolt = <1200000>;
 229                 };
 230                 opp@1008000000 {
 231                         opp-hz = /bits/ 64 <1008000000>;
 232                         opp-microvolt = <1200000>;
 233                 };
 234                 opp@1200000000 {
 235                         opp-hz = /bits/ 64 <1200000000>;
 236                         opp-microvolt = <1200000>;
 237                 };
 238         };
 239
 240         cluster1_opp: opp_table1 {
 241                 compatible = "operating-points-v2";
 242                 opp-shared;
 243
 244                 opp@408000000 {
 245                         opp-hz = /bits/ 64 <408000000>;
 246                         opp-microvolt = <1200000>;
 247                         clock-latency-ns = <40000>;
 248                         opp-suspend;
 249                 };
 250                 opp@600000000 {
 251                         opp-hz = /bits/ 64 <600000000>;
 252                         opp-microvolt = <1200000>;
 253                 };
 254                 opp@816000000 {
 255                         opp-hz = /bits/ 64 <816000000>;
 256                         opp-microvolt = <1200000>;
 257                 };
 258                 opp@1008000000 {
 259                         opp-hz = /bits/ 64 <1008000000>;
 260                         opp-microvolt = <1200000>;
 261                 };
 262         };
 263
 264         arm-pmu {
 265                 compatible = "arm,armv8-pmuv3";
 266                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 274                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 275                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 276                                      <&cpu_b2>, <&cpu_b3>;
 277         };
 278
 279         amba {
 280                 compatible = "arm,amba-bus";
 281                 #address-cells = <2>;
 282                 #size-cells = <2>;
 283                 ranges;
 284
 285                 dmac_peri: dma-controller@ff250000 {
 286                         compatible = "arm,pl330", "arm,primecell";
 287                         reg = <0x0 0xff250000 0x0 0x4000>;
 288                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 289                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 290                         #dma-cells = <1>;
 291                         clocks = <&cru ACLK_DMAC_PERI>;
 292                         clock-names = "apb_pclk";
 293                         arm,pl330-broken-no-flushp;
 294                         peripherals-req-type-burst;
 295                 };
 296
 297                 dmac_bus: dma-controller@ff600000 {
 298                         compatible = "arm,pl330", "arm,primecell";
 299                         reg = <0x0 0xff600000 0x0 0x4000>;
 300                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 301                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 302                         #dma-cells = <1>;
 303                         clocks = <&cru ACLK_DMAC_BUS>;
 304                         clock-names = "apb_pclk";
 305                         arm,pl330-broken-no-flushp;
 306                         peripherals-req-type-burst;
 307                 };
 308         };
 309
 310         psci {
 311                 compatible = "arm,psci-0.2";
 312                 method = "smc";
 313         };
 314
 315         timer {
 316                 compatible = "arm,armv8-timer";
 317                 interrupts = <GIC_PPI 13
 318                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 319                              <GIC_PPI 14
 320                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 321                              <GIC_PPI 11
 322                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 323                              <GIC_PPI 10
 324                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 325         };
 326
 327         xin24m: oscillator {
 328                 compatible = "fixed-clock";
 329                 clock-frequency = <24000000>;
 330                 clock-output-names = "xin24m";
 331                 #clock-cells = <0>;
 332         };
 333
 334         sdmmc: rksdmmc@ff0c0000 {
 335                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 336                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 337                 clock-freq-min-max = <400000 150000000>;
 338                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 339                 clock-names = "biu", "ciu";
 340                 fifo-depth = <0x100>;
 341                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 342                 status = "disabled";
 343         };
 344
 345         sdio0: dwmmc@ff0d0000 {
 346                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 347                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 348                 clock-freq-min-max = <400000 150000000>;
 349                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 350                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 351                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 352                 fifo-depth = <0x100>;
 353                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 354                 status = "disabled";
 355         };
 356
 357         emmc: rksdmmc@ff0f0000 {
 358                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 359                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 360                 clock-freq-min-max = <400000 150000000>;
 361                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 362                 clock-names = "biu", "ciu";
 363                 fifo-depth = <0x100>;
 364                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 365                 status = "disabled";
 366         };
 367
 368         saradc: saradc@ff100000 {
 369                 compatible = "rockchip,saradc";
 370                 reg = <0x0 0xff100000 0x0 0x100>;
 371                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 372                 #io-channel-cells = <1>;
 373                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 374                 clock-names = "saradc", "apb_pclk";
 375                 resets = <&cru SRST_SARADC>;
 376                 reset-names = "saradc-apb";
 377                 status = "disabled";
 378         };
 379
 380         spi0: spi@ff110000 {
 381                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 382                 reg = <0x0 0xff110000 0x0 0x1000>;
 383                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 384                 clock-names = "spiclk", "apb_pclk";
 385                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 status = "disabled";
 391         };
 392
 393         spi1: spi@ff120000 {
 394                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 395                 reg = <0x0 0xff120000 0x0 0x1000>;
 396                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 397                 clock-names = "spiclk", "apb_pclk";
 398                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 status = "disabled";
 404         };
 405
 406         spi2: spi@ff130000 {
 407                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 408                 reg = <0x0 0xff130000 0x0 0x1000>;
 409                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 410                 clock-names = "spiclk", "apb_pclk";
 411                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 status = "disabled";
 417         };
 418
 419         i2c0: i2c@ff650000 {
 420                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 421                 reg = <0x0 0xff650000 0x0 0x1000>;
 422                 clocks = <&cru PCLK_I2C0>;
 423                 clock-names = "i2c";
 424                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&i2c0_xfer>;
 427                 #address-cells = <1>;
 428                 #size-cells = <0>;
 429                 status = "disabled";
 430         };
 431
 432         i2c2: i2c@ff140000 {
 433                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 434                 reg = <0x0 0xff140000 0x0 0x1000>;
 435                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 436                 #address-cells = <1>;
 437                 #size-cells = <0>;
 438                 clock-names = "i2c";
 439                 clocks = <&cru PCLK_I2C2>;
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&i2c2_xfer>;
 442                 status = "disabled";
 443         };
 444
 445         i2c3: i2c@ff150000 {
 446                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 447                 reg = <0x0 0xff150000 0x0 0x1000>;
 448                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 clock-names = "i2c";
 452                 clocks = <&cru PCLK_I2C3>;
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&i2c3_xfer>;
 455                 status = "disabled";
 456         };
 457
 458         i2c4: i2c@ff160000 {
 459                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 460                 reg = <0x0 0xff160000 0x0 0x1000>;
 461                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 clock-names = "i2c";
 465                 clocks = <&cru PCLK_I2C4>;
 466                 pinctrl-names = "default";
 467                 pinctrl-0 = <&i2c4_xfer>;
 468                 status = "disabled";
 469         };
 470
 471         i2c5: i2c@ff170000 {
 472                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 473                 reg = <0x0 0xff170000 0x0 0x1000>;
 474                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 clock-names = "i2c";
 478                 clocks = <&cru PCLK_I2C5>;
 479                 pinctrl-names = "default";
 480                 pinctrl-0 = <&i2c5_xfer>;
 481                 status = "disabled";
 482         };
 483
 484         uart0: serial@ff180000 {
 485                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 486                 reg = <0x0 0xff180000 0x0 0x100>;
 487                 clock-frequency = <24000000>;
 488                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 489                 clock-names = "baudclk", "apb_pclk";
 490                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 491                 reg-shift = <2>;
 492                 reg-io-width = <4>;
 493                 status = "disabled";
 494         };
 495
 496         uart1: serial@ff190000 {
 497                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 498                 reg = <0x0 0xff190000 0x0 0x100>;
 499                 clock-frequency = <24000000>;
 500                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 501                 clock-names = "baudclk", "apb_pclk";
 502                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 503                 reg-shift = <2>;
 504                 reg-io-width = <4>;
 505                 status = "disabled";
 506         };
 507
 508         uart3: serial@ff1b0000 {
 509                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 510                 reg = <0x0 0xff1b0000 0x0 0x100>;
 511                 clock-frequency = <24000000>;
 512                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 513                 clock-names = "baudclk", "apb_pclk";
 514                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 515                 reg-shift = <2>;
 516                 reg-io-width = <4>;
 517                 status = "disabled";
 518         };
 519
 520         uart4: serial@ff1c0000 {
 521                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 522                 reg = <0x0 0xff1c0000 0x0 0x100>;
 523                 clock-frequency = <24000000>;
 524                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 525                 clock-names = "baudclk", "apb_pclk";
 526                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 527                 reg-shift = <2>;
 528                 reg-io-width = <4>;
 529                 status = "disabled";
 530         };
 531
 532         thermal-zones {
 533                 #include "rk3368-thermal.dtsi"
 534         };
 535
 536         tsadc: tsadc@ff280000 {
 537                 compatible = "rockchip,rk3368-tsadc";
 538                 reg = <0x0 0xff280000 0x0 0x100>;
 539                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 540                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 541                 clock-names = "tsadc", "apb_pclk";
 542                 resets = <&cru SRST_TSADC>;
 543                 reset-names = "tsadc-apb";
 544                 pinctrl-names = "init", "default", "sleep";
 545                 pinctrl-0 = <&otp_gpio>;
 546                 pinctrl-1 = <&otp_out>;
 547                 pinctrl-2 = <&otp_gpio>;
 548                 #thermal-sensor-cells = <1>;
 549                 rockchip,hw-tshut-temp = <95000>;
 550                 status = "disabled";
 551         };
 552
 553         gmac: ethernet@ff290000 {
 554                 compatible = "rockchip,rk3368-gmac";
 555                 reg = <0x0 0xff290000 0x0 0x10000>;
 556                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 557                 interrupt-names = "macirq";
 558                 rockchip,grf = <&grf>;
 559                 clocks = <&cru SCLK_MAC>,
 560                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 561                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 562                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 563                 clock-names = "stmmaceth",
 564                         "mac_clk_rx", "mac_clk_tx",
 565                         "clk_mac_ref", "clk_mac_refout",
 566                         "aclk_mac", "pclk_mac";
 567                 status = "disabled";
 568         };
 569
 570         nandc0: nandc@ff400000 {
 571                 compatible = "rockchip,rk-nandc";
 572                 reg = <0x0 0xff400000 0x0 0x4000>;
 573                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 574                 nandc_id = <0>;
 575                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 576                 clock-names = "clk_nandc", "hclk_nandc";
 577                 status = "disabled";
 578         };
 579
 580         usb_host0_ehci: usb@ff500000 {
 581                 compatible = "generic-ehci";
 582                 reg = <0x0 0xff500000 0x0 0x100>;
 583                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 584                 clocks = <&cru HCLK_HOST0>;
 585                 clock-names = "usbhost";
 586                 status = "disabled";
 587         };
 588
 589         usb_otg: usb@ff580000 {
 590                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 591                                 "snps,dwc2";
 592                 reg = <0x0 0xff580000 0x0 0x40000>;
 593                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 594                 clocks = <&cru HCLK_OTG0>;
 595                 clock-names = "otg";
 596                 dr_mode = "otg";
 597                 g-np-tx-fifo-size = <16>;
 598                 g-rx-fifo-size = <275>;
 599                 g-tx-fifo-size = <256 128 128 64 64 32>;
 600                 g-use-dma;
 601                 status = "disabled";
 602         };
 603
 604         ddrpctl: syscon@ff610000 {
 605                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 606                 reg = <0x0 0xff610000 0x0 0x400>;
 607         };
 608
 609         i2c1: i2c@ff660000 {
 610                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 611                 reg = <0x0 0xff660000 0x0 0x1000>;
 612                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 613                 #address-cells = <1>;
 614                 #size-cells = <0>;
 615                 clock-names = "i2c";
 616                 clocks = <&cru PCLK_I2C1>;
 617                 pinctrl-names = "default";
 618                 pinctrl-0 = <&i2c1_xfer>;
 619                 status = "disabled";
 620         };
 621
 622         pwm0: pwm@ff680000 {
 623                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 624                 reg = <0x0 0xff680000 0x0 0x10>;
 625                 #pwm-cells = <3>;
 626                 pinctrl-names = "default";
 627                 pinctrl-0 = <&pwm0_pin>;
 628                 clocks = <&cru PCLK_PWM1>;
 629                 clock-names = "pwm";
 630                 status = "disabled";
 631         };
 632
 633         pwm1: pwm@ff680010 {
 634                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 635                 reg = <0x0 0xff680010 0x0 0x10>;
 636                 #pwm-cells = <3>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&pwm1_pin>;
 639                 clocks = <&cru PCLK_PWM1>;
 640                 clock-names = "pwm";
 641                 status = "disabled";
 642         };
 643
 644         pwm2: pwm@ff680020 {
 645                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 646                 reg = <0x0 0xff680020 0x0 0x10>;
 647                 #pwm-cells = <3>;
 648                 clocks = <&cru PCLK_PWM1>;
 649                 clock-names = "pwm";
 650                 status = "disabled";
 651         };
 652
 653         pwm3: pwm@ff680030 {
 654                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 655                 reg = <0x0 0xff680030 0x0 0x10>;
 656                 #pwm-cells = <3>;
 657                 pinctrl-names = "default";
 658                 pinctrl-0 = <&pwm3_pin>;
 659                 clocks = <&cru PCLK_PWM1>;
 660                 clock-names = "pwm";
 661                 status = "disabled";
 662         };
 663
 664         uart2: serial@ff690000 {
 665                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 666                 reg = <0x0 0xff690000 0x0 0x100>;
 667                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 668                 clock-names = "baudclk", "apb_pclk";
 669                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 670                 pinctrl-names = "default";
 671                 pinctrl-0 = <&uart2_xfer>;
 672                 reg-shift = <2>;
 673                 reg-io-width = <4>;
 674                 status = "disabled";
 675         };
 676
 677         pmu: power-management@ff730000 {
 678                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 679                 reg = <0x0 0xff730000 0x0 0x1000>;
 680
 681                 power: power-controller {
 682                         status = "disabled";
 683                         compatible = "rockchip,rk3368-power-controller";
 684                         #power-domain-cells = <1>;
 685                         #address-cells = <1>;
 686                         #size-cells = <0>;
 687
 688                         /*
 689                          * Note: Although SCLK_* are the working clocks
 690                          * of device without including on the NOC, needed for
 691                          * synchronous reset.
 692                          *
 693                          * The clocks on the which NOC:
 694                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 695                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 696                          * ACLK_RGA is on ACLK_RGA_NIU.
 697                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 698                          *
 699                          * Which clock are device clocks:
 700                          *      clocks          devices
 701                          *      *_IEP           IEP:Image Enhancement Processor
 702                          *      *_ISP           ISP:Image Signal Processing
 703                          *      *_VIP           VIP:Video Input Processor
 704                          *      *_VOP*          VOP:Visual Output Processor
 705                          *      *_RGA           RGA
 706                          *      *_EDP*          EDP
 707                          *      *_DPHY*         LVDS
 708                          *      *_HDMI          HDMI
 709                          *      *_MIPI_*        MIPI
 710                          */
 711                         pd_vio {
 712                                 reg = <RK3368_PD_VIO>;
 713                                 clocks = <&cru ACLK_IEP>,
 714                                          <&cru ACLK_ISP>,
 715                                          <&cru ACLK_VIP>,
 716                                          <&cru ACLK_RGA>,
 717                                          <&cru ACLK_VOP>,
 718                                          <&cru ACLK_VOP_IEP>,
 719                                          <&cru DCLK_VOP>,
 720                                          <&cru HCLK_IEP>,
 721                                          <&cru HCLK_ISP>,
 722                                          <&cru HCLK_RGA>,
 723                                          <&cru HCLK_VIP>,
 724                                          <&cru HCLK_VOP>,
 725                                          <&cru HCLK_VIO_HDCPMMU>,
 726                                          <&cru PCLK_EDP_CTRL>,
 727                                          <&cru PCLK_HDMI_CTRL>,
 728                                          <&cru PCLK_HDCP>,
 729                                          <&cru PCLK_ISP>,
 730                                          <&cru PCLK_VIP>,
 731                                          <&cru PCLK_DPHYRX>,
 732                                          <&cru PCLK_DPHYTX0>,
 733                                          <&cru PCLK_MIPI_CSI>,
 734                                          <&cru PCLK_MIPI_DSI0>,
 735                                          <&cru SCLK_VOP0_PWM>,
 736                                          <&cru SCLK_EDP_24M>,
 737                                          <&cru SCLK_EDP>,
 738                                          <&cru SCLK_HDCP>,
 739                                          <&cru SCLK_ISP>,
 740                                          <&cru SCLK_RGA>,
 741                                          <&cru SCLK_HDMI_CEC>,
 742                                          <&cru SCLK_HDMI_HDCP>;
 743                         };
 744                         /*
 745                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 746                          * (video endecoder & decoder) clocks that on the
 747                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 748                          */
 749                         pd_video {
 750                                 reg = <RK3368_PD_VIDEO>;
 751                                 clocks = <&cru ACLK_VIDEO>,
 752                                          <&cru HCLK_VIDEO>,
 753                                          <&cru SCLK_HEVC_CABAC>,
 754                                          <&cru SCLK_HEVC_CORE>;
 755                         };
 756                         /*
 757                          * Note: ACLK_GPU is the GPU clock,
 758                          * and on the ACLK_GPU_NIU (NOC).
 759                          */
 760                         pd_gpu_1 {
 761                                 reg = <RK3368_PD_GPU_1>;
 762                                 clocks = <&cru ACLK_GPU_CFG>,
 763                                          <&cru ACLK_GPU_MEM>,
 764                                          <&cru SCLK_GPU_CORE>;
 765                         };
 766                 };
 767         };
 768
 769         pmugrf: syscon@ff738000 {
 770                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 771                 reg = <0x0 0xff738000 0x0 0x1000>;
 772
 773                 reboot-mode {
 774                         compatible = "syscon-reboot-mode";
 775                         offset = <0x200>;
 776                         mode-normal = <BOOT_NORMAL>;
 777                         mode-recovery = <BOOT_RECOVERY>;
 778                         mode-bootloader = <BOOT_FASTBOOT>;
 779                         mode-loader = <BOOT_BL_DOWNLOAD>;
 780
 781                 };
 782         };
 783
 784         cru: clock-controller@ff760000 {
 785                 compatible = "rockchip,rk3368-cru";
 786                 reg = <0x0 0xff760000 0x0 0x1000>;
 787                 rockchip,grf = <&grf>;
 788                 #clock-cells = <1>;
 789                 #reset-cells = <1>;
 790                 assigned-clocks =
 791                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 792                         <&cru PLL_NPLL>,
 793                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
 794                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
 795                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
 796                 assigned-clock-rates =
 797                         <576000000>, <400000000>,
 798                         <1188000000>,
 799                         <300000000>, <300000000>,
 800                         <150000000>, <150000000>,
 801                         <75000000>, <75000000>;
 802         };
 803
 804         grf: syscon@ff770000 {
 805                 compatible = "rockchip,rk3368-grf", "syscon";
 806                 reg = <0x0 0xff770000 0x0 0x1000>;
 807         };
 808
 809         wdt: watchdog@ff800000 {
 810                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 811                 reg = <0x0 0xff800000 0x0 0x100>;
 812                 clocks = <&cru PCLK_WDT>;
 813                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 814                 status = "disabled";
 815         };
 816
 817         timer@ff810000 {
 818                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
 819                 reg = <0x0 0xff810000 0x0 0x20>;
 820                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 821         };
 822
 823         gic: interrupt-controller@ffb71000 {
 824                 compatible = "arm,gic-400";
 825                 interrupt-controller;
 826                 #interrupt-cells = <3>;
 827                 #address-cells = <0>;
 828
 829                 reg = <0x0 0xffb71000 0x0 0x1000>,
 830                       <0x0 0xffb72000 0x0 0x2000>,
 831                       <0x0 0xffb74000 0x0 0x2000>,
 832                       <0x0 0xffb76000 0x0 0x2000>;
 833                 interrupts = <GIC_PPI 9
 834                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 835         };
 836
 837         gpu: rogue-g6110@ffa30000 {
 838                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
 839                 reg = <0x0 0xffa30000 0x0 0x10000>;
 840                 clocks =
 841                         <&cru SCLK_GPU_CORE>,
 842                         <&cru ACLK_GPU_MEM>,
 843                         <&cru ACLK_GPU_CFG>;
 844                 clock-names =
 845                         "sclk_gpu_core",
 846                         "aclk_gpu_mem",
 847                         "aclk_gpu_cfg";
 848                 operating-points = <
 849                         /* KHz uV */
 850                         200000 1100000
 851                         288000 1100000
 852                         400000 1150000
 853                         576000 1200000
 854                 >;
 855                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 856                 interrupt-names = "rogue-g6110-irq";
 857         };
 858
 859         i2s_2ch: i2s-2ch@ff890000 {
 860                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 861                 reg = <0x0 0xff890000 0x0 0x1000>;
 862                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 863                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 864                 dma-names = "tx", "rx";
 865                 clock-names = "i2s_clk", "i2s_hclk";
 866                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 867                 status = "disabled";
 868         };
 869
 870         i2s_8ch: i2s-8ch@ff898000 {
 871                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 872                 reg = <0x0 0xff898000 0x0 0x1000>;
 873                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 874                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 875                 dma-names = "tx", "rx";
 876                 clock-names = "i2s_clk", "i2s_hclk";
 877                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 878                 pinctrl-names = "default";
 879                 pinctrl-0 = <&i2s_8ch_bus>;
 880                 status = "disabled";
 881         };
 882
 883         isp: isp@ff910000 {
 884                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
 885                 reg = <0x0 0xff910000 0x0 0x10000>;
 886                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 887                 /*power-domains = <&power PD_VIO>;*/
 888                 clocks =
 889                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
 890                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
 891                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
 892                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
 893                 clock-names =
 894                         "aclk_isp", "hclk_isp", "clk_isp",
 895                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
 896                         "clk_cif_pll", "hclk_mipiphy1",
 897                         "pclk_dphyrx", "clk_vio0_noc";
 898                 pinctrl-names =
 899                         "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
 900                         "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
 901                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 902                         "isp_flash_as_trigger_out";
 903                 pinctrl-0 = <&cif_clkout>;
 904                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
 905                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
 906                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
 907                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
 908                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
 909                 pinctrl-6 = <&cif_clkout>;
 910                 pinctrl-7 = <&cif_clkout &isp_prelight>;
 911                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
 912                 pinctrl-9 = <&isp_flash_trigger>;
 913                 rockchip,isp,mipiphy = <2>;
 914                 rockchip,isp,cifphy = <1>;
 915                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
 916                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
 917                 rockchip,grf = <&grf>;
 918                 rockchip,cru = <&cru>;
 919                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 920                 rockchip,isp,iommu_enable = <1>;
 921                 status = "disabled";
 922         };
 923
 924         rga: rga@ff920000 {
 925                 compatible = "rockchip,rga2";
 926                 dev_mode = <1>;
 927                 reg = <0x0 0xff920000 0x0 0x1000>;
 928                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 929                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 930                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 931                 status = "disabled";
 932         };
 933
 934         pinctrl: pinctrl {
 935                 compatible = "rockchip,rk3368-pinctrl";
 936                 rockchip,grf = <&grf>;
 937                 rockchip,pmu = <&pmugrf>;
 938                 #address-cells = <0x2>;
 939                 #size-cells = <0x2>;
 940                 ranges;
 941
 942                 gpio0: gpio0@ff750000 {
 943                         compatible = "rockchip,gpio-bank";
 944                         reg = <0x0 0xff750000 0x0 0x100>;
 945                         clocks = <&cru PCLK_GPIO0>;
 946                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 947
 948                         gpio-controller;
 949                         #gpio-cells = <0x2>;
 950
 951                         interrupt-controller;
 952                         #interrupt-cells = <0x2>;
 953                 };
 954
 955                 gpio1: gpio1@ff780000 {
 956                         compatible = "rockchip,gpio-bank";
 957                         reg = <0x0 0xff780000 0x0 0x100>;
 958                         clocks = <&cru PCLK_GPIO1>;
 959                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 960
 961                         gpio-controller;
 962                         #gpio-cells = <0x2>;
 963
 964                         interrupt-controller;
 965                         #interrupt-cells = <0x2>;
 966                 };
 967
 968                 gpio2: gpio2@ff790000 {
 969                         compatible = "rockchip,gpio-bank";
 970                         reg = <0x0 0xff790000 0x0 0x100>;
 971                         clocks = <&cru PCLK_GPIO2>;
 972                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
 973
 974                         gpio-controller;
 975                         #gpio-cells = <0x2>;
 976
 977                         interrupt-controller;
 978                         #interrupt-cells = <0x2>;
 979                 };
 980
 981                 gpio3: gpio3@ff7a0000 {
 982                         compatible = "rockchip,gpio-bank";
 983                         reg = <0x0 0xff7a0000 0x0 0x100>;
 984                         clocks = <&cru PCLK_GPIO3>;
 985                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
 986
 987                         gpio-controller;
 988                         #gpio-cells = <0x2>;
 989
 990                         interrupt-controller;
 991                         #interrupt-cells = <0x2>;
 992                 };
 993
 994                 pcfg_pull_up: pcfg-pull-up {
 995                         bias-pull-up;
 996                 };
 997
 998                 pcfg_pull_down: pcfg-pull-down {
 999                         bias-pull-down;
1000                 };
1001
1002                 pcfg_pull_none: pcfg-pull-none {
1003                         bias-disable;
1004                 };
1005
1006                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1007                         bias-disable;
1008                         drive-strength = <12>;
1009                 };
1010
1011                 emmc {
1012                         emmc_clk: emmc-clk {
1013                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1014                         };
1015
1016                         emmc_cmd: emmc-cmd {
1017                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1018                         };
1019
1020                         emmc_pwr: emmc-pwr {
1021                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1022                         };
1023
1024                         emmc_bus1: emmc-bus1 {
1025                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1026                         };
1027
1028                         emmc_bus4: emmc-bus4 {
1029                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1030                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1031                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1032                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1033                         };
1034
1035                         emmc_bus8: emmc-bus8 {
1036                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1037                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1038                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1039                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1040                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1041                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1042                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1043                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1044                         };
1045                 };
1046
1047                 gmac {
1048                         rgmii_pins: rgmii-pins {
1049                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1050                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1051                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1052                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1053                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1054                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1055                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1056                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1057                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1058                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1059                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1060                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1061                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1062                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1063                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1064                         };
1065
1066                         rmii_pins: rmii-pins {
1067                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1068                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1069                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1070                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1071                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1072                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1073                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1074                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1075                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1076                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1077                         };
1078                 };
1079
1080                 hdmi_i2c {
1081                         hdmii2c_xfer: hdmii2c-xfer {
1082                                 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1083                                                 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1084                         };
1085                 };
1086
1087                 hdmi_pin {
1088                         hdmi_cec: hdmi-cec {
1089                                 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1090                         };
1091                 };
1092
1093                 i2c0 {
1094                         i2c0_xfer: i2c0-xfer {
1095                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1096                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1097                         };
1098                 };
1099
1100                 i2c1 {
1101                         i2c1_xfer: i2c1-xfer {
1102                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1103                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1104                         };
1105                 };
1106
1107                 i2c2 {
1108                         i2c2_xfer: i2c2-xfer {
1109                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1110                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1111                         };
1112                 };
1113
1114                 i2c3 {
1115                         i2c3_xfer: i2c3-xfer {
1116                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1117                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1118                         };
1119                 };
1120
1121                 i2c4 {
1122                         i2c4_xfer: i2c4-xfer {
1123                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1124                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1125                         };
1126                 };
1127
1128                 i2c5 {
1129                         i2c5_xfer: i2c5-xfer {
1130                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1131                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1132                         };
1133                         i2c5_gpio: i2c5-gpio {
1134                                 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
1135                                                 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
1136                         };
1137                 };
1138
1139                 i2s {
1140                         i2s_8ch_bus: i2s-8ch-bus {
1141                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1142                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1143                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1144                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1145                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1146                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1147                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1148                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1149                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1150                         };
1151                 };
1152
1153                 sdio0 {
1154                         sdio0_bus1: sdio0-bus1 {
1155                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1156                         };
1157
1158                         sdio0_bus4: sdio0-bus4 {
1159                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1160                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1161                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1162                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1163                         };
1164
1165                         sdio0_cmd: sdio0-cmd {
1166                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1167                         };
1168
1169                         sdio0_clk: sdio0-clk {
1170                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1171                         };
1172
1173                         sdio0_cd: sdio0-cd {
1174                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1175                         };
1176
1177                         sdio0_wp: sdio0-wp {
1178                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1179                         };
1180
1181                         sdio0_pwr: sdio0-pwr {
1182                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1183                         };
1184
1185                         sdio0_bkpwr: sdio0-bkpwr {
1186                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1187                         };
1188
1189                         sdio0_int: sdio0-int {
1190                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1191                         };
1192                 };
1193
1194                 sdmmc {
1195                         sdmmc_clk: sdmmc-clk {
1196                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1197                         };
1198
1199                         sdmmc_cmd: sdmmc-cmd {
1200                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1201                         };
1202
1203                         sdmmc_cd: sdmmc-cd {
1204                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1205                         };
1206
1207                         sdmmc_bus1: sdmmc-bus1 {
1208                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1209                         };
1210
1211                         sdmmc_bus4: sdmmc-bus4 {
1212                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1213                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1214                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1215                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1216                         };
1217                 };
1218
1219                 spi0 {
1220                         spi0_clk: spi0-clk {
1221                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1222                         };
1223                         spi0_cs0: spi0-cs0 {
1224                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1225                         };
1226                         spi0_cs1: spi0-cs1 {
1227                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1228                         };
1229                         spi0_tx: spi0-tx {
1230                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1231                         };
1232                         spi0_rx: spi0-rx {
1233                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1234                         };
1235                 };
1236
1237                 spi1 {
1238                         spi1_clk: spi1-clk {
1239                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1240                         };
1241                         spi1_cs0: spi1-cs0 {
1242                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1243                         };
1244                         spi1_cs1: spi1-cs1 {
1245                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1246                         };
1247                         spi1_rx: spi1-rx {
1248                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1249                         };
1250                         spi1_tx: spi1-tx {
1251                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1252                         };
1253                 };
1254
1255                 spi2 {
1256                         spi2_clk: spi2-clk {
1257                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1258                         };
1259                         spi2_cs0: spi2-cs0 {
1260                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1261                         };
1262                         spi2_rx: spi2-rx {
1263                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1264                         };
1265                         spi2_tx: spi2-tx {
1266                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1267                         };
1268                 };
1269
1270                 tsadc {
1271                         otp_gpio: otp-gpio {
1272                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1273                         };
1274
1275                         otp_out: otp-out {
1276                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1277                         };
1278                 };
1279
1280                 uart0 {
1281                         uart0_xfer: uart0-xfer {
1282                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1283                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1284                         };
1285
1286                         uart0_cts: uart0-cts {
1287                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1288                         };
1289
1290                         uart0_rts: uart0-rts {
1291                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1292                         };
1293                 };
1294
1295                 uart1 {
1296                         uart1_xfer: uart1-xfer {
1297                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1298                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1299                         };
1300
1301                         uart1_cts: uart1-cts {
1302                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1303                         };
1304
1305                         uart1_rts: uart1-rts {
1306                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1307                         };
1308                 };
1309
1310                 uart2 {
1311                         uart2_xfer: uart2-xfer {
1312                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1313                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1314                         };
1315                         /* no rts / cts for uart2 */
1316                 };
1317
1318                 uart3 {
1319                         uart3_xfer: uart3-xfer {
1320                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1321                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1322                         };
1323
1324                         uart3_cts: uart3-cts {
1325                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1326                         };
1327
1328                         uart3_rts: uart3-rts {
1329                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1330                         };
1331                 };
1332
1333                 uart4 {
1334                         uart4_xfer: uart4-xfer {
1335                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1336                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1337                         };
1338
1339                         uart4_cts: uart4-cts {
1340                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1341                         };
1342
1343                         uart4_rts: uart4-rts {
1344                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1345                         };
1346                 };
1347
1348                 pwm0 {
1349                         pwm0_pin: pwm0-pin {
1350                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1351                         };
1352
1353                         vop_pwm_pin: vop-pwm {
1354                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1355                         };
1356                 };
1357
1358                 pwm1 {
1359                         pwm1_pin: pwm1-pin {
1360                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1361                         };
1362                 };
1363
1364                 pwm3 {
1365                         pwm3_pin: pwm3-pin {
1366                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1367                         };
1368                 };
1369
1370                 lcdc {
1371                         lcdc_lcdc: lcdc-lcdc {
1372                                 rockchip,pins =
1373                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1374                                                 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1375                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1376                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1377                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1378                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1379                                                 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1380                                                 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1381                                                 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1382                                                 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1383                                                 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1384                                                 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1385                                                 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1386                                                 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1387                                                 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1388                                                 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1389                                                 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1390                                                 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1391                         };
1392
1393                         lcdc_gpio: lcdc-gpio {
1394                                 rockchip,pins =
1395                                                 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1396                                                 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1397                                                 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1398                                                 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1399                                                 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1400                                                 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1401                                                 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1402                                                 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1403                                                 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1404                                                 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1405                                                 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1406                                                 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1407                                                 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1408                                                 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1409                                                 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1410                                                 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1411                                                 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1412                                                 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1413                         };
1414                 };
1415
1416                 isp {
1417                         cif_clkout: cif-clkout {
1418                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1419                         };
1420
1421                         isp_dvp_d2d9: isp-dvp-d2d9 {
1422                                 rockchip,pins =
1423                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1424                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1425                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1426                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1427                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1428                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1429                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1430                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1431                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1432                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1433                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1434                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1435                         };
1436
1437                         isp_dvp_d0d1: isp-dvp-d0d1 {
1438                                 rockchip,pins =
1439                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1440                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1441                         };
1442
1443                         isp_dvp_d10d11:isp_d10d11 {
1444                                 rockchip,pins =
1445                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1446                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1447                         };
1448
1449                         isp_dvp_d0d7: isp-dvp-d0d7 {
1450                                 rockchip,pins =
1451                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1452                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1453                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1454                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1455                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1456                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1457                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1458                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1459                         };
1460
1461                         isp_dvp_d4d11: isp-dvp-d4d11 {
1462                                 rockchip,pins =
1463                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1464                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1465                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1466                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1467                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1468                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1469                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1470                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1471                         };
1472
1473                         isp_shutter: isp-shutter {
1474                                 rockchip,pins =
1475                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1476                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1477                         };
1478
1479                         isp_flash_trigger: isp-flash-trigger {
1480                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1481                         };
1482
1483                         isp_prelight: isp-prelight {
1484                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1485                         };
1486
1487                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1488                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1489                         };
1490                 };
1491         };
1492
1493         fb: fb {
1494                 compatible = "rockchip,rk-fb";
1495                 rockchip,disp-mode = <NO_DUAL>;
1496                 status = "disabled";
1497         };
1498
1499         rk_screen: screen {
1500                 compatible = "rockchip,screen";
1501                 status = "disabled";
1502         };
1503
1504         lcdc: lcdc@ff930000 {
1505                 compatible = "rockchip,rk3368-lcdc";
1506                 rockchip,grf = <&grf>;
1507                 rockchip,pmugrf = <&pmugrf>;
1508                 rockchip,cru = <&cru>;
1509                 rockchip,prop = <PRMRY>;
1510                 rockchip,pwr18 = <0>;
1511                 rockchip,iommu-enabled = <1>;
1512                 reg = <0x0 0xff930000 0x0 0x10000>;
1513                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1514                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1515                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1516                 /*power-domains = <&power PD_VIO>;*/
1517                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1518                 reset-names = "axi", "ahb", "dclk";
1519                 status = "disabled";
1520         };
1521
1522         mipi: mipi@ff960000 {
1523                 compatible = "rockchip,rk3368-dsi";
1524                 rockchip,prop = <0>;
1525                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1526                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1527                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1528                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1529                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1530                 /*power-domains = <&power PD_VIO>;*/
1531                 status = "disabled";
1532         };
1533
1534         lvds: lvds@ff968000 {
1535                 compatible = "rockchip,rk3368-lvds";
1536                 rockchip,grf = <&grf>;
1537                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1538                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1539                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1540                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1541                 /*power-domains = <&power PD_VIO>;*/
1542                 status = "disabled";
1543         };
1544
1545         edp: edp@ff970000 {
1546                 compatible = "rockchip,rk32-edp";
1547                 reg = <0x0 0xff970000 0x0 0x4000>;
1548                 rockchip,grf = <&grf>;
1549                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1550                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1551                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1552                 /*power-domains = <&power PD_VIO>;*/
1553                 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1554                 reset-names = "edp_24m", "edp_apb";
1555                 status = "disabled";
1556         };
1557
1558         hdmi: hdmi@ff980000 {
1559                 compatible = "rockchip,rk3368-hdmi";
1560                 reg = <0x0 0xff980000 0x0 0x20000>;
1561                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1562                 clocks = <&cru PCLK_HDMI_CTRL>,
1563                          <&cru SCLK_HDMI_HDCP>,
1564                          <&cru SCLK_HDMI_CEC>;
1565                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
1566                 /*power-domains = <&power PD_VIO>;*/
1567                 resets = <&cru SRST_HDMI>;
1568                 reset-names = "hdmi";
1569                 pinctrl-names = "default", "gpio";
1570                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1571                 pinctrl-1 = <&i2c5_gpio>;
1572                 status = "disabled";
1573         };
1574
1575         iep_mmu: iep-mmu {
1576                 dbgname = "iep";
1577                 compatible = "rockchip,iep_mmu";
1578                 reg = <0x0 0xff900800 0x0 0x100>;
1579                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1580                 interrupt-names = "iep_mmu";
1581                 status = "disabled";
1582         };
1583
1584         vip_mmu: vip-mmu {
1585                 dbgname = "vip";
1586                 compatible = "rockchip,vip_mmu";
1587                 reg = <0x0 0xff950800 0x0 0x100>;
1588                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1589                 interrupt-names = "vip_mmu";
1590                 status = "disabled";
1591         };
1592
1593         vopb_mmu: vopb-mmu {
1594                 dbgname = "vop";
1595                 compatible = "rockchip,vopb_mmu";
1596                 reg = <0x0 0xff930300 0x0 0x100>;
1597                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1598                 interrupt-names = "vop_mmu";
1599                 status = "disabled";
1600         };
1601
1602         isp_mmu: isp-mmu {
1603                 dbgname = "isp_mmu";
1604                 compatible = "rockchip,isp_mmu";
1605                 reg = <0x0 0xff914000 0x0 0x100>,
1606                       <0x0 0xff915000 0x0 0x100>;
1607                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1608                 interrupt-names = "isp_mmu";
1609                 status = "disabled";
1610         };
1611
1612         hdcp_mmu: hdcp-mmu {
1613                  dbgname = "hdcp_mmu";
1614                  compatible = "rockchip,hdcp_mmu";
1615                  reg = <0x0 0xff940000 0x0 0x100>;
1616                  interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1617                  interrupt-names = "hdcp_mmu";
1618                 status = "disabled";
1619         };
1620
1621         hevc_mmu: hevc-mmu {
1622                 dbgname = "hevc";
1623                 compatible = "rockchip,hevc_mmu";
1624                 reg = <0x0 0xff9a0440 0x0 0x40>,
1625                       <0x0 0xff9a0480 0x0 0x40>;
1626                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1627                 interrupt-names = "hevc_mmu";
1628                 status = "disabled";
1629         };
1630
1631         vpu_mmu: vpu-mmu {
1632                 dbgname = "vpu";
1633                 compatible = "rockchip,vpu_mmu";
1634                 reg = <0x0 0xff9a0800 0x0 0x100>;
1635                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1636                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1637                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1638                 status = "disabled";
1639         };
1640 };