2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/power/rk3368-power.h>
52 compatible = "rockchip,rk3368";
53 interrupt-parent = <&gic>;
76 #address-cells = <0x2>;
112 entry-method = "psci";
114 cpu_sleep: cpu-sleep-0 {
115 compatible = "arm,idle-state";
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
125 compatible = "arm,cortex-a53", "arm,armv8";
127 cpu-idle-states = <&cpu_sleep>;
128 enable-method = "psci";
129 clocks = <&cru ARMCLKL>;
130 operating-points-v2 = <&cluster1_opp>;
135 compatible = "arm,cortex-a53", "arm,armv8";
137 cpu-idle-states = <&cpu_sleep>;
138 enable-method = "psci";
139 operating-points-v2 = <&cluster1_opp>;
144 compatible = "arm,cortex-a53", "arm,armv8";
146 cpu-idle-states = <&cpu_sleep>;
147 enable-method = "psci";
148 operating-points-v2 = <&cluster1_opp>;
153 compatible = "arm,cortex-a53", "arm,armv8";
155 cpu-idle-states = <&cpu_sleep>;
156 enable-method = "psci";
157 operating-points-v2 = <&cluster1_opp>;
162 compatible = "arm,cortex-a53", "arm,armv8";
164 cpu-idle-states = <&cpu_sleep>;
165 enable-method = "psci";
166 clocks = <&cru ARMCLKB>;
167 operating-points-v2 = <&cluster0_opp>;
172 compatible = "arm,cortex-a53", "arm,armv8";
174 cpu-idle-states = <&cpu_sleep>;
175 enable-method = "psci";
176 operating-points-v2 = <&cluster0_opp>;
181 compatible = "arm,cortex-a53", "arm,armv8";
183 cpu-idle-states = <&cpu_sleep>;
184 enable-method = "psci";
185 operating-points-v2 = <&cluster0_opp>;
190 compatible = "arm,cortex-a53", "arm,armv8";
192 cpu-idle-states = <&cpu_sleep>;
193 enable-method = "psci";
194 operating-points-v2 = <&cluster0_opp>;
198 cluster0_opp: opp_table0 {
199 compatible = "operating-points-v2";
203 opp-hz = /bits/ 64 <408000000>;
204 opp-microvolt = <1200000>;
205 clock-latency-ns = <40000>;
209 opp-hz = /bits/ 64 <600000000>;
210 opp-microvolt = <1200000>;
213 opp-hz = /bits/ 64 <816000000>;
214 opp-microvolt = <1200000>;
217 opp-hz = /bits/ 64 <1008000000>;
218 opp-microvolt = <1200000>;
221 opp-hz = /bits/ 64 <1200000000>;
222 opp-microvolt = <1200000>;
226 cluster1_opp: opp_table1 {
227 compatible = "operating-points-v2";
231 opp-hz = /bits/ 64 <408000000>;
232 opp-microvolt = <1200000>;
233 clock-latency-ns = <40000>;
237 opp-hz = /bits/ 64 <600000000>;
238 opp-microvolt = <1200000>;
241 opp-hz = /bits/ 64 <816000000>;
242 opp-microvolt = <1200000>;
245 opp-hz = /bits/ 64 <1008000000>;
246 opp-microvolt = <1200000>;
251 compatible = "arm,armv8-pmuv3";
252 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
260 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
261 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
262 <&cpu_b2>, <&cpu_b3>;
266 compatible = "arm,amba-bus";
267 #address-cells = <2>;
271 dmac_peri: dma-controller@ff250000 {
272 compatible = "arm,pl330", "arm,primecell";
273 reg = <0x0 0xff250000 0x0 0x4000>;
274 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&cru ACLK_DMAC_PERI>;
278 clock-names = "apb_pclk";
281 dmac_bus: dma-controller@ff600000 {
282 compatible = "arm,pl330", "arm,primecell";
283 reg = <0x0 0xff600000 0x0 0x4000>;
284 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cru ACLK_DMAC_BUS>;
288 clock-names = "apb_pclk";
293 compatible = "arm,psci-0.2";
298 compatible = "arm,armv8-timer";
299 interrupts = <GIC_PPI 13
300 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
302 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
304 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
306 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
310 compatible = "fixed-clock";
311 clock-frequency = <24000000>;
312 clock-output-names = "xin24m";
316 sdmmc: rksdmmc@ff0c0000 {
317 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
318 reg = <0x0 0xff0c0000 0x0 0x4000>;
319 clock-freq-min-max = <400000 150000000>;
320 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
321 clock-names = "biu", "ciu";
322 fifo-depth = <0x100>;
323 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
327 sdio0: dwmmc@ff0d0000 {
328 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
329 reg = <0x0 0xff0d0000 0x0 0x4000>;
330 clock-freq-min-max = <400000 150000000>;
331 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
332 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
333 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
334 fifo-depth = <0x100>;
335 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
339 emmc: rksdmmc@ff0f0000 {
340 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
341 reg = <0x0 0xff0f0000 0x0 0x4000>;
342 clock-freq-min-max = <400000 150000000>;
343 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
344 clock-names = "biu", "ciu";
345 fifo-depth = <0x100>;
346 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
350 saradc: saradc@ff100000 {
351 compatible = "rockchip,saradc";
352 reg = <0x0 0xff100000 0x0 0x100>;
353 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
354 #io-channel-cells = <1>;
355 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
356 clock-names = "saradc", "apb_pclk";
361 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
362 reg = <0x0 0xff110000 0x0 0x1000>;
363 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
364 clock-names = "spiclk", "apb_pclk";
365 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
368 #address-cells = <1>;
374 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
375 reg = <0x0 0xff120000 0x0 0x1000>;
376 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
377 clock-names = "spiclk", "apb_pclk";
378 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
381 #address-cells = <1>;
387 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
388 reg = <0x0 0xff130000 0x0 0x1000>;
389 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
390 clock-names = "spiclk", "apb_pclk";
391 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
394 #address-cells = <1>;
400 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
401 reg = <0x0 0xff650000 0x0 0x1000>;
402 clocks = <&cru PCLK_I2C0>;
404 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
405 pinctrl-names = "default";
406 pinctrl-0 = <&i2c0_xfer>;
407 #address-cells = <1>;
413 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
414 reg = <0x0 0xff140000 0x0 0x1000>;
415 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
416 #address-cells = <1>;
419 clocks = <&cru PCLK_I2C2>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&i2c2_xfer>;
426 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
427 reg = <0x0 0xff150000 0x0 0x1000>;
428 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
429 #address-cells = <1>;
432 clocks = <&cru PCLK_I2C3>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&i2c3_xfer>;
439 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
440 reg = <0x0 0xff160000 0x0 0x1000>;
441 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
442 #address-cells = <1>;
445 clocks = <&cru PCLK_I2C4>;
446 pinctrl-names = "default";
447 pinctrl-0 = <&i2c4_xfer>;
452 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
453 reg = <0x0 0xff170000 0x0 0x1000>;
454 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
455 #address-cells = <1>;
458 clocks = <&cru PCLK_I2C5>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&i2c5_xfer>;
464 uart0: serial@ff180000 {
465 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
466 reg = <0x0 0xff180000 0x0 0x100>;
467 clock-frequency = <24000000>;
468 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
469 clock-names = "baudclk", "apb_pclk";
470 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
476 uart1: serial@ff190000 {
477 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
478 reg = <0x0 0xff190000 0x0 0x100>;
479 clock-frequency = <24000000>;
480 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
481 clock-names = "baudclk", "apb_pclk";
482 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
488 uart3: serial@ff1b0000 {
489 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
490 reg = <0x0 0xff1b0000 0x0 0x100>;
491 clock-frequency = <24000000>;
492 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
493 clock-names = "baudclk", "apb_pclk";
494 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
500 uart4: serial@ff1c0000 {
501 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
502 reg = <0x0 0xff1c0000 0x0 0x100>;
503 clock-frequency = <24000000>;
504 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
505 clock-names = "baudclk", "apb_pclk";
506 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
512 gmac: ethernet@ff290000 {
513 compatible = "rockchip,rk3368-gmac";
514 reg = <0x0 0xff290000 0x0 0x10000>;
515 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
516 interrupt-names = "macirq";
517 rockchip,grf = <&grf>;
518 clocks = <&cru SCLK_MAC>,
519 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
520 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
521 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
522 clock-names = "stmmaceth",
523 "mac_clk_rx", "mac_clk_tx",
524 "clk_mac_ref", "clk_mac_refout",
525 "aclk_mac", "pclk_mac";
529 nandc0: nandc@ff400000 {
530 compatible = "rockchip,rk-nandc";
531 reg = <0x0 0xff400000 0x0 0x4000>;
532 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
535 clock-names = "clk_nandc", "hclk_nandc";
539 usb_host0_ehci: usb@ff500000 {
540 compatible = "generic-ehci";
541 reg = <0x0 0xff500000 0x0 0x100>;
542 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cru HCLK_HOST0>;
544 clock-names = "usbhost";
548 usb_otg: usb@ff580000 {
549 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
551 reg = <0x0 0xff580000 0x0 0x40000>;
552 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cru HCLK_OTG0>;
556 g-np-tx-fifo-size = <16>;
557 g-rx-fifo-size = <275>;
558 g-tx-fifo-size = <256 128 128 64 64 32>;
563 ddrpctl: syscon@ff610000 {
564 compatible = "rockchip,rk3368-ddrpctl", "syscon";
565 reg = <0x0 0xff610000 0x0 0x400>;
569 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
570 reg = <0x0 0xff660000 0x0 0x1000>;
571 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
572 #address-cells = <1>;
575 clocks = <&cru PCLK_I2C1>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&i2c1_xfer>;
582 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
583 reg = <0x0 0xff680000 0x0 0x10>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&pwm0_pin>;
587 clocks = <&cru PCLK_PWM1>;
593 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
594 reg = <0x0 0xff680010 0x0 0x10>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&pwm1_pin>;
598 clocks = <&cru PCLK_PWM1>;
604 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
605 reg = <0x0 0xff680020 0x0 0x10>;
607 clocks = <&cru PCLK_PWM1>;
613 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
614 reg = <0x0 0xff680030 0x0 0x10>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&pwm3_pin>;
618 clocks = <&cru PCLK_PWM1>;
623 uart2: serial@ff690000 {
624 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
625 reg = <0x0 0xff690000 0x0 0x100>;
626 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
627 clock-names = "baudclk", "apb_pclk";
628 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&uart2_xfer>;
636 pmu: power-management@ff730000 {
637 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
638 reg = <0x0 0xff730000 0x0 0x1000>;
640 power: power-controller {
642 compatible = "rockchip,rk3368-power-controller";
643 #power-domain-cells = <1>;
644 #address-cells = <1>;
648 * Note: Although SCLK_* are the working clocks
649 * of device without including on the NOC, needed for
652 * The clocks on the which NOC:
653 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
654 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
655 * ACLK_RGA is on ACLK_RGA_NIU.
656 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
658 * Which clock are device clocks:
660 * *_IEP IEP:Image Enhancement Processor
661 * *_ISP ISP:Image Signal Processing
662 * *_VIP VIP:Video Input Processor
663 * *_VOP* VOP:Visual Output Processor
671 reg = <RK3368_PD_VIO>;
672 clocks = <&cru ACLK_IEP>,
684 <&cru HCLK_VIO_HDCPMMU>,
685 <&cru PCLK_EDP_CTRL>,
686 <&cru PCLK_HDMI_CTRL>,
692 <&cru PCLK_MIPI_CSI>,
693 <&cru PCLK_MIPI_DSI0>,
694 <&cru SCLK_VOP0_PWM>,
700 <&cru SCLK_HDMI_CEC>,
701 <&cru SCLK_HDMI_HDCP>;
704 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
705 * (video endecoder & decoder) clocks that on the
706 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
709 reg = <RK3368_PD_VIDEO>;
710 clocks = <&cru ACLK_VIDEO>,
712 <&cru SCLK_HEVC_CABAC>,
713 <&cru SCLK_HEVC_CORE>;
716 * Note: ACLK_GPU is the GPU clock,
717 * and on the ACLK_GPU_NIU (NOC).
720 reg = <RK3368_PD_GPU_1>;
721 clocks = <&cru ACLK_GPU_CFG>,
723 <&cru SCLK_GPU_CORE>;
728 pmugrf: syscon@ff738000 {
729 compatible = "rockchip,rk3368-pmugrf", "syscon";
730 reg = <0x0 0xff738000 0x0 0x1000>;
733 cru: clock-controller@ff760000 {
734 compatible = "rockchip,rk3368-cru";
735 reg = <0x0 0xff760000 0x0 0x1000>;
736 rockchip,grf = <&grf>;
741 grf: syscon@ff770000 {
742 compatible = "rockchip,rk3368-grf", "syscon";
743 reg = <0x0 0xff770000 0x0 0x1000>;
746 wdt: watchdog@ff800000 {
747 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
748 reg = <0x0 0xff800000 0x0 0x100>;
749 clocks = <&cru PCLK_WDT>;
750 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
754 gic: interrupt-controller@ffb71000 {
755 compatible = "arm,gic-400";
756 interrupt-controller;
757 #interrupt-cells = <3>;
758 #address-cells = <0>;
760 reg = <0x0 0xffb71000 0x0 0x1000>,
761 <0x0 0xffb72000 0x0 0x1000>,
762 <0x0 0xffb74000 0x0 0x2000>,
763 <0x0 0xffb76000 0x0 0x2000>;
764 interrupts = <GIC_PPI 9
765 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
768 gpu: rogue-g6110@ffa30000 {
769 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
770 reg = <0x0 0xffa30000 0x0 0x10000>;
772 <&cru SCLK_GPU_CORE>,
779 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
780 interrupt-names = "rogue-g6110-irq";
783 i2s_2ch: i2s-2ch@ff890000 {
784 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
785 reg = <0x0 0xff898000 0x0 0x1000>;
786 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
787 #address-cells = <2>;
789 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
790 dma-names = "tx", "rx";
791 clock-names = "i2s_hclk", "i2s_clk";
792 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
796 i2s_8ch: i2s-8ch@ff898000 {
797 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
798 reg = <0x0 0xff898000 0x0 0x1000>;
799 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
800 #address-cells = <1>;
802 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
803 dma-names = "tx", "rx";
804 clock-names = "i2s_hclk", "i2s_clk";
805 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
806 pinctrl-names = "default";
807 pinctrl-0 = <&i2s_8ch_bus>;
812 compatible = "rockchip,rga2";
814 reg = <0x0 0xff920000 0x0 0x1000>;
815 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
817 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
822 compatible = "rockchip,rk3368-pinctrl";
823 rockchip,grf = <&grf>;
824 rockchip,pmu = <&pmugrf>;
825 #address-cells = <0x2>;
829 gpio0: gpio0@ff750000 {
830 compatible = "rockchip,gpio-bank";
831 reg = <0x0 0xff750000 0x0 0x100>;
832 clocks = <&cru PCLK_GPIO0>;
833 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
838 interrupt-controller;
839 #interrupt-cells = <0x2>;
842 gpio1: gpio1@ff780000 {
843 compatible = "rockchip,gpio-bank";
844 reg = <0x0 0xff780000 0x0 0x100>;
845 clocks = <&cru PCLK_GPIO1>;
846 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
851 interrupt-controller;
852 #interrupt-cells = <0x2>;
855 gpio2: gpio2@ff790000 {
856 compatible = "rockchip,gpio-bank";
857 reg = <0x0 0xff790000 0x0 0x100>;
858 clocks = <&cru PCLK_GPIO2>;
859 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
864 interrupt-controller;
865 #interrupt-cells = <0x2>;
868 gpio3: gpio3@ff7a0000 {
869 compatible = "rockchip,gpio-bank";
870 reg = <0x0 0xff7a0000 0x0 0x100>;
871 clocks = <&cru PCLK_GPIO3>;
872 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
877 interrupt-controller;
878 #interrupt-cells = <0x2>;
881 pcfg_pull_up: pcfg-pull-up {
885 pcfg_pull_down: pcfg-pull-down {
889 pcfg_pull_none: pcfg-pull-none {
893 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
895 drive-strength = <12>;
900 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
904 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
908 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
911 emmc_bus1: emmc-bus1 {
912 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
915 emmc_bus4: emmc-bus4 {
916 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
917 <1 19 RK_FUNC_2 &pcfg_pull_up>,
918 <1 20 RK_FUNC_2 &pcfg_pull_up>,
919 <1 21 RK_FUNC_2 &pcfg_pull_up>;
922 emmc_bus8: emmc-bus8 {
923 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
924 <1 19 RK_FUNC_2 &pcfg_pull_up>,
925 <1 20 RK_FUNC_2 &pcfg_pull_up>,
926 <1 21 RK_FUNC_2 &pcfg_pull_up>,
927 <1 22 RK_FUNC_2 &pcfg_pull_up>,
928 <1 23 RK_FUNC_2 &pcfg_pull_up>,
929 <1 24 RK_FUNC_2 &pcfg_pull_up>,
930 <1 25 RK_FUNC_2 &pcfg_pull_up>;
935 rgmii_pins: rgmii-pins {
936 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
937 <3 24 RK_FUNC_1 &pcfg_pull_none>,
938 <3 19 RK_FUNC_1 &pcfg_pull_none>,
939 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
940 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
941 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
942 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
943 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
944 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
945 <3 15 RK_FUNC_1 &pcfg_pull_none>,
946 <3 16 RK_FUNC_1 &pcfg_pull_none>,
947 <3 17 RK_FUNC_1 &pcfg_pull_none>,
948 <3 18 RK_FUNC_1 &pcfg_pull_none>,
949 <3 25 RK_FUNC_1 &pcfg_pull_none>,
950 <3 20 RK_FUNC_1 &pcfg_pull_none>;
953 rmii_pins: rmii-pins {
954 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
955 <3 24 RK_FUNC_1 &pcfg_pull_none>,
956 <3 19 RK_FUNC_1 &pcfg_pull_none>,
957 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
958 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
959 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
960 <3 15 RK_FUNC_1 &pcfg_pull_none>,
961 <3 16 RK_FUNC_1 &pcfg_pull_none>,
962 <3 20 RK_FUNC_1 &pcfg_pull_none>,
963 <3 21 RK_FUNC_1 &pcfg_pull_none>;
968 i2c0_xfer: i2c0-xfer {
969 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
970 <0 7 RK_FUNC_1 &pcfg_pull_none>;
975 i2c1_xfer: i2c1-xfer {
976 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
977 <2 22 RK_FUNC_1 &pcfg_pull_none>;
982 i2c2_xfer: i2c2-xfer {
983 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
984 <3 31 RK_FUNC_2 &pcfg_pull_none>;
989 i2c3_xfer: i2c3-xfer {
990 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
991 <1 17 RK_FUNC_1 &pcfg_pull_none>;
996 i2c4_xfer: i2c4-xfer {
997 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
998 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1003 i2c5_xfer: i2c5-xfer {
1004 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1005 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1010 i2s_8ch_bus: i2s-8ch-bus {
1011 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1012 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1013 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1014 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1015 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1016 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1017 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1018 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1019 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1024 sdio0_bus1: sdio0-bus1 {
1025 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1028 sdio0_bus4: sdio0-bus4 {
1029 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1030 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1031 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1032 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1035 sdio0_cmd: sdio0-cmd {
1036 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1039 sdio0_clk: sdio0-clk {
1040 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1043 sdio0_cd: sdio0-cd {
1044 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1047 sdio0_wp: sdio0-wp {
1048 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1051 sdio0_pwr: sdio0-pwr {
1052 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1055 sdio0_bkpwr: sdio0-bkpwr {
1056 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1059 sdio0_int: sdio0-int {
1060 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1065 sdmmc_clk: sdmmc-clk {
1066 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1069 sdmmc_cmd: sdmmc-cmd {
1070 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1073 sdmmc_cd: sdmcc-cd {
1074 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1077 sdmmc_bus1: sdmmc-bus1 {
1078 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1081 sdmmc_bus4: sdmmc-bus4 {
1082 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1083 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1084 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1085 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1090 spi0_clk: spi0-clk {
1091 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1093 spi0_cs0: spi0-cs0 {
1094 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1096 spi0_cs1: spi0-cs1 {
1097 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1100 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1103 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1108 spi1_clk: spi1-clk {
1109 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1111 spi1_cs0: spi1-cs0 {
1112 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1114 spi1_cs1: spi1-cs1 {
1115 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1118 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1121 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1126 spi2_clk: spi2-clk {
1127 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1129 spi2_cs0: spi2-cs0 {
1130 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1133 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1136 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1141 uart0_xfer: uart0-xfer {
1142 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1143 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1146 uart0_cts: uart0-cts {
1147 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1150 uart0_rts: uart0-rts {
1151 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1156 uart1_xfer: uart1-xfer {
1157 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1158 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1161 uart1_cts: uart1-cts {
1162 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1165 uart1_rts: uart1-rts {
1166 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1171 uart2_xfer: uart2-xfer {
1172 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1173 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1175 /* no rts / cts for uart2 */
1179 uart3_xfer: uart3-xfer {
1180 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1181 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1184 uart3_cts: uart3-cts {
1185 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1188 uart3_rts: uart3-rts {
1189 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1194 uart4_xfer: uart4-xfer {
1195 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1196 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1199 uart4_cts: uart4-cts {
1200 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1203 uart4_rts: uart4-rts {
1204 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1209 pwm0_pin: pwm0-pin {
1210 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1213 vop_pwm_pin: vop-pwm {
1214 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1219 pwm1_pin: pwm1-pin {
1220 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1225 pwm3_pin: pwm3-pin {
1226 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1231 lcdc_lcdc: lcdc-lcdc {
1233 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1234 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1235 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1236 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1237 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1238 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1239 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1240 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1241 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1242 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1243 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1244 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1245 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1246 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1247 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1248 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1249 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1250 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1253 lcdc_gpio: lcdc-gpio {
1255 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1256 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1257 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1258 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1259 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1260 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1261 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1262 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1263 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1264 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1265 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1266 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1267 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1268 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1269 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1270 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1271 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1272 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1278 compatible = "rockchip,rk-fb";
1279 rockchip,disp-mode = <NO_DUAL>;
1280 status = "disabled";
1284 compatible = "rockchip,screen";
1285 status = "disabled";
1288 lcdc: lcdc@ff930000 {
1289 compatible = "rockchip,rk3368-lcdc";
1290 rockchip,grf = <&grf>;
1291 rockchip,pmugrf = <&pmugrf>;
1292 rockchip,cru = <&cru>;
1293 rockchip,prop = <PRMRY>;
1294 rockchip,pwr18 = <0>;
1295 rockchip,iommu-enabled = <1>;
1296 reg = <0x0 0xff930000 0x0 0x10000>;
1297 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1299 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1300 /*power-domains = <&power PD_VIO>;*/
1301 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1302 reset-names = "axi", "ahb", "dclk";
1303 status = "disabled";
1306 mipi: mipi@ff960000 {
1307 compatible = "rockchip,rk3368-dsi";
1308 rockchip,prop = <0>;
1309 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1310 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1311 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1312 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1313 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1314 /*power-domains = <&power PD_VIO>;*/
1315 status = "disabled";
1318 lvds: lvds@ff968000 {
1319 compatible = "rockchip,rk3368-lvds";
1320 rockchip,grf = <&grf>;
1321 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1322 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1323 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1324 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1325 /*power-domains = <&power PD_VIO>;*/
1326 status = "disabled";
1330 compatible = "rockchip,rk32-edp";
1331 reg = <0x0 0xff970000 0x0 0x4000>;
1332 rockchip,grf = <&grf>;
1333 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1334 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1335 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1336 /*power-domains = <&power PD_VIO>;*/
1337 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1338 reset-names = "edp_24m", "edp_apb";
1339 status = "disabled";
1344 compatible = "rockchip,iep_mmu";
1345 reg = <0x0 0xff900800 0x0 0x100>;
1346 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1347 interrupt-names = "iep_mmu";
1348 status = "disabled";
1353 compatible = "rockchip,vip_mmu";
1354 reg = <0x0 0xff950800 0x0 0x100>;
1355 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1356 interrupt-names = "vip_mmu";
1357 status = "disabled";
1360 vopb_mmu: vopb-mmu {
1362 compatible = "rockchip,vopb_mmu";
1363 reg = <0x0 0xff930300 0x0 0x100>;
1364 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1365 interrupt-names = "vop_mmu";
1366 status = "disabled";
1370 dbgname = "isp_mmu";
1371 compatible = "rockchip,isp_mmu";
1372 reg = <0x0 0xff914000 0x0 0x100>,
1373 <0x0 0xff915000 0x0 0x100>;
1374 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1375 interrupt-names = "isp_mmu";
1376 status = "disabled";
1379 hdcp_mmu: hdcp-mmu {
1380 dbgname = "hdcp_mmu";
1381 compatible = "rockchip,hdcp_mmu";
1382 reg = <0x0 0xff940000 0x0 0x100>;
1383 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1384 interrupt-names = "hdcp_mmu";
1385 status = "disabled";
1388 hevc_mmu: hevc-mmu {
1390 compatible = "rockchip,hevc_mmu";
1391 reg = <0x0 0xff9a0440 0x0 0x40>,
1392 <0x0 0xff9a0480 0x0 0x40>;
1393 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1394 interrupt-names = "hevc_mmu";
1395 status = "disabled";
1400 compatible = "rockchip,vpu_mmu";
1401 reg = <0x0 0xff9a0800 0x0 0x100>;
1402 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1404 interrupt-names = "vepu_mmu", "vdpu_mmu";
1405 status = "disabled";