arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/display/mipi_dsi.h>
  50 #include <dt-bindings/power/rk3368-power.h>
  51 #include <dt-bindings/soc/rockchip,boot-mode.h>
  52
  53 / {
  54         compatible = "rockchip,rk3368";
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 ethernet0 = &gmac;
  61                 i2c0 = &i2c0;
  62                 i2c1 = &i2c1;
  63                 i2c2 = &i2c2;
  64                 i2c3 = &i2c3;
  65                 i2c4 = &i2c4;
  66                 i2c5 = &i2c5;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72                 spi0 = &spi0;
  73                 spi1 = &spi1;
  74                 spi2 = &spi2;
  75                 lcdc = &lcdc;
  76         };
  77
  78         cpus {
  79                 #address-cells = <0x2>;
  80                 #size-cells = <0x0>;
  81
  82                 cpu-map {
  83                         cluster0 {
  84                                 core0 {
  85                                         cpu = <&cpu_b0>;
  86                                 };
  87                                 core1 {
  88                                         cpu = <&cpu_b1>;
  89                                 };
  90                                 core2 {
  91                                         cpu = <&cpu_b2>;
  92                                 };
  93                                 core3 {
  94                                         cpu = <&cpu_b3>;
  95                                 };
  96                         };
  97
  98                         cluster1 {
  99                                 core0 {
 100                                         cpu = <&cpu_l0>;
 101                                 };
 102                                 core1 {
 103                                         cpu = <&cpu_l1>;
 104                                 };
 105                                 core2 {
 106                                         cpu = <&cpu_l2>;
 107                                 };
 108                                 core3 {
 109                                         cpu = <&cpu_l3>;
 110                                 };
 111                         };
 112                 };
 113
 114                 idle-states {
 115                         entry-method = "psci";
 116
 117                         cpu_sleep: cpu-sleep-0 {
 118                                 compatible = "arm,idle-state";
 119                                 arm,psci-suspend-param = <0x1010000>;
 120                                 entry-latency-us = <0x3fffffff>;
 121                                 exit-latency-us = <0x40000000>;
 122                                 min-residency-us = <0xffffffff>;
 123                         };
 124                 };
 125
 126                 cpu_l0: cpu@0 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a53", "arm,armv8";
 129                         reg = <0x0 0x0>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         enable-method = "psci";
 132                         clocks = <&cru ARMCLKL>;
 133                         operating-points-v2 = <&cluster1_opp>;
 134                 };
 135
 136                 cpu_l1: cpu@1 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53", "arm,armv8";
 139                         reg = <0x0 0x1>;
 140                         cpu-idle-states = <&cpu_sleep>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster1_opp>;
 144                 };
 145
 146                 cpu_l2: cpu@2 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x2>;
 150                         cpu-idle-states = <&cpu_sleep>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKL>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_l3: cpu@3 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a53", "arm,armv8";
 159                         reg = <0x0 0x3>;
 160                         cpu-idle-states = <&cpu_sleep>;
 161                         enable-method = "psci";
 162                         clocks = <&cru ARMCLKL>;
 163                         operating-points-v2 = <&cluster1_opp>;
 164                 };
 165
 166                 cpu_b0: cpu@100 {
 167                         device_type = "cpu";
 168                         compatible = "arm,cortex-a53", "arm,armv8";
 169                         reg = <0x0 0x100>;
 170                         cpu-idle-states = <&cpu_sleep>;
 171                         enable-method = "psci";
 172                         clocks = <&cru ARMCLKB>;
 173                         operating-points-v2 = <&cluster0_opp>;
 174                 };
 175
 176                 cpu_b1: cpu@101 {
 177                         device_type = "cpu";
 178                         compatible = "arm,cortex-a53", "arm,armv8";
 179                         reg = <0x0 0x101>;
 180                         cpu-idle-states = <&cpu_sleep>;
 181                         enable-method = "psci";
 182                         clocks = <&cru ARMCLKB>;
 183                         operating-points-v2 = <&cluster0_opp>;
 184                 };
 185
 186                 cpu_b2: cpu@102 {
 187                         device_type = "cpu";
 188                         compatible = "arm,cortex-a53", "arm,armv8";
 189                         reg = <0x0 0x102>;
 190                         cpu-idle-states = <&cpu_sleep>;
 191                         enable-method = "psci";
 192                         clocks = <&cru ARMCLKB>;
 193                         operating-points-v2 = <&cluster0_opp>;
 194                 };
 195
 196                 cpu_b3: cpu@103 {
 197                         device_type = "cpu";
 198                         compatible = "arm,cortex-a53", "arm,armv8";
 199                         reg = <0x0 0x103>;
 200                         cpu-idle-states = <&cpu_sleep>;
 201                         enable-method = "psci";
 202                         clocks = <&cru ARMCLKB>;
 203                         operating-points-v2 = <&cluster0_opp>;
 204                 };
 205         };
 206
 207         cluster0_opp: opp_table0 {
 208                 compatible = "operating-points-v2";
 209                 opp-shared;
 210
 211                 opp@408000000 {
 212                         opp-hz = /bits/ 64 <408000000>;
 213                         opp-microvolt = <1200000>;
 214                         clock-latency-ns = <40000>;
 215                         opp-suspend;
 216                 };
 217                 opp@600000000 {
 218                         opp-hz = /bits/ 64 <600000000>;
 219                         opp-microvolt = <1200000>;
 220                 };
 221                 opp@816000000 {
 222                         opp-hz = /bits/ 64 <816000000>;
 223                         opp-microvolt = <1200000>;
 224                 };
 225                 opp@1008000000 {
 226                         opp-hz = /bits/ 64 <1008000000>;
 227                         opp-microvolt = <1200000>;
 228                 };
 229                 opp@1200000000 {
 230                         opp-hz = /bits/ 64 <1200000000>;
 231                         opp-microvolt = <1200000>;
 232                 };
 233         };
 234
 235         cluster1_opp: opp_table1 {
 236                 compatible = "operating-points-v2";
 237                 opp-shared;
 238
 239                 opp@408000000 {
 240                         opp-hz = /bits/ 64 <408000000>;
 241                         opp-microvolt = <1200000>;
 242                         clock-latency-ns = <40000>;
 243                         opp-suspend;
 244                 };
 245                 opp@600000000 {
 246                         opp-hz = /bits/ 64 <600000000>;
 247                         opp-microvolt = <1200000>;
 248                 };
 249                 opp@816000000 {
 250                         opp-hz = /bits/ 64 <816000000>;
 251                         opp-microvolt = <1200000>;
 252                 };
 253                 opp@1008000000 {
 254                         opp-hz = /bits/ 64 <1008000000>;
 255                         opp-microvolt = <1200000>;
 256                 };
 257         };
 258
 259         arm-pmu {
 260                 compatible = "arm,armv8-pmuv3";
 261                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 269                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 270                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 271                                      <&cpu_b2>, <&cpu_b3>;
 272         };
 273
 274         amba {
 275                 compatible = "arm,amba-bus";
 276                 #address-cells = <2>;
 277                 #size-cells = <2>;
 278                 ranges;
 279
 280                 dmac_peri: dma-controller@ff250000 {
 281                         compatible = "arm,pl330", "arm,primecell";
 282                         reg = <0x0 0xff250000 0x0 0x4000>;
 283                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 284                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 285                         #dma-cells = <1>;
 286                         clocks = <&cru ACLK_DMAC_PERI>;
 287                         clock-names = "apb_pclk";
 288                         arm,pl330-broken-no-flushp;
 289                         peripherals-req-type-burst;
 290                 };
 291
 292                 dmac_bus: dma-controller@ff600000 {
 293                         compatible = "arm,pl330", "arm,primecell";
 294                         reg = <0x0 0xff600000 0x0 0x4000>;
 295                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 297                         #dma-cells = <1>;
 298                         clocks = <&cru ACLK_DMAC_BUS>;
 299                         clock-names = "apb_pclk";
 300                         arm,pl330-broken-no-flushp;
 301                         peripherals-req-type-burst;
 302                 };
 303         };
 304
 305         psci {
 306                 compatible = "arm,psci-0.2";
 307                 method = "smc";
 308         };
 309
 310         timer {
 311                 compatible = "arm,armv8-timer";
 312                 interrupts = <GIC_PPI 13
 313                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 314                              <GIC_PPI 14
 315                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 316                              <GIC_PPI 11
 317                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 318                              <GIC_PPI 10
 319                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 320         };
 321
 322         xin24m: oscillator {
 323                 compatible = "fixed-clock";
 324                 clock-frequency = <24000000>;
 325                 clock-output-names = "xin24m";
 326                 #clock-cells = <0>;
 327         };
 328
 329         sdmmc: rksdmmc@ff0c0000 {
 330                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 331                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 332                 clock-freq-min-max = <400000 150000000>;
 333                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 334                 clock-names = "biu", "ciu";
 335                 fifo-depth = <0x100>;
 336                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 337                 status = "disabled";
 338         };
 339
 340         sdio0: dwmmc@ff0d0000 {
 341                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 342                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 343                 clock-freq-min-max = <400000 150000000>;
 344                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 345                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 346                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 347                 fifo-depth = <0x100>;
 348                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 349                 status = "disabled";
 350         };
 351
 352         emmc: rksdmmc@ff0f0000 {
 353                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 354                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 355                 clock-freq-min-max = <400000 150000000>;
 356                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 357                 clock-names = "biu", "ciu";
 358                 fifo-depth = <0x100>;
 359                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 360                 status = "disabled";
 361         };
 362
 363         saradc: saradc@ff100000 {
 364                 compatible = "rockchip,saradc";
 365                 reg = <0x0 0xff100000 0x0 0x100>;
 366                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 367                 #io-channel-cells = <1>;
 368                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 369                 clock-names = "saradc", "apb_pclk";
 370                 resets = <&cru SRST_SARADC>;
 371                 reset-names = "saradc-apb";
 372                 status = "disabled";
 373         };
 374
 375         spi0: spi@ff110000 {
 376                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 377                 reg = <0x0 0xff110000 0x0 0x1000>;
 378                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 379                 clock-names = "spiclk", "apb_pclk";
 380                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 383                 #address-cells = <1>;
 384                 #size-cells = <0>;
 385                 status = "disabled";
 386         };
 387
 388         spi1: spi@ff120000 {
 389                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 390                 reg = <0x0 0xff120000 0x0 0x1000>;
 391                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 392                 clock-names = "spiclk", "apb_pclk";
 393                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 394                 pinctrl-names = "default";
 395                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398                 status = "disabled";
 399         };
 400
 401         spi2: spi@ff130000 {
 402                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 403                 reg = <0x0 0xff130000 0x0 0x1000>;
 404                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 405                 clock-names = "spiclk", "apb_pclk";
 406                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 409                 #address-cells = <1>;
 410                 #size-cells = <0>;
 411                 status = "disabled";
 412         };
 413
 414         i2c0: i2c@ff650000 {
 415                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 416                 reg = <0x0 0xff650000 0x0 0x1000>;
 417                 clocks = <&cru PCLK_I2C0>;
 418                 clock-names = "i2c";
 419                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&i2c0_xfer>;
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 status = "disabled";
 425         };
 426
 427         i2c2: i2c@ff140000 {
 428                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 429                 reg = <0x0 0xff140000 0x0 0x1000>;
 430                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 431                 #address-cells = <1>;
 432                 #size-cells = <0>;
 433                 clock-names = "i2c";
 434                 clocks = <&cru PCLK_I2C2>;
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&i2c2_xfer>;
 437                 status = "disabled";
 438         };
 439
 440         i2c3: i2c@ff150000 {
 441                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 442                 reg = <0x0 0xff150000 0x0 0x1000>;
 443                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 clock-names = "i2c";
 447                 clocks = <&cru PCLK_I2C3>;
 448                 pinctrl-names = "default";
 449                 pinctrl-0 = <&i2c3_xfer>;
 450                 status = "disabled";
 451         };
 452
 453         i2c4: i2c@ff160000 {
 454                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 455                 reg = <0x0 0xff160000 0x0 0x1000>;
 456                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 457                 #address-cells = <1>;
 458                 #size-cells = <0>;
 459                 clock-names = "i2c";
 460                 clocks = <&cru PCLK_I2C4>;
 461                 pinctrl-names = "default";
 462                 pinctrl-0 = <&i2c4_xfer>;
 463                 status = "disabled";
 464         };
 465
 466         i2c5: i2c@ff170000 {
 467                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 468                 reg = <0x0 0xff170000 0x0 0x1000>;
 469                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 470                 #address-cells = <1>;
 471                 #size-cells = <0>;
 472                 clock-names = "i2c";
 473                 clocks = <&cru PCLK_I2C5>;
 474                 pinctrl-names = "default";
 475                 pinctrl-0 = <&i2c5_xfer>;
 476                 status = "disabled";
 477         };
 478
 479         uart0: serial@ff180000 {
 480                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 481                 reg = <0x0 0xff180000 0x0 0x100>;
 482                 clock-frequency = <24000000>;
 483                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 484                 clock-names = "baudclk", "apb_pclk";
 485                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 486                 reg-shift = <2>;
 487                 reg-io-width = <4>;
 488                 status = "disabled";
 489         };
 490
 491         uart1: serial@ff190000 {
 492                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 493                 reg = <0x0 0xff190000 0x0 0x100>;
 494                 clock-frequency = <24000000>;
 495                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 496                 clock-names = "baudclk", "apb_pclk";
 497                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 498                 reg-shift = <2>;
 499                 reg-io-width = <4>;
 500                 status = "disabled";
 501         };
 502
 503         uart3: serial@ff1b0000 {
 504                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 505                 reg = <0x0 0xff1b0000 0x0 0x100>;
 506                 clock-frequency = <24000000>;
 507                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 508                 clock-names = "baudclk", "apb_pclk";
 509                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 510                 reg-shift = <2>;
 511                 reg-io-width = <4>;
 512                 status = "disabled";
 513         };
 514
 515         uart4: serial@ff1c0000 {
 516                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 517                 reg = <0x0 0xff1c0000 0x0 0x100>;
 518                 clock-frequency = <24000000>;
 519                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 520                 clock-names = "baudclk", "apb_pclk";
 521                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 522                 reg-shift = <2>;
 523                 reg-io-width = <4>;
 524                 status = "disabled";
 525         };
 526
 527         gmac: ethernet@ff290000 {
 528                 compatible = "rockchip,rk3368-gmac";
 529                 reg = <0x0 0xff290000 0x0 0x10000>;
 530                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 531                 interrupt-names = "macirq";
 532                 rockchip,grf = <&grf>;
 533                 clocks = <&cru SCLK_MAC>,
 534                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 535                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 536                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 537                 clock-names = "stmmaceth",
 538                         "mac_clk_rx", "mac_clk_tx",
 539                         "clk_mac_ref", "clk_mac_refout",
 540                         "aclk_mac", "pclk_mac";
 541                 status = "disabled";
 542         };
 543
 544         nandc0: nandc@ff400000 {
 545                 compatible = "rockchip,rk-nandc";
 546                 reg = <0x0 0xff400000 0x0 0x4000>;
 547                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 548                 nandc_id = <0>;
 549                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 550                 clock-names = "clk_nandc", "hclk_nandc";
 551                 status = "disabled";
 552         };
 553
 554         usb_host0_ehci: usb@ff500000 {
 555                 compatible = "generic-ehci";
 556                 reg = <0x0 0xff500000 0x0 0x100>;
 557                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 558                 clocks = <&cru HCLK_HOST0>;
 559                 clock-names = "usbhost";
 560                 status = "disabled";
 561         };
 562
 563         usb_otg: usb@ff580000 {
 564                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 565                                 "snps,dwc2";
 566                 reg = <0x0 0xff580000 0x0 0x40000>;
 567                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 568                 clocks = <&cru HCLK_OTG0>;
 569                 clock-names = "otg";
 570                 dr_mode = "otg";
 571                 g-np-tx-fifo-size = <16>;
 572                 g-rx-fifo-size = <275>;
 573                 g-tx-fifo-size = <256 128 128 64 64 32>;
 574                 g-use-dma;
 575                 status = "disabled";
 576         };
 577
 578         ddrpctl: syscon@ff610000 {
 579                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 580                 reg = <0x0 0xff610000 0x0 0x400>;
 581         };
 582
 583         i2c1: i2c@ff660000 {
 584                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 585                 reg = <0x0 0xff660000 0x0 0x1000>;
 586                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 clock-names = "i2c";
 590                 clocks = <&cru PCLK_I2C1>;
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&i2c1_xfer>;
 593                 status = "disabled";
 594         };
 595
 596         pwm0: pwm@ff680000 {
 597                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 598                 reg = <0x0 0xff680000 0x0 0x10>;
 599                 #pwm-cells = <3>;
 600                 pinctrl-names = "default";
 601                 pinctrl-0 = <&pwm0_pin>;
 602                 clocks = <&cru PCLK_PWM1>;
 603                 clock-names = "pwm";
 604                 status = "disabled";
 605         };
 606
 607         pwm1: pwm@ff680010 {
 608                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 609                 reg = <0x0 0xff680010 0x0 0x10>;
 610                 #pwm-cells = <3>;
 611                 pinctrl-names = "default";
 612                 pinctrl-0 = <&pwm1_pin>;
 613                 clocks = <&cru PCLK_PWM1>;
 614                 clock-names = "pwm";
 615                 status = "disabled";
 616         };
 617
 618         pwm2: pwm@ff680020 {
 619                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 620                 reg = <0x0 0xff680020 0x0 0x10>;
 621                 #pwm-cells = <3>;
 622                 clocks = <&cru PCLK_PWM1>;
 623                 clock-names = "pwm";
 624                 status = "disabled";
 625         };
 626
 627         pwm3: pwm@ff680030 {
 628                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 629                 reg = <0x0 0xff680030 0x0 0x10>;
 630                 #pwm-cells = <3>;
 631                 pinctrl-names = "default";
 632                 pinctrl-0 = <&pwm3_pin>;
 633                 clocks = <&cru PCLK_PWM1>;
 634                 clock-names = "pwm";
 635                 status = "disabled";
 636         };
 637
 638         uart2: serial@ff690000 {
 639                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 640                 reg = <0x0 0xff690000 0x0 0x100>;
 641                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 642                 clock-names = "baudclk", "apb_pclk";
 643                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 644                 pinctrl-names = "default";
 645                 pinctrl-0 = <&uart2_xfer>;
 646                 reg-shift = <2>;
 647                 reg-io-width = <4>;
 648                 status = "disabled";
 649         };
 650
 651         pmu: power-management@ff730000 {
 652                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 653                 reg = <0x0 0xff730000 0x0 0x1000>;
 654
 655                 power: power-controller {
 656                         status = "disabled";
 657                         compatible = "rockchip,rk3368-power-controller";
 658                         #power-domain-cells = <1>;
 659                         #address-cells = <1>;
 660                         #size-cells = <0>;
 661
 662                         /*
 663                          * Note: Although SCLK_* are the working clocks
 664                          * of device without including on the NOC, needed for
 665                          * synchronous reset.
 666                          *
 667                          * The clocks on the which NOC:
 668                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 669                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 670                          * ACLK_RGA is on ACLK_RGA_NIU.
 671                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 672                          *
 673                          * Which clock are device clocks:
 674                          *      clocks          devices
 675                          *      *_IEP           IEP:Image Enhancement Processor
 676                          *      *_ISP           ISP:Image Signal Processing
 677                          *      *_VIP           VIP:Video Input Processor
 678                          *      *_VOP*          VOP:Visual Output Processor
 679                          *      *_RGA           RGA
 680                          *      *_EDP*          EDP
 681                          *      *_DPHY*         LVDS
 682                          *      *_HDMI          HDMI
 683                          *      *_MIPI_*        MIPI
 684                          */
 685                         pd_vio {
 686                                 reg = <RK3368_PD_VIO>;
 687                                 clocks = <&cru ACLK_IEP>,
 688                                          <&cru ACLK_ISP>,
 689                                          <&cru ACLK_VIP>,
 690                                          <&cru ACLK_RGA>,
 691                                          <&cru ACLK_VOP>,
 692                                          <&cru ACLK_VOP_IEP>,
 693                                          <&cru DCLK_VOP>,
 694                                          <&cru HCLK_IEP>,
 695                                          <&cru HCLK_ISP>,
 696                                          <&cru HCLK_RGA>,
 697                                          <&cru HCLK_VIP>,
 698                                          <&cru HCLK_VOP>,
 699                                          <&cru HCLK_VIO_HDCPMMU>,
 700                                          <&cru PCLK_EDP_CTRL>,
 701                                          <&cru PCLK_HDMI_CTRL>,
 702                                          <&cru PCLK_HDCP>,
 703                                          <&cru PCLK_ISP>,
 704                                          <&cru PCLK_VIP>,
 705                                          <&cru PCLK_DPHYRX>,
 706                                          <&cru PCLK_DPHYTX0>,
 707                                          <&cru PCLK_MIPI_CSI>,
 708                                          <&cru PCLK_MIPI_DSI0>,
 709                                          <&cru SCLK_VOP0_PWM>,
 710                                          <&cru SCLK_EDP_24M>,
 711                                          <&cru SCLK_EDP>,
 712                                          <&cru SCLK_HDCP>,
 713                                          <&cru SCLK_ISP>,
 714                                          <&cru SCLK_RGA>,
 715                                          <&cru SCLK_HDMI_CEC>,
 716                                          <&cru SCLK_HDMI_HDCP>;
 717                         };
 718                         /*
 719                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 720                          * (video endecoder & decoder) clocks that on the
 721                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 722                          */
 723                         pd_video {
 724                                 reg = <RK3368_PD_VIDEO>;
 725                                 clocks = <&cru ACLK_VIDEO>,
 726                                          <&cru HCLK_VIDEO>,
 727                                          <&cru SCLK_HEVC_CABAC>,
 728                                          <&cru SCLK_HEVC_CORE>;
 729                         };
 730                         /*
 731                          * Note: ACLK_GPU is the GPU clock,
 732                          * and on the ACLK_GPU_NIU (NOC).
 733                          */
 734                         pd_gpu_1 {
 735                                 reg = <RK3368_PD_GPU_1>;
 736                                 clocks = <&cru ACLK_GPU_CFG>,
 737                                          <&cru ACLK_GPU_MEM>,
 738                                          <&cru SCLK_GPU_CORE>;
 739                         };
 740                 };
 741         };
 742
 743         pmugrf: syscon@ff738000 {
 744                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 745                 reg = <0x0 0xff738000 0x0 0x1000>;
 746
 747                 reboot-mode {
 748                         compatible = "syscon-reboot-mode";
 749                         offset = <0x200>;
 750                         mode-normal = <BOOT_NORMAL>;
 751                         mode-recovery = <BOOT_RECOVERY>;
 752                         mode-bootloader = <BOOT_FASTBOOT>;
 753                         mode-loader = <BOOT_BL_DOWNLOAD>;
 754
 755                 };
 756         };
 757
 758         cru: clock-controller@ff760000 {
 759                 compatible = "rockchip,rk3368-cru";
 760                 reg = <0x0 0xff760000 0x0 0x1000>;
 761                 rockchip,grf = <&grf>;
 762                 #clock-cells = <1>;
 763                 #reset-cells = <1>;
 764                 assigned-clocks =
 765                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 766                         <&cru PLL_NPLL>,
 767                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
 768                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
 769                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
 770                 assigned-clock-rates =
 771                         <576000000>, <400000000>,
 772                         <1188000000>,
 773                         <300000000>, <300000000>,
 774                         <150000000>, <150000000>,
 775                         <75000000>, <75000000>;
 776         };
 777
 778         grf: syscon@ff770000 {
 779                 compatible = "rockchip,rk3368-grf", "syscon";
 780                 reg = <0x0 0xff770000 0x0 0x1000>;
 781         };
 782
 783         wdt: watchdog@ff800000 {
 784                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 785                 reg = <0x0 0xff800000 0x0 0x100>;
 786                 clocks = <&cru PCLK_WDT>;
 787                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 788                 status = "disabled";
 789         };
 790
 791         gic: interrupt-controller@ffb71000 {
 792                 compatible = "arm,gic-400";
 793                 interrupt-controller;
 794                 #interrupt-cells = <3>;
 795                 #address-cells = <0>;
 796
 797                 reg = <0x0 0xffb71000 0x0 0x1000>,
 798                       <0x0 0xffb72000 0x0 0x2000>,
 799                       <0x0 0xffb74000 0x0 0x2000>,
 800                       <0x0 0xffb76000 0x0 0x2000>;
 801                 interrupts = <GIC_PPI 9
 802                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 803         };
 804
 805         gpu: rogue-g6110@ffa30000 {
 806                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
 807                 reg = <0x0 0xffa30000 0x0 0x10000>;
 808                 clocks =
 809                         <&cru SCLK_GPU_CORE>,
 810                         <&cru ACLK_GPU_MEM>,
 811                         <&cru ACLK_GPU_CFG>;
 812                 clock-names =
 813                         "sclk_gpu_core",
 814                         "aclk_gpu_mem",
 815                         "aclk_gpu_cfg";
 816                 operating-points = <
 817                         /* KHz uV */
 818                         200000 1100000
 819                         288000 1100000
 820                         400000 1150000
 821                         576000 1200000
 822                 >;
 823                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 824                 interrupt-names = "rogue-g6110-irq";
 825         };
 826
 827         i2s_2ch: i2s-2ch@ff890000 {
 828                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 829                 reg = <0x0 0xff890000 0x0 0x1000>;
 830                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 831                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 832                 dma-names = "tx", "rx";
 833                 clock-names = "i2s_clk", "i2s_hclk";
 834                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 835                 status = "disabled";
 836         };
 837
 838         i2s_8ch: i2s-8ch@ff898000 {
 839                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 840                 reg = <0x0 0xff898000 0x0 0x1000>;
 841                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 842                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 843                 dma-names = "tx", "rx";
 844                 clock-names = "i2s_clk", "i2s_hclk";
 845                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 846                 pinctrl-names = "default";
 847                 pinctrl-0 = <&i2s_8ch_bus>;
 848                 status = "disabled";
 849         };
 850
 851         isp: isp@ff910000 {
 852                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
 853                 reg = <0x0 0xff910000 0x0 0x10000>;
 854                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 855                 /*power-domains = <&power PD_VIO>;*/
 856                 clocks =
 857                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
 858                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
 859                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
 860                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
 861                 clock-names =
 862                         "aclk_isp", "hclk_isp", "clk_isp",
 863                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
 864                         "clk_cif_pll", "hclk_mipiphy1",
 865                         "pclk_dphyrx", "clk_vio0_noc";
 866                 pinctrl-names =
 867                         "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
 868                         "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
 869                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 870                         "isp_flash_as_trigger_out";
 871                 pinctrl-0 = <&cif_clkout>;
 872                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
 873                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
 874                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
 875                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
 876                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
 877                 pinctrl-6 = <&cif_clkout>;
 878                 pinctrl-7 = <&cif_clkout &isp_prelight>;
 879                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
 880                 pinctrl-9 = <&isp_flash_trigger>;
 881                 rockchip,isp,mipiphy = <2>;
 882                 rockchip,isp,cifphy = <1>;
 883                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
 884                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
 885                 rockchip,grf = <&grf>;
 886                 rockchip,cru = <&cru>;
 887                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 888                 rockchip,isp,iommu_enable = <1>;
 889                 status = "disabled";
 890         };
 891
 892         rga: rga@ff920000 {
 893                 compatible = "rockchip,rga2";
 894                 dev_mode = <1>;
 895                 reg = <0x0 0xff920000 0x0 0x1000>;
 896                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 897                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 898                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 899                 status = "disabled";
 900         };
 901
 902         pinctrl: pinctrl {
 903                 compatible = "rockchip,rk3368-pinctrl";
 904                 rockchip,grf = <&grf>;
 905                 rockchip,pmu = <&pmugrf>;
 906                 #address-cells = <0x2>;
 907                 #size-cells = <0x2>;
 908                 ranges;
 909
 910                 gpio0: gpio0@ff750000 {
 911                         compatible = "rockchip,gpio-bank";
 912                         reg = <0x0 0xff750000 0x0 0x100>;
 913                         clocks = <&cru PCLK_GPIO0>;
 914                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 915
 916                         gpio-controller;
 917                         #gpio-cells = <0x2>;
 918
 919                         interrupt-controller;
 920                         #interrupt-cells = <0x2>;
 921                 };
 922
 923                 gpio1: gpio1@ff780000 {
 924                         compatible = "rockchip,gpio-bank";
 925                         reg = <0x0 0xff780000 0x0 0x100>;
 926                         clocks = <&cru PCLK_GPIO1>;
 927                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 928
 929                         gpio-controller;
 930                         #gpio-cells = <0x2>;
 931
 932                         interrupt-controller;
 933                         #interrupt-cells = <0x2>;
 934                 };
 935
 936                 gpio2: gpio2@ff790000 {
 937                         compatible = "rockchip,gpio-bank";
 938                         reg = <0x0 0xff790000 0x0 0x100>;
 939                         clocks = <&cru PCLK_GPIO2>;
 940                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
 941
 942                         gpio-controller;
 943                         #gpio-cells = <0x2>;
 944
 945                         interrupt-controller;
 946                         #interrupt-cells = <0x2>;
 947                 };
 948
 949                 gpio3: gpio3@ff7a0000 {
 950                         compatible = "rockchip,gpio-bank";
 951                         reg = <0x0 0xff7a0000 0x0 0x100>;
 952                         clocks = <&cru PCLK_GPIO3>;
 953                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
 954
 955                         gpio-controller;
 956                         #gpio-cells = <0x2>;
 957
 958                         interrupt-controller;
 959                         #interrupt-cells = <0x2>;
 960                 };
 961
 962                 pcfg_pull_up: pcfg-pull-up {
 963                         bias-pull-up;
 964                 };
 965
 966                 pcfg_pull_down: pcfg-pull-down {
 967                         bias-pull-down;
 968                 };
 969
 970                 pcfg_pull_none: pcfg-pull-none {
 971                         bias-disable;
 972                 };
 973
 974                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 975                         bias-disable;
 976                         drive-strength = <12>;
 977                 };
 978
 979                 emmc {
 980                         emmc_clk: emmc-clk {
 981                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 982                         };
 983
 984                         emmc_cmd: emmc-cmd {
 985                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
 986                         };
 987
 988                         emmc_pwr: emmc-pwr {
 989                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
 990                         };
 991
 992                         emmc_bus1: emmc-bus1 {
 993                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
 994                         };
 995
 996                         emmc_bus4: emmc-bus4 {
 997                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 998                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 999                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1000                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1001                         };
1002
1003                         emmc_bus8: emmc-bus8 {
1004                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1005                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1006                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1007                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1008                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1009                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1010                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1011                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1012                         };
1013                 };
1014
1015                 gmac {
1016                         rgmii_pins: rgmii-pins {
1017                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1018                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1019                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1020                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1021                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1022                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1023                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1024                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1025                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1026                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1027                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1028                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1029                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1030                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1031                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1032                         };
1033
1034                         rmii_pins: rmii-pins {
1035                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1036                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1037                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1038                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1039                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1040                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1041                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1042                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1043                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1044                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1045                         };
1046                 };
1047
1048                 hdmi_i2c {
1049                         hdmii2c_xfer: hdmii2c-xfer {
1050                                 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1051                                                 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1052                         };
1053                 };
1054
1055                 hdmi_pin {
1056                         hdmi_cec: hdmi-cec {
1057                                 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1058                         };
1059                 };
1060
1061                 i2c0 {
1062                         i2c0_xfer: i2c0-xfer {
1063                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1064                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1065                         };
1066                 };
1067
1068                 i2c1 {
1069                         i2c1_xfer: i2c1-xfer {
1070                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1071                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1072                         };
1073                 };
1074
1075                 i2c2 {
1076                         i2c2_xfer: i2c2-xfer {
1077                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1078                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1079                         };
1080                 };
1081
1082                 i2c3 {
1083                         i2c3_xfer: i2c3-xfer {
1084                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1085                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1086                         };
1087                 };
1088
1089                 i2c4 {
1090                         i2c4_xfer: i2c4-xfer {
1091                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1092                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1093                         };
1094                 };
1095
1096                 i2c5 {
1097                         i2c5_xfer: i2c5-xfer {
1098                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1099                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1100                         };
1101                         i2c5_gpio: i2c5-gpio {
1102                                 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
1103                                                 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
1104                         };
1105                 };
1106
1107                 i2s {
1108                         i2s_8ch_bus: i2s-8ch-bus {
1109                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1110                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1111                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1112                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1113                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1114                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1115                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1116                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1117                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1118                         };
1119                 };
1120
1121                 sdio0 {
1122                         sdio0_bus1: sdio0-bus1 {
1123                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1124                         };
1125
1126                         sdio0_bus4: sdio0-bus4 {
1127                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1128                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1129                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1130                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1131                         };
1132
1133                         sdio0_cmd: sdio0-cmd {
1134                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1135                         };
1136
1137                         sdio0_clk: sdio0-clk {
1138                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1139                         };
1140
1141                         sdio0_cd: sdio0-cd {
1142                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1143                         };
1144
1145                         sdio0_wp: sdio0-wp {
1146                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1147                         };
1148
1149                         sdio0_pwr: sdio0-pwr {
1150                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1151                         };
1152
1153                         sdio0_bkpwr: sdio0-bkpwr {
1154                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1155                         };
1156
1157                         sdio0_int: sdio0-int {
1158                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1159                         };
1160                 };
1161
1162                 sdmmc {
1163                         sdmmc_clk: sdmmc-clk {
1164                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1165                         };
1166
1167                         sdmmc_cmd: sdmmc-cmd {
1168                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1169                         };
1170
1171                         sdmmc_cd: sdmcc-cd {
1172                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1173                         };
1174
1175                         sdmmc_bus1: sdmmc-bus1 {
1176                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1177                         };
1178
1179                         sdmmc_bus4: sdmmc-bus4 {
1180                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1181                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1182                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1183                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1184                         };
1185                 };
1186
1187                 spi0 {
1188                         spi0_clk: spi0-clk {
1189                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1190                         };
1191                         spi0_cs0: spi0-cs0 {
1192                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1193                         };
1194                         spi0_cs1: spi0-cs1 {
1195                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1196                         };
1197                         spi0_tx: spi0-tx {
1198                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1199                         };
1200                         spi0_rx: spi0-rx {
1201                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1202                         };
1203                 };
1204
1205                 spi1 {
1206                         spi1_clk: spi1-clk {
1207                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1208                         };
1209                         spi1_cs0: spi1-cs0 {
1210                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1211                         };
1212                         spi1_cs1: spi1-cs1 {
1213                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1214                         };
1215                         spi1_rx: spi1-rx {
1216                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1217                         };
1218                         spi1_tx: spi1-tx {
1219                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1220                         };
1221                 };
1222
1223                 spi2 {
1224                         spi2_clk: spi2-clk {
1225                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1226                         };
1227                         spi2_cs0: spi2-cs0 {
1228                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1229                         };
1230                         spi2_rx: spi2-rx {
1231                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1232                         };
1233                         spi2_tx: spi2-tx {
1234                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1235                         };
1236                 };
1237
1238                 uart0 {
1239                         uart0_xfer: uart0-xfer {
1240                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1241                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1242                         };
1243
1244                         uart0_cts: uart0-cts {
1245                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1246                         };
1247
1248                         uart0_rts: uart0-rts {
1249                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1250                         };
1251                 };
1252
1253                 uart1 {
1254                         uart1_xfer: uart1-xfer {
1255                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1256                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1257                         };
1258
1259                         uart1_cts: uart1-cts {
1260                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1261                         };
1262
1263                         uart1_rts: uart1-rts {
1264                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1265                         };
1266                 };
1267
1268                 uart2 {
1269                         uart2_xfer: uart2-xfer {
1270                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1271                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1272                         };
1273                         /* no rts / cts for uart2 */
1274                 };
1275
1276                 uart3 {
1277                         uart3_xfer: uart3-xfer {
1278                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1279                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1280                         };
1281
1282                         uart3_cts: uart3-cts {
1283                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1284                         };
1285
1286                         uart3_rts: uart3-rts {
1287                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1288                         };
1289                 };
1290
1291                 uart4 {
1292                         uart4_xfer: uart4-xfer {
1293                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1294                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1295                         };
1296
1297                         uart4_cts: uart4-cts {
1298                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1299                         };
1300
1301                         uart4_rts: uart4-rts {
1302                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1303                         };
1304                 };
1305
1306                 pwm0 {
1307                         pwm0_pin: pwm0-pin {
1308                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1309                         };
1310
1311                         vop_pwm_pin: vop-pwm {
1312                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1313                         };
1314                 };
1315
1316                 pwm1 {
1317                         pwm1_pin: pwm1-pin {
1318                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1319                         };
1320                 };
1321
1322                 pwm3 {
1323                         pwm3_pin: pwm3-pin {
1324                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1325                         };
1326                 };
1327
1328                 lcdc {
1329                         lcdc_lcdc: lcdc-lcdc {
1330                                 rockchip,pins =
1331                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1332                                                 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1333                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1334                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1335                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1336                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1337                                                 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1338                                                 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1339                                                 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1340                                                 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1341                                                 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1342                                                 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1343                                                 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1344                                                 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1345                                                 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1346                                                 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1347                                                 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1348                                                 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1349                         };
1350
1351                         lcdc_gpio: lcdc-gpio {
1352                                 rockchip,pins =
1353                                                 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1354                                                 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1355                                                 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1356                                                 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1357                                                 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1358                                                 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1359                                                 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1360                                                 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1361                                                 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1362                                                 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1363                                                 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1364                                                 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1365                                                 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1366                                                 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1367                                                 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1368                                                 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1369                                                 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1370                                                 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1371                         };
1372                 };
1373
1374                 isp {
1375                         cif_clkout: cif-clkout {
1376                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1377                         };
1378
1379                         isp_dvp_d2d9: isp-dvp-d2d9 {
1380                                 rockchip,pins =
1381                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1382                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1383                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1384                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1385                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1386                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1387                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1388                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1389                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1390                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1391                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1392                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1393                         };
1394
1395                         isp_dvp_d0d1: isp-dvp-d0d1 {
1396                                 rockchip,pins =
1397                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1398                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1399                         };
1400
1401                         isp_dvp_d10d11:isp_d10d11 {
1402                                 rockchip,pins =
1403                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1404                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1405                         };
1406
1407                         isp_dvp_d0d7: isp-dvp-d0d7 {
1408                                 rockchip,pins =
1409                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1410                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1411                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1412                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1413                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1414                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1415                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1416                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1417                         };
1418
1419                         isp_dvp_d4d11: isp-dvp-d4d11 {
1420                                 rockchip,pins =
1421                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1422                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1423                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1424                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1425                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1426                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1427                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1428                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1429                         };
1430
1431                         isp_shutter: isp-shutter {
1432                                 rockchip,pins =
1433                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1434                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1435                         };
1436
1437                         isp_flash_trigger: isp-flash-trigger {
1438                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1439                         };
1440
1441                         isp_prelight: isp-prelight {
1442                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1443                         };
1444
1445                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1446                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1447                         };
1448                 };
1449         };
1450
1451         fb: fb {
1452                 compatible = "rockchip,rk-fb";
1453                 rockchip,disp-mode = <NO_DUAL>;
1454                 status = "disabled";
1455         };
1456
1457         rk_screen: screen {
1458                 compatible = "rockchip,screen";
1459                 status = "disabled";
1460         };
1461
1462         lcdc: lcdc@ff930000 {
1463                 compatible = "rockchip,rk3368-lcdc";
1464                 rockchip,grf = <&grf>;
1465                 rockchip,pmugrf = <&pmugrf>;
1466                 rockchip,cru = <&cru>;
1467                 rockchip,prop = <PRMRY>;
1468                 rockchip,pwr18 = <0>;
1469                 rockchip,iommu-enabled = <1>;
1470                 reg = <0x0 0xff930000 0x0 0x10000>;
1471                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1472                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1473                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1474                 /*power-domains = <&power PD_VIO>;*/
1475                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1476                 reset-names = "axi", "ahb", "dclk";
1477                 status = "disabled";
1478         };
1479
1480         mipi: mipi@ff960000 {
1481                 compatible = "rockchip,rk3368-dsi";
1482                 rockchip,prop = <0>;
1483                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1484                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1485                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1486                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1487                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1488                 /*power-domains = <&power PD_VIO>;*/
1489                 status = "disabled";
1490         };
1491
1492         lvds: lvds@ff968000 {
1493                 compatible = "rockchip,rk3368-lvds";
1494                 rockchip,grf = <&grf>;
1495                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1496                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1497                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1498                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1499                 /*power-domains = <&power PD_VIO>;*/
1500                 status = "disabled";
1501         };
1502
1503         edp: edp@ff970000 {
1504                 compatible = "rockchip,rk32-edp";
1505                 reg = <0x0 0xff970000 0x0 0x4000>;
1506                 rockchip,grf = <&grf>;
1507                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1508                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1509                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1510                 /*power-domains = <&power PD_VIO>;*/
1511                 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1512                 reset-names = "edp_24m", "edp_apb";
1513                 status = "disabled";
1514         };
1515
1516         hdmi: hdmi@ff980000 {
1517                 compatible = "rockchip,rk3368-hdmi";
1518                 reg = <0x0 0xff980000 0x0 0x20000>;
1519                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1520                 clocks = <&cru PCLK_HDMI_CTRL>,
1521                          <&cru SCLK_HDMI_HDCP>,
1522                          <&cru SCLK_HDMI_CEC>;
1523                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
1524                 /*power-domains = <&power PD_VIO>;*/
1525                 resets = <&cru SRST_HDMI>;
1526                 reset-names = "hdmi";
1527                 pinctrl-names = "default", "gpio";
1528                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1529                 pinctrl-1 = <&i2c5_gpio>;
1530                 status = "disabled";
1531         };
1532
1533         iep_mmu: iep-mmu {
1534                 dbgname = "iep";
1535                 compatible = "rockchip,iep_mmu";
1536                 reg = <0x0 0xff900800 0x0 0x100>;
1537                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1538                 interrupt-names = "iep_mmu";
1539                 status = "disabled";
1540         };
1541
1542         vip_mmu: vip-mmu {
1543                 dbgname = "vip";
1544                 compatible = "rockchip,vip_mmu";
1545                 reg = <0x0 0xff950800 0x0 0x100>;
1546                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1547                 interrupt-names = "vip_mmu";
1548                 status = "disabled";
1549         };
1550
1551         vopb_mmu: vopb-mmu {
1552                 dbgname = "vop";
1553                 compatible = "rockchip,vopb_mmu";
1554                 reg = <0x0 0xff930300 0x0 0x100>;
1555                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1556                 interrupt-names = "vop_mmu";
1557                 status = "disabled";
1558         };
1559
1560         isp_mmu: isp-mmu {
1561                 dbgname = "isp_mmu";
1562                 compatible = "rockchip,isp_mmu";
1563                 reg = <0x0 0xff914000 0x0 0x100>,
1564                       <0x0 0xff915000 0x0 0x100>;
1565                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1566                 interrupt-names = "isp_mmu";
1567                 status = "disabled";
1568         };
1569
1570         hdcp_mmu: hdcp-mmu {
1571                  dbgname = "hdcp_mmu";
1572                  compatible = "rockchip,hdcp_mmu";
1573                  reg = <0x0 0xff940000 0x0 0x100>;
1574                  interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1575                  interrupt-names = "hdcp_mmu";
1576                 status = "disabled";
1577         };
1578
1579         hevc_mmu: hevc-mmu {
1580                 dbgname = "hevc";
1581                 compatible = "rockchip,hevc_mmu";
1582                 reg = <0x0 0xff9a0440 0x0 0x40>,
1583                       <0x0 0xff9a0480 0x0 0x40>;
1584                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1585                 interrupt-names = "hevc_mmu";
1586                 status = "disabled";
1587         };
1588
1589         vpu_mmu: vpu-mmu {
1590                 dbgname = "vpu";
1591                 compatible = "rockchip,vpu_mmu";
1592                 reg = <0x0 0xff9a0800 0x0 0x100>;
1593                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1594                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1595                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1596                 status = "disabled";
1597         };
1598 };