2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/display/mipi_dsi.h>
50 #include <dt-bindings/power/rk3368-power.h>
51 #include <dt-bindings/soc/rockchip,boot-mode.h>
52 #include <dt-bindings/thermal/thermal.h>
55 compatible = "rockchip,rk3368";
56 interrupt-parent = <&gic>;
80 #address-cells = <0x2>;
116 entry-method = "psci";
118 cpu_sleep: cpu-sleep-0 {
119 compatible = "arm,idle-state";
120 arm,psci-suspend-param = <0x1010000>;
121 entry-latency-us = <0x3fffffff>;
122 exit-latency-us = <0x40000000>;
123 min-residency-us = <0xffffffff>;
129 compatible = "arm,cortex-a53", "arm,armv8";
131 cpu-idle-states = <&cpu_sleep>;
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster1_opp>;
136 #cooling-cells = <2>; /* min followed by max */
141 compatible = "arm,cortex-a53", "arm,armv8";
143 cpu-idle-states = <&cpu_sleep>;
144 enable-method = "psci";
145 clocks = <&cru ARMCLKL>;
146 operating-points-v2 = <&cluster1_opp>;
151 compatible = "arm,cortex-a53", "arm,armv8";
153 cpu-idle-states = <&cpu_sleep>;
154 enable-method = "psci";
155 clocks = <&cru ARMCLKL>;
156 operating-points-v2 = <&cluster1_opp>;
161 compatible = "arm,cortex-a53", "arm,armv8";
163 cpu-idle-states = <&cpu_sleep>;
164 enable-method = "psci";
165 clocks = <&cru ARMCLKL>;
166 operating-points-v2 = <&cluster1_opp>;
171 compatible = "arm,cortex-a53", "arm,armv8";
173 cpu-idle-states = <&cpu_sleep>;
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 operating-points-v2 = <&cluster0_opp>;
178 #cooling-cells = <2>; /* min followed by max */
183 compatible = "arm,cortex-a53", "arm,armv8";
185 cpu-idle-states = <&cpu_sleep>;
186 enable-method = "psci";
187 clocks = <&cru ARMCLKB>;
188 operating-points-v2 = <&cluster0_opp>;
193 compatible = "arm,cortex-a53", "arm,armv8";
195 cpu-idle-states = <&cpu_sleep>;
196 enable-method = "psci";
197 clocks = <&cru ARMCLKB>;
198 operating-points-v2 = <&cluster0_opp>;
203 compatible = "arm,cortex-a53", "arm,armv8";
205 cpu-idle-states = <&cpu_sleep>;
206 enable-method = "psci";
207 clocks = <&cru ARMCLKB>;
208 operating-points-v2 = <&cluster0_opp>;
212 cluster0_opp: opp_table0 {
213 compatible = "operating-points-v2";
217 opp-hz = /bits/ 64 <408000000>;
218 opp-microvolt = <1200000>;
219 clock-latency-ns = <40000>;
223 opp-hz = /bits/ 64 <600000000>;
224 opp-microvolt = <1200000>;
227 opp-hz = /bits/ 64 <816000000>;
228 opp-microvolt = <1200000>;
231 opp-hz = /bits/ 64 <1008000000>;
232 opp-microvolt = <1200000>;
235 opp-hz = /bits/ 64 <1200000000>;
236 opp-microvolt = <1200000>;
240 cluster1_opp: opp_table1 {
241 compatible = "operating-points-v2";
245 opp-hz = /bits/ 64 <408000000>;
246 opp-microvolt = <1200000>;
247 clock-latency-ns = <40000>;
251 opp-hz = /bits/ 64 <600000000>;
252 opp-microvolt = <1200000>;
255 opp-hz = /bits/ 64 <816000000>;
256 opp-microvolt = <1200000>;
259 opp-hz = /bits/ 64 <1008000000>;
260 opp-microvolt = <1200000>;
265 compatible = "arm,armv8-pmuv3";
266 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
274 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
275 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
276 <&cpu_b2>, <&cpu_b3>;
280 compatible = "arm,amba-bus";
281 #address-cells = <2>;
285 dmac_peri: dma-controller@ff250000 {
286 compatible = "arm,pl330", "arm,primecell";
287 reg = <0x0 0xff250000 0x0 0x4000>;
288 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&cru ACLK_DMAC_PERI>;
292 clock-names = "apb_pclk";
293 arm,pl330-broken-no-flushp;
294 peripherals-req-type-burst;
297 dmac_bus: dma-controller@ff600000 {
298 compatible = "arm,pl330", "arm,primecell";
299 reg = <0x0 0xff600000 0x0 0x4000>;
300 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&cru ACLK_DMAC_BUS>;
304 clock-names = "apb_pclk";
305 arm,pl330-broken-no-flushp;
306 peripherals-req-type-burst;
311 compatible = "arm,psci-0.2";
316 compatible = "arm,armv8-timer";
317 interrupts = <GIC_PPI 13
318 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
320 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
322 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
324 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
328 compatible = "fixed-clock";
329 clock-frequency = <24000000>;
330 clock-output-names = "xin24m";
334 sdmmc: rksdmmc@ff0c0000 {
335 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
336 reg = <0x0 0xff0c0000 0x0 0x4000>;
337 clock-freq-min-max = <400000 150000000>;
338 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
339 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
340 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
341 fifo-depth = <0x100>;
342 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
346 sdio0: dwmmc@ff0d0000 {
347 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
348 reg = <0x0 0xff0d0000 0x0 0x4000>;
349 clock-freq-min-max = <400000 150000000>;
350 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
351 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
352 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
353 fifo-depth = <0x100>;
354 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
358 emmc: rksdmmc@ff0f0000 {
359 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
360 reg = <0x0 0xff0f0000 0x0 0x4000>;
361 clock-freq-min-max = <400000 150000000>;
362 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
363 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
364 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
365 fifo-depth = <0x100>;
366 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
370 saradc: saradc@ff100000 {
371 compatible = "rockchip,saradc";
372 reg = <0x0 0xff100000 0x0 0x100>;
373 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
374 #io-channel-cells = <1>;
375 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
376 clock-names = "saradc", "apb_pclk";
377 resets = <&cru SRST_SARADC>;
378 reset-names = "saradc-apb";
383 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
384 reg = <0x0 0xff110000 0x0 0x1000>;
385 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
386 clock-names = "spiclk", "apb_pclk";
387 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
388 pinctrl-names = "default";
389 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
390 #address-cells = <1>;
396 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
397 reg = <0x0 0xff120000 0x0 0x1000>;
398 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
399 clock-names = "spiclk", "apb_pclk";
400 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
403 #address-cells = <1>;
409 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
410 reg = <0x0 0xff130000 0x0 0x1000>;
411 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
412 clock-names = "spiclk", "apb_pclk";
413 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
416 #address-cells = <1>;
422 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
423 reg = <0x0 0xff650000 0x0 0x1000>;
424 clocks = <&cru PCLK_I2C0>;
426 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&i2c0_xfer>;
429 #address-cells = <1>;
435 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
436 reg = <0x0 0xff140000 0x0 0x1000>;
437 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
438 #address-cells = <1>;
441 clocks = <&cru PCLK_I2C2>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&i2c2_xfer>;
448 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
449 reg = <0x0 0xff150000 0x0 0x1000>;
450 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
451 #address-cells = <1>;
454 clocks = <&cru PCLK_I2C3>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&i2c3_xfer>;
461 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
462 reg = <0x0 0xff160000 0x0 0x1000>;
463 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
467 clocks = <&cru PCLK_I2C4>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&i2c4_xfer>;
474 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
475 reg = <0x0 0xff170000 0x0 0x1000>;
476 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
477 #address-cells = <1>;
480 clocks = <&cru PCLK_I2C5>;
481 pinctrl-names = "default";
482 pinctrl-0 = <&i2c5_xfer>;
486 uart0: serial@ff180000 {
487 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
488 reg = <0x0 0xff180000 0x0 0x100>;
489 clock-frequency = <24000000>;
490 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
491 clock-names = "baudclk", "apb_pclk";
492 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
498 uart1: serial@ff190000 {
499 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
500 reg = <0x0 0xff190000 0x0 0x100>;
501 clock-frequency = <24000000>;
502 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
503 clock-names = "baudclk", "apb_pclk";
504 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
510 uart3: serial@ff1b0000 {
511 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
512 reg = <0x0 0xff1b0000 0x0 0x100>;
513 clock-frequency = <24000000>;
514 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
515 clock-names = "baudclk", "apb_pclk";
516 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
522 uart4: serial@ff1c0000 {
523 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
524 reg = <0x0 0xff1c0000 0x0 0x100>;
525 clock-frequency = <24000000>;
526 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
527 clock-names = "baudclk", "apb_pclk";
528 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
535 #include "rk3368-thermal.dtsi"
538 tsadc: tsadc@ff280000 {
539 compatible = "rockchip,rk3368-tsadc";
540 reg = <0x0 0xff280000 0x0 0x100>;
541 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
543 clock-names = "tsadc", "apb_pclk";
544 resets = <&cru SRST_TSADC>;
545 reset-names = "tsadc-apb";
546 pinctrl-names = "init", "default", "sleep";
547 pinctrl-0 = <&otp_gpio>;
548 pinctrl-1 = <&otp_out>;
549 pinctrl-2 = <&otp_gpio>;
550 #thermal-sensor-cells = <1>;
551 rockchip,hw-tshut-temp = <95000>;
555 gmac: ethernet@ff290000 {
556 compatible = "rockchip,rk3368-gmac";
557 reg = <0x0 0xff290000 0x0 0x10000>;
558 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
559 interrupt-names = "macirq";
560 rockchip,grf = <&grf>;
561 clocks = <&cru SCLK_MAC>,
562 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
563 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
564 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
565 clock-names = "stmmaceth",
566 "mac_clk_rx", "mac_clk_tx",
567 "clk_mac_ref", "clk_mac_refout",
568 "aclk_mac", "pclk_mac";
572 nandc0: nandc@ff400000 {
573 compatible = "rockchip,rk-nandc";
574 reg = <0x0 0xff400000 0x0 0x4000>;
575 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
578 clock-names = "clk_nandc", "hclk_nandc";
582 usb_host0_ehci: usb@ff500000 {
583 compatible = "generic-ehci";
584 reg = <0x0 0xff500000 0x0 0x100>;
585 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&cru HCLK_HOST0>;
587 clock-names = "usbhost";
591 usb_otg: usb@ff580000 {
592 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
594 reg = <0x0 0xff580000 0x0 0x40000>;
595 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&cru HCLK_OTG0>;
599 g-np-tx-fifo-size = <16>;
600 g-rx-fifo-size = <275>;
601 g-tx-fifo-size = <256 128 128 64 64 32>;
606 ddrpctl: syscon@ff610000 {
607 compatible = "rockchip,rk3368-ddrpctl", "syscon";
608 reg = <0x0 0xff610000 0x0 0x400>;
612 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
613 reg = <0x0 0xff660000 0x0 0x1000>;
614 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
615 #address-cells = <1>;
618 clocks = <&cru PCLK_I2C1>;
619 pinctrl-names = "default";
620 pinctrl-0 = <&i2c1_xfer>;
625 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
626 reg = <0x0 0xff680000 0x0 0x10>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&pwm0_pin>;
630 clocks = <&cru PCLK_PWM1>;
636 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
637 reg = <0x0 0xff680010 0x0 0x10>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&pwm1_pin>;
641 clocks = <&cru PCLK_PWM1>;
647 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
648 reg = <0x0 0xff680020 0x0 0x10>;
650 clocks = <&cru PCLK_PWM1>;
656 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
657 reg = <0x0 0xff680030 0x0 0x10>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&pwm3_pin>;
661 clocks = <&cru PCLK_PWM1>;
666 uart2: serial@ff690000 {
667 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
668 reg = <0x0 0xff690000 0x0 0x100>;
669 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
670 clock-names = "baudclk", "apb_pclk";
671 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&uart2_xfer>;
679 mbox: mbox@ff6b0000 {
680 compatible = "rockchip,rk3368-mailbox";
681 reg = <0x0 0xff6b0000 0x0 0x1000>;
682 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&cru PCLK_MAILBOX>;
687 clock-names = "pclk_mailbox";
691 pmu: power-management@ff730000 {
692 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
693 reg = <0x0 0xff730000 0x0 0x1000>;
695 power: power-controller {
697 compatible = "rockchip,rk3368-power-controller";
698 #power-domain-cells = <1>;
699 #address-cells = <1>;
703 * Note: Although SCLK_* are the working clocks
704 * of device without including on the NOC, needed for
707 * The clocks on the which NOC:
708 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
709 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
710 * ACLK_RGA is on ACLK_RGA_NIU.
711 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
713 * Which clock are device clocks:
715 * *_IEP IEP:Image Enhancement Processor
716 * *_ISP ISP:Image Signal Processing
717 * *_VIP VIP:Video Input Processor
718 * *_VOP* VOP:Visual Output Processor
726 reg = <RK3368_PD_VIO>;
727 clocks = <&cru ACLK_IEP>,
739 <&cru HCLK_VIO_HDCPMMU>,
740 <&cru PCLK_EDP_CTRL>,
741 <&cru PCLK_HDMI_CTRL>,
747 <&cru PCLK_MIPI_CSI>,
748 <&cru PCLK_MIPI_DSI0>,
749 <&cru SCLK_VOP0_PWM>,
755 <&cru SCLK_HDMI_CEC>,
756 <&cru SCLK_HDMI_HDCP>;
759 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
760 * (video endecoder & decoder) clocks that on the
761 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
764 reg = <RK3368_PD_VIDEO>;
765 clocks = <&cru ACLK_VIDEO>,
767 <&cru SCLK_HEVC_CABAC>,
768 <&cru SCLK_HEVC_CORE>;
771 * Note: ACLK_GPU is the GPU clock,
772 * and on the ACLK_GPU_NIU (NOC).
775 reg = <RK3368_PD_GPU_1>;
776 clocks = <&cru ACLK_GPU_CFG>,
778 <&cru SCLK_GPU_CORE>;
783 pmugrf: syscon@ff738000 {
784 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
785 reg = <0x0 0xff738000 0x0 0x1000>;
788 compatible = "syscon-reboot-mode";
790 mode-normal = <BOOT_NORMAL>;
791 mode-recovery = <BOOT_RECOVERY>;
792 mode-bootloader = <BOOT_FASTBOOT>;
793 mode-loader = <BOOT_BL_DOWNLOAD>;
798 cru: clock-controller@ff760000 {
799 compatible = "rockchip,rk3368-cru";
800 reg = <0x0 0xff760000 0x0 0x1000>;
801 rockchip,grf = <&grf>;
805 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
807 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
808 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
809 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
810 assigned-clock-rates =
811 <576000000>, <400000000>,
813 <300000000>, <300000000>,
814 <150000000>, <150000000>,
815 <75000000>, <75000000>;
818 grf: syscon@ff770000 {
819 compatible = "rockchip,rk3368-grf", "syscon";
820 reg = <0x0 0xff770000 0x0 0x1000>;
823 wdt: watchdog@ff800000 {
824 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
825 reg = <0x0 0xff800000 0x0 0x100>;
826 clocks = <&cru PCLK_WDT>;
827 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
832 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
833 reg = <0x0 0xff810000 0x0 0x20>;
834 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
837 gic: interrupt-controller@ffb71000 {
838 compatible = "arm,gic-400";
839 interrupt-controller;
840 #interrupt-cells = <3>;
841 #address-cells = <0>;
843 reg = <0x0 0xffb71000 0x0 0x1000>,
844 <0x0 0xffb72000 0x0 0x2000>,
845 <0x0 0xffb74000 0x0 0x2000>,
846 <0x0 0xffb76000 0x0 0x2000>;
847 interrupts = <GIC_PPI 9
848 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
851 gpu: rogue-g6110@ffa30000 {
852 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
853 reg = <0x0 0xffa30000 0x0 0x10000>;
855 <&cru SCLK_GPU_CORE>,
869 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
870 interrupt-names = "rogue-g6110-irq";
873 i2s_2ch: i2s-2ch@ff890000 {
874 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
875 reg = <0x0 0xff890000 0x0 0x1000>;
876 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
877 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
878 dma-names = "tx", "rx";
879 clock-names = "i2s_clk", "i2s_hclk";
880 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
884 i2s_8ch: i2s-8ch@ff898000 {
885 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
886 reg = <0x0 0xff898000 0x0 0x1000>;
887 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
888 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
889 dma-names = "tx", "rx";
890 clock-names = "i2s_clk", "i2s_hclk";
891 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
892 pinctrl-names = "default";
893 pinctrl-0 = <&i2s_8ch_bus>;
898 compatible = "rockchip,rk3368-isp", "rockchip,isp";
899 reg = <0x0 0xff910000 0x0 0x10000>;
900 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
901 /*power-domains = <&power PD_VIO>;*/
903 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
904 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
905 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
906 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
908 "aclk_isp", "hclk_isp", "clk_isp",
909 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
910 "clk_cif_pll", "hclk_mipiphy1",
911 "pclk_dphyrx", "clk_vio0_noc";
913 "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
914 "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
915 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
916 "isp_flash_as_trigger_out";
917 pinctrl-0 = <&cif_clkout>;
918 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
919 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
920 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
921 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
922 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
923 pinctrl-6 = <&cif_clkout>;
924 pinctrl-7 = <&cif_clkout &isp_prelight>;
925 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
926 pinctrl-9 = <&isp_flash_trigger>;
927 rockchip,isp,mipiphy = <2>;
928 rockchip,isp,cifphy = <1>;
929 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
930 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
931 rockchip,grf = <&grf>;
932 rockchip,cru = <&cru>;
933 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
934 rockchip,isp,iommu_enable = <1>;
939 compatible = "rockchip,rga2";
941 reg = <0x0 0xff920000 0x0 0x1000>;
942 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
944 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
949 compatible = "rockchip,rk3368-pinctrl";
950 rockchip,grf = <&grf>;
951 rockchip,pmu = <&pmugrf>;
952 #address-cells = <0x2>;
956 gpio0: gpio0@ff750000 {
957 compatible = "rockchip,gpio-bank";
958 reg = <0x0 0xff750000 0x0 0x100>;
959 clocks = <&cru PCLK_GPIO0>;
960 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller;
966 #interrupt-cells = <0x2>;
969 gpio1: gpio1@ff780000 {
970 compatible = "rockchip,gpio-bank";
971 reg = <0x0 0xff780000 0x0 0x100>;
972 clocks = <&cru PCLK_GPIO1>;
973 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
978 interrupt-controller;
979 #interrupt-cells = <0x2>;
982 gpio2: gpio2@ff790000 {
983 compatible = "rockchip,gpio-bank";
984 reg = <0x0 0xff790000 0x0 0x100>;
985 clocks = <&cru PCLK_GPIO2>;
986 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
991 interrupt-controller;
992 #interrupt-cells = <0x2>;
995 gpio3: gpio3@ff7a0000 {
996 compatible = "rockchip,gpio-bank";
997 reg = <0x0 0xff7a0000 0x0 0x100>;
998 clocks = <&cru PCLK_GPIO3>;
999 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1002 #gpio-cells = <0x2>;
1004 interrupt-controller;
1005 #interrupt-cells = <0x2>;
1008 pcfg_pull_up: pcfg-pull-up {
1012 pcfg_pull_down: pcfg-pull-down {
1016 pcfg_pull_none: pcfg-pull-none {
1020 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1022 drive-strength = <12>;
1026 emmc_clk: emmc-clk {
1027 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1030 emmc_cmd: emmc-cmd {
1031 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1034 emmc_pwr: emmc-pwr {
1035 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1038 emmc_bus1: emmc-bus1 {
1039 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1042 emmc_bus4: emmc-bus4 {
1043 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1044 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1045 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1046 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1049 emmc_bus8: emmc-bus8 {
1050 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1051 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1052 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1053 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1054 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1055 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1056 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1057 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1062 rgmii_pins: rgmii-pins {
1063 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1064 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1065 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1066 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1067 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1068 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1069 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1070 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1071 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1072 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1073 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1074 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1075 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1076 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1077 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1080 rmii_pins: rmii-pins {
1081 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1082 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1083 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1084 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1085 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1086 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1087 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1088 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1089 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1090 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1095 hdmii2c_xfer: hdmii2c-xfer {
1096 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1097 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1102 hdmi_cec: hdmi-cec {
1103 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1108 i2c0_xfer: i2c0-xfer {
1109 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1110 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1115 i2c1_xfer: i2c1-xfer {
1116 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1117 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1122 i2c2_xfer: i2c2-xfer {
1123 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1124 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1129 i2c3_xfer: i2c3-xfer {
1130 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1131 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1136 i2c4_xfer: i2c4-xfer {
1137 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1138 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1143 i2c5_xfer: i2c5-xfer {
1144 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1145 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1147 i2c5_gpio: i2c5-gpio {
1148 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
1149 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
1154 i2s_8ch_bus: i2s-8ch-bus {
1155 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1156 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1157 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1158 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1159 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1160 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1161 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1162 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1163 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1168 sdio0_bus1: sdio0-bus1 {
1169 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1172 sdio0_bus4: sdio0-bus4 {
1173 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1174 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1175 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1176 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1179 sdio0_cmd: sdio0-cmd {
1180 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1183 sdio0_clk: sdio0-clk {
1184 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1187 sdio0_cd: sdio0-cd {
1188 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1191 sdio0_wp: sdio0-wp {
1192 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1195 sdio0_pwr: sdio0-pwr {
1196 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1199 sdio0_bkpwr: sdio0-bkpwr {
1200 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1203 sdio0_int: sdio0-int {
1204 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1209 sdmmc_clk: sdmmc-clk {
1210 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1213 sdmmc_cmd: sdmmc-cmd {
1214 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1217 sdmmc_cd: sdmmc-cd {
1218 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1221 sdmmc_bus1: sdmmc-bus1 {
1222 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1225 sdmmc_bus4: sdmmc-bus4 {
1226 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1227 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1228 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1229 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1234 spi0_clk: spi0-clk {
1235 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1237 spi0_cs0: spi0-cs0 {
1238 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1240 spi0_cs1: spi0-cs1 {
1241 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1244 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1247 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1252 spi1_clk: spi1-clk {
1253 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1255 spi1_cs0: spi1-cs0 {
1256 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1258 spi1_cs1: spi1-cs1 {
1259 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1262 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1265 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1270 spi2_clk: spi2-clk {
1271 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1273 spi2_cs0: spi2-cs0 {
1274 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1277 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1280 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1285 otp_gpio: otp-gpio {
1286 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1290 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1295 uart0_xfer: uart0-xfer {
1296 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1297 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1300 uart0_cts: uart0-cts {
1301 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1304 uart0_rts: uart0-rts {
1305 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1310 uart1_xfer: uart1-xfer {
1311 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1312 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1315 uart1_cts: uart1-cts {
1316 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1319 uart1_rts: uart1-rts {
1320 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1325 uart2_xfer: uart2-xfer {
1326 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1327 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1329 /* no rts / cts for uart2 */
1333 uart3_xfer: uart3-xfer {
1334 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1335 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1338 uart3_cts: uart3-cts {
1339 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1342 uart3_rts: uart3-rts {
1343 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1348 uart4_xfer: uart4-xfer {
1349 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1350 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1353 uart4_cts: uart4-cts {
1354 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1357 uart4_rts: uart4-rts {
1358 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1363 pwm0_pin: pwm0-pin {
1364 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1367 vop_pwm_pin: vop-pwm {
1368 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1373 pwm1_pin: pwm1-pin {
1374 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1379 pwm3_pin: pwm3-pin {
1380 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1385 lcdc_lcdc: lcdc-lcdc {
1387 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1388 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1389 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1390 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1391 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1392 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1393 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1394 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1395 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1396 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1397 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1398 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1399 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1400 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1401 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1402 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1403 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1404 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1407 lcdc_gpio: lcdc-gpio {
1409 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1410 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1411 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1412 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1413 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1414 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1415 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1416 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1417 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1418 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1419 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1420 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1421 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1422 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1423 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1424 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1425 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1426 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1431 cif_clkout: cif-clkout {
1432 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1435 isp_dvp_d2d9: isp-dvp-d2d9 {
1437 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1438 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1439 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1440 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1441 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1442 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1443 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1444 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1445 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1446 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1447 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1448 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1451 isp_dvp_d0d1: isp-dvp-d0d1 {
1453 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1454 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1457 isp_dvp_d10d11:isp_d10d11 {
1459 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1460 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1463 isp_dvp_d0d7: isp-dvp-d0d7 {
1465 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1466 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1467 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1468 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1469 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1470 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1471 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1472 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1475 isp_dvp_d4d11: isp-dvp-d4d11 {
1477 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1478 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1479 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1480 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1481 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1482 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1483 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1484 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1487 isp_shutter: isp-shutter {
1489 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1490 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1493 isp_flash_trigger: isp-flash-trigger {
1494 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1497 isp_prelight: isp-prelight {
1498 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1501 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1502 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1508 compatible = "rockchip,rk-fb";
1509 rockchip,disp-mode = <NO_DUAL>;
1510 status = "disabled";
1514 compatible = "rockchip,screen";
1515 status = "disabled";
1518 lcdc: lcdc@ff930000 {
1519 compatible = "rockchip,rk3368-lcdc";
1520 rockchip,grf = <&grf>;
1521 rockchip,pmugrf = <&pmugrf>;
1522 rockchip,cru = <&cru>;
1523 rockchip,prop = <PRMRY>;
1524 rockchip,pwr18 = <0>;
1525 rockchip,iommu-enabled = <1>;
1526 reg = <0x0 0xff930000 0x0 0x10000>;
1527 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1528 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1529 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1530 /*power-domains = <&power PD_VIO>;*/
1531 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1532 reset-names = "axi", "ahb", "dclk";
1533 status = "disabled";
1536 mipi: mipi@ff960000 {
1537 compatible = "rockchip,rk3368-dsi";
1538 rockchip,prop = <0>;
1539 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1540 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1541 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1542 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1543 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1544 /*power-domains = <&power PD_VIO>;*/
1545 status = "disabled";
1548 lvds: lvds@ff968000 {
1549 compatible = "rockchip,rk3368-lvds";
1550 rockchip,grf = <&grf>;
1551 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1552 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1553 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1554 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1555 /*power-domains = <&power PD_VIO>;*/
1556 status = "disabled";
1560 compatible = "rockchip,rk32-edp";
1561 reg = <0x0 0xff970000 0x0 0x4000>;
1562 rockchip,grf = <&grf>;
1563 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1564 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1565 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1566 /*power-domains = <&power PD_VIO>;*/
1567 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1568 reset-names = "edp_24m", "edp_apb";
1569 status = "disabled";
1572 hdmi: hdmi@ff980000 {
1573 compatible = "rockchip,rk3368-hdmi";
1574 reg = <0x0 0xff980000 0x0 0x20000>;
1575 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1576 clocks = <&cru PCLK_HDMI_CTRL>,
1577 <&cru SCLK_HDMI_HDCP>,
1578 <&cru SCLK_HDMI_CEC>;
1579 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
1580 /*power-domains = <&power PD_VIO>;*/
1581 resets = <&cru SRST_HDMI>;
1582 reset-names = "hdmi";
1583 pinctrl-names = "default", "gpio";
1584 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1585 pinctrl-1 = <&i2c5_gpio>;
1586 status = "disabled";
1591 compatible = "rockchip,iep_mmu";
1592 reg = <0x0 0xff900800 0x0 0x100>;
1593 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1594 interrupt-names = "iep_mmu";
1595 status = "disabled";
1600 compatible = "rockchip,vip_mmu";
1601 reg = <0x0 0xff950800 0x0 0x100>;
1602 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1603 interrupt-names = "vip_mmu";
1604 status = "disabled";
1607 vopb_mmu: vopb-mmu {
1609 compatible = "rockchip,vopb_mmu";
1610 reg = <0x0 0xff930300 0x0 0x100>;
1611 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1612 interrupt-names = "vop_mmu";
1613 status = "disabled";
1617 dbgname = "isp_mmu";
1618 compatible = "rockchip,isp_mmu";
1619 reg = <0x0 0xff914000 0x0 0x100>,
1620 <0x0 0xff915000 0x0 0x100>;
1621 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1622 interrupt-names = "isp_mmu";
1623 status = "disabled";
1626 hdcp_mmu: hdcp-mmu {
1627 dbgname = "hdcp_mmu";
1628 compatible = "rockchip,hdcp_mmu";
1629 reg = <0x0 0xff940000 0x0 0x100>;
1630 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1631 interrupt-names = "hdcp_mmu";
1632 status = "disabled";
1635 hevc_mmu: hevc-mmu {
1637 compatible = "rockchip,hevc_mmu";
1638 reg = <0x0 0xff9a0440 0x0 0x40>,
1639 <0x0 0xff9a0480 0x0 0x40>;
1640 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1641 interrupt-names = "hevc_mmu";
1642 status = "disabled";
1647 compatible = "rockchip,vpu_mmu";
1648 reg = <0x0 0xff9a0800 0x0 0x100>;
1649 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1650 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1651 interrupt-names = "vepu_mmu", "vdpu_mmu";
1652 status = "disabled";