arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3368";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 ethernet0 = &gmac;
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74         };
  75
  76         cpus {
  77                 #address-cells = <0x2>;
  78                 #size-cells = <0x0>;
  79
  80                 cpu-map {
  81                         cluster0 {
  82                                 core0 {
  83                                         cpu = <&cpu_l0>;
  84                                 };
  85                                 core1 {
  86                                         cpu = <&cpu_l1>;
  87                                 };
  88                                 core2 {
  89                                         cpu = <&cpu_l2>;
  90                                 };
  91                                 core3 {
  92                                         cpu = <&cpu_l3>;
  93                                 };
  94                         };
  95
  96                         cluster1 {
  97                                 core0 {
  98                                         cpu = <&cpu_b0>;
  99                                 };
 100                                 core1 {
 101                                         cpu = <&cpu_b1>;
 102                                 };
 103                                 core2 {
 104                                         cpu = <&cpu_b2>;
 105                                 };
 106                                 core3 {
 107                                         cpu = <&cpu_b3>;
 108                                 };
 109                         };
 110                 };
 111
 112                 idle-states {
 113                         entry-method = "psci";
 114
 115                         cpu_sleep: cpu-sleep-0 {
 116                                 compatible = "arm,idle-state";
 117                                 arm,psci-suspend-param = <0x1010000>;
 118                                 entry-latency-us = <0x3fffffff>;
 119                                 exit-latency-us = <0x40000000>;
 120                                 min-residency-us = <0xffffffff>;
 121                         };
 122                 };
 123
 124                 cpu_l0: cpu@0 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x0>;
 128                         cpu-idle-states = <&cpu_sleep>;
 129                         enable-method = "psci";
 130                         clocks = <&cru ARMCLKL>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132
 133                         #cooling-cells = <2>; /* min followed by max */
 134                 };
 135
 136                 cpu_l1: cpu@1 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53", "arm,armv8";
 139                         reg = <0x0 0x1>;
 140                         cpu-idle-states = <&cpu_sleep>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu_l2: cpu@2 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x2>;
 150                         cpu-idle-states = <&cpu_sleep>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKL>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                 };
 155
 156                 cpu_l3: cpu@3 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a53", "arm,armv8";
 159                         reg = <0x0 0x3>;
 160                         cpu-idle-states = <&cpu_sleep>;
 161                         enable-method = "psci";
 162                         clocks = <&cru ARMCLKL>;
 163                         operating-points-v2 = <&cluster0_opp>;
 164                 };
 165
 166                 cpu_b0: cpu@100 {
 167                         device_type = "cpu";
 168                         compatible = "arm,cortex-a53", "arm,armv8";
 169                         reg = <0x0 0x100>;
 170                         cpu-idle-states = <&cpu_sleep>;
 171                         enable-method = "psci";
 172                         clocks = <&cru ARMCLKB>;
 173                         operating-points-v2 = <&cluster1_opp>;
 174
 175                         #cooling-cells = <2>; /* min followed by max */
 176                 };
 177
 178                 cpu_b1: cpu@101 {
 179                         device_type = "cpu";
 180                         compatible = "arm,cortex-a53", "arm,armv8";
 181                         reg = <0x0 0x101>;
 182                         cpu-idle-states = <&cpu_sleep>;
 183                         enable-method = "psci";
 184                         clocks = <&cru ARMCLKB>;
 185                         operating-points-v2 = <&cluster1_opp>;
 186                 };
 187
 188                 cpu_b2: cpu@102 {
 189                         device_type = "cpu";
 190                         compatible = "arm,cortex-a53", "arm,armv8";
 191                         reg = <0x0 0x102>;
 192                         cpu-idle-states = <&cpu_sleep>;
 193                         enable-method = "psci";
 194                         clocks = <&cru ARMCLKB>;
 195                         operating-points-v2 = <&cluster1_opp>;
 196                 };
 197
 198                 cpu_b3: cpu@103 {
 199                         device_type = "cpu";
 200                         compatible = "arm,cortex-a53", "arm,armv8";
 201                         reg = <0x0 0x103>;
 202                         cpu-idle-states = <&cpu_sleep>;
 203                         enable-method = "psci";
 204                         clocks = <&cru ARMCLKB>;
 205                         operating-points-v2 = <&cluster1_opp>;
 206                 };
 207         };
 208
 209         cluster0_opp: opp_table0 {
 210                 compatible = "operating-points-v2";
 211                 opp-shared;
 212
 213                 opp@216000000 {
 214                         opp-hz = /bits/ 64 <216000000>;
 215                         opp-microvolt = <950000 950000 1350000>;
 216                         clock-latency-ns = <40000>;
 217                         opp-suspend;
 218                 };
 219                 opp@408000000 {
 220                         opp-hz = /bits/ 64 <408000000>;
 221                         opp-microvolt = <950000 950000 1350000>;
 222                         clock-latency-ns = <40000>;
 223                 };
 224                 opp@600000000 {
 225                         opp-hz = /bits/ 64 <600000000>;
 226                         opp-microvolt = <950000 950000 1350000>;
 227                         clock-latency-ns = <40000>;
 228                 };
 229                 opp@816000000 {
 230                         opp-hz = /bits/ 64 <816000000>;
 231                         opp-microvolt = <1025000 1025000 1350000>;
 232                         clock-latency-ns = <40000>;
 233                 };
 234                 opp@1008000000 {
 235                         opp-hz = /bits/ 64 <1008000000>;
 236                         opp-microvolt = <1125000 1125000 1350000>;
 237                         clock-latency-ns = <40000>;
 238                 };
 239                 opp@1200000000 {
 240                         opp-hz = /bits/ 64 <1200000000>;
 241                         opp-microvolt = <1225000 1225000 1350000>;
 242                         clock-latency-ns = <40000>;
 243                 };
 244         };
 245
 246         cluster1_opp: opp_table1 {
 247                 compatible = "operating-points-v2";
 248                 opp-shared;
 249
 250                 opp@216000000 {
 251                         opp-hz = /bits/ 64 <216000000>;
 252                         opp-microvolt = <950000 950000 1350000>;
 253                         clock-latency-ns = <40000>;
 254                         opp-suspend;
 255                 };
 256                 opp@408000000 {
 257                         opp-hz = /bits/ 64 <408000000>;
 258                         opp-microvolt = <950000 950000 1350000>;
 259                         clock-latency-ns = <40000>;
 260                 };
 261                 opp@600000000 {
 262                         opp-hz = /bits/ 64 <600000000>;
 263                         opp-microvolt = <950000 950000 1350000>;
 264                         clock-latency-ns = <40000>;
 265                 };
 266                 opp@816000000 {
 267                         opp-hz = /bits/ 64 <816000000>;
 268                         opp-microvolt = <975000 975000 1350000>;
 269                         clock-latency-ns = <40000>;
 270                 };
 271                 opp@1008000000 {
 272                         opp-hz = /bits/ 64 <1008000000>;
 273                         opp-microvolt = <1050000 1050000 1350000>;
 274                         clock-latency-ns = <40000>;
 275                 };
 276                 opp@1200000000 {
 277                         opp-hz = /bits/ 64 <1200000000>;
 278                         opp-microvolt = <1150000 1150000 1350000>;
 279                         clock-latency-ns = <40000>;
 280                 };
 281                 opp@1296000000 {
 282                         opp-hz = /bits/ 64 <1296000000>;
 283                         opp-microvolt = <1225000 1225000 1350000>;
 284                         clock-latency-ns = <40000>;
 285                 };
 286                 opp@1416000000 {
 287                         opp-hz = /bits/ 64 <1416000000>;
 288                         opp-microvolt = <1300000 1300000 1350000>;
 289                         clock-latency-ns = <40000>;
 290                 };
 291                 opp@1512000000 {
 292                         opp-hz = /bits/ 64 <1512000000>;
 293                         opp-microvolt = <1350000 1350000 1350000>;
 294                         clock-latency-ns = <40000>;
 295                 };
 296         };
 297
 298         cpu_avs: cpu-avs {
 299                 cluster0-avs {
 300                         cluster-id = <0>;
 301                         min-volt = <950000>; /* uV */
 302                         min-freq = <216000>; /* KHz */
 303                         leakage-adjust-volt = <
 304                         /*  mA        mA         uV */
 305                             0         254        0
 306                         >;
 307                         nvmem-cells = <&cpu_leakage>;
 308                         nvmem-cell-names = "cpu_leakage";
 309                 };
 310                 cluster1-avs {
 311                         cluster-id = <1>;
 312                         min-volt = <950000>; /* uV */
 313                         min-freq = <216000>; /* KHz */
 314                         leakage-adjust-volt = <
 315                         /*  mA        mA         uV */
 316                             0         254        0
 317                         >;
 318                         nvmem-cells = <&cpu_leakage>;
 319                         nvmem-cell-names = "cpu_leakage";
 320                 };
 321         };
 322
 323         arm-pmu {
 324                 compatible = "arm,armv8-pmuv3";
 325                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 326                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 327                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 328                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 329                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 330                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 331                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 332                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 333                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 334                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 335                                      <&cpu_b2>, <&cpu_b3>;
 336         };
 337
 338         amba {
 339                 compatible = "arm,amba-bus";
 340                 #address-cells = <2>;
 341                 #size-cells = <2>;
 342                 ranges;
 343
 344                 dmac_peri: dma-controller@ff250000 {
 345                         compatible = "arm,pl330", "arm,primecell";
 346                         reg = <0x0 0xff250000 0x0 0x4000>;
 347                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 348                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 349                         #dma-cells = <1>;
 350                         clocks = <&cru ACLK_DMAC_PERI>;
 351                         clock-names = "apb_pclk";
 352                         arm,pl330-broken-no-flushp;
 353                         peripherals-req-type-burst;
 354                 };
 355
 356                 dmac_bus: dma-controller@ff600000 {
 357                         compatible = "arm,pl330", "arm,primecell";
 358                         reg = <0x0 0xff600000 0x0 0x4000>;
 359                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 360                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 361                         #dma-cells = <1>;
 362                         clocks = <&cru ACLK_DMAC_BUS>;
 363                         clock-names = "apb_pclk";
 364                         arm,pl330-broken-no-flushp;
 365                         peripherals-req-type-burst;
 366                 };
 367         };
 368
 369         psci {
 370                 compatible = "arm,psci-0.2";
 371                 method = "smc";
 372         };
 373
 374         timer {
 375                 compatible = "arm,armv8-timer";
 376                 interrupts = <GIC_PPI 13
 377                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 378                              <GIC_PPI 14
 379                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 380                              <GIC_PPI 11
 381                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 382                              <GIC_PPI 10
 383                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 384         };
 385
 386         xin24m: oscillator {
 387                 compatible = "fixed-clock";
 388                 clock-frequency = <24000000>;
 389                 clock-output-names = "xin24m";
 390                 #clock-cells = <0>;
 391         };
 392
 393         sdmmc: rksdmmc@ff0c0000 {
 394                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 395                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 396                 clock-freq-min-max = <400000 150000000>;
 397                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 398                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 399                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 400                 fifo-depth = <0x100>;
 401                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 402                 status = "disabled";
 403         };
 404
 405         sdio0: dwmmc@ff0d0000 {
 406                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 407                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 408                 clock-freq-min-max = <400000 150000000>;
 409                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 410                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 411                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 412                 fifo-depth = <0x100>;
 413                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 414                 status = "disabled";
 415         };
 416
 417         emmc: rksdmmc@ff0f0000 {
 418                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 419                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 420                 clock-freq-min-max = <400000 150000000>;
 421                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 422                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 423                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 424                 fifo-depth = <0x100>;
 425                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 426                 status = "disabled";
 427         };
 428
 429         saradc: saradc@ff100000 {
 430                 compatible = "rockchip,saradc";
 431                 reg = <0x0 0xff100000 0x0 0x100>;
 432                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 433                 #io-channel-cells = <1>;
 434                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 435                 clock-names = "saradc", "apb_pclk";
 436                 resets = <&cru SRST_SARADC>;
 437                 reset-names = "saradc-apb";
 438                 status = "disabled";
 439         };
 440
 441         spi0: spi@ff110000 {
 442                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 443                 reg = <0x0 0xff110000 0x0 0x1000>;
 444                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 445                 clock-names = "spiclk", "apb_pclk";
 446                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 status = "disabled";
 452         };
 453
 454         spi1: spi@ff120000 {
 455                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 456                 reg = <0x0 0xff120000 0x0 0x1000>;
 457                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 458                 clock-names = "spiclk", "apb_pclk";
 459                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 status = "disabled";
 465         };
 466
 467         spi2: spi@ff130000 {
 468                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 469                 reg = <0x0 0xff130000 0x0 0x1000>;
 470                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 471                 clock-names = "spiclk", "apb_pclk";
 472                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 status = "disabled";
 478         };
 479
 480         i2c0: i2c@ff650000 {
 481                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 482                 reg = <0x0 0xff650000 0x0 0x1000>;
 483                 clocks = <&cru PCLK_I2C0>;
 484                 clock-names = "i2c";
 485                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&i2c0_xfer>;
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 status = "disabled";
 491         };
 492
 493         i2c2: i2c@ff140000 {
 494                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 495                 reg = <0x0 0xff140000 0x0 0x1000>;
 496                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 497                 #address-cells = <1>;
 498                 #size-cells = <0>;
 499                 clock-names = "i2c";
 500                 clocks = <&cru PCLK_I2C2>;
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&i2c2_xfer>;
 503                 status = "disabled";
 504         };
 505
 506         i2c3: i2c@ff150000 {
 507                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 508                 reg = <0x0 0xff150000 0x0 0x1000>;
 509                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 510                 #address-cells = <1>;
 511                 #size-cells = <0>;
 512                 clock-names = "i2c";
 513                 clocks = <&cru PCLK_I2C3>;
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&i2c3_xfer>;
 516                 status = "disabled";
 517         };
 518
 519         i2c4: i2c@ff160000 {
 520                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 521                 reg = <0x0 0xff160000 0x0 0x1000>;
 522                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 523                 #address-cells = <1>;
 524                 #size-cells = <0>;
 525                 clock-names = "i2c";
 526                 clocks = <&cru PCLK_I2C4>;
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&i2c4_xfer>;
 529                 status = "disabled";
 530         };
 531
 532         i2c5: i2c@ff170000 {
 533                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 534                 reg = <0x0 0xff170000 0x0 0x1000>;
 535                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 536                 #address-cells = <1>;
 537                 #size-cells = <0>;
 538                 clock-names = "i2c";
 539                 clocks = <&cru PCLK_I2C5>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&i2c5_xfer>;
 542                 status = "disabled";
 543         };
 544
 545         uart0: serial@ff180000 {
 546                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 547                 reg = <0x0 0xff180000 0x0 0x100>;
 548                 clock-frequency = <24000000>;
 549                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 550                 clock-names = "baudclk", "apb_pclk";
 551                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 552                 reg-shift = <2>;
 553                 reg-io-width = <4>;
 554                 status = "disabled";
 555         };
 556
 557         uart1: serial@ff190000 {
 558                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 559                 reg = <0x0 0xff190000 0x0 0x100>;
 560                 clock-frequency = <24000000>;
 561                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 562                 clock-names = "baudclk", "apb_pclk";
 563                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 564                 reg-shift = <2>;
 565                 reg-io-width = <4>;
 566                 status = "disabled";
 567         };
 568
 569         uart3: serial@ff1b0000 {
 570                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 571                 reg = <0x0 0xff1b0000 0x0 0x100>;
 572                 clock-frequency = <24000000>;
 573                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 574                 clock-names = "baudclk", "apb_pclk";
 575                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 576                 reg-shift = <2>;
 577                 reg-io-width = <4>;
 578                 status = "disabled";
 579         };
 580
 581         uart4: serial@ff1c0000 {
 582                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 583                 reg = <0x0 0xff1c0000 0x0 0x100>;
 584                 clock-frequency = <24000000>;
 585                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 586                 clock-names = "baudclk", "apb_pclk";
 587                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 588                 reg-shift = <2>;
 589                 reg-io-width = <4>;
 590                 status = "disabled";
 591         };
 592
 593         thermal-zones {
 594                 cpu {
 595                         polling-delay-passive = <100>; /* milliseconds */
 596                         polling-delay = <5000>; /* milliseconds */
 597
 598                         thermal-sensors = <&tsadc 0>;
 599
 600                         trips {
 601                                 cpu_alert0: cpu_alert0 {
 602                                         temperature = <75000>; /* millicelsius */
 603                                         hysteresis = <2000>; /* millicelsius */
 604                                         type = "passive";
 605                                 };
 606                                 cpu_alert1: cpu_alert1 {
 607                                         temperature = <80000>; /* millicelsius */
 608                                         hysteresis = <2000>; /* millicelsius */
 609                                         type = "passive";
 610                                 };
 611                                 cpu_crit: cpu_crit {
 612                                         temperature = <95000>; /* millicelsius */
 613                                         hysteresis = <2000>; /* millicelsius */
 614                                         type = "critical";
 615                                 };
 616                         };
 617
 618                         cooling-maps {
 619                                 map0 {
 620                                         trip = <&cpu_alert0>;
 621                                         cooling-device =
 622                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 623                                 };
 624                                 map1 {
 625                                         trip = <&cpu_alert1>;
 626                                         cooling-device =
 627                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 628                                 };
 629                         };
 630                 };
 631
 632                 gpu {
 633                         polling-delay-passive = <100>; /* milliseconds */
 634                         polling-delay = <5000>; /* milliseconds */
 635
 636                         thermal-sensors = <&tsadc 1>;
 637
 638                         trips {
 639                                 gpu_alert0: gpu_alert0 {
 640                                         temperature = <80000>; /* millicelsius */
 641                                         hysteresis = <2000>; /* millicelsius */
 642                                         type = "passive";
 643                                 };
 644                                 gpu_crit: gpu_crit {
 645                                         temperature = <115000>; /* millicelsius */
 646                                         hysteresis = <2000>; /* millicelsius */
 647                                         type = "critical";
 648                                 };
 649                         };
 650
 651                         cooling-maps {
 652                                 map0 {
 653                                         trip = <&gpu_alert0>;
 654                                         cooling-device =
 655                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 656                                 };
 657                         };
 658                 };
 659         };
 660
 661         tsadc: tsadc@ff280000 {
 662                 compatible = "rockchip,rk3368-tsadc";
 663                 reg = <0x0 0xff280000 0x0 0x100>;
 664                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 665                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 666                 clock-names = "tsadc", "apb_pclk";
 667                 resets = <&cru SRST_TSADC>;
 668                 reset-names = "tsadc-apb";
 669                 pinctrl-names = "init", "default", "sleep";
 670                 pinctrl-0 = <&otp_gpio>;
 671                 pinctrl-1 = <&otp_out>;
 672                 pinctrl-2 = <&otp_gpio>;
 673                 #thermal-sensor-cells = <1>;
 674                 rockchip,hw-tshut-temp = <95000>;
 675                 status = "disabled";
 676         };
 677
 678         gmac: ethernet@ff290000 {
 679                 compatible = "rockchip,rk3368-gmac";
 680                 reg = <0x0 0xff290000 0x0 0x10000>;
 681                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 682                 interrupt-names = "macirq";
 683                 rockchip,grf = <&grf>;
 684                 clocks = <&cru SCLK_MAC>,
 685                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 686                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 687                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 688                 clock-names = "stmmaceth",
 689                         "mac_clk_rx", "mac_clk_tx",
 690                         "clk_mac_ref", "clk_mac_refout",
 691                         "aclk_mac", "pclk_mac";
 692                 status = "disabled";
 693         };
 694
 695         nandc0: nandc@ff400000 {
 696                 compatible = "rockchip,rk-nandc";
 697                 reg = <0x0 0xff400000 0x0 0x4000>;
 698                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 699                 nandc_id = <0>;
 700                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 701                 clock-names = "clk_nandc", "hclk_nandc";
 702                 status = "disabled";
 703         };
 704
 705         usb_host0_ehci: usb@ff500000 {
 706                 compatible = "generic-ehci";
 707                 reg = <0x0 0xff500000 0x0 0x20000>;
 708                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 709                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 710                 clock-names = "usbhost", "utmi";
 711                 phys = <&u2phy_host>;
 712                 phy-names = "usb";
 713                 status = "disabled";
 714         };
 715
 716         usb_host0_ohci: usb@ff520000 {
 717                 compatible = "generic-ohci";
 718                 reg = <0x0 0xff520000 0x0 0x20000>;
 719                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 720                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 721                 clock-names = "usbhost", "utmi";
 722                 phys = <&u2phy_host>;
 723                 phy-names = "usb";
 724                 status = "disabled";
 725         };
 726
 727         usb_otg: usb@ff580000 {
 728                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 729                                 "snps,dwc2";
 730                 reg = <0x0 0xff580000 0x0 0x40000>;
 731                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 732                 clocks = <&cru HCLK_OTG0>;
 733                 clock-names = "otg";
 734                 dr_mode = "otg";
 735                 g-np-tx-fifo-size = <16>;
 736                 g-rx-fifo-size = <275>;
 737                 g-tx-fifo-size = <256 128 128 64 64 32>;
 738                 g-use-dma;
 739                 status = "disabled";
 740         };
 741
 742         ddrpctl: syscon@ff610000 {
 743                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 744                 reg = <0x0 0xff610000 0x0 0x400>;
 745         };
 746
 747         i2c1: i2c@ff660000 {
 748                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 749                 reg = <0x0 0xff660000 0x0 0x1000>;
 750                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 751                 #address-cells = <1>;
 752                 #size-cells = <0>;
 753                 clock-names = "i2c";
 754                 clocks = <&cru PCLK_I2C1>;
 755                 pinctrl-names = "default";
 756                 pinctrl-0 = <&i2c1_xfer>;
 757                 status = "disabled";
 758         };
 759
 760         pwm0: pwm@ff680000 {
 761                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 762                 reg = <0x0 0xff680000 0x0 0x10>;
 763                 #pwm-cells = <3>;
 764                 pinctrl-names = "default";
 765                 pinctrl-0 = <&pwm0_pin>;
 766                 clocks = <&cru PCLK_PWM1>;
 767                 clock-names = "pwm";
 768                 status = "disabled";
 769         };
 770
 771         pwm1: pwm@ff680010 {
 772                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 773                 reg = <0x0 0xff680010 0x0 0x10>;
 774                 #pwm-cells = <3>;
 775                 pinctrl-names = "default";
 776                 pinctrl-0 = <&pwm1_pin>;
 777                 clocks = <&cru PCLK_PWM1>;
 778                 clock-names = "pwm";
 779                 status = "disabled";
 780         };
 781
 782         pwm2: pwm@ff680020 {
 783                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 784                 reg = <0x0 0xff680020 0x0 0x10>;
 785                 #pwm-cells = <3>;
 786                 clocks = <&cru PCLK_PWM1>;
 787                 clock-names = "pwm";
 788                 status = "disabled";
 789         };
 790
 791         pwm3: pwm@ff680030 {
 792                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 793                 reg = <0x0 0xff680030 0x0 0x10>;
 794                 #pwm-cells = <3>;
 795                 pinctrl-names = "default";
 796                 pinctrl-0 = <&pwm3_pin>;
 797                 clocks = <&cru PCLK_PWM1>;
 798                 clock-names = "pwm";
 799                 status = "disabled";
 800         };
 801
 802         uart2: serial@ff690000 {
 803                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 804                 reg = <0x0 0xff690000 0x0 0x100>;
 805                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 806                 clock-names = "baudclk", "apb_pclk";
 807                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 808                 pinctrl-names = "default";
 809                 pinctrl-0 = <&uart2_xfer>;
 810                 reg-shift = <2>;
 811                 reg-io-width = <4>;
 812                 status = "disabled";
 813         };
 814
 815         mbox: mbox@ff6b0000 {
 816                 compatible = "rockchip,rk3368-mailbox";
 817                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 818                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 819                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 820                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 821                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 822                 clocks = <&cru PCLK_MAILBOX>;
 823                 clock-names = "pclk_mailbox";
 824                 #mbox-cells = <1>;
 825                 status = "disabled";
 826         };
 827
 828         mailbox: mailbox@ff6b0000 {
 829                 compatible = "rockchip,rk3368-mbox-legacy";
 830                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 831                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 832                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 833                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 834                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 835                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 836                 clocks = <&cru PCLK_MAILBOX>;
 837                 clock-names = "pclk_mailbox";
 838                 #mbox-cells = <1>;
 839                 status = "disabled";
 840         };
 841
 842         mailbox_scpi: mailbox-scpi {
 843                 compatible = "rockchip,rk3368-scpi-legacy";
 844                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 845                 chan-nums = <3>;
 846                 status = "disabled";
 847         };
 848
 849         pmu: power-management@ff730000 {
 850                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 851                 reg = <0x0 0xff730000 0x0 0x1000>;
 852
 853                 power: power-controller {
 854                         status = "disabled";
 855                         compatible = "rockchip,rk3368-power-controller";
 856                         #power-domain-cells = <1>;
 857                         #address-cells = <1>;
 858                         #size-cells = <0>;
 859
 860                         /*
 861                          * Note: Although SCLK_* are the working clocks
 862                          * of device without including on the NOC, needed for
 863                          * synchronous reset.
 864                          *
 865                          * The clocks on the which NOC:
 866                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 867                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 868                          * ACLK_RGA is on ACLK_RGA_NIU.
 869                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 870                          *
 871                          * Which clock are device clocks:
 872                          *      clocks          devices
 873                          *      *_IEP           IEP:Image Enhancement Processor
 874                          *      *_ISP           ISP:Image Signal Processing
 875                          *      *_VIP           VIP:Video Input Processor
 876                          *      *_VOP*          VOP:Visual Output Processor
 877                          *      *_RGA           RGA
 878                          *      *_EDP*          EDP
 879                          *      *_DPHY*         LVDS
 880                          *      *_HDMI          HDMI
 881                          *      *_MIPI_*        MIPI
 882                          */
 883                         pd_vio {
 884                                 reg = <RK3368_PD_VIO>;
 885                                 clocks = <&cru ACLK_IEP>,
 886                                          <&cru ACLK_ISP>,
 887                                          <&cru ACLK_VIP>,
 888                                          <&cru ACLK_RGA>,
 889                                          <&cru ACLK_VOP>,
 890                                          <&cru ACLK_VOP_IEP>,
 891                                          <&cru DCLK_VOP>,
 892                                          <&cru HCLK_IEP>,
 893                                          <&cru HCLK_ISP>,
 894                                          <&cru HCLK_RGA>,
 895                                          <&cru HCLK_VIP>,
 896                                          <&cru HCLK_VOP>,
 897                                          <&cru HCLK_VIO_HDCPMMU>,
 898                                          <&cru PCLK_EDP_CTRL>,
 899                                          <&cru PCLK_HDMI_CTRL>,
 900                                          <&cru PCLK_HDCP>,
 901                                          <&cru PCLK_ISP>,
 902                                          <&cru PCLK_VIP>,
 903                                          <&cru PCLK_DPHYRX>,
 904                                          <&cru PCLK_DPHYTX0>,
 905                                          <&cru PCLK_MIPI_CSI>,
 906                                          <&cru PCLK_MIPI_DSI0>,
 907                                          <&cru SCLK_VOP0_PWM>,
 908                                          <&cru SCLK_EDP_24M>,
 909                                          <&cru SCLK_EDP>,
 910                                          <&cru SCLK_HDCP>,
 911                                          <&cru SCLK_ISP>,
 912                                          <&cru SCLK_RGA>,
 913                                          <&cru SCLK_HDMI_CEC>,
 914                                          <&cru SCLK_HDMI_HDCP>;
 915                         };
 916                         /*
 917                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 918                          * (video endecoder & decoder) clocks that on the
 919                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 920                          */
 921                         pd_video {
 922                                 reg = <RK3368_PD_VIDEO>;
 923                                 clocks = <&cru ACLK_VIDEO>,
 924                                          <&cru HCLK_VIDEO>,
 925                                          <&cru SCLK_HEVC_CABAC>,
 926                                          <&cru SCLK_HEVC_CORE>;
 927                         };
 928                         /*
 929                          * Note: ACLK_GPU is the GPU clock,
 930                          * and on the ACLK_GPU_NIU (NOC).
 931                          */
 932                         pd_gpu_1 {
 933                                 reg = <RK3368_PD_GPU_1>;
 934                                 clocks = <&cru ACLK_GPU_CFG>,
 935                                          <&cru ACLK_GPU_MEM>,
 936                                          <&cru SCLK_GPU_CORE>;
 937                         };
 938                 };
 939         };
 940
 941         pmugrf: syscon@ff738000 {
 942                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 943                 reg = <0x0 0xff738000 0x0 0x1000>;
 944
 945                 pmu_io_domains: io-domains {
 946                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
 947                         status = "disabled";
 948                 };
 949
 950                 reboot-mode {
 951                         compatible = "syscon-reboot-mode";
 952                         offset = <0x200>;
 953                         mode-normal = <BOOT_NORMAL>;
 954                         mode-recovery = <BOOT_RECOVERY>;
 955                         mode-bootloader = <BOOT_FASTBOOT>;
 956                         mode-loader = <BOOT_BL_DOWNLOAD>;
 957                 };
 958         };
 959
 960         cru: clock-controller@ff760000 {
 961                 compatible = "rockchip,rk3368-cru";
 962                 reg = <0x0 0xff760000 0x0 0x1000>;
 963                 rockchip,grf = <&grf>;
 964                 #clock-cells = <1>;
 965                 #reset-cells = <1>;
 966                 assigned-clocks =
 967                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 968                         <&cru PLL_NPLL>,
 969                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
 970                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
 971                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
 972                 assigned-clock-rates =
 973                         <576000000>, <400000000>,
 974                         <1188000000>,
 975                         <300000000>, <300000000>,
 976                         <150000000>, <150000000>,
 977                         <75000000>, <75000000>;
 978         };
 979
 980         grf: syscon@ff770000 {
 981                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
 982                 reg = <0x0 0xff770000 0x0 0x1000>;
 983                 #address-cells = <1>;
 984                 #size-cells = <1>;
 985
 986                 io_domains: io-domains {
 987                         compatible = "rockchip,rk3368-io-voltage-domain";
 988                         status = "disabled";
 989                 };
 990
 991                 u2phy: usb2-phy@700 {
 992                         compatible = "rockchip,rk3368-usb2phy";
 993                         reg = <0x700 0x2c>;
 994                         clocks = <&cru SCLK_OTGPHY0>;
 995                         clock-names = "phyclk";
 996                         #clock-cells = <0>;
 997                         clock-output-names = "usbotg_out";
 998                         assigned-clocks = <&cru SCLK_USBPHY480M>;
 999                         assigned-clock-parents = <&u2phy>;
1000                         status = "disabled";
1001
1002                         u2phy_host: host-port {
1003                                 #phy-cells = <0>;
1004                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1005                                 interrupt-names = "linestate";
1006                                 status = "disabled";
1007                         };
1008                 };
1009         };
1010
1011         wdt: watchdog@ff800000 {
1012                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1013                 reg = <0x0 0xff800000 0x0 0x100>;
1014                 clocks = <&cru PCLK_WDT>;
1015                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1016                 status = "disabled";
1017         };
1018
1019         timer@ff810000 {
1020                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1021                 reg = <0x0 0xff810000 0x0 0x20>;
1022                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1023         };
1024
1025         i2s_2ch: i2s-2ch@ff890000 {
1026                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1027                 reg = <0x0 0xff890000 0x0 0x1000>;
1028                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1029                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1030                 dma-names = "tx", "rx";
1031                 clock-names = "i2s_clk", "i2s_hclk";
1032                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1033                 status = "disabled";
1034         };
1035
1036         i2s_8ch: i2s-8ch@ff898000 {
1037                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1038                 reg = <0x0 0xff898000 0x0 0x1000>;
1039                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1040                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1041                 dma-names = "tx", "rx";
1042                 clock-names = "i2s_clk", "i2s_hclk";
1043                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1044                 pinctrl-names = "default";
1045                 pinctrl-0 = <&i2s_8ch_bus>;
1046                 status = "disabled";
1047         };
1048
1049         isp_mmu: iommu@ff914000 {
1050                 compatible = "rockchip,iommu";
1051                 reg = <0x0 0xff914000 0x0 0x100>,
1052                       <0x0 0xff915000 0x0 0x100>;
1053                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1054                 interrupt-names = "isp_mmu";
1055                 #iommu-cells = <0>;
1056                 status = "disabled";
1057         };
1058
1059         vop: vop@ff930000 {
1060                 compatible = "rockchip,rk3368-vop";
1061                 reg = <0x0 0xff930000 0x0 0x2fc>;
1062                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1063                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1064                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1065                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1066                 reset-names = "axi", "ahb", "dclk";
1067                 power-domains = <&power RK3368_PD_VIO>;
1068                 iommus = <&vop_mmu>;
1069                 status = "disabled";
1070
1071                 vop_out: port {
1072                         #address-cells = <1>;
1073                         #size-cells = <0>;
1074                 };
1075         };
1076
1077         display_subsystem: display-subsystem {
1078                 compatible = "rockchip,display-subsystem";
1079                 ports = <&vop_out>;
1080                 status = "disabled";
1081         };
1082
1083         vop_mmu: iommu@ff930300 {
1084                 compatible = "rockchip,iommu";
1085                 reg = <0x0 0xff930300 0x0 0x100>;
1086                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1087                 interrupt-names = "vop_mmu";
1088                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1089                 clock-names = "aclk", "hclk";
1090                 power-domains = <&power RK3368_PD_VIO>;
1091                 #iommu-cells = <0>;
1092                 status = "disabled";
1093         };
1094
1095         hevc_mmu: iommu@ff9a0440 {
1096                 compatible = "rockchip,iommu";
1097                 reg = <0x0 0xff9a0440 0x0 0x100>,
1098                       <0x0 0xff9a0480 0x0 0x100>;
1099                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1100                 interrupt-names = "hevc_mmu";
1101                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1102                 clock-names = "aclk", "hclk";
1103                 power-domains = <&power RK3368_PD_VIDEO>;
1104                 #iommu-cells = <0>;
1105                 status = "disabled";
1106         };
1107
1108         vpu_mmu: iommu@ff9a0800 {
1109                 compatible = "rockchip,iommu";
1110                 reg = <0x0 0xff9a0800 0x0 0x100>;
1111                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1112                 interrupt-names = "vpu_mmu";
1113                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1114                 clock-names = "aclk", "hclk";
1115                 power-domains = <&power RK3368_PD_VIDEO>;
1116                 #iommu-cells = <0>;
1117                 status = "disabled";
1118         };
1119
1120         gic: interrupt-controller@ffb71000 {
1121                 compatible = "arm,gic-400";
1122                 interrupt-controller;
1123                 #interrupt-cells = <3>;
1124                 #address-cells = <0>;
1125
1126                 reg = <0x0 0xffb71000 0x0 0x1000>,
1127                       <0x0 0xffb72000 0x0 0x2000>,
1128                       <0x0 0xffb74000 0x0 0x2000>,
1129                       <0x0 0xffb76000 0x0 0x2000>;
1130                 interrupts = <GIC_PPI 9
1131                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1132         };
1133
1134         gpu: rogue-g6110@ffa30000 {
1135                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1136                 reg = <0x0 0xffa30000 0x0 0x10000>;
1137                 clocks =
1138                         <&cru SCLK_GPU_CORE>,
1139                         <&cru ACLK_GPU_MEM>,
1140                         <&cru ACLK_GPU_CFG>;
1141                 clock-names =
1142                         "sclk_gpu_core",
1143                         "aclk_gpu_mem",
1144                         "aclk_gpu_cfg";
1145                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1146                 interrupt-names = "rogue-g6110-irq";
1147                 operating-points-v2 = <&gpu_opp_table>;
1148         };
1149
1150         gpu_opp_table: gpu_opp_table {
1151                 compatible = "operating-points-v2";
1152                 opp-shared;
1153
1154                 opp@200000000 {
1155                         opp-hz = /bits/ 64 <200000000>;
1156                         opp-microvolt = <1100000>;
1157                 };
1158                 opp@288000000 {
1159                         opp-hz = /bits/ 64 <288000000>;
1160                         opp-microvolt = <1100000>;
1161                 };
1162                 opp@400000000 {
1163                         opp-hz = /bits/ 64 <400000000>;
1164                         opp-microvolt = <1100000>;
1165                 };
1166                 opp@576000000 {
1167                         opp-hz = /bits/ 64 <576000000>;
1168                         opp-microvolt = <1200000>;
1169                 };
1170         };
1171
1172         efuse: efuse@ffb00000 {
1173                 compatible = "rockchip,rk3368-efuse";
1174                 reg = <0x0 0xffb00000 0x0 0x20>;
1175                 #address-cells = <1>;
1176                 #size-cells = <1>;
1177                 clocks = <&cru PCLK_EFUSE256>;
1178                 clock-names = "pclk_efuse";
1179
1180                 /* Data cells */
1181                 cpu_leakage: cpu-leakage@17 {
1182                         reg = <0x17 0x1>;
1183                 };
1184                 temp_adjust: temp-adjust@1f {
1185                         reg = <0x1f 0x1>;
1186                 };
1187         };
1188
1189         pinctrl: pinctrl {
1190                 compatible = "rockchip,rk3368-pinctrl";
1191                 rockchip,grf = <&grf>;
1192                 rockchip,pmu = <&pmugrf>;
1193                 #address-cells = <0x2>;
1194                 #size-cells = <0x2>;
1195                 ranges;
1196
1197                 gpio0: gpio0@ff750000 {
1198                         compatible = "rockchip,gpio-bank";
1199                         reg = <0x0 0xff750000 0x0 0x100>;
1200                         clocks = <&cru PCLK_GPIO0>;
1201                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1202
1203                         gpio-controller;
1204                         #gpio-cells = <0x2>;
1205
1206                         interrupt-controller;
1207                         #interrupt-cells = <0x2>;
1208                 };
1209
1210                 gpio1: gpio1@ff780000 {
1211                         compatible = "rockchip,gpio-bank";
1212                         reg = <0x0 0xff780000 0x0 0x100>;
1213                         clocks = <&cru PCLK_GPIO1>;
1214                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1215
1216                         gpio-controller;
1217                         #gpio-cells = <0x2>;
1218
1219                         interrupt-controller;
1220                         #interrupt-cells = <0x2>;
1221                 };
1222
1223                 gpio2: gpio2@ff790000 {
1224                         compatible = "rockchip,gpio-bank";
1225                         reg = <0x0 0xff790000 0x0 0x100>;
1226                         clocks = <&cru PCLK_GPIO2>;
1227                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1228
1229                         gpio-controller;
1230                         #gpio-cells = <0x2>;
1231
1232                         interrupt-controller;
1233                         #interrupt-cells = <0x2>;
1234                 };
1235
1236                 gpio3: gpio3@ff7a0000 {
1237                         compatible = "rockchip,gpio-bank";
1238                         reg = <0x0 0xff7a0000 0x0 0x100>;
1239                         clocks = <&cru PCLK_GPIO3>;
1240                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1241
1242                         gpio-controller;
1243                         #gpio-cells = <0x2>;
1244
1245                         interrupt-controller;
1246                         #interrupt-cells = <0x2>;
1247                 };
1248
1249                 pcfg_pull_up: pcfg-pull-up {
1250                         bias-pull-up;
1251                 };
1252
1253                 pcfg_pull_down: pcfg-pull-down {
1254                         bias-pull-down;
1255                 };
1256
1257                 pcfg_pull_none: pcfg-pull-none {
1258                         bias-disable;
1259                 };
1260
1261                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1262                         bias-disable;
1263                         drive-strength = <12>;
1264                 };
1265
1266                 emmc {
1267                         emmc_clk: emmc-clk {
1268                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1269                         };
1270
1271                         emmc_cmd: emmc-cmd {
1272                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1273                         };
1274
1275                         emmc_pwr: emmc-pwr {
1276                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1277                         };
1278
1279                         emmc_bus1: emmc-bus1 {
1280                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1281                         };
1282
1283                         emmc_bus4: emmc-bus4 {
1284                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1285                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1286                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1287                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1288                         };
1289
1290                         emmc_bus8: emmc-bus8 {
1291                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1292                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1293                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1294                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1295                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1296                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1297                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1298                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1299                         };
1300                 };
1301
1302                 gmac {
1303                         rgmii_pins: rgmii-pins {
1304                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1305                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1306                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1307                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1308                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1309                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1310                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1311                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1312                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1313                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1314                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1315                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1316                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1317                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1318                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1319                         };
1320
1321                         rmii_pins: rmii-pins {
1322                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1323                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1324                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1325                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1326                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1327                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1328                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1329                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1330                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1331                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1332                         };
1333                 };
1334
1335                 i2c0 {
1336                         i2c0_xfer: i2c0-xfer {
1337                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1338                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1339                         };
1340                 };
1341
1342                 i2c1 {
1343                         i2c1_xfer: i2c1-xfer {
1344                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1345                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1346                         };
1347                 };
1348
1349                 i2c2 {
1350                         i2c2_xfer: i2c2-xfer {
1351                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1352                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1353                         };
1354                 };
1355
1356                 i2c3 {
1357                         i2c3_xfer: i2c3-xfer {
1358                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1359                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1360                         };
1361                 };
1362
1363                 i2c4 {
1364                         i2c4_xfer: i2c4-xfer {
1365                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1366                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1367                         };
1368                 };
1369
1370                 i2c5 {
1371                         i2c5_xfer: i2c5-xfer {
1372                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1373                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1374                         };
1375                 };
1376
1377                 i2s {
1378                         i2s_8ch_bus: i2s-8ch-bus {
1379                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1380                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1381                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1382                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1383                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1384                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1385                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1386                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1387                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1388                         };
1389                 };
1390
1391                 pwm0 {
1392                         pwm0_pin: pwm0-pin {
1393                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1394                         };
1395
1396                         vop_pwm_pin: vop-pwm {
1397                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1398                         };
1399                 };
1400
1401                 pwm1 {
1402                         pwm1_pin: pwm1-pin {
1403                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1404                         };
1405                 };
1406
1407                 pwm3 {
1408                         pwm3_pin: pwm3-pin {
1409                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1410                         };
1411                 };
1412
1413                 sdio0 {
1414                         sdio0_bus1: sdio0-bus1 {
1415                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1416                         };
1417
1418                         sdio0_bus4: sdio0-bus4 {
1419                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1420                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1421                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1422                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1423                         };
1424
1425                         sdio0_cmd: sdio0-cmd {
1426                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1427                         };
1428
1429                         sdio0_clk: sdio0-clk {
1430                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1431                         };
1432
1433                         sdio0_cd: sdio0-cd {
1434                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1435                         };
1436
1437                         sdio0_wp: sdio0-wp {
1438                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1439                         };
1440
1441                         sdio0_pwr: sdio0-pwr {
1442                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1443                         };
1444
1445                         sdio0_bkpwr: sdio0-bkpwr {
1446                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1447                         };
1448
1449                         sdio0_int: sdio0-int {
1450                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1451                         };
1452                 };
1453
1454                 sdmmc {
1455                         sdmmc_clk: sdmmc-clk {
1456                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1457                         };
1458
1459                         sdmmc_cmd: sdmmc-cmd {
1460                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1461                         };
1462
1463                         sdmmc_cd: sdmmc-cd {
1464                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1465                         };
1466
1467                         sdmmc_bus1: sdmmc-bus1 {
1468                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1469                         };
1470
1471                         sdmmc_bus4: sdmmc-bus4 {
1472                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1473                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1474                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1475                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1476                         };
1477                 };
1478
1479                 spi0 {
1480                         spi0_clk: spi0-clk {
1481                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1482                         };
1483                         spi0_cs0: spi0-cs0 {
1484                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1485                         };
1486                         spi0_cs1: spi0-cs1 {
1487                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1488                         };
1489                         spi0_tx: spi0-tx {
1490                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1491                         };
1492                         spi0_rx: spi0-rx {
1493                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1494                         };
1495                 };
1496
1497                 spi1 {
1498                         spi1_clk: spi1-clk {
1499                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1500                         };
1501                         spi1_cs0: spi1-cs0 {
1502                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1503                         };
1504                         spi1_cs1: spi1-cs1 {
1505                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1506                         };
1507                         spi1_rx: spi1-rx {
1508                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1509                         };
1510                         spi1_tx: spi1-tx {
1511                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1512                         };
1513                 };
1514
1515                 spi2 {
1516                         spi2_clk: spi2-clk {
1517                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1518                         };
1519                         spi2_cs0: spi2-cs0 {
1520                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1521                         };
1522                         spi2_rx: spi2-rx {
1523                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1524                         };
1525                         spi2_tx: spi2-tx {
1526                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1527                         };
1528                 };
1529
1530                 tsadc {
1531                         otp_gpio: otp-gpio {
1532                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1533                         };
1534
1535                         otp_out: otp-out {
1536                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1537                         };
1538                 };
1539
1540                 uart0 {
1541                         uart0_xfer: uart0-xfer {
1542                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1543                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1544                         };
1545
1546                         uart0_cts: uart0-cts {
1547                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1548                         };
1549
1550                         uart0_rts: uart0-rts {
1551                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1552                         };
1553                 };
1554
1555                 uart1 {
1556                         uart1_xfer: uart1-xfer {
1557                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1558                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1559                         };
1560
1561                         uart1_cts: uart1-cts {
1562                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1563                         };
1564
1565                         uart1_rts: uart1-rts {
1566                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1567                         };
1568                 };
1569
1570                 uart2 {
1571                         uart2_xfer: uart2-xfer {
1572                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1573                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1574                         };
1575                         /* no rts / cts for uart2 */
1576                 };
1577
1578                 uart3 {
1579                         uart3_xfer: uart3-xfer {
1580                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1581                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1582                         };
1583
1584                         uart3_cts: uart3-cts {
1585                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1586                         };
1587
1588                         uart3_rts: uart3-rts {
1589                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1590                         };
1591                 };
1592
1593                 uart4 {
1594                         uart4_xfer: uart4-xfer {
1595                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1596                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1597                         };
1598
1599                         uart4_cts: uart4-cts {
1600                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1601                         };
1602
1603                         uart4_rts: uart4-rts {
1604                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1605                         };
1606                 };
1607         };
1608 };