arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51 #include <dt-bindings/display/mipi_dsi.h>
  52 #include <dt-bindings/display/drm_mipi_dsi.h>
  53 #include <dt-bindings/display/media-bus-format.h>
  54
  55 / {
  56         compatible = "rockchip,rk3368";
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 ethernet0 = &gmac;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         cpus {
  80                 #address-cells = <0x2>;
  81                 #size-cells = <0x0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                                 core2 {
 107                                         cpu = <&cpu_b2>;
 108                                 };
 109                                 core3 {
 110                                         cpu = <&cpu_b3>;
 111                                 };
 112                         };
 113                 };
 114
 115                 idle-states {
 116                         entry-method = "psci";
 117
 118                         cpu_sleep: cpu-sleep-0 {
 119                                 compatible = "arm,idle-state";
 120                                 arm,psci-suspend-param = <0x1010000>;
 121                                 entry-latency-us = <0x3fffffff>;
 122                                 exit-latency-us = <0x40000000>;
 123                                 min-residency-us = <0xffffffff>;
 124                         };
 125                 };
 126
 127                 cpu_l0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x0 0x0>;
 131                         cpu-idle-states = <&cpu_sleep>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 136                         #cooling-cells = <2>; /* min followed by max */
 137                         dynamic-power-coefficient = <149>;
 138                 };
 139
 140                 cpu_l1: cpu@1 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a53", "arm,armv8";
 143                         reg = <0x0 0x1>;
 144                         cpu-idle-states = <&cpu_sleep>;
 145                         enable-method = "psci";
 146                         clocks = <&cru ARMCLKL>;
 147                         operating-points-v2 = <&cluster0_opp>;
 148                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 149                 };
 150
 151                 cpu_l2: cpu@2 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a53", "arm,armv8";
 154                         reg = <0x0 0x2>;
 155                         cpu-idle-states = <&cpu_sleep>;
 156                         enable-method = "psci";
 157                         clocks = <&cru ARMCLKL>;
 158                         operating-points-v2 = <&cluster0_opp>;
 159                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 160                 };
 161
 162                 cpu_l3: cpu@3 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-a53", "arm,armv8";
 165                         reg = <0x0 0x3>;
 166                         cpu-idle-states = <&cpu_sleep>;
 167                         enable-method = "psci";
 168                         clocks = <&cru ARMCLKL>;
 169                         operating-points-v2 = <&cluster0_opp>;
 170                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 171                 };
 172
 173                 cpu_b0: cpu@100 {
 174                         device_type = "cpu";
 175                         compatible = "arm,cortex-a53", "arm,armv8";
 176                         reg = <0x0 0x100>;
 177                         cpu-idle-states = <&cpu_sleep>;
 178                         enable-method = "psci";
 179                         clocks = <&cru ARMCLKB>;
 180                         operating-points-v2 = <&cluster1_opp>;
 181                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 182                         #cooling-cells = <2>; /* min followed by max */
 183                         dynamic-power-coefficient = <160>;
 184                 };
 185
 186                 cpu_b1: cpu@101 {
 187                         device_type = "cpu";
 188                         compatible = "arm,cortex-a53", "arm,armv8";
 189                         reg = <0x0 0x101>;
 190                         cpu-idle-states = <&cpu_sleep>;
 191                         enable-method = "psci";
 192                         clocks = <&cru ARMCLKB>;
 193                         operating-points-v2 = <&cluster1_opp>;
 194                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 195                 };
 196
 197                 cpu_b2: cpu@102 {
 198                         device_type = "cpu";
 199                         compatible = "arm,cortex-a53", "arm,armv8";
 200                         reg = <0x0 0x102>;
 201                         cpu-idle-states = <&cpu_sleep>;
 202                         enable-method = "psci";
 203                         clocks = <&cru ARMCLKB>;
 204                         operating-points-v2 = <&cluster1_opp>;
 205                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 206                 };
 207
 208                 cpu_b3: cpu@103 {
 209                         device_type = "cpu";
 210                         compatible = "arm,cortex-a53", "arm,armv8";
 211                         reg = <0x0 0x103>;
 212                         cpu-idle-states = <&cpu_sleep>;
 213                         enable-method = "psci";
 214                         clocks = <&cru ARMCLKB>;
 215                         operating-points-v2 = <&cluster1_opp>;
 216                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 217                 };
 218         };
 219
 220         cluster0_opp: opp_table0 {
 221                 compatible = "operating-points-v2";
 222                 opp-shared;
 223
 224                 opp@216000000 {
 225                         opp-hz = /bits/ 64 <216000000>;
 226                         opp-microvolt = <950000 950000 1350000>;
 227                         clock-latency-ns = <40000>;
 228                         opp-suspend;
 229                 };
 230                 opp@408000000 {
 231                         opp-hz = /bits/ 64 <408000000>;
 232                         opp-microvolt = <950000 950000 1350000>;
 233                         clock-latency-ns = <40000>;
 234                 };
 235                 opp@600000000 {
 236                         opp-hz = /bits/ 64 <600000000>;
 237                         opp-microvolt = <950000 950000 1350000>;
 238                         clock-latency-ns = <40000>;
 239                 };
 240                 opp@816000000 {
 241                         opp-hz = /bits/ 64 <816000000>;
 242                         opp-microvolt = <1025000 1025000 1350000>;
 243                         clock-latency-ns = <40000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <1125000 1125000 1350000>;
 248                         clock-latency-ns = <40000>;
 249                 };
 250                 opp@1200000000 {
 251                         opp-hz = /bits/ 64 <1200000000>;
 252                         opp-microvolt = <1225000 1225000 1350000>;
 253                         clock-latency-ns = <40000>;
 254                 };
 255         };
 256
 257         cluster1_opp: opp_table1 {
 258                 compatible = "operating-points-v2";
 259                 opp-shared;
 260
 261                 opp@216000000 {
 262                         opp-hz = /bits/ 64 <216000000>;
 263                         opp-microvolt = <950000 950000 1350000>;
 264                         clock-latency-ns = <40000>;
 265                         opp-suspend;
 266                 };
 267                 opp@408000000 {
 268                         opp-hz = /bits/ 64 <408000000>;
 269                         opp-microvolt = <950000 950000 1350000>;
 270                         clock-latency-ns = <40000>;
 271                 };
 272                 opp@600000000 {
 273                         opp-hz = /bits/ 64 <600000000>;
 274                         opp-microvolt = <950000 950000 1350000>;
 275                         clock-latency-ns = <40000>;
 276                 };
 277                 opp@816000000 {
 278                         opp-hz = /bits/ 64 <816000000>;
 279                         opp-microvolt = <975000 975000 1350000>;
 280                         clock-latency-ns = <40000>;
 281                 };
 282                 opp@1008000000 {
 283                         opp-hz = /bits/ 64 <1008000000>;
 284                         opp-microvolt = <1050000 1050000 1350000>;
 285                         clock-latency-ns = <40000>;
 286                 };
 287                 opp@1200000000 {
 288                         opp-hz = /bits/ 64 <1200000000>;
 289                         opp-microvolt = <1150000 1150000 1350000>;
 290                         clock-latency-ns = <40000>;
 291                 };
 292                 opp@1296000000 {
 293                         opp-hz = /bits/ 64 <1296000000>;
 294                         opp-microvolt = <1225000 1225000 1350000>;
 295                         clock-latency-ns = <40000>;
 296                 };
 297                 opp@1416000000 {
 298                         opp-hz = /bits/ 64 <1416000000>;
 299                         opp-microvolt = <1300000 1300000 1350000>;
 300                         clock-latency-ns = <40000>;
 301                 };
 302                 opp@1512000000 {
 303                         opp-hz = /bits/ 64 <1512000000>;
 304                         opp-microvolt = <1350000 1350000 1350000>;
 305                         clock-latency-ns = <40000>;
 306                 };
 307         };
 308
 309         energy-costs {
 310                 RK3368_CPU_COST_0: rk3368-core-cost0 {
 311                         busy-cost-data = <
 312                                 146    44       /*  216M */
 313                                 276    72       /*  408M */
 314                                 406    99       /*  600M */
 315                                 552    147      /*  816M */
 316                                 682    200      /* 1008M */
 317                                 812    255      /* 1200M */
 318                         >;
 319                         idle-cost-data = <
 320                                   6
 321                                   6
 322                                   0
 323                         >;
 324                 };
 325
 326                 RK3368_CPU_COST_1: rk3368-core-cost1 {
 327                         busy-cost-data = <
 328                                 146    53       /*  216M */
 329                                 276    86       /*  408M */
 330                                 406    118      /*  600M */
 331                                 552    166      /*  816M */
 332                                 682    226      /* 1008M */
 333                                 812    309      /* 1200M */
 334                                 878    371      /* 1200M */
 335                                 959    446      /* 1416M */
 336                                 1024   513      /* 1512M */
 337                         >;
 338                         idle-cost-data = <
 339                                    6
 340                                    6
 341                                    0
 342                         >;
 343                 };
 344
 345                 RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
 346                         busy-cost-data = <
 347                                 146    9        /*  216M */
 348                                 276    14       /*  408M */
 349                                 406    20       /*  600M */
 350                                 552    29       /*  816M */
 351                                 682    40       /* 1008M */
 352                                 812    51       /* 1200M */
 353                         >;
 354                         idle-cost-data = <
 355                                 56
 356                                 56
 357                                 56
 358                         >;
 359                 };
 360
 361                 RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
 362                         busy-cost-data = <
 363                                 146    11       /*  216M */
 364                                 276    17       /*  408M */
 365                                 406    24       /*  600M */
 366                                 552    33       /*  816M */
 367                                 682    45       /* 1008M */
 368                                 812    62       /* 1200M */
 369                                 878    74       /* 1200M */
 370                                 959    89       /* 1416M */
 371                                 1024   103      /* 1512M */
 372                         >;
 373                         idle-cost-data = <
 374                                 56
 375                                 56
 376                                 56
 377                         >;
 378                 };
 379         };
 380
 381         cpu_avs: cpu-avs {
 382                 cluster0-avs {
 383                         cluster-id = <0>;
 384                         min-volt = <950000>; /* uV */
 385                         min-freq = <216000>; /* KHz */
 386                         leakage-adjust-volt = <
 387                         /*  mA        mA         uV */
 388                             0         254        0
 389                         >;
 390                         nvmem-cells = <&cpu_leakage>;
 391                         nvmem-cell-names = "cpu_leakage";
 392                 };
 393                 cluster1-avs {
 394                         cluster-id = <1>;
 395                         min-volt = <950000>; /* uV */
 396                         min-freq = <216000>; /* KHz */
 397                         leakage-adjust-volt = <
 398                         /*  mA        mA         uV */
 399                             0         254        0
 400                         >;
 401                         nvmem-cells = <&cpu_leakage>;
 402                         nvmem-cell-names = "cpu_leakage";
 403                 };
 404         };
 405
 406         arm-pmu {
 407                 compatible = "arm,armv8-pmuv3";
 408                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 409                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 410                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 411                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 412                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 413                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 414                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 415                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 416                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 417                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 418                                      <&cpu_b2>, <&cpu_b3>;
 419         };
 420
 421         amba {
 422                 compatible = "arm,amba-bus";
 423                 #address-cells = <2>;
 424                 #size-cells = <2>;
 425                 ranges;
 426
 427                 dmac_peri: dma-controller@ff250000 {
 428                         compatible = "arm,pl330", "arm,primecell";
 429                         reg = <0x0 0xff250000 0x0 0x4000>;
 430                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 431                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 432                         #dma-cells = <1>;
 433                         clocks = <&cru ACLK_DMAC_PERI>;
 434                         clock-names = "apb_pclk";
 435                         arm,pl330-broken-no-flushp;
 436                         peripherals-req-type-burst;
 437                 };
 438
 439                 dmac_bus: dma-controller@ff600000 {
 440                         compatible = "arm,pl330", "arm,primecell";
 441                         reg = <0x0 0xff600000 0x0 0x4000>;
 442                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 443                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 444                         #dma-cells = <1>;
 445                         clocks = <&cru ACLK_DMAC_BUS>;
 446                         clock-names = "apb_pclk";
 447                         arm,pl330-broken-no-flushp;
 448                         peripherals-req-type-burst;
 449                 };
 450         };
 451
 452         psci {
 453                 compatible = "arm,psci-0.2";
 454                 method = "smc";
 455         };
 456
 457         timer {
 458                 compatible = "arm,armv8-timer";
 459                 interrupts = <GIC_PPI 13
 460                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 461                              <GIC_PPI 14
 462                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 463                              <GIC_PPI 11
 464                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 465                              <GIC_PPI 10
 466                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 467         };
 468
 469         xin24m: oscillator {
 470                 compatible = "fixed-clock";
 471                 clock-frequency = <24000000>;
 472                 clock-output-names = "xin24m";
 473                 #clock-cells = <0>;
 474         };
 475
 476         xin32k: xin32k {
 477                 compatible = "fixed-clock";
 478                 clock-frequency = <32768>;
 479                 clock-output-names = "xin32k";
 480                 #clock-cells = <0>;
 481         };
 482
 483         sdmmc: dwmmc@ff0c0000 {
 484                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 485                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 486                 clock-freq-min-max = <400000 150000000>;
 487                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 488                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 489                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 490                 fifo-depth = <0x100>;
 491                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 492                 status = "disabled";
 493         };
 494
 495         sdio0: dwmmc@ff0d0000 {
 496                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 497                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 498                 clock-freq-min-max = <400000 150000000>;
 499                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 500                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 501                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 502                 fifo-depth = <0x100>;
 503                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 504                 status = "disabled";
 505         };
 506
 507         emmc: dwmmc@ff0f0000 {
 508                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 509                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 510                 clock-freq-min-max = <400000 150000000>;
 511                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 512                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 513                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 514                 fifo-depth = <0x100>;
 515                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 516                 status = "disabled";
 517         };
 518
 519         saradc: saradc@ff100000 {
 520                 compatible = "rockchip,saradc";
 521                 reg = <0x0 0xff100000 0x0 0x100>;
 522                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 523                 #io-channel-cells = <1>;
 524                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 525                 clock-names = "saradc", "apb_pclk";
 526                 resets = <&cru SRST_SARADC>;
 527                 reset-names = "saradc-apb";
 528                 status = "disabled";
 529         };
 530
 531         spi0: spi@ff110000 {
 532                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 533                 reg = <0x0 0xff110000 0x0 0x1000>;
 534                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 535                 clock-names = "spiclk", "apb_pclk";
 536                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 status = "disabled";
 542         };
 543
 544         spi1: spi@ff120000 {
 545                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 546                 reg = <0x0 0xff120000 0x0 0x1000>;
 547                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 548                 clock-names = "spiclk", "apb_pclk";
 549                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 552                 #address-cells = <1>;
 553                 #size-cells = <0>;
 554                 status = "disabled";
 555         };
 556
 557         spi2: spi@ff130000 {
 558                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 559                 reg = <0x0 0xff130000 0x0 0x1000>;
 560                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 561                 clock-names = "spiclk", "apb_pclk";
 562                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 status = "disabled";
 568         };
 569
 570         i2c0: i2c@ff650000 {
 571                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 572                 reg = <0x0 0xff650000 0x0 0x1000>;
 573                 clocks = <&cru PCLK_I2C0>;
 574                 clock-names = "i2c";
 575                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&i2c0_xfer>;
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 status = "disabled";
 581         };
 582
 583         i2c2: i2c@ff140000 {
 584                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 585                 reg = <0x0 0xff140000 0x0 0x1000>;
 586                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 clock-names = "i2c";
 590                 clocks = <&cru PCLK_I2C2>;
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&i2c2_xfer>;
 593                 status = "disabled";
 594         };
 595
 596         i2c3: i2c@ff150000 {
 597                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 598                 reg = <0x0 0xff150000 0x0 0x1000>;
 599                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 clock-names = "i2c";
 603                 clocks = <&cru PCLK_I2C3>;
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&i2c3_xfer>;
 606                 status = "disabled";
 607         };
 608
 609         i2c4: i2c@ff160000 {
 610                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 611                 reg = <0x0 0xff160000 0x0 0x1000>;
 612                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 613                 #address-cells = <1>;
 614                 #size-cells = <0>;
 615                 clock-names = "i2c";
 616                 clocks = <&cru PCLK_I2C4>;
 617                 pinctrl-names = "default";
 618                 pinctrl-0 = <&i2c4_xfer>;
 619                 status = "disabled";
 620         };
 621
 622         i2c5: i2c@ff170000 {
 623                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 624                 reg = <0x0 0xff170000 0x0 0x1000>;
 625                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628                 clock-names = "i2c";
 629                 clocks = <&cru PCLK_I2C5>;
 630                 pinctrl-names = "default";
 631                 pinctrl-0 = <&i2c5_xfer>;
 632                 status = "disabled";
 633         };
 634
 635         uart0: serial@ff180000 {
 636                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 637                 reg = <0x0 0xff180000 0x0 0x100>;
 638                 clock-frequency = <24000000>;
 639                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 640                 clock-names = "baudclk", "apb_pclk";
 641                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 642                 reg-shift = <2>;
 643                 reg-io-width = <4>;
 644                 status = "disabled";
 645         };
 646
 647         uart1: serial@ff190000 {
 648                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 649                 reg = <0x0 0xff190000 0x0 0x100>;
 650                 clock-frequency = <24000000>;
 651                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 652                 clock-names = "baudclk", "apb_pclk";
 653                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 654                 reg-shift = <2>;
 655                 reg-io-width = <4>;
 656                 status = "disabled";
 657         };
 658
 659         uart3: serial@ff1b0000 {
 660                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 661                 reg = <0x0 0xff1b0000 0x0 0x100>;
 662                 clock-frequency = <24000000>;
 663                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 664                 clock-names = "baudclk", "apb_pclk";
 665                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 666                 reg-shift = <2>;
 667                 reg-io-width = <4>;
 668                 status = "disabled";
 669         };
 670
 671         uart4: serial@ff1c0000 {
 672                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 673                 reg = <0x0 0xff1c0000 0x0 0x100>;
 674                 clock-frequency = <24000000>;
 675                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 676                 clock-names = "baudclk", "apb_pclk";
 677                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 678                 reg-shift = <2>;
 679                 reg-io-width = <4>;
 680                 status = "disabled";
 681         };
 682
 683         thermal_zones: thermal-zones {
 684                 soc_thermal: soc-thermal {
 685                         polling-delay-passive = <200>; /* milliseconds */
 686                         polling-delay = <200>; /* milliseconds */
 687                         sustainable-power = <600>; /* milliwatts */
 688
 689                         thermal-sensors = <&tsadc 0>;
 690                         trips {
 691                                 threshold: trip-point@0 {
 692                                         temperature = <70000>; /* millicelsius */
 693                                         hysteresis = <2000>; /* millicelsius */
 694                                         type = "passive";
 695                                 };
 696                                 target: trip-point@1 {
 697                                         temperature = <80000>; /* millicelsius */
 698                                         hysteresis = <2000>; /* millicelsius */
 699                                         type = "passive";
 700                                 };
 701                                 soc_crit: soc-crit {
 702                                         temperature = <95000>; /* millicelsius */
 703                                         hysteresis = <2000>; /* millicelsius */
 704                                         type = "critical";
 705                                 };
 706                         };
 707
 708                         cooling-maps {
 709                                 map0 {
 710                                         trip = <&target>;
 711                                         cooling-device =
 712                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 713                                         contribution = <1024>;
 714                                 };
 715                                 map1 {
 716                                         trip = <&target>;
 717                                         cooling-device =
 718                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 719                                         contribution = <1024>;
 720                                 };
 721                                 map2 {
 722                                         trip = <&target>;
 723                                         cooling-device =
 724                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 725                                         contribution = <1024>;
 726                                 };
 727                         };
 728                 };
 729
 730                 gpu_thermal: gpu-thermal {
 731                         polling-delay-passive = <200>; /* milliseconds */
 732                         polling-delay = <200>; /* milliseconds */
 733                         thermal-sensors = <&tsadc 1>;
 734                 };
 735         };
 736
 737         tsadc: tsadc@ff280000 {
 738                 compatible = "rockchip,rk3368-tsadc-legacy";
 739                 reg = <0x0 0xff280000 0x0 0x100>;
 740                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 741                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 742                 clock-names = "tsadc", "apb_pclk";
 743                 clock-frequency = <32768>;
 744                 resets = <&cru SRST_TSADC>;
 745                 reset-names = "tsadc-apb";
 746                 nvmem-cells = <&temp_adjust>;
 747                 nvmem-cell-names = "temp_adjust";
 748                 #thermal-sensor-cells = <1>;
 749                 hw-shut-temp = <95000>;
 750                 latency-bound = <50000>;
 751                 status = "disabled";
 752         };
 753
 754         gmac: ethernet@ff290000 {
 755                 compatible = "rockchip,rk3368-gmac";
 756                 reg = <0x0 0xff290000 0x0 0x10000>;
 757                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 758                 interrupt-names = "macirq";
 759                 rockchip,grf = <&grf>;
 760                 clocks = <&cru SCLK_MAC>,
 761                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 762                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 763                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 764                 clock-names = "stmmaceth",
 765                         "mac_clk_rx", "mac_clk_tx",
 766                         "clk_mac_ref", "clk_mac_refout",
 767                         "aclk_mac", "pclk_mac";
 768                 status = "disabled";
 769         };
 770
 771         nandc0: nandc@ff400000 {
 772                 compatible = "rockchip,rk-nandc";
 773                 reg = <0x0 0xff400000 0x0 0x4000>;
 774                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 775                 nandc_id = <0>;
 776                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 777                 clock-names = "clk_nandc", "hclk_nandc";
 778                 status = "disabled";
 779         };
 780
 781         usb_host0_ehci: usb@ff500000 {
 782                 compatible = "generic-ehci";
 783                 reg = <0x0 0xff500000 0x0 0x20000>;
 784                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 785                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 786                 clock-names = "usbhost", "utmi";
 787                 phys = <&u2phy_host>;
 788                 phy-names = "usb";
 789                 status = "disabled";
 790         };
 791
 792         usb_host0_ohci: usb@ff520000 {
 793                 compatible = "generic-ohci";
 794                 reg = <0x0 0xff520000 0x0 0x20000>;
 795                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 796                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 797                 clock-names = "usbhost", "utmi";
 798                 phys = <&u2phy_host>;
 799                 phy-names = "usb";
 800                 status = "disabled";
 801         };
 802
 803         usb_otg: usb@ff580000 {
 804                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 805                                 "snps,dwc2";
 806                 reg = <0x0 0xff580000 0x0 0x40000>;
 807                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 808                 clocks = <&cru HCLK_OTG0>;
 809                 clock-names = "otg";
 810                 dr_mode = "otg";
 811                 g-np-tx-fifo-size = <16>;
 812                 g-rx-fifo-size = <275>;
 813                 g-tx-fifo-size = <256 128 128 64 64 32>;
 814                 g-use-dma;
 815                 status = "disabled";
 816         };
 817
 818         ddrpctl: syscon@ff610000 {
 819                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 820                 reg = <0x0 0xff610000 0x0 0x400>;
 821         };
 822
 823         i2c1: i2c@ff660000 {
 824                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 825                 reg = <0x0 0xff660000 0x0 0x1000>;
 826                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 827                 #address-cells = <1>;
 828                 #size-cells = <0>;
 829                 clock-names = "i2c";
 830                 clocks = <&cru PCLK_I2C1>;
 831                 pinctrl-names = "default";
 832                 pinctrl-0 = <&i2c1_xfer>;
 833                 status = "disabled";
 834         };
 835
 836         pwm0: pwm@ff680000 {
 837                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 838                 reg = <0x0 0xff680000 0x0 0x10>;
 839                 #pwm-cells = <3>;
 840                 pinctrl-names = "default";
 841                 pinctrl-0 = <&pwm0_pin>;
 842                 clocks = <&cru PCLK_PWM1>;
 843                 clock-names = "pwm";
 844                 status = "disabled";
 845         };
 846
 847         pwm1: pwm@ff680010 {
 848                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 849                 reg = <0x0 0xff680010 0x0 0x10>;
 850                 #pwm-cells = <3>;
 851                 pinctrl-names = "default";
 852                 pinctrl-0 = <&pwm1_pin>;
 853                 clocks = <&cru PCLK_PWM1>;
 854                 clock-names = "pwm";
 855                 status = "disabled";
 856         };
 857
 858         pwm2: pwm@ff680020 {
 859                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 860                 reg = <0x0 0xff680020 0x0 0x10>;
 861                 #pwm-cells = <3>;
 862                 clocks = <&cru PCLK_PWM1>;
 863                 clock-names = "pwm";
 864                 status = "disabled";
 865         };
 866
 867         pwm3: pwm@ff680030 {
 868                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 869                 reg = <0x0 0xff680030 0x0 0x10>;
 870                 #pwm-cells = <3>;
 871                 pinctrl-names = "default";
 872                 pinctrl-0 = <&pwm3_pin>;
 873                 clocks = <&cru PCLK_PWM1>;
 874                 clock-names = "pwm";
 875                 status = "disabled";
 876         };
 877
 878         uart2: serial@ff690000 {
 879                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 880                 reg = <0x0 0xff690000 0x0 0x100>;
 881                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 882                 clock-names = "baudclk", "apb_pclk";
 883                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 884                 pinctrl-names = "default";
 885                 pinctrl-0 = <&uart2_xfer>;
 886                 reg-shift = <2>;
 887                 reg-io-width = <4>;
 888                 status = "disabled";
 889         };
 890
 891         mbox: mbox@ff6b0000 {
 892                 compatible = "rockchip,rk3368-mailbox";
 893                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 894                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 895                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 896                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 897                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 898                 clocks = <&cru PCLK_MAILBOX>;
 899                 clock-names = "pclk_mailbox";
 900                 #mbox-cells = <1>;
 901                 status = "disabled";
 902         };
 903
 904         mailbox: mailbox@ff6b0000 {
 905                 compatible = "rockchip,rk3368-mbox-legacy";
 906                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 907                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 908                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 909                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 910                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 911                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 912                 clocks = <&cru PCLK_MAILBOX>;
 913                 clock-names = "pclk_mailbox";
 914                 #mbox-cells = <1>;
 915                 status = "disabled";
 916         };
 917
 918         mailbox_scpi: mailbox-scpi {
 919                 compatible = "rockchip,rk3368-scpi-legacy";
 920                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 921                 chan-nums = <3>;
 922                 status = "disabled";
 923         };
 924
 925         qos_iep: qos@ffad0000 {
 926                 compatible = "syscon";
 927                 reg = <0x0 0xffad0000 0x0 0x20>;
 928         };
 929
 930         qos_isp_r0: qos@ffad0080 {
 931                 compatible = "syscon";
 932                 reg = <0x0 0xffad0080 0x0 0x20>;
 933         };
 934
 935         qos_isp_r1: qos@ffad0100 {
 936                 compatible = "syscon";
 937                 reg = <0x0 0xffad0100 0x0 0x20>;
 938         };
 939
 940         qos_isp_w0: qos@ffad0180 {
 941                 compatible = "syscon";
 942                 reg = <0x0 0xffad0180 0x0 0x20>;
 943         };
 944
 945         qos_isp_w1: qos@ffad0200 {
 946                 compatible = "syscon";
 947                 reg = <0x0 0xffad0200 0x0 0x20>;
 948         };
 949
 950         qos_vip: qos@ffad0280 {
 951                 compatible = "syscon";
 952                 reg = <0x0 0xffad0280 0x0 0x20>;
 953         };
 954
 955         qos_vop: qos@ffad0300 {
 956                 compatible = "syscon";
 957                 reg = <0x0 0xffad0300 0x0 0x20>;
 958         };
 959
 960         qos_rga_r: qos@ffad0380 {
 961                 compatible = "syscon";
 962                 reg = <0x0 0xffad0380 0x0 0x20>;
 963         };
 964
 965         qos_rga_w: qos@ffad0400 {
 966                 compatible = "syscon";
 967                 reg = <0x0 0xffad0400 0x0 0x20>;
 968         };
 969
 970         qos_hevc_r: qos@ffae0000 {
 971                 compatible = "syscon";
 972                 reg = <0x0 0xffae0000 0x0 0x20>;
 973         };
 974
 975         qos_vpu_r: qos@ffae0100 {
 976                 compatible = "syscon";
 977                 reg = <0x0 0xffae0100 0x0 0x20>;
 978         };
 979
 980         qos_vpu_w: qos@ffae0180 {
 981                 compatible = "syscon";
 982                 reg = <0x0 0xffae0180 0x0 0x20>;
 983         };
 984
 985         qos_gpu: qos@ffaf0000 {
 986                 compatible = "syscon";
 987                 reg = <0x0 0xffaf0000 0x0 0x20>;
 988         };
 989
 990         pmu: power-management@ff730000 {
 991                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 992                 reg = <0x0 0xff730000 0x0 0x1000>;
 993
 994                 power: power-controller {
 995                         compatible = "rockchip,rk3368-power-controller";
 996                         #power-domain-cells = <1>;
 997                         #address-cells = <1>;
 998                         #size-cells = <0>;
 999
1000                         /*
1001                          * Note: Although SCLK_* are the working clocks
1002                          * of device without including on the NOC, needed for
1003                          * synchronous reset.
1004                          *
1005                          * The clocks on the which NOC:
1006                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
1007                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
1008                          * ACLK_RGA is on ACLK_RGA_NIU.
1009                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
1010                          *
1011                          * Which clock are device clocks:
1012                          *      clocks          devices
1013                          *      *_IEP           IEP:Image Enhancement Processor
1014                          *      *_ISP           ISP:Image Signal Processing
1015                          *      *_VIP           VIP:Video Input Processor
1016                          *      *_VOP*          VOP:Visual Output Processor
1017                          *      *_RGA           RGA
1018                          *      *_EDP*          EDP
1019                          *      *_DPHY*         LVDS
1020                          *      *_HDMI          HDMI
1021                          *      *_MIPI_*        MIPI
1022                          */
1023                         pd_vio {
1024                                 reg = <RK3368_PD_VIO>;
1025                                 clocks = <&cru ACLK_IEP>,
1026                                          <&cru ACLK_ISP>,
1027                                          <&cru ACLK_VIP>,
1028                                          <&cru ACLK_RGA>,
1029                                          <&cru ACLK_VOP>,
1030                                          <&cru ACLK_VOP_IEP>,
1031                                          <&cru DCLK_VOP>,
1032                                          <&cru HCLK_IEP>,
1033                                          <&cru HCLK_ISP>,
1034                                          <&cru HCLK_RGA>,
1035                                          <&cru HCLK_VIP>,
1036                                          <&cru HCLK_VOP>,
1037                                          <&cru HCLK_VIO_HDCPMMU>,
1038                                          <&cru PCLK_EDP_CTRL>,
1039                                          <&cru PCLK_HDMI_CTRL>,
1040                                          <&cru PCLK_HDCP>,
1041                                          <&cru PCLK_ISP>,
1042                                          <&cru PCLK_VIP>,
1043                                          <&cru PCLK_DPHYRX>,
1044                                          <&cru PCLK_DPHYTX0>,
1045                                          <&cru PCLK_MIPI_CSI>,
1046                                          <&cru PCLK_MIPI_DSI0>,
1047                                          <&cru SCLK_VOP0_PWM>,
1048                                          <&cru SCLK_EDP_24M>,
1049                                          <&cru SCLK_EDP>,
1050                                          <&cru SCLK_HDCP>,
1051                                          <&cru SCLK_ISP>,
1052                                          <&cru SCLK_RGA>,
1053                                          <&cru SCLK_HDMI_CEC>,
1054                                          <&cru SCLK_HDMI_HDCP>;
1055                                 pm_qos = <&qos_iep>,
1056                                          <&qos_isp_r0>,
1057                                          <&qos_isp_r1>,
1058                                          <&qos_isp_w0>,
1059                                          <&qos_isp_w1>,
1060                                          <&qos_vip>,
1061                                          <&qos_vop>,
1062                                          <&qos_rga_r>,
1063                                          <&qos_rga_w>;
1064                         };
1065                         /*
1066                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
1067                          * (video endecoder & decoder) clocks that on the
1068                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
1069                          */
1070                         pd_video {
1071                                 reg = <RK3368_PD_VIDEO>;
1072                                 clocks = <&cru ACLK_VIDEO>,
1073                                          <&cru HCLK_VIDEO>,
1074                                          <&cru SCLK_HEVC_CABAC>,
1075                                          <&cru SCLK_HEVC_CORE>;
1076                                 pm_qos = <&qos_hevc_r>,
1077                                          <&qos_vpu_r>,
1078                                          <&qos_vpu_w>;
1079                         };
1080                         /*
1081                          * Note: ACLK_GPU is the GPU clock,
1082                          * and on the ACLK_GPU_NIU (NOC).
1083                          */
1084                         pd_gpu_1 {
1085                                 reg = <RK3368_PD_GPU_1>;
1086                                 clocks = <&cru ACLK_GPU_CFG>,
1087                                          <&cru ACLK_GPU_MEM>,
1088                                          <&cru SCLK_GPU_CORE>;
1089                                 pm_qos = <&qos_gpu>;
1090                         };
1091                 };
1092         };
1093
1094         pmugrf: syscon@ff738000 {
1095                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1096                 reg = <0x0 0xff738000 0x0 0x1000>;
1097
1098                 pmu_io_domains: io-domains {
1099                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1100                         status = "disabled";
1101                 };
1102
1103                 reboot-mode {
1104                         compatible = "syscon-reboot-mode";
1105                         offset = <0x200>;
1106                         mode-normal = <BOOT_NORMAL>;
1107                         mode-recovery = <BOOT_RECOVERY>;
1108                         mode-bootloader = <BOOT_FASTBOOT>;
1109                         mode-loader = <BOOT_BL_DOWNLOAD>;
1110                 };
1111         };
1112
1113         cru: clock-controller@ff760000 {
1114                 compatible = "rockchip,rk3368-cru";
1115                 reg = <0x0 0xff760000 0x0 0x1000>;
1116                 rockchip,grf = <&grf>;
1117                 #clock-cells = <1>;
1118                 #reset-cells = <1>;
1119                 assigned-clocks =
1120                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1121                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1122                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1123                         <&cru PCLK_BUS>, <&cru PCLK_PERI>,
1124                         <&cru ACLK_CCI_PRE>;
1125                 assigned-clock-rates =
1126                         <576000000>, <400000000>,
1127                         <300000000>, <300000000>,
1128                         <150000000>, <150000000>,
1129                         <75000000>, <75000000>,
1130                         <576000000>;
1131         };
1132
1133         grf: syscon@ff770000 {
1134                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1135                 reg = <0x0 0xff770000 0x0 0x1000>;
1136                 #address-cells = <1>;
1137                 #size-cells = <1>;
1138
1139                 edp_phy: edp-phy {
1140                         compatible = "rockchip,rk3368-dp-phy";
1141                         clocks = <&cru SCLK_EDP_24M>;
1142                         clock-names = "24m";
1143                         resets = <&cru SRST_EDP_24M>;
1144                         reset-names = "edp_24m";
1145                         #phy-cells = <0>;
1146                         status = "disabled";
1147                 };
1148
1149                 io_domains: io-domains {
1150                         compatible = "rockchip,rk3368-io-voltage-domain";
1151                         status = "disabled";
1152                 };
1153
1154                 u2phy: usb2-phy@700 {
1155                         compatible = "rockchip,rk3368-usb2phy";
1156                         reg = <0x700 0x2c>;
1157                         clocks = <&cru SCLK_OTGPHY0>;
1158                         clock-names = "phyclk";
1159                         #clock-cells = <0>;
1160                         clock-output-names = "usbotg_out";
1161                         assigned-clocks = <&cru SCLK_USBPHY480M>;
1162                         assigned-clock-parents = <&u2phy>;
1163                         status = "disabled";
1164
1165                         u2phy_host: host-port {
1166                                 #phy-cells = <0>;
1167                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1168                                 interrupt-names = "linestate";
1169                                 status = "disabled";
1170                         };
1171                 };
1172         };
1173
1174         wdt: watchdog@ff800000 {
1175                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1176                 reg = <0x0 0xff800000 0x0 0x100>;
1177                 clocks = <&cru PCLK_WDT>;
1178                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1179                 status = "disabled";
1180         };
1181
1182         timer@ff810000 {
1183                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1184                 reg = <0x0 0xff810000 0x0 0x20>;
1185                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1186         };
1187
1188         i2s_2ch: i2s-2ch@ff890000 {
1189                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1190                 reg = <0x0 0xff890000 0x0 0x1000>;
1191                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1192                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1193                 dma-names = "tx", "rx";
1194                 clock-names = "i2s_clk", "i2s_hclk";
1195                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1196                 status = "disabled";
1197         };
1198
1199         i2s_8ch: i2s-8ch@ff898000 {
1200                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1201                 reg = <0x0 0xff898000 0x0 0x1000>;
1202                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1203                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1204                 dma-names = "tx", "rx";
1205                 clock-names = "i2s_clk", "i2s_hclk";
1206                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1207                 pinctrl-names = "default";
1208                 pinctrl-0 = <&i2s_8ch_bus>;
1209                 status = "disabled";
1210         };
1211
1212         iep: iep@ff900000 {
1213                 compatible = "rockchip,iep";
1214                 iommu_enabled = <1>;
1215                 iommus = <&iep_mmu>;
1216                 reg = <0x0 0xff900000 0x0 0x800>;
1217                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1218                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1219                 clock-names = "aclk_iep", "hclk_iep";
1220                 power-domains = <&power RK3368_PD_VIO>;
1221                 allocator = <1>;
1222                 version = <2>;
1223                 status = "disabled";
1224         };
1225
1226         iep_mmu: iommu@ff900800 {
1227                 compatible = "rockchip,iommu";
1228                 reg = <0x0 0xff900800 0x0 0x100>;
1229                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1230                 interrupt-names = "iep_mmu";
1231                 power-domains = <&power RK3368_PD_VIO>;
1232                 #iommu-cells = <0>;
1233                 status = "disabled";
1234         };
1235
1236         isp: isp@ff910000 {
1237                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
1238                 reg = <0x0 0xff910000 0x0 0x4000>;
1239                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1240                 power-domains = <&power RK3368_PD_VIO>;
1241                 clocks =
1242                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1243                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1244                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1245                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1246                 clock-names =
1247                         "aclk_isp", "hclk_isp", "clk_isp",
1248                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1249                         "clk_cif_pll", "hclk_mipiphy1",
1250                         "pclk_dphyrx", "clk_vio0_noc";
1251
1252                 pinctrl-names =
1253                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1254                         "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1255                         "isp_mipi_fl", "isp_mipi_fl_prefl",
1256                         "isp_flash_as_gpio", "isp_flash_as_trigger_out";
1257                 pinctrl-0 = <&cif_clkout>;
1258                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1259                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1260                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1261                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1262                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1263                 pinctrl-6 = <&cif_clkout>;
1264                 pinctrl-7 = <&cif_clkout &isp_prelight>;
1265                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1266                 pinctrl-9 = <&isp_flash_trigger>;
1267                 rockchip,isp,mipiphy = <2>;
1268                 rockchip,isp,cifphy = <1>;
1269                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1270                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1271                 rockchip,grf = <&grf>;
1272                 rockchip,cru = <&cru>;
1273                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1274                 rockchip,isp,iommu-enable = <1>;
1275                 iommus = <&isp_mmu>;
1276                 status = "disabled";
1277         };
1278
1279         isp_mmu: iommu@ff914000 {
1280                 compatible = "rockchip,iommu";
1281                 reg = <0x0 0xff914000 0x0 0x100>,
1282                       <0x0 0xff915000 0x0 0x100>;
1283                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1284                 interrupt-names = "isp_mmu";
1285                 clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
1286                 clock-names = "aclk", "hclk";
1287                 rk_iommu,disable_reset_quirk;
1288                 #iommu-cells = <0>;
1289                 power-domains = <&power RK3368_PD_VIO>;
1290                 status = "disabled";
1291         };
1292
1293         vop: vop@ff930000 {
1294                 compatible = "rockchip,rk3368-vop";
1295                 reg = <0x0 0xff930000 0x0 0x2fc>;
1296                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1297                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1298                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1299                 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1300                 assigned-clock-rates = <400000000>, <200000000>;
1301                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1302                 reset-names = "axi", "ahb", "dclk";
1303                 power-domains = <&power RK3368_PD_VIO>;
1304                 iommus = <&vop_mmu>;
1305                 status = "disabled";
1306
1307                 vop_out: port {
1308                         #address-cells = <1>;
1309                         #size-cells = <0>;
1310
1311                         vop_out_mipi: endpoint@0 {
1312                                 reg = <0>;
1313                                 remote-endpoint = <&mipi_in_vop>;
1314                         };
1315
1316                         vop_out_edp: endpoint@1 {
1317                                 reg = <1>;
1318                                 remote-endpoint = <&edp_in_vop>;
1319                         };
1320                 };
1321         };
1322
1323         display_subsystem: display-subsystem {
1324                 compatible = "rockchip,display-subsystem";
1325                 ports = <&vop_out>;
1326                 status = "disabled";
1327         };
1328
1329         vop_mmu: iommu@ff930300 {
1330                 compatible = "rockchip,iommu";
1331                 reg = <0x0 0xff930300 0x0 0x100>;
1332                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1333                 interrupt-names = "vop_mmu";
1334                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1335                 clock-names = "aclk", "hclk";
1336                 power-domains = <&power RK3368_PD_VIO>;
1337                 #iommu-cells = <0>;
1338                 status = "disabled";
1339         };
1340
1341         mipi_dsi_host: mipi-dsi-host@ff960000 {
1342                 compatible = "rockchip,rk3368-mipi-dsi";
1343                 reg = <0x0 0xff960000 0x0 0x4000>;
1344                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1345                 clocks = <&cru PCLK_MIPI_DSI0>;
1346                 clock-names = "pclk";
1347                 resets = <&cru SRST_MIPIDSI0>;
1348                 reset-names = "apb";
1349                 phys = <&mipi_dphy>;
1350                 phy-names = "mipi_dphy";
1351                 rockchip,grf = <&grf>;
1352                 power-domains = <&power RK3368_PD_VIO>;
1353                 #address-cells = <1>;
1354                 #size-cells = <0>;
1355                 status = "disabled";
1356
1357                 ports {
1358                         port {
1359                                 mipi_in_vop: endpoint {
1360                                         remote-endpoint = <&vop_out_mipi>;
1361                                 };
1362                         };
1363                 };
1364         };
1365
1366         mipi_dphy: mipi-dphy@ff968000 {
1367                 compatible = "rockchip,rk3368-mipi-dphy";
1368                 reg = <0x0 0xff968000 0x0 0x4000>;
1369                 #phy-cells = <0>;
1370                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1371                 clock-names = "ref", "pclk";
1372                 resets = <&cru SRST_MIPIDPHYTX>;
1373                 reset-names = "apb";
1374                 status = "disabled";
1375         };
1376
1377         edp: edp@ff970000 {
1378                 compatible = "rockchip,rk3368-edp";
1379                 reg = <0x0 0xff970000 0x0 0x8000>;
1380                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1381                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1382                 clock-names = "dp", "pclk";
1383                 resets = <&cru SRST_EDP>;
1384                 reset-names = "dp";
1385                 power-domains = <&power RK3368_PD_VIO>;
1386                 rockchip,grf = <&grf>;
1387                 phys = <&edp_phy>;
1388                 phy-names = "dp";
1389                 pinctrl-names = "default";
1390                 pinctrl-0 = <&edp_hpd>;
1391                 status = "disabled";
1392
1393                 ports {
1394                         #address-cells = <1>;
1395                         #size-cells = <0>;
1396
1397                         edp_in: port@0 {
1398                                 reg = <0>;
1399
1400                                 edp_in_vop: endpoint {
1401                                         remote-endpoint = <&vop_out_edp>;
1402                                 };
1403                         };
1404                 };
1405         };
1406
1407         hevc_mmu: iommu@ff9a0440 {
1408                 compatible = "rockchip,iommu";
1409                 reg = <0x0 0xff9a0440 0x0 0x40>,
1410                       <0x0 0xff9a0480 0x0 0x40>;
1411                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1412                 interrupt-names = "hevc_mmu";
1413                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1414                 clock-names = "aclk", "hclk";
1415                 power-domains = <&power RK3368_PD_VIDEO>;
1416                 #iommu-cells = <0>;
1417                 status = "disabled";
1418         };
1419
1420         vpu_mmu: iommu@ff9a0800 {
1421                 compatible = "rockchip,iommu";
1422                 reg = <0x0 0xff9a0800 0x0 0x100>;
1423                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1424                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1425                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1426                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1427                 clock-names = "aclk", "hclk";
1428                 power-domains = <&power RK3368_PD_VIDEO>;
1429                 #iommu-cells = <0>;
1430                 status = "disabled";
1431         };
1432
1433         vpu: vpu_service {
1434                 compatible = "rockchip,vpu_sub";
1435                 iommu_enabled = <1>;
1436                 iommus = <&vpu_mmu>;
1437                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1438                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1439                 interrupt-names = "irq_enc","irq_dec";
1440                 dev_mode = <0>;
1441                 name = "vpu_service";
1442                 allocator = <1>;
1443         };
1444
1445         hevc: hevc_service {
1446                 compatible = "rockchip,hevc_sub";
1447                 iommu_enabled = <1>;
1448                 iommus = <&hevc_mmu>;
1449                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1450                 interrupt-names = "irq_dec";
1451                 dev_mode = <1>;
1452                 name = "hevc_service";
1453                 allocator = <1>;
1454         };
1455
1456         vpu_combo: vpu_combo@ff9a0000 {
1457                 compatible = "rockchip,vpu_combo";
1458                 reg = <0x0 0xff9a0000 0x0 0x440>;
1459                 rockchip,grf = <&grf>;
1460                 subcnt = <2>;
1461                 rockchip,sub = <&vpu>, <&hevc>;
1462                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1463                          <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1464                 clock-names = "aclk_vcodec", "hclk_vcodec",
1465                               "clk_core", "clk_cabac";
1466                 resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1467                          <&cru SRST_VIDEO>;
1468                 reset-names = "video_a", "video_h", "video";
1469                 mode_bit = <12>;
1470                 mode_ctrl = <0x418>;
1471                 name = "vpu_combo";
1472                 power-domains = <&power RK3368_PD_VIDEO>;
1473                 status = "disabled";
1474         };
1475
1476         gic: interrupt-controller@ffb71000 {
1477                 compatible = "arm,gic-400";
1478                 interrupt-controller;
1479                 #interrupt-cells = <3>;
1480                 #address-cells = <0>;
1481
1482                 reg = <0x0 0xffb71000 0x0 0x1000>,
1483                       <0x0 0xffb72000 0x0 0x2000>,
1484                       <0x0 0xffb74000 0x0 0x2000>,
1485                       <0x0 0xffb76000 0x0 0x2000>;
1486                 interrupts = <GIC_PPI 9
1487                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1488         };
1489
1490         gpu: rogue-g6110@ffa30000 {
1491                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1492                 reg = <0x0 0xffa30000 0x0 0x10000>;
1493                 clocks =
1494                         <&cru SCLK_GPU_CORE>,
1495                         <&cru ACLK_GPU_MEM>,
1496                         <&cru ACLK_GPU_CFG>;
1497                 clock-names =
1498                         "sclk_gpu_core",
1499                         "aclk_gpu_mem",
1500                         "aclk_gpu_cfg";
1501                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1502                 interrupt-names = "rogue-g6110-irq";
1503                 power-domains = <&power RK3368_PD_GPU_1>;
1504                 operating-points-v2 = <&gpu_opp_table>;
1505                 #cooling-cells = <2>; /* min followed by max */
1506                 gpu_power_model: power_model {
1507                         compatible = "arm,mali-simple-power-model";
1508                         voltage = <900>;
1509                         frequency = <500>;
1510                         static-power = <300>;
1511                         dynamic-power = <396>;
1512                         ts = <32000 4700 (-80) 2>;
1513                         thermal-zone = "gpu-thermal";
1514                 };
1515         };
1516
1517         gpu_opp_table: gpu_opp_table {
1518                 compatible = "operating-points-v2";
1519                 opp-shared;
1520
1521                 opp@200000000 {
1522                         opp-hz = /bits/ 64 <200000000>;
1523                         opp-microvolt = <1100000>;
1524                 };
1525                 opp@288000000 {
1526                         opp-hz = /bits/ 64 <288000000>;
1527                         opp-microvolt = <1100000>;
1528                 };
1529                 opp@400000000 {
1530                         opp-hz = /bits/ 64 <400000000>;
1531                         opp-microvolt = <1100000>;
1532                 };
1533                 opp@576000000 {
1534                         opp-hz = /bits/ 64 <576000000>;
1535                         opp-microvolt = <1200000>;
1536                 };
1537         };
1538
1539         efuse: efuse@ffb00000 {
1540                 compatible = "rockchip,rk3368-efuse";
1541                 reg = <0x0 0xffb00000 0x0 0x20>;
1542                 #address-cells = <1>;
1543                 #size-cells = <1>;
1544                 clocks = <&cru PCLK_EFUSE256>;
1545                 clock-names = "pclk_efuse";
1546
1547                 /* Data cells */
1548                 cpu_leakage: cpu-leakage@17 {
1549                         reg = <0x17 0x1>;
1550                 };
1551                 temp_adjust: temp-adjust@1f {
1552                         reg = <0x1f 0x1>;
1553                 };
1554         };
1555
1556         pinctrl: pinctrl {
1557                 compatible = "rockchip,rk3368-pinctrl";
1558                 rockchip,grf = <&grf>;
1559                 rockchip,pmu = <&pmugrf>;
1560                 #address-cells = <0x2>;
1561                 #size-cells = <0x2>;
1562                 ranges;
1563
1564                 gpio0: gpio0@ff750000 {
1565                         compatible = "rockchip,gpio-bank";
1566                         reg = <0x0 0xff750000 0x0 0x100>;
1567                         clocks = <&cru PCLK_GPIO0>;
1568                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1569
1570                         gpio-controller;
1571                         #gpio-cells = <0x2>;
1572
1573                         interrupt-controller;
1574                         #interrupt-cells = <0x2>;
1575                 };
1576
1577                 gpio1: gpio1@ff780000 {
1578                         compatible = "rockchip,gpio-bank";
1579                         reg = <0x0 0xff780000 0x0 0x100>;
1580                         clocks = <&cru PCLK_GPIO1>;
1581                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1582
1583                         gpio-controller;
1584                         #gpio-cells = <0x2>;
1585
1586                         interrupt-controller;
1587                         #interrupt-cells = <0x2>;
1588                 };
1589
1590                 gpio2: gpio2@ff790000 {
1591                         compatible = "rockchip,gpio-bank";
1592                         reg = <0x0 0xff790000 0x0 0x100>;
1593                         clocks = <&cru PCLK_GPIO2>;
1594                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1595
1596                         gpio-controller;
1597                         #gpio-cells = <0x2>;
1598
1599                         interrupt-controller;
1600                         #interrupt-cells = <0x2>;
1601                 };
1602
1603                 gpio3: gpio3@ff7a0000 {
1604                         compatible = "rockchip,gpio-bank";
1605                         reg = <0x0 0xff7a0000 0x0 0x100>;
1606                         clocks = <&cru PCLK_GPIO3>;
1607                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1608
1609                         gpio-controller;
1610                         #gpio-cells = <0x2>;
1611
1612                         interrupt-controller;
1613                         #interrupt-cells = <0x2>;
1614                 };
1615
1616                 pcfg_pull_up: pcfg-pull-up {
1617                         bias-pull-up;
1618                 };
1619
1620                 pcfg_pull_down: pcfg-pull-down {
1621                         bias-pull-down;
1622                 };
1623
1624                 pcfg_pull_none: pcfg-pull-none {
1625                         bias-disable;
1626                 };
1627
1628                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1629                         bias-disable;
1630                         drive-strength = <12>;
1631                 };
1632
1633                 edp {
1634                         edp_hpd: edp-hpd {
1635                                 rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>;
1636                         };
1637                 };
1638
1639                 emmc {
1640                         emmc_clk: emmc-clk {
1641                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1642                         };
1643
1644                         emmc_cmd: emmc-cmd {
1645                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1646                         };
1647
1648                         emmc_pwr: emmc-pwr {
1649                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1650                         };
1651
1652                         emmc_bus1: emmc-bus1 {
1653                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1654                         };
1655
1656                         emmc_bus4: emmc-bus4 {
1657                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1658                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1659                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1660                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1661                         };
1662
1663                         emmc_bus8: emmc-bus8 {
1664                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1665                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1666                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1667                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1668                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1669                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1670                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1671                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1672                         };
1673                 };
1674
1675                 gmac {
1676                         rgmii_pins: rgmii-pins {
1677                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1678                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1679                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1680                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1681                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1682                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1683                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1684                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1685                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1686                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1687                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1688                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1689                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1690                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1691                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1692                         };
1693
1694                         rmii_pins: rmii-pins {
1695                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1696                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1697                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1698                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1699                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1700                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1701                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1702                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1703                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1704                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1705                         };
1706                 };
1707
1708                 i2c0 {
1709                         i2c0_xfer: i2c0-xfer {
1710                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1711                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1712                         };
1713                 };
1714
1715                 i2c1 {
1716                         i2c1_xfer: i2c1-xfer {
1717                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1718                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1719                         };
1720                 };
1721
1722                 i2c2 {
1723                         i2c2_xfer: i2c2-xfer {
1724                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1725                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1726                         };
1727                 };
1728
1729                 i2c3 {
1730                         i2c3_xfer: i2c3-xfer {
1731                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1732                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1733                         };
1734                 };
1735
1736                 i2c4 {
1737                         i2c4_xfer: i2c4-xfer {
1738                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1739                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1740                         };
1741                 };
1742
1743                 i2c5 {
1744                         i2c5_xfer: i2c5-xfer {
1745                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1746                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1747                         };
1748                 };
1749
1750                 i2s {
1751                         i2s_8ch_bus: i2s-8ch-bus {
1752                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1753                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1754                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1755                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1756                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1757                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1758                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1759                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1760                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1761                         };
1762                 };
1763
1764                 pwm0 {
1765                         pwm0_pin: pwm0-pin {
1766                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1767                         };
1768
1769                         vop_pwm_pin: vop-pwm {
1770                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1771                         };
1772                 };
1773
1774                 pwm1 {
1775                         pwm1_pin: pwm1-pin {
1776                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1777                         };
1778                 };
1779
1780                 pwm3 {
1781                         pwm3_pin: pwm3-pin {
1782                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1783                         };
1784                 };
1785
1786                 sdio0 {
1787                         sdio0_bus1: sdio0-bus1 {
1788                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1789                         };
1790
1791                         sdio0_bus4: sdio0-bus4 {
1792                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1793                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1794                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1795                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1796                         };
1797
1798                         sdio0_cmd: sdio0-cmd {
1799                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1800                         };
1801
1802                         sdio0_clk: sdio0-clk {
1803                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1804                         };
1805
1806                         sdio0_cd: sdio0-cd {
1807                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1808                         };
1809
1810                         sdio0_wp: sdio0-wp {
1811                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1812                         };
1813
1814                         sdio0_pwr: sdio0-pwr {
1815                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1816                         };
1817
1818                         sdio0_bkpwr: sdio0-bkpwr {
1819                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1820                         };
1821
1822                         sdio0_int: sdio0-int {
1823                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1824                         };
1825                 };
1826
1827                 sdmmc {
1828                         sdmmc_clk: sdmmc-clk {
1829                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1830                         };
1831
1832                         sdmmc_cmd: sdmmc-cmd {
1833                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1834                         };
1835
1836                         sdmmc_cd: sdmmc-cd {
1837                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1838                         };
1839
1840                         sdmmc_bus1: sdmmc-bus1 {
1841                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1842                         };
1843
1844                         sdmmc_bus4: sdmmc-bus4 {
1845                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1846                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1847                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1848                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1849                         };
1850                 };
1851
1852                 spi0 {
1853                         spi0_clk: spi0-clk {
1854                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1855                         };
1856                         spi0_cs0: spi0-cs0 {
1857                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1858                         };
1859                         spi0_cs1: spi0-cs1 {
1860                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1861                         };
1862                         spi0_tx: spi0-tx {
1863                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1864                         };
1865                         spi0_rx: spi0-rx {
1866                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1867                         };
1868                 };
1869
1870                 spi1 {
1871                         spi1_clk: spi1-clk {
1872                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1873                         };
1874                         spi1_cs0: spi1-cs0 {
1875                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1876                         };
1877                         spi1_cs1: spi1-cs1 {
1878                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1879                         };
1880                         spi1_rx: spi1-rx {
1881                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1882                         };
1883                         spi1_tx: spi1-tx {
1884                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1885                         };
1886                 };
1887
1888                 spi2 {
1889                         spi2_clk: spi2-clk {
1890                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1891                         };
1892                         spi2_cs0: spi2-cs0 {
1893                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1894                         };
1895                         spi2_rx: spi2-rx {
1896                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1897                         };
1898                         spi2_tx: spi2-tx {
1899                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1900                         };
1901                 };
1902
1903                 uart0 {
1904                         uart0_xfer: uart0-xfer {
1905                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1906                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1907                         };
1908
1909                         uart0_cts: uart0-cts {
1910                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1911                         };
1912
1913                         uart0_rts: uart0-rts {
1914                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1915                         };
1916                 };
1917
1918                 uart1 {
1919                         uart1_xfer: uart1-xfer {
1920                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1921                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1922                         };
1923
1924                         uart1_cts: uart1-cts {
1925                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1926                         };
1927
1928                         uart1_rts: uart1-rts {
1929                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1930                         };
1931                 };
1932
1933                 uart2 {
1934                         uart2_xfer: uart2-xfer {
1935                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1936                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1937                         };
1938                         /* no rts / cts for uart2 */
1939                 };
1940
1941                 uart3 {
1942                         uart3_xfer: uart3-xfer {
1943                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1944                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1945                         };
1946
1947                         uart3_cts: uart3-cts {
1948                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1949                         };
1950
1951                         uart3_rts: uart3-rts {
1952                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1953                         };
1954                 };
1955
1956                 uart4 {
1957                         uart4_xfer: uart4-xfer {
1958                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1959                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1960                         };
1961
1962                         uart4_cts: uart4-cts {
1963                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1964                         };
1965
1966                         uart4_rts: uart4-rts {
1967                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1968                         };
1969                 };
1970
1971                 isp {
1972                         cif_clkout: cif-clkout {
1973                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1974                         };
1975
1976                         isp_dvp_d2d9: isp-dvp-d2d9 {
1977                                 rockchip,pins =
1978                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1979                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1980                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1981                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1982                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1983                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1984                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1985                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1986                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1987                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1988                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1989                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1990                         };
1991
1992                         isp_dvp_d0d1: isp-dvp-d0d1 {
1993                                 rockchip,pins =
1994                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1995                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1996                         };
1997
1998                         isp_dvp_d10d11:isp_d10d11 {
1999                                 rockchip,pins =
2000                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2001                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2002                         };
2003
2004                         isp_dvp_d0d7: isp-dvp-d0d7 {
2005                                 rockchip,pins =
2006                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2007                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2008                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2009                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2010                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2011                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2012                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2013                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2014                         };
2015
2016                         isp_dvp_d4d11: isp-dvp-d4d11 {
2017                                 rockchip,pins =
2018                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2019                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2020                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2021                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2022                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2023                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2024                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2025                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2026                         };
2027
2028                         isp_shutter: isp-shutter {
2029                                 rockchip,pins =
2030                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2031                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2032                         };
2033
2034                         isp_flash_trigger: isp-flash-trigger {
2035                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2036                         };
2037
2038                         isp_prelight: isp-prelight {
2039                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2040                         };
2041
2042                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2043                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2044                         };
2045                 };
2046         };
2047 };