arch/arm64/boot/dts/rockchip/rk3368-android.dtsi

   1 /*
   2  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/display/rk_fb.h>
  44 #include <dt-bindings/display/mipi_dsi.h>
  45
  46 / {
  47         aliases {
  48                 lcdc = &lcdc;
  49         };
  50
  51         chosen {
  52                 bootargs = "earlycon=uart8250,mmio32,0xff690000 swiotlb=1 firmware_class.path=/system/vendor/firmware";
  53         };
  54
  55         fiq_debugger: fiq-debugger {
  56                 compatible = "rockchip,fiq-debugger";
  57                 rockchip,serial-id = <2>;
  58                 rockchip,signal-irq = <186>;
  59                 rockchip,wake-irq = <0>;
  60                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
  61                 rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
  62                 pinctrl-names = "default";
  63                 pinctrl-0 = <&uart2_xfer>;
  64         };
  65
  66         reserved-memory {
  67                 #address-cells = <2>;
  68                 #size-cells = <2>;
  69                 ranges;
  70
  71                 /* global autoconfigured region for contiguous allocations */
  72                 linux,cma {
  73                         compatible = "shared-dma-pool";
  74                         reusable;
  75                         size = <0x0 0x8000000>;
  76                         linux,cma-default;
  77                 };
  78
  79                 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
  80                 rockchip_logo: rockchip-logo@00000000 {
  81                         compatible = "rockchip,fb-logo";
  82                         reg = <0x0 0x0 0x0 0x0>;
  83                 };
  84         };
  85
  86         ion {
  87                 compatible = "rockchip,ion";
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90
  91                 cma-heap {
  92                         reg = <0x00000000 0x02000000>;
  93                 };
  94
  95                 system-heap {
  96                 };
  97         };
  98
  99         isp: isp@ff910000 {
 100                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
 101                 reg = <0x0 0xff910000 0x0 0x10000>;
 102                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 103                 /*power-domains = <&power PD_VIO>;*/
 104                 clocks =
 105                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
 106                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
 107                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
 108                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
 109                 clock-names =
 110                         "aclk_isp", "hclk_isp", "clk_isp",
 111                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
 112                         "clk_cif_pll", "hclk_mipiphy1",
 113                         "pclk_dphyrx", "clk_vio0_noc";
 114                 pinctrl-names =
 115                         "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
 116                         "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
 117                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 118                         "isp_flash_as_trigger_out";
 119                 pinctrl-0 = <&cif_clkout>;
 120                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
 121                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
 122                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
 123                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
 124                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
 125                 pinctrl-6 = <&cif_clkout>;
 126                 pinctrl-7 = <&cif_clkout &isp_prelight>;
 127                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
 128                 pinctrl-9 = <&isp_flash_trigger>;
 129                 rockchip,isp,mipiphy = <2>;
 130                 rockchip,isp,cifphy = <1>;
 131                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
 132                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
 133                 rockchip,grf = <&grf>;
 134                 rockchip,cru = <&cru>;
 135                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 136                 rockchip,isp,iommu_enable = <1>;
 137                 status = "disabled";
 138         };
 139
 140         rga@ff920000 {
 141                 compatible = "rockchip,rga2";
 142                 dev_mode = <1>;
 143                 reg = <0x0 0xff920000 0x0 0x1000>;
 144                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 145                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 146                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 147                 status = "disabled";
 148         };
 149
 150         fb {
 151                 compatible = "rockchip,rk-fb";
 152                 status = "okay";
 153
 154                 rockchip,disp-mode = <NO_DUAL>;
 155                 rockchip,uboot-logo-on = <0>;
 156
 157         };
 158
 159         screen {
 160                 compatible = "rockchip,screen";
 161                 status = "okay";
 162
 163                 #include <dt-bindings/display/screen-timing/lcd-tv080wum-mipi.dtsi>
 164         };
 165
 166         lcdc: lcdc@ff930000 {
 167                 compatible = "rockchip,rk3368-lcdc";
 168                 rockchip,grf = <&grf>;
 169                 rockchip,pmugrf = <&pmugrf>;
 170                 rockchip,cru = <&cru>;
 171                 rockchip,prop = <PRMRY>;
 172                 rockchip,pwr18 = <0>;
 173                 rockchip,iommu-enabled = <1>;
 174                 reg = <0x0 0xff930000 0x0 0x10000>;
 175                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
 177                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 178                 assigned-clocks = <&cru ACLK_VOP>;
 179                 assigned-clock-rates = <400000000>;
 180                 /*power-domains = <&power PD_VIO>;*/
 181                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 182                 reset-names = "axi", "ahb", "dclk";
 183         };
 184
 185         mipi: mipi@ff960000 {
 186                 compatible = "rockchip,rk3368-dsi";
 187                 rockchip,prop = <0>;
 188                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 189                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 190                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 191                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
 192                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 193                 /*power-domains = <&power PD_VIO>;*/
 194         };
 195
 196         lvds: lvds@ff968000 {
 197                 compatible = "rockchip,rk3368-lvds";
 198                 rockchip,grf = <&grf>;
 199                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 200                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 201                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
 202                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 203                 /*power-domains = <&power PD_VIO>;*/
 204                 status = "disabled";
 205         };
 206
 207         edp: edp@ff970000 {
 208                 compatible = "rockchip,rk32-edp";
 209                 reg = <0x0 0xff970000 0x0 0x4000>;
 210                 rockchip,grf = <&grf>;
 211                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 212                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
 213                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 214                 /*power-domains = <&power PD_VIO>;*/
 215                 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
 216                 reset-names = "edp_24m", "edp_apb";
 217                 status = "disabled";
 218         };
 219
 220         hdmi: hdmi@ff980000 {
 221                 compatible = "rockchip,rk3368-hdmi";
 222                 reg = <0x0 0xff980000 0x0 0x20000>;
 223                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 224                 clocks = <&cru PCLK_HDMI_CTRL>,
 225                          <&cru SCLK_HDMI_HDCP>,
 226                          <&cru SCLK_HDMI_CEC>;
 227                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 228                 /*power-domains = <&power PD_VIO>;*/
 229                 resets = <&cru SRST_HDMI>;
 230                 reset-names = "hdmi";
 231                 pinctrl-names = "default", "gpio";
 232                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 233                 pinctrl-1 = <&i2c5_gpio>;
 234                 status = "okay";
 235         };
 236
 237         iep-mmu {
 238                 dbgname = "iep";
 239                 compatible = "rockchip,iep_mmu";
 240                 reg = <0x0 0xff900800 0x0 0x100>;
 241                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 242                 interrupt-names = "iep_mmu";
 243         };
 244
 245         vip-mmu {
 246                 dbgname = "vip";
 247                 compatible = "rockchip,vip_mmu";
 248                 reg = <0x0 0xff950800 0x0 0x100>;
 249                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 250                 interrupt-names = "vip_mmu";
 251         };
 252
 253         vopb-mmu {
 254                 dbgname = "vop";
 255                 compatible = "rockchip,vopb_mmu";
 256                 reg = <0x0 0xff930300 0x0 0x100>;
 257                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 258                 interrupt-names = "vop_mmu";
 259         };
 260
 261         isp-mmu {
 262                 dbgname = "isp_mmu";
 263                 compatible = "rockchip,isp_mmu";
 264                 reg = <0x0 0xff914000 0x0 0x100>,
 265                       <0x0 0xff915000 0x0 0x100>;
 266                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 267                 interrupt-names = "isp_mmu";
 268         };
 269
 270         hdcp-mmu {
 271                 dbgname = "hdcp_mmu";
 272                 compatible = "rockchip,hdcp_mmu";
 273                 reg = <0x0 0xff940000 0x0 0x100>;
 274                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 275                 interrupt-names = "hdcp_mmu";
 276         };
 277
 278         hevc-mmu {
 279                 dbgname = "hevc";
 280                 compatible = "rockchip,hevc_mmu";
 281                 reg = <0x0 0xff9a0440 0x0 0x40>,
 282                       <0x0 0xff9a0480 0x0 0x40>;
 283                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 284                 interrupt-names = "hevc_mmu";
 285         };
 286
 287         vpu-mmu {
 288                 dbgname = "vpu";
 289                 compatible = "rockchip,vpu_mmu";
 290                 reg = <0x0 0xff9a0800 0x0 0x100>;
 291                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 293                 interrupt-names = "vepu_mmu", "vdpu_mmu";
 294         };
 295
 296         dwc_control_usb: dwc-control-usb {
 297                 compatible = "rockchip,rk3368-dwc-control-usb";
 298                 status = "okay";
 299
 300                 rockchip,grf = <&grf>;
 301                 grf-offset = <0x04bc>; /* GRF_SOC_STATUS for USB2.0 OTG */
 302                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 306                 interrupt-names = "otg_id", "otg_bvalid",
 307                                   "otg_linestate", "host0_linestate";
 308                 clocks = <&cru HCLK_USB_PERI>;
 309                 clock-names = "hclk_usb_peri";
 310
 311                 otg_drv_gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
 312                 rockchip,remote_wakeup;
 313                 rockchip,usb_irq_wakeup;
 314
 315                 usb_bc {
 316                         compatible = "inno,phy";
 317                         regbase = &dwc_control_usb;
 318                         rk_usb,bvalid     = <0x4bc 23 1>;
 319                         rk_usb,iddig      = <0x4bc 26 1>;
 320                         rk_usb,vdmsrcen   = <0x718 12 1>;
 321                         rk_usb,vdpsrcen   = <0x718 11 1>;
 322                         rk_usb,rdmpden    = <0x718 10 1>;
 323                         rk_usb,idpsrcen   = <0x718  9 1>;
 324                         rk_usb,idmsinken  = <0x718  8 1>;
 325                         rk_usb,idpsinken  = <0x718  7 1>;
 326                         rk_usb,dpattach   = <0x4b8 31 1>;
 327                         rk_usb,cpdet      = <0x4b8 30 1>;
 328                         rk_usb,dcpattach  = <0x4b8 29 1>;
 329                 };
 330         };
 331 };
 332
 333 &usb_otg {
 334         clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>;
 335         clock-names = "sclk_otgphy0", "otg";
 336         resets = <&cru SRST_USBOTG_AHB>,
 337                  <&cru SRST_USBOTG_PHY>,
 338                  <&cru SRST_USBOTG_CON>;
 339         reset-names = "otg_ahb", "otg_phy", "otg_controller";
 340         /* 0 - Normal, 1 - Force Host, 2 - Force Device */
 341         rockchip,usb-mode = <0>;
 342 };
 343
 344 &lcdc {
 345         status = "okay";
 346         backlight = <&backlight>;
 347         rockchip,mirror = <NO_MIRROR>;
 348         rockchip,cabc_mode = <0>;
 349         rockchip,fb-win-map = <FB_DEFAULT_ORDER>;
 350         power_ctr: power_ctr {
 351                 rockchip,debug = <0>;
 352                 lcd_en: lcd-en {
 353                         rockchip,power_type = <GPIO>;
 354                         gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;/*GPIO_C6 = 22*/
 355                         rockchip,delay = <120>;
 356                 };
 357
 358                 lcd_cs: lcd-cs {
 359                         rockchip,power_type = <GPIO>;
 360                         gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;/*GPIO_C5 = 21*/
 361                         rockchip,delay = <10>;
 362                 };
 363
 364                 /*lcd_rst: lcd-rst {
 365                         rockchip,power_type = <GPIO>;
 366                         gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
 367                         rockchip,delay = <5>;
 368                 };*/
 369         };
 370 };
 371
 372 &pinctrl {
 373         hdmi_i2c {
 374                 hdmii2c_xfer: hdmii2c-xfer {
 375                         rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
 376                                         <3 27 RK_FUNC_1 &pcfg_pull_none>;
 377                 };
 378         };
 379
 380         hdmi_pin {
 381                 hdmi_cec: hdmi-cec {
 382                         rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
 383                 };
 384         };
 385
 386         i2c5 {
 387                 i2c5_gpio: i2c5-gpio {
 388                         rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
 389                                         <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
 390                 };
 391         };
 392
 393         lcdc {
 394                 lcdc_lcdc: lcdc-lcdc {
 395                         rockchip,pins =
 396                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
 397                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
 398                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
 399                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
 400                                         <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
 401                                         <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
 402                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
 403                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
 404                                         <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
 405                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
 406                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
 407                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
 408                                         <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
 409                                         <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
 410                                         <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
 411                                         <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
 412                                         <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
 413                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
 414                 };
 415
 416                 lcdc_gpio: lcdc-gpio {
 417                         rockchip,pins =
 418                                         <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
 419                                         <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
 420                                         <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
 421                                         <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
 422                                         <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
 423                                         <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
 424                                         <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
 425                                         <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
 426                                         <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
 427                                         <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
 428                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
 429                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
 430                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
 431                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
 432                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
 433                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
 434                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
 435                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
 436                 };
 437         };
 438
 439         isp {
 440                 cif_clkout: cif-clkout {
 441                         rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
 442                 };
 443
 444                 isp_dvp_d2d9: isp-dvp-d2d9 {
 445                         rockchip,pins =
 446                                         <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
 447                                         <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
 448                                         <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
 449                                         <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
 450                                         <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
 451                                         <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
 452                                         <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
 453                                         <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
 454                                         <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
 455                                         <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
 456                                         <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
 457                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
 458                 };
 459
 460                 isp_dvp_d0d1: isp-dvp-d0d1 {
 461                         rockchip,pins =
 462                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
 463                                         <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
 464                 };
 465
 466                 isp_dvp_d10d11:isp_d10d11 {
 467                         rockchip,pins =
 468                                         <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
 469                                         <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
 470                 };
 471
 472                 isp_dvp_d0d7: isp-dvp-d0d7 {
 473                         rockchip,pins =
 474                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
 475                                         <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
 476                                         <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
 477                                         <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
 478                                         <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
 479                                         <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
 480                                         <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
 481                                         <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
 482                 };
 483
 484                 isp_dvp_d4d11: isp-dvp-d4d11 {
 485                         rockchip,pins =
 486                                         <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
 487                                         <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
 488                                         <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
 489                                         <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
 490                                         <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
 491                                         <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
 492                                         <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
 493                                         <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
 494                 };
 495
 496                 isp_shutter: isp-shutter {
 497                         rockchip,pins =
 498                                         <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
 499                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
 500                 };
 501
 502                 isp_flash_trigger: isp-flash-trigger {
 503                         rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
 504                 };
 505
 506                 isp_prelight: isp-prelight {
 507                         rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
 508                 };
 509
 510                 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
 511                         rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
 512                 };
 513         };
 514 };