2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/display/rk_fb.h>
44 #include <dt-bindings/display/mipi_dsi.h>
52 bootargs = "earlycon=uart8250,mmio32,0xff690000 swiotlb=1 firmware_class.path=/system/vendor/firmware";
55 fiq_debugger: fiq-debugger {
56 compatible = "rockchip,fiq-debugger";
57 rockchip,serial-id = <2>;
58 rockchip,signal-irq = <186>;
59 rockchip,wake-irq = <0>;
60 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
61 rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
62 pinctrl-names = "default";
63 pinctrl-0 = <&uart2_xfer>;
71 /* global autoconfigured region for contiguous allocations */
73 compatible = "shared-dma-pool";
75 size = <0x0 0x8000000>;
79 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
80 rockchip_logo: rockchip-logo@00000000 {
81 compatible = "rockchip,fb-logo";
82 reg = <0x0 0x0 0x0 0x0>;
87 compatible = "rockchip,ion";
92 reg = <0x00000000 0x02000000>;
100 compatible = "rockchip,rk3368-isp", "rockchip,isp";
101 reg = <0x0 0xff910000 0x0 0x10000>;
102 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
103 /*power-domains = <&power PD_VIO>;*/
105 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
106 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
107 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
108 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
110 "aclk_isp", "hclk_isp", "clk_isp",
111 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
112 "clk_cif_pll", "hclk_mipiphy1",
113 "pclk_dphyrx", "clk_vio0_noc";
115 "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
116 "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
117 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
118 "isp_flash_as_trigger_out";
119 pinctrl-0 = <&cif_clkout>;
120 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
121 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
122 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
123 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
124 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
125 pinctrl-6 = <&cif_clkout>;
126 pinctrl-7 = <&cif_clkout &isp_prelight>;
127 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
128 pinctrl-9 = <&isp_flash_trigger>;
129 rockchip,isp,mipiphy = <2>;
130 rockchip,isp,cifphy = <1>;
131 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
132 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
133 rockchip,grf = <&grf>;
134 rockchip,cru = <&cru>;
135 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
136 rockchip,isp,iommu_enable = <1>;
141 compatible = "rockchip,rga2";
143 reg = <0x0 0xff920000 0x0 0x1000>;
144 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
146 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
151 compatible = "rockchip,rk-fb";
152 rockchip,disp-mode = <NO_DUAL>;
157 compatible = "rockchip,screen";
161 lcdc: lcdc@ff930000 {
162 compatible = "rockchip,rk3368-lcdc";
163 rockchip,grf = <&grf>;
164 rockchip,pmugrf = <&pmugrf>;
165 rockchip,cru = <&cru>;
166 rockchip,prop = <PRMRY>;
167 rockchip,pwr18 = <0>;
168 rockchip,iommu-enabled = <1>;
169 reg = <0x0 0xff930000 0x0 0x10000>;
170 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
172 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
173 assigned-clocks = <&cru ACLK_VOP>;
174 assigned-clock-rates = <400000000>;
175 /*power-domains = <&power PD_VIO>;*/
176 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
177 reset-names = "axi", "ahb", "dclk";
181 mipi: mipi@ff960000 {
182 compatible = "rockchip,rk3368-dsi";
184 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
185 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
186 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
188 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
189 /*power-domains = <&power PD_VIO>;*/
193 lvds: lvds@ff968000 {
194 compatible = "rockchip,rk3368-lvds";
195 rockchip,grf = <&grf>;
196 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
197 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
198 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
199 clock-names = "pclk_lvds", "pclk_lvds_ctl";
200 /*power-domains = <&power PD_VIO>;*/
205 compatible = "rockchip,rk32-edp";
206 reg = <0x0 0xff970000 0x0 0x4000>;
207 rockchip,grf = <&grf>;
208 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
210 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
211 /*power-domains = <&power PD_VIO>;*/
212 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
213 reset-names = "edp_24m", "edp_apb";
217 hdmi: hdmi@ff980000 {
218 compatible = "rockchip,rk3368-hdmi";
219 reg = <0x0 0xff980000 0x0 0x20000>;
220 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cru PCLK_HDMI_CTRL>,
222 <&cru SCLK_HDMI_HDCP>,
223 <&cru SCLK_HDMI_CEC>;
224 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
225 /*power-domains = <&power PD_VIO>;*/
226 resets = <&cru SRST_HDMI>;
227 reset-names = "hdmi";
228 pinctrl-names = "default", "gpio";
229 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
230 pinctrl-1 = <&i2c5_gpio>;
236 compatible = "rockchip,iep_mmu";
237 reg = <0x0 0xff900800 0x0 0x100>;
238 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
239 interrupt-names = "iep_mmu";
245 compatible = "rockchip,vip_mmu";
246 reg = <0x0 0xff950800 0x0 0x100>;
247 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
248 interrupt-names = "vip_mmu";
254 compatible = "rockchip,vopb_mmu";
255 reg = <0x0 0xff930300 0x0 0x100>;
256 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
257 interrupt-names = "vop_mmu";
263 compatible = "rockchip,isp_mmu";
264 reg = <0x0 0xff914000 0x0 0x100>,
265 <0x0 0xff915000 0x0 0x100>;
266 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
267 interrupt-names = "isp_mmu";
272 dbgname = "hdcp_mmu";
273 compatible = "rockchip,hdcp_mmu";
274 reg = <0x0 0xff940000 0x0 0x100>;
275 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "hdcp_mmu";
282 compatible = "rockchip,hevc_mmu";
283 reg = <0x0 0xff9a0440 0x0 0x40>,
284 <0x0 0xff9a0480 0x0 0x40>;
285 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
286 interrupt-names = "hevc_mmu";
292 compatible = "rockchip,vpu_mmu";
293 reg = <0x0 0xff9a0800 0x0 0x100>;
294 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-names = "vepu_mmu", "vdpu_mmu";
300 dwc_control_usb: dwc-control-usb {
301 compatible = "rockchip,rk3368-dwc-control-usb";
302 rockchip,grf = <&grf>;
303 grf-offset = <0x04bc>; /* GRF_SOC_STATUS for USB2.0 OTG */
304 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
308 interrupt-names = "otg_id", "otg_bvalid",
309 "otg_linestate", "host0_linestate";
310 clocks = <&cru HCLK_USB_PERI>;
311 clock-names = "hclk_usb_peri";
315 compatible = "inno,phy";
316 regbase = &dwc_control_usb;
317 rk_usb,bvalid = <0x4bc 23 1>;
318 rk_usb,iddig = <0x4bc 26 1>;
319 rk_usb,vdmsrcen = <0x718 12 1>;
320 rk_usb,vdpsrcen = <0x718 11 1>;
321 rk_usb,rdmpden = <0x718 10 1>;
322 rk_usb,idpsrcen = <0x718 9 1>;
323 rk_usb,idmsinken = <0x718 8 1>;
324 rk_usb,idpsinken = <0x718 7 1>;
325 rk_usb,dpattach = <0x4b8 31 1>;
326 rk_usb,cpdet = <0x4b8 30 1>;
327 rk_usb,dcpattach = <0x4b8 29 1>;
333 hdmii2c_xfer: hdmii2c-xfer {
334 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
335 <3 27 RK_FUNC_1 &pcfg_pull_none>;
341 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
346 i2c5_gpio: i2c5-gpio {
347 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
348 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
353 lcdc_lcdc: lcdc-lcdc {
355 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
356 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
357 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
358 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
359 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
360 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
361 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
362 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
363 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
364 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
365 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
366 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
367 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
368 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
369 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
370 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
371 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
372 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
375 lcdc_gpio: lcdc-gpio {
377 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
378 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
379 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
380 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
381 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
382 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
383 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
384 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
385 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
386 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
387 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
388 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
389 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
390 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
391 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
392 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
393 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
394 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
399 cif_clkout: cif-clkout {
400 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
403 isp_dvp_d2d9: isp-dvp-d2d9 {
405 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
406 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
407 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
408 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
409 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
410 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
411 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
412 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
413 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
414 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
415 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
416 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
419 isp_dvp_d0d1: isp-dvp-d0d1 {
421 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
422 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
425 isp_dvp_d10d11:isp_d10d11 {
427 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
428 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
431 isp_dvp_d0d7: isp-dvp-d0d7 {
433 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
434 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
435 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
436 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
437 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
438 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
439 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
440 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
443 isp_dvp_d4d11: isp-dvp-d4d11 {
445 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
446 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
447 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
448 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
449 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
450 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
451 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
452 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
455 isp_shutter: isp-shutter {
457 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
458 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
461 isp_flash_trigger: isp-flash-trigger {
462 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
465 isp_prelight: isp-prelight {
466 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
469 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
470 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
477 clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>;
478 clock-names = "sclk_otgphy0", "otg";
479 resets = <&cru SRST_USBOTG_AHB>,
480 <&cru SRST_USBOTG_PHY>,
481 <&cru SRST_USBOTG_CON>;
482 reset-names = "otg_ahb", "otg_phy", "otg_controller";
483 /* 0 - Normal, 1 - Force Host, 2 - Force Device */
484 rockchip,usb-mode = <0>;