2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/display/rk_fb.h>
44 #include <dt-bindings/display/mipi_dsi.h>
52 compatible = "rockchip,rk3368-isp", "rockchip,isp";
53 reg = <0x0 0xff910000 0x0 0x10000>;
54 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
55 /*power-domains = <&power PD_VIO>;*/
57 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
58 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
59 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
60 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
62 "aclk_isp", "hclk_isp", "clk_isp",
63 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
64 "clk_cif_pll", "hclk_mipiphy1",
65 "pclk_dphyrx", "clk_vio0_noc";
67 "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
68 "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
69 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
70 "isp_flash_as_trigger_out";
71 pinctrl-0 = <&cif_clkout>;
72 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
73 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
74 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
75 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
76 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
77 pinctrl-6 = <&cif_clkout>;
78 pinctrl-7 = <&cif_clkout &isp_prelight>;
79 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
80 pinctrl-9 = <&isp_flash_trigger>;
81 rockchip,isp,mipiphy = <2>;
82 rockchip,isp,cifphy = <1>;
83 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
84 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
85 rockchip,grf = <&grf>;
86 rockchip,cru = <&cru>;
87 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
88 rockchip,isp,iommu_enable = <1>;
93 compatible = "rockchip,rga2";
95 reg = <0x0 0xff920000 0x0 0x1000>;
96 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
97 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
98 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
103 compatible = "rockchip,rk-fb";
104 rockchip,disp-mode = <NO_DUAL>;
109 compatible = "rockchip,screen";
113 lcdc: lcdc@ff930000 {
114 compatible = "rockchip,rk3368-lcdc";
115 rockchip,grf = <&grf>;
116 rockchip,pmugrf = <&pmugrf>;
117 rockchip,cru = <&cru>;
118 rockchip,prop = <PRMRY>;
119 rockchip,pwr18 = <0>;
120 rockchip,iommu-enabled = <1>;
121 reg = <0x0 0xff930000 0x0 0x10000>;
122 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
124 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
125 /*power-domains = <&power PD_VIO>;*/
126 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
127 reset-names = "axi", "ahb", "dclk";
131 mipi: mipi@ff960000 {
132 compatible = "rockchip,rk3368-dsi";
134 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
135 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
136 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
138 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
139 /*power-domains = <&power PD_VIO>;*/
143 lvds: lvds@ff968000 {
144 compatible = "rockchip,rk3368-lvds";
145 rockchip,grf = <&grf>;
146 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
147 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
148 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
149 clock-names = "pclk_lvds", "pclk_lvds_ctl";
150 /*power-domains = <&power PD_VIO>;*/
155 compatible = "rockchip,rk32-edp";
156 reg = <0x0 0xff970000 0x0 0x4000>;
157 rockchip,grf = <&grf>;
158 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
160 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
161 /*power-domains = <&power PD_VIO>;*/
162 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
163 reset-names = "edp_24m", "edp_apb";
167 hdmi: hdmi@ff980000 {
168 compatible = "rockchip,rk3368-hdmi";
169 reg = <0x0 0xff980000 0x0 0x20000>;
170 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&cru PCLK_HDMI_CTRL>,
172 <&cru SCLK_HDMI_HDCP>,
173 <&cru SCLK_HDMI_CEC>;
174 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
175 /*power-domains = <&power PD_VIO>;*/
176 resets = <&cru SRST_HDMI>;
177 reset-names = "hdmi";
178 pinctrl-names = "default", "gpio";
179 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
180 pinctrl-1 = <&i2c5_gpio>;
186 compatible = "rockchip,iep_mmu";
187 reg = <0x0 0xff900800 0x0 0x100>;
188 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
189 interrupt-names = "iep_mmu";
195 compatible = "rockchip,vip_mmu";
196 reg = <0x0 0xff950800 0x0 0x100>;
197 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
198 interrupt-names = "vip_mmu";
204 compatible = "rockchip,vopb_mmu";
205 reg = <0x0 0xff930300 0x0 0x100>;
206 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
207 interrupt-names = "vop_mmu";
213 compatible = "rockchip,isp_mmu";
214 reg = <0x0 0xff914000 0x0 0x100>,
215 <0x0 0xff915000 0x0 0x100>;
216 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
217 interrupt-names = "isp_mmu";
222 dbgname = "hdcp_mmu";
223 compatible = "rockchip,hdcp_mmu";
224 reg = <0x0 0xff940000 0x0 0x100>;
225 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
226 interrupt-names = "hdcp_mmu";
232 compatible = "rockchip,hevc_mmu";
233 reg = <0x0 0xff9a0440 0x0 0x40>,
234 <0x0 0xff9a0480 0x0 0x40>;
235 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-names = "hevc_mmu";
242 compatible = "rockchip,vpu_mmu";
243 reg = <0x0 0xff9a0800 0x0 0x100>;
244 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
246 interrupt-names = "vepu_mmu", "vdpu_mmu";
252 hdmii2c_xfer: hdmii2c-xfer {
253 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
254 <3 27 RK_FUNC_1 &pcfg_pull_none>;
260 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
265 i2c5_gpio: i2c5-gpio {
266 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
267 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
272 lcdc_lcdc: lcdc-lcdc {
274 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
275 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
276 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
277 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
278 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
279 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
280 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
281 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
282 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
283 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
284 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
285 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
286 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
287 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
288 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
289 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
290 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
291 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
294 lcdc_gpio: lcdc-gpio {
296 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
297 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
298 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
299 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
300 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
301 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
302 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
303 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
304 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
305 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
306 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
307 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
308 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
309 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
310 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
311 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
312 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
313 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
318 cif_clkout: cif-clkout {
319 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
322 isp_dvp_d2d9: isp-dvp-d2d9 {
324 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
325 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
326 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
327 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
328 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
329 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
330 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
331 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
332 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
333 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
334 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
335 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
338 isp_dvp_d0d1: isp-dvp-d0d1 {
340 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
341 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
344 isp_dvp_d10d11:isp_d10d11 {
346 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
347 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
350 isp_dvp_d0d7: isp-dvp-d0d7 {
352 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
353 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
354 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
355 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
356 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
357 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
358 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
359 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
362 isp_dvp_d4d11: isp-dvp-d4d11 {
364 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
365 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
366 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
367 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
368 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
369 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
370 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
371 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
374 isp_shutter: isp-shutter {
376 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
377 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
380 isp_flash_trigger: isp-flash-trigger {
381 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
384 isp_prelight: isp-prelight {
385 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
388 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
389 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU