arch/arm64/boot/dts/rockchip/rk3368-android.dtsi

   1 /*
   2  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 / {
  44         chosen {
  45                 bootargs = "earlycon=uart8250,mmio32,0xff690000 swiotlb=1 firmware_class.path=/system/vendor/firmware";
  46         };
  47
  48         fiq_debugger: fiq-debugger {
  49                 compatible = "rockchip,fiq-debugger";
  50                 rockchip,serial-id = <2>;
  51                 rockchip,signal-irq = <186>;
  52                 rockchip,wake-irq = <0>;
  53                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
  54                 rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
  55                 pinctrl-names = "default";
  56                 pinctrl-0 = <&uart2_xfer>;
  57         };
  58
  59         reserved-memory {
  60                 #address-cells = <2>;
  61                 #size-cells = <2>;
  62                 ranges;
  63
  64                 /* global autoconfigured region for contiguous allocations */
  65                 linux,cma {
  66                         compatible = "shared-dma-pool";
  67                         reusable;
  68                         size = <0x0 0x8000000>;
  69                         linux,cma-default;
  70                 };
  71
  72                 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
  73                 rockchip_logo: rockchip-logo@00000000 {
  74                         compatible = "rockchip,drm-logo";
  75                         reg = <0x0 0x0 0x0 0x0>;
  76                 };
  77         };
  78
  79         ion {
  80                 compatible = "rockchip,ion";
  81                 #address-cells = <1>;
  82                 #size-cells = <0>;
  83
  84                 cma-heap {
  85                         reg = <0x00000000 0x02000000>;
  86                 };
  87
  88                 system-heap {
  89                 };
  90         };
  91
  92         isp: isp@ff910000 {
  93                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
  94                 reg = <0x0 0xff910000 0x0 0x10000>;
  95                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  96                 power-domains = <&power RK3368_PD_VIO>;
  97                 clocks =
  98                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
  99                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
 100                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
 101                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
 102                 clock-names =
 103                         "aclk_isp", "hclk_isp", "clk_isp",
 104                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
 105                         "clk_cif_pll", "hclk_mipiphy1",
 106                         "pclk_dphyrx", "clk_vio0_noc";
 107                 pinctrl-names =
 108                         "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
 109                         "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
 110                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 111                         "isp_flash_as_trigger_out";
 112                 pinctrl-0 = <&cif_clkout>;
 113                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
 114                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
 115                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
 116                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
 117                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
 118                 pinctrl-6 = <&cif_clkout>;
 119                 pinctrl-7 = <&cif_clkout &isp_prelight>;
 120                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
 121                 pinctrl-9 = <&isp_flash_trigger>;
 122                 rockchip,isp,mipiphy = <2>;
 123                 rockchip,isp,cifphy = <1>;
 124                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
 125                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
 126                 rockchip,grf = <&grf>;
 127                 rockchip,cru = <&cru>;
 128                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 129                 rockchip,isp,iommu_enable = <1>;
 130                 status = "disabled";
 131         };
 132
 133         rga@ff920000 {
 134                 compatible = "rockchip,rga2";
 135                 dev_mode = <1>;
 136                 reg = <0x0 0xff920000 0x0 0x1000>;
 137                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 138                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 139                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 140                 status = "disabled";
 141         };
 142
 143         hdmi: hdmi@ff980000 {
 144                 compatible = "rockchip,rk3368-hdmi";
 145                 reg = <0x0 0xff980000 0x0 0x20000>;
 146                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 147                 clocks = <&cru PCLK_HDMI_CTRL>,
 148                          <&cru SCLK_HDMI_HDCP>,
 149                          <&cru SCLK_HDMI_CEC>;
 150                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 151                 power-domains = <&power RK3368_PD_VIO>;
 152                 resets = <&cru SRST_HDMI>;
 153                 reset-names = "hdmi";
 154                 pinctrl-names = "default", "gpio";
 155                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 156                 pinctrl-1 = <&i2c5_gpio>;
 157                 status = "okay";
 158         };
 159
 160         dwc_control_usb: dwc-control-usb {
 161                 compatible = "rockchip,rk3368-dwc-control-usb";
 162                 status = "okay";
 163
 164                 rockchip,grf = <&grf>;
 165                 grf-offset = <0x04bc>; /* GRF_SOC_STATUS for USB2.0 OTG */
 166                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 170                 interrupt-names = "otg_id", "otg_bvalid",
 171                                   "otg_linestate", "host0_linestate";
 172                 clocks = <&cru HCLK_USB_PERI>;
 173                 clock-names = "hclk_usb_peri";
 174
 175                 otg_drv_gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
 176                 rockchip,remote_wakeup;
 177                 rockchip,usb_irq_wakeup;
 178
 179                 usb_bc {
 180                         compatible = "inno,phy";
 181                         regbase = &dwc_control_usb;
 182                         rk_usb,bvalid     = <0x4bc 23 1>;
 183                         rk_usb,iddig      = <0x4bc 26 1>;
 184                         rk_usb,vdmsrcen   = <0x718 12 1>;
 185                         rk_usb,vdpsrcen   = <0x718 11 1>;
 186                         rk_usb,rdmpden    = <0x718 10 1>;
 187                         rk_usb,idpsrcen   = <0x718  9 1>;
 188                         rk_usb,idmsinken  = <0x718  8 1>;
 189                         rk_usb,idpsinken  = <0x718  7 1>;
 190                         rk_usb,dpattach   = <0x4b8 31 1>;
 191                         rk_usb,cpdet      = <0x4b8 30 1>;
 192                         rk_usb,dcpattach  = <0x4b8 29 1>;
 193                 };
 194         };
 195 };
 196
 197 &display_subsystem {
 198         status = "okay";
 199 };
 200
 201 &vop {
 202         status = "okay";
 203 };
 204
 205 &vop_mmu {
 206         status = "okay";
 207 };
 208
 209 &usb_otg {
 210         status = "okay";
 211         clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>;
 212         clock-names = "sclk_otgphy0", "otg";
 213         resets = <&cru SRST_USBOTG_AHB>,
 214                  <&cru SRST_USBOTG_PHY>,
 215                  <&cru SRST_USBOTG_CON>;
 216         reset-names = "otg_ahb", "otg_phy", "otg_controller";
 217         /* 0 - Normal, 1 - Force Host, 2 - Force Device */
 218         rockchip,usb-mode = <0>;
 219 };
 220
 221 &pinctrl {
 222         hdmi_i2c {
 223                 hdmii2c_xfer: hdmii2c-xfer {
 224                         rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
 225                                         <3 27 RK_FUNC_1 &pcfg_pull_none>;
 226                 };
 227         };
 228
 229         hdmi_pin {
 230                 hdmi_cec: hdmi-cec {
 231                         rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
 232                 };
 233         };
 234
 235         i2c5 {
 236                 i2c5_gpio: i2c5-gpio {
 237                         rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
 238                                         <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
 239                 };
 240         };
 241
 242         isp {
 243                 cif_clkout: cif-clkout {
 244                         rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
 245                 };
 246
 247                 isp_dvp_d2d9: isp-dvp-d2d9 {
 248                         rockchip,pins =
 249                                         <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
 250                                         <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
 251                                         <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
 252                                         <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
 253                                         <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
 254                                         <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
 255                                         <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
 256                                         <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
 257                                         <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
 258                                         <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
 259                                         <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
 260                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
 261                 };
 262
 263                 isp_dvp_d0d1: isp-dvp-d0d1 {
 264                         rockchip,pins =
 265                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
 266                                         <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
 267                 };
 268
 269                 isp_dvp_d10d11:isp_d10d11 {
 270                         rockchip,pins =
 271                                         <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
 272                                         <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
 273                 };
 274
 275                 isp_dvp_d0d7: isp-dvp-d0d7 {
 276                         rockchip,pins =
 277                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
 278                                         <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
 279                                         <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
 280                                         <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
 281                                         <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
 282                                         <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
 283                                         <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
 284                                         <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
 285                 };
 286
 287                 isp_dvp_d4d11: isp-dvp-d4d11 {
 288                         rockchip,pins =
 289                                         <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
 290                                         <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
 291                                         <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
 292                                         <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
 293                                         <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
 294                                         <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
 295                                         <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
 296                                         <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
 297                 };
 298
 299                 isp_shutter: isp-shutter {
 300                         rockchip,pins =
 301                                         <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
 302                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
 303                 };
 304
 305                 isp_flash_trigger: isp-flash-trigger {
 306                         rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
 307                 };
 308
 309                 isp_prelight: isp-prelight {
 310                         rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
 311                 };
 312
 313                 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
 314                         rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
 315                 };
 316         };
 317 };