arch/arm64/boot/dts/rockchip/rk3368-android.dtsi

   1 /*
   2  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/display/rk_fb.h>
  44 #include <dt-bindings/display/mipi_dsi.h>
  45
  46 / {
  47         aliases {
  48                 lcdc = &lcdc;
  49         };
  50
  51         chosen {
  52                 bootargs = "earlycon=uart8250,mmio32,0xff690000 swiotlb=1";
  53         };
  54
  55         fiq_debugger: fiq-debugger {
  56                 compatible = "rockchip,fiq-debugger";
  57                 rockchip,serial-id = <2>;
  58                 rockchip,signal-irq = <186>;
  59                 rockchip,wake-irq = <0>;
  60                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
  61                 rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
  62                 pinctrl-names = "default";
  63                 pinctrl-0 = <&uart2_xfer>;
  64         };
  65
  66         reserved-memory {
  67                 #address-cells = <2>;
  68                 #size-cells = <2>;
  69                 ranges;
  70
  71                 /* global autoconfigured region for contiguous allocations */
  72                 linux,cma {
  73                         compatible = "shared-dma-pool";
  74                         reusable;
  75                         size = <0x0 0x8000000>;
  76                         linux,cma-default;
  77                 };
  78
  79                 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
  80                 rockchip_logo: rockchip-logo@00000000 {
  81                         compatible = "rockchip,fb-logo";
  82                         reg = <0x0 0x0 0x0 0x0>;
  83                 };
  84         };
  85
  86         ion {
  87                 compatible = "rockchip,ion";
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90
  91                 cma-heap {
  92                         reg = <0x00000000 0x02000000>;
  93                 };
  94
  95                 system-heap {
  96                 };
  97         };
  98
  99         isp: isp@ff910000 {
 100                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
 101                 reg = <0x0 0xff910000 0x0 0x10000>;
 102                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 103                 /*power-domains = <&power PD_VIO>;*/
 104                 clocks =
 105                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
 106                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
 107                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
 108                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
 109                 clock-names =
 110                         "aclk_isp", "hclk_isp", "clk_isp",
 111                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
 112                         "clk_cif_pll", "hclk_mipiphy1",
 113                         "pclk_dphyrx", "clk_vio0_noc";
 114                 pinctrl-names =
 115                         "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
 116                         "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
 117                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 118                         "isp_flash_as_trigger_out";
 119                 pinctrl-0 = <&cif_clkout>;
 120                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
 121                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
 122                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
 123                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
 124                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
 125                 pinctrl-6 = <&cif_clkout>;
 126                 pinctrl-7 = <&cif_clkout &isp_prelight>;
 127                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
 128                 pinctrl-9 = <&isp_flash_trigger>;
 129                 rockchip,isp,mipiphy = <2>;
 130                 rockchip,isp,cifphy = <1>;
 131                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
 132                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
 133                 rockchip,grf = <&grf>;
 134                 rockchip,cru = <&cru>;
 135                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 136                 rockchip,isp,iommu_enable = <1>;
 137                 status = "disabled";
 138         };
 139
 140         rga: rga@ff920000 {
 141                 compatible = "rockchip,rga2";
 142                 dev_mode = <1>;
 143                 reg = <0x0 0xff920000 0x0 0x1000>;
 144                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 145                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 146                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 147                 status = "disabled";
 148         };
 149
 150         fb: fb {
 151                 compatible = "rockchip,rk-fb";
 152                 rockchip,disp-mode = <NO_DUAL>;
 153                 status = "disabled";
 154         };
 155
 156         rk_screen: screen {
 157                 compatible = "rockchip,screen";
 158                 status = "disabled";
 159         };
 160
 161         lcdc: lcdc@ff930000 {
 162                 compatible = "rockchip,rk3368-lcdc";
 163                 rockchip,grf = <&grf>;
 164                 rockchip,pmugrf = <&pmugrf>;
 165                 rockchip,cru = <&cru>;
 166                 rockchip,prop = <PRMRY>;
 167                 rockchip,pwr18 = <0>;
 168                 rockchip,iommu-enabled = <1>;
 169                 reg = <0x0 0xff930000 0x0 0x10000>;
 170                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 171                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
 172                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 173                 /*power-domains = <&power PD_VIO>;*/
 174                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 175                 reset-names = "axi", "ahb", "dclk";
 176                 status = "disabled";
 177         };
 178
 179         mipi: mipi@ff960000 {
 180                 compatible = "rockchip,rk3368-dsi";
 181                 rockchip,prop = <0>;
 182                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 183                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 184                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 185                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
 186                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 187                 /*power-domains = <&power PD_VIO>;*/
 188                 status = "disabled";
 189         };
 190
 191         lvds: lvds@ff968000 {
 192                 compatible = "rockchip,rk3368-lvds";
 193                 rockchip,grf = <&grf>;
 194                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 195                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 196                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
 197                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 198                 /*power-domains = <&power PD_VIO>;*/
 199                 status = "disabled";
 200         };
 201
 202         edp: edp@ff970000 {
 203                 compatible = "rockchip,rk32-edp";
 204                 reg = <0x0 0xff970000 0x0 0x4000>;
 205                 rockchip,grf = <&grf>;
 206                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 207                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
 208                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 209                 /*power-domains = <&power PD_VIO>;*/
 210                 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
 211                 reset-names = "edp_24m", "edp_apb";
 212                 status = "disabled";
 213         };
 214
 215         hdmi: hdmi@ff980000 {
 216                 compatible = "rockchip,rk3368-hdmi";
 217                 reg = <0x0 0xff980000 0x0 0x20000>;
 218                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&cru PCLK_HDMI_CTRL>,
 220                          <&cru SCLK_HDMI_HDCP>,
 221                          <&cru SCLK_HDMI_CEC>;
 222                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 223                 /*power-domains = <&power PD_VIO>;*/
 224                 resets = <&cru SRST_HDMI>;
 225                 reset-names = "hdmi";
 226                 pinctrl-names = "default", "gpio";
 227                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 228                 pinctrl-1 = <&i2c5_gpio>;
 229                 status = "disabled";
 230         };
 231
 232         iep_mmu: iep-mmu {
 233                 dbgname = "iep";
 234                 compatible = "rockchip,iep_mmu";
 235                 reg = <0x0 0xff900800 0x0 0x100>;
 236                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 237                 interrupt-names = "iep_mmu";
 238                 status = "disabled";
 239         };
 240
 241         vip_mmu: vip-mmu {
 242                 dbgname = "vip";
 243                 compatible = "rockchip,vip_mmu";
 244                 reg = <0x0 0xff950800 0x0 0x100>;
 245                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 246                 interrupt-names = "vip_mmu";
 247                 status = "disabled";
 248         };
 249
 250         vopb_mmu: vopb-mmu {
 251                 dbgname = "vop";
 252                 compatible = "rockchip,vopb_mmu";
 253                 reg = <0x0 0xff930300 0x0 0x100>;
 254                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 255                 interrupt-names = "vop_mmu";
 256                 status = "disabled";
 257         };
 258
 259         isp_mmu: isp-mmu {
 260                 dbgname = "isp_mmu";
 261                 compatible = "rockchip,isp_mmu";
 262                 reg = <0x0 0xff914000 0x0 0x100>,
 263                       <0x0 0xff915000 0x0 0x100>;
 264                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 265                 interrupt-names = "isp_mmu";
 266                 status = "disabled";
 267         };
 268
 269         hdcp_mmu: hdcp-mmu {
 270                  dbgname = "hdcp_mmu";
 271                  compatible = "rockchip,hdcp_mmu";
 272                  reg = <0x0 0xff940000 0x0 0x100>;
 273                  interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 274                  interrupt-names = "hdcp_mmu";
 275                 status = "disabled";
 276         };
 277
 278         hevc_mmu: hevc-mmu {
 279                 dbgname = "hevc";
 280                 compatible = "rockchip,hevc_mmu";
 281                 reg = <0x0 0xff9a0440 0x0 0x40>,
 282                       <0x0 0xff9a0480 0x0 0x40>;
 283                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 284                 interrupt-names = "hevc_mmu";
 285                 status = "disabled";
 286         };
 287
 288         vpu_mmu: vpu-mmu {
 289                 dbgname = "vpu";
 290                 compatible = "rockchip,vpu_mmu";
 291                 reg = <0x0 0xff9a0800 0x0 0x100>;
 292                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 294                 interrupt-names = "vepu_mmu", "vdpu_mmu";
 295                 status = "disabled";
 296         };
 297
 298         pinctrl {
 299                 hdmi_i2c {
 300                         hdmii2c_xfer: hdmii2c-xfer {
 301                                 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
 302                                                 <3 27 RK_FUNC_1 &pcfg_pull_none>;
 303                         };
 304                 };
 305
 306                 hdmi_pin {
 307                         hdmi_cec: hdmi-cec {
 308                                 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
 309                         };
 310                 };
 311
 312                 i2c5 {
 313                         i2c5_gpio: i2c5-gpio {
 314                                 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
 315                                                 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
 316                         };
 317                 };
 318
 319                 lcdc {
 320                         lcdc_lcdc: lcdc-lcdc {
 321                                 rockchip,pins =
 322                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
 323                                                 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
 324                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
 325                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
 326                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
 327                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
 328                                                 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
 329                                                 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
 330                                                 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
 331                                                 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
 332                                                 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
 333                                                 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
 334                                                 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
 335                                                 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
 336                                                 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
 337                                                 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
 338                                                 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
 339                                                 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
 340                         };
 341
 342                         lcdc_gpio: lcdc-gpio {
 343                                 rockchip,pins =
 344                                                 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
 345                                                 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
 346                                                 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
 347                                                 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
 348                                                 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
 349                                                 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
 350                                                 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
 351                                                 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
 352                                                 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
 353                                                 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
 354                                                 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
 355                                                 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
 356                                                 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
 357                                                 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
 358                                                 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
 359                                                 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
 360                                                 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
 361                                                 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
 362                         };
 363                 };
 364
 365                 isp {
 366                         cif_clkout: cif-clkout {
 367                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
 368                         };
 369
 370                         isp_dvp_d2d9: isp-dvp-d2d9 {
 371                                 rockchip,pins =
 372                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
 373                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
 374                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
 375                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
 376                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
 377                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
 378                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
 379                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
 380                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
 381                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
 382                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
 383                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
 384                         };
 385
 386                         isp_dvp_d0d1: isp-dvp-d0d1 {
 387                                 rockchip,pins =
 388                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
 389                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
 390                         };
 391
 392                         isp_dvp_d10d11:isp_d10d11 {
 393                                 rockchip,pins =
 394                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
 395                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
 396                         };
 397
 398                         isp_dvp_d0d7: isp-dvp-d0d7 {
 399                                 rockchip,pins =
 400                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
 401                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
 402                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
 403                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
 404                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
 405                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
 406                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
 407                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
 408                         };
 409
 410                         isp_dvp_d4d11: isp-dvp-d4d11 {
 411                                 rockchip,pins =
 412                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
 413                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
 414                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
 415                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
 416                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
 417                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
 418                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
 419                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
 420                         };
 421
 422                         isp_shutter: isp-shutter {
 423                                 rockchip,pins =
 424                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
 425                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
 426                         };
 427
 428                         isp_flash_trigger: isp-flash-trigger {
 429                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
 430                         };
 431
 432                         isp_prelight: isp-prelight {
 433                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
 434                         };
 435
 436                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
 437                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
 438                         };
 439                 };
 440         };
 441 };