arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/power/rk3366-power.h>
  50 #include <dt-bindings/soc/rockchip_boot-mode.h>
  51
  52 / {
  53         compatible = "rockchip,rk3366";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 serial0 = &uart0;
  66                 serial2 = &uart2;
  67                 serial3 = &uart3;
  68                 spi0 = &spi0;
  69                 spi1 = &spi1;
  70         };
  71
  72         cpus {
  73                 #address-cells = <0x2>;
  74                 #size-cells = <0x0>;
  75
  76                 cpu0: cpu@0 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53","arm,armv8";
  79                         reg = <0x0 0x0>;
  80                         enable-method = "psci";
  81                         clocks = <&cru ARMCLK>;
  82                         operating-points-v2 = <&cpu0_opp_table>;
  83                 };
  84
  85                 cpu1: cpu@1 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a53","arm,armv8";
  88                         reg = <0x0 0x1>;
  89                         enable-method = "psci";
  90                         operating-points-v2 = <&cpu0_opp_table>;
  91                 };
  92
  93                 cpu2: cpu@2 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53","arm,armv8";
  96                         reg = <0x0 0x2>;
  97                         enable-method = "psci";
  98                         operating-points-v2 = <&cpu0_opp_table>;
  99                 };
 100
 101                 cpu3: cpu@3 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53","arm,armv8";
 104                         reg = <0x0 0x3>;
 105                         enable-method = "psci";
 106                         operating-points-v2 = <&cpu0_opp_table>;
 107                 };
 108         };
 109
 110         cpu0_opp_table: opp_table0 {
 111                 compatible = "operating-points-v2";
 112                 opp-shared;
 113
 114                 opp00 {
 115                         opp-hz = /bits/ 64 <408000000>;
 116                         opp-microvolt = <1200000>;
 117                         clock-latency-ns = <40000>;
 118                         opp-suspend;
 119                 };
 120                 opp01 {
 121                         opp-hz = /bits/ 64 <600000000>;
 122                         opp-microvolt = <1200000>;
 123                 };
 124                 opp02 {
 125                         opp-hz = /bits/ 64 <816000000>;
 126                         opp-microvolt = <1200000>;
 127                 };
 128                 opp03 {
 129                         opp-hz = /bits/ 64 <1008000000>;
 130                         opp-microvolt = <1200000>;
 131                 };
 132                 opp04 {
 133                         opp-hz = /bits/ 64 <1200000000>;
 134                         opp-microvolt = <1200000>;
 135                 };
 136         };
 137
 138         psci {
 139                 compatible = "arm,psci-1.0";
 140                 method = "smc";
 141         };
 142
 143         timer {
 144                 compatible = "arm,armv8-timer";
 145                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 146                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 147                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 148                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 149         };
 150
 151         xin24m: xin24m {
 152                 compatible = "fixed-clock";
 153                 #clock-cells = <0>;
 154                 clock-frequency = <24000000>;
 155                 clock-output-names = "xin24m";
 156         };
 157
 158         gic: interrupt-controller@ffb71000 {
 159                 compatible = "arm,gic-400";
 160                 interrupt-controller;
 161                 #interrupt-cells = <3>;
 162                 #address-cells = <0>;
 163
 164                 reg = <0x0 0xffb71000 0x0 0x1000>,
 165                       <0x0 0xffb72000 0x0 0x1000>,
 166                       <0x0 0xffb74000 0x0 0x2000>,
 167                       <0x0 0xffb76000 0x0 0x2000>;
 168                 interrupts = <GIC_PPI 9
 169                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 170         };
 171
 172         nandc0: nandc@ff0c0000 {
 173                 compatible = "rockchip,rk-nandc";
 174                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 175                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 176                 nandc_id = <0>;
 177                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 178                 clock-names = "clk_nandc", "hclk_nandc";
 179                 status = "disabled";
 180         };
 181
 182         saradc: saradc@ff100000 {
 183                 compatible = "rockchip,saradc";
 184                 reg = <0x0 0xff100000 0x0 0x100>;
 185                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 186                 #io-channel-cells = <1>;
 187                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 188                 clock-names = "saradc", "apb_pclk";
 189                 status = "disabled";
 190         };
 191
 192         spi0: spi@ff110000 {
 193                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 194                 reg = <0x0 0xff110000 0x0 0x1000>;
 195                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 196                 clock-names = "spiclk", "apb_pclk";
 197                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 198                 pinctrl-names = "default";
 199                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 200                 #address-cells = <1>;
 201                 #size-cells = <0>;
 202                 status = "disabled";
 203         };
 204
 205         spi1: spi@ff120000 {
 206                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 207                 reg = <0x0 0xff120000 0x0 0x1000>;
 208                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 209                 clock-names = "spiclk", "apb_pclk";
 210                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 213                 #address-cells = <1>;
 214                 #size-cells = <0>;
 215                 status = "disabled";
 216         };
 217
 218         sdmmc: rksdmmc@ff400000 {
 219                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 220                 clock-freq-min-max = <400000 150000000>;
 221                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 222                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 223                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 224                 fifo-depth = <0x100>;
 225                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 226                 reg = <0x0 0xff400000 0x0 0x4000>;
 227                 status = "disabled";
 228         };
 229
 230         sdio: rksdmmc@ff410000 {
 231                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 232                 clock-freq-min-max = <400000 150000000>;
 233                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 234                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 235                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 236                 fifo-depth = <0x100>;
 237                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 238                 reg = <0x0 0xff410000 0x0 0x4000>;
 239                 status = "disabled";
 240         };
 241
 242         emmc: rksdmmc@ff420000 {
 243                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 244                 clock-freq-min-max = <400000 150000000>;
 245                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 246                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 247                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 248                 fifo-depth = <0x100>;
 249                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 250                 reg = <0x0 0xff420000 0x0 0x4000>;
 251                 status = "disabled";
 252         };
 253
 254         gmac: eth@ff440000 {
 255                 compatible = "rockchip,rk3366-gmac";
 256                 reg = <0x0 0xff440000 0x0 0x10000>;
 257                 rockchip,grf = <&grf>;
 258                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 259                 interrupt-names = "macirq";
 260                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 261                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 262                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 263                          <&cru PCLK_GMAC>;
 264                 clock-names = "stmmaceth", "mac_clk_rx",
 265                               "mac_clk_tx", "clk_mac_ref",
 266                               "clk_mac_refout", "aclk_mac",
 267                               "pclk_mac";
 268                 resets = <&cru SRST_MAC>;
 269                 reset-names = "stmmaceth";
 270                 status = "disabled";
 271         };
 272
 273         i2c0: i2c@ff650000 {
 274                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 275                 reg = <0x0 0xff728000 0x0 0x1000>;
 276                 clocks = <&cru PCLK_I2C0>;
 277                 clock-names = "i2c";
 278                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&i2c0_xfer>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 status = "disabled";
 284         };
 285
 286         i2c2: i2c@ff140000 {
 287                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 288                 reg = <0x0 0xff140000 0x0 0x1000>;
 289                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 290                 #address-cells = <1>;
 291                 #size-cells = <0>;
 292                 clock-names = "i2c";
 293                 clocks = <&cru PCLK_I2C2>;
 294                 pinctrl-names = "default";
 295                 pinctrl-0 = <&i2c2_xfer>;
 296                 status = "disabled";
 297         };
 298
 299         i2c3: i2c@ff150000 {
 300                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 301                 reg = <0x0 0xff150000 0x0 0x1000>;
 302                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 clock-names = "i2c";
 306                 clocks = <&cru PCLK_I2C3>;
 307                 pinctrl-names = "default";
 308                 pinctrl-0 = <&i2c3_xfer>;
 309                 status = "disabled";
 310         };
 311
 312         i2c4: i2c@ff160000 {
 313                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 314                 reg = <0x0 0xff160000 0x0 0x1000>;
 315                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 clock-names = "i2c";
 319                 clocks = <&cru PCLK_I2C4>;
 320                 pinctrl-names = "default";
 321                 pinctrl-0 = <&i2c4_xfer>;
 322                 status = "disabled";
 323         };
 324
 325         i2c5: i2c@ff170000 {
 326                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 327                 reg = <0x0 0xff170000 0x0 0x1000>;
 328                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331                 clock-names = "i2c";
 332                 clocks = <&cru PCLK_I2C5>;
 333                 pinctrl-names = "default";
 334                 pinctrl-0 = <&i2c5_xfer>;
 335                 status = "disabled";
 336         };
 337
 338         uart0: serial@ff180000 {
 339                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 340                 reg = <0x0 0xff180000 0x0 0x100>;
 341                 clock-frequency = <24000000>;
 342                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 343                 clock-names = "baudclk", "apb_pclk";
 344                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 345                 reg-shift = <2>;
 346                 reg-io-width = <4>;
 347                 pinctrl-names = "default";
 348                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 349                 status = "disabled";
 350         };
 351
 352         uart3: serial@ff1b0000 {
 353                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 354                 reg = <0x0 0xff1b0000 0x0 0x100>;
 355                 clock-frequency = <24000000>;
 356                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 357                 clock-names = "baudclk", "apb_pclk";
 358                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 359                 reg-shift = <2>;
 360                 reg-io-width = <4>;
 361                 pinctrl-names = "default";
 362                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 363                 status = "disabled";
 364         };
 365
 366         usbphy: phy {
 367                 compatible = "rockchip,rk336x-usb-phy";
 368                 rockchip,grf = <&grf>;
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371
 372                 usbphy0: usb-phy0 {
 373                         #phy-cells = <0>;
 374                         #clock-cells = <0>;
 375                         reg = <0x700>;
 376                 };
 377
 378                 usbphy1: usb-phy1 {
 379                         #phy-cells = <0>;
 380                         #clock-cells = <0>;
 381                         reg = <0x728>;
 382                 };
 383         };
 384
 385         usb_host0_echi: usb@ff480000 {
 386                 compatible = "generic-ehci";
 387                 reg = <0x0 0xff480000 0x0 0x20000>;
 388                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 389                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 390                 clock-names = "sclk_otgphy0", "hclk_host0";
 391                 phys = <&usbphy1>;
 392                 phy-names = "usb";
 393                 status = "disabled";
 394         };
 395
 396         usb_host0_ohci: usb@ff4a0000 {
 397                 compatible = "generic-ohci";
 398                 reg = <0x0 0xff4a0000 0x0 0x20000>;
 399                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 400                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 401                 clock-names = "sclk_otgphy0", "hclk_host0";
 402                 status = "disabled";
 403         };
 404
 405         usb_otg: usb@ff4c0000 {
 406                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 407                              "snps,dwc2";
 408                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 409                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 410                 clocks = <&cru HCLK_OTG>;
 411                 clock-names = "otg";
 412                 dr_mode = "otg";
 413                 g-np-tx-fifo-size = <16>;
 414                 g-rx-fifo-size = <275>;
 415                 g-tx-fifo-size = <256 128 128 64 64 32>;
 416                 g-use-dma;
 417                 status = "disabled";
 418         };
 419
 420         i2c1: i2c@ff660000 {
 421                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 422                 reg = <0x0 0xff660000 0x0 0x1000>;
 423                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426                 clock-names = "i2c";
 427                 clocks = <&cru PCLK_I2C1>;
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&i2c1_xfer>;
 430                 status = "disabled";
 431         };
 432
 433         pwm0: pwm@ff680000 {
 434                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 435                 reg = <0x0 0xff680000 0x0 0x10>;
 436                 #pwm-cells = <3>;
 437                 pinctrl-names = "default";
 438                 pinctrl-0 = <&pwm0_pin>;
 439                 clocks = <&cru PCLK_RKPWM>;
 440                 clock-names = "pwm";
 441                 status = "disabled";
 442         };
 443
 444         pwm1: pwm@ff680010 {
 445                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 446                 reg = <0x0 0xff680010 0x0 0x10>;
 447                 #pwm-cells = <3>;
 448                 pinctrl-names = "default";
 449                 pinctrl-0 = <&pwm1_pin>;
 450                 clocks = <&cru PCLK_RKPWM>;
 451                 clock-names = "pwm";
 452                 status = "disabled";
 453         };
 454
 455         pwm2: pwm@ff680020 {
 456                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 457                 reg = <0x0 0xff680020 0x0 0x10>;
 458                 #pwm-cells = <3>;
 459                 clocks = <&cru PCLK_RKPWM>;
 460                 clock-names = "pwm";
 461                 status = "disabled";
 462         };
 463
 464         pwm3: pwm@ff680030 {
 465                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 466                 reg = <0x0 0xff680030 0x0 0x10>;
 467                 #pwm-cells = <3>;
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&pwm3_t2_pin>;
 470                 clocks = <&cru PCLK_RKPWM>;
 471                 clock-names = "pwm";
 472                 status = "disabled";
 473         };
 474
 475         uart2: serial@ff690000 {
 476                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 477                 reg = <0x0 0xff690000 0x0 0x100>;
 478                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 479                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 480                 clock-names = "baudclk", "apb_pclk";
 481                 reg-shift = <2>;
 482                 reg-io-width = <4>;
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&uart2_t1_xfer>;
 485                 status = "disabled";
 486         };
 487
 488         pmu: power-management@ff730000 {
 489                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 490                 reg = <0x0 0xff730000 0x0 0x1000>;
 491
 492                 power: power-controller {
 493                         status = "disabled";
 494                         compatible = "rockchip,rk3366-power-controller";
 495                         #power-domain-cells = <1>;
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498
 499                         /*
 500                          * Note: Although SCLK_* are the working clocks
 501                          * of device without including on the NOC, needed for
 502                          * synchronous reset.
 503                          *
 504                          * The clocks on the which NOC:
 505                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 506                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 507                          * ACLK_ISP is on ACLK_ISP_NIU.
 508                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 509                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 510                          *
 511                          * Which clock are device clocks:
 512                          *      clocks          devices
 513                          *      *_IEP           IEP:Image Enhancement Processor
 514                          *      *_ISP           ISP:Image Signal Processing
 515                          *      *_VOP*          VOP:Visual Output Processor
 516                          *      *_RGA           RGA
 517                          *      *_DPHY*         LVDS
 518                          *      *_HDMI          HDMI
 519                          *      *_MIPI_*        MIPI
 520                          */
 521                         pd_vio {
 522                                 reg = <RK3366_PD_VIO>;
 523                                 clocks = <&cru ACLK_IEP>,
 524                                          <&cru ACLK_ISP>,
 525                                          <&cru ACLK_RGA>,
 526                                          <&cru ACLK_HDCP>,
 527                                          <&cru ACLK_VOP_FULL>,
 528                                          <&cru ACLK_VOP_LITE>,
 529                                          <&cru ACLK_VOP_IEP>,
 530                                          <&cru DCLK_VOP_FULL>,
 531                                          <&cru DCLK_VOP_LITE>,
 532                                          <&cru HCLK_IEP>,
 533                                          <&cru HCLK_ISP>,
 534                                          <&cru HCLK_RGA>,
 535                                          <&cru HCLK_VOP_FULL>,
 536                                          <&cru HCLK_VOP_LITE>,
 537                                          <&cru HCLK_VIO_HDCPMMU>,
 538                                          <&cru PCLK_HDMI_CTRL>,
 539                                          <&cru PCLK_HDCP>,
 540                                          <&cru PCLK_MIPI_DSI0>,
 541                                          <&cru SCLK_VOP_FULL_PWM>,
 542                                          <&cru SCLK_HDCP>,
 543                                          <&cru SCLK_ISP>,
 544                                          <&cru SCLK_RGA>,
 545                                          <&cru SCLK_HDMI_CEC>,
 546                                          <&cru SCLK_HDMI_HDCP>;
 547                         };
 548
 549                         /*
 550                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 551                          * (video endecoder & decoder) clocks that on the
 552                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 553                          */
 554                         pd_vpu {
 555                                 reg = <RK3366_PD_VPU>;
 556                                 clocks = <&cru ACLK_VIDEO>,
 557                                          <&cru HCLK_VIDEO>;
 558                         };
 559
 560                         /*
 561                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 562                          * (video decoder) clocks that on the
 563                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 564                          */
 565                         pd_rkvdec {
 566                                 reg = <RK3366_PD_RKVDEC>;
 567                                 clocks = <&cru ACLK_RKVDEC>,
 568                                          <&cru HCLK_RKVDEC>;
 569                         };
 570
 571                         pd_video {
 572                                 reg = <RK3366_PD_VIDEO>;
 573                                 clocks = <&cru ACLK_VIDEO>,
 574                                          <&cru ACLK_RKVDEC>,
 575                                          <&cru HCLK_VIDEO>,
 576                                          <&cru HCLK_RKVDEC>,
 577                                          <&cru SCLK_HEVC_CABAC>,
 578                                          <&cru SCLK_HEVC_CORE>;
 579                         };
 580
 581                         /*
 582                          * Note: ACLK_GPU is the GPU clock,
 583                          * and on the ACLK_GPU_NIU (NOC).
 584                          */
 585                         pd_gpu {
 586                                 reg = <RK3366_PD_GPU>;
 587                                 clocks = <&cru ACLK_GPU>;
 588                         };
 589                 };
 590         };
 591
 592         pmugrf: syscon@ff738000 {
 593                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 594                 reg = <0x0 0xff738000 0x0 0x1000>;
 595
 596                 reboot-mode {
 597                         compatible = "syscon-reboot-mode";
 598                         offset = <0x200>;
 599                         mode-normal = <BOOT_NORMAL>;
 600                         mode-recovery = <BOOT_RECOVERY>;
 601                         mode-fastboot = <BOOT_FASTBOOT>;
 602                         mode-loader = <BOOT_LOADER>;
 603                 };
 604         };
 605
 606         amba {
 607                 compatible = "arm,amba-bus";
 608                 #address-cells = <2>;
 609                 #size-cells = <2>;
 610                 ranges;
 611
 612                 dmac_peri: dma-controller@ff250000 {
 613                         compatible = "arm,pl330", "arm,primecell";
 614                         reg = <0x0 0xff250000 0x0 0x4000>;
 615                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 616                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 617                         #dma-cells = <1>;
 618                         clocks = <&cru ACLK_DMAC_PERI>;
 619                         clock-names = "apb_pclk";
 620                 };
 621
 622                 dmac_bus: dma-controller@ff600000 {
 623                         compatible = "arm,pl330", "arm,primecell";
 624                         reg = <0x0 0xff600000 0x0 0x4000>;
 625                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 626                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 627                         #dma-cells = <1>;
 628                         clocks = <&cru ACLK_DMAC_BUS>;
 629                         clock-names = "apb_pclk";
 630                 };
 631         };
 632
 633         cru: clock-controller@ff760000 {
 634                 compatible = "rockchip,rk3366-cru";
 635                 reg = <0x0 0xff760000 0x0 0x1000>;
 636                 rockchip,grf = <&grf>;
 637                 #clock-cells = <1>;
 638                 #reset-cells = <1>;
 639                 assigned-clocks =
 640                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 641                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 642                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 643                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 644                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
 645                 assigned-clock-rates =
 646                         <750000000>, <576000000>,
 647                         <594000000>, <594000000>,
 648                         <960000000>, <520000000>,
 649                         <375000000>, <288000000>,
 650                         <100000000>, <100000000>;
 651         };
 652
 653         grf: syscon@ff770000 {
 654                 compatible = "rockchip,rk3366-grf", "syscon";
 655                 reg = <0x0 0xff770000 0x0 0x1000>;
 656         };
 657
 658         wdt: watchdog@ff800000 {
 659                 compatible = "snps,dw-wdt";
 660                 reg = <0x0 0xff800000 0x0 0x100>;
 661                 clocks = <&cru PCLK_WDT>;
 662                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 663                 status = "disabled";
 664         };
 665
 666         spdif: spdif@ff880000 {
 667                 compatible = "rockchip,rk3366-spdif";
 668                 reg = <0x0 0xff880000 0x0 0x1000>;
 669                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 670                 dmas = <&dmac_bus 3>;
 671                 dma-names = "tx";
 672                 clock-names = "hclk", "mclk";
 673                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 674                 pinctrl-names = "default";
 675                 pinctrl-0 = <&spdif_bus>;
 676                 status = "disabled";
 677         };
 678
 679         i2s_2ch: i2s-2ch@ff890000 {
 680                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 681                 reg = <0x0 0xff890000 0x0 0x1000>;
 682                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 683                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 684                 dma-names = "tx", "rx";
 685                 clock-names = "i2s_hclk", "i2s_clk";
 686                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 687                 status = "disabled";
 688         };
 689
 690         i2s_8ch: i2s-8ch@ff898000 {
 691                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 692                 reg = <0x0 0xff898000 0x0 0x1000>;
 693                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 694                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 695                 dma-names = "tx", "rx";
 696                 clock-names = "i2s_hclk", "i2s_clk";
 697                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 698                 pinctrl-names = "default";
 699                 pinctrl-0 = <&i2s_8ch_bus>;
 700                 status = "disabled";
 701         };
 702
 703         fb: fb {
 704                 compatible = "rockchip,rk-fb";
 705                 rockchip,disp-mode = <DUAL>;
 706                 status = "disabled";
 707         };
 708
 709         rk_screen: screen {
 710                 compatible = "rockchip,screen";
 711                 status = "disabled";
 712         };
 713
 714         vop_lite: vop@ff8f0000 {
 715                 compatible = "rockchip,rk3366-lcdc-lite";
 716                 rockchip,grf = <&grf>;
 717                 rockchip,pwr18 = <0>;
 718                 rockchip,iommu-enabled = <1>;
 719                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 720                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 721                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 722                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 723                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 724                 reset-names = "axi", "ahb", "dclk";
 725                 status = "disabled";
 726         };
 727
 728         vopl_mmu: vopl-mmu {
 729                 dbgname = "vop";
 730                 compatible = "rockchip,vopl_mmu";
 731                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 732                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 733                 interrupt-names = "vopl_mmu";
 734                 status = "disabled";
 735         };
 736
 737         iep: iep@ff900000 {
 738                 compatible = "rockchip,iep";
 739                 iommu_enabled = <1>;
 740                 reg = <0x0 0xff900000 0x0 0x800>;
 741                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 742                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 743                 clock-names = "aclk_iep", "hclk_iep";
 744                 version = <2>;
 745                 status = "disabled";
 746         };
 747
 748         rga: rga@ff920000 {
 749                 compatible = "rockchip,rga2";
 750                 dev_mode = <1>;
 751                 reg = <0x0 0xff920000 0x0 0x1000>;
 752                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 753                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 754                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 755                 status = "disabled";
 756         };
 757
 758         vop_big: vop@ff930000 {
 759                 compatible = "rockchip,rk3366-lcdc-big";
 760                 rockchip,grf = <&grf>;
 761                 rockchip,prop = <PRMRY>;
 762                 rockchip,pwr18 = <0>;
 763                 rockchip,iommu-enabled = <1>;
 764                 reg = <0x0 0xff930000 0x0 0x23f0>;
 765                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 766                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 767                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 768                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 769                 reset-names = "axi", "ahb", "dclk";
 770                 status = "disabled";
 771         };
 772
 773         vopb_mmu: vopb-mmu {
 774                 dbgname = "vop";
 775                 compatible = "rockchip,vopb_mmu";
 776                 reg = <0x0 0xff932400 0x0 0x100>;
 777                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 778                 interrupt-names = "vop_mmu";
 779                 status = "disabled";
 780         };
 781
 782         iep_mmu: iep-mmu {
 783                 dbgname = "iep";
 784                 compatible = "rockchip,iep_mmu";
 785                 reg = <0x0 0xff900800 0x0 0x100>;
 786                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 787                 interrupt-names = "iep_mmu";
 788                 status = "disabled";
 789         };
 790
 791         vpu_mmu: vpu_mmu {
 792                 dbgname = "vpu";
 793                 compatible = "rockchip,vpu_mmu";
 794                 reg = <0x0 0xff9a0800 0x0 0x100>;
 795                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 796                 interrupt-names = "vpu_mmu";
 797                 status = "disabled";
 798         };
 799
 800         vdec_mmu: vdec_mmu {
 801                 dbgname = "vdec";
 802                 compatible = "rockchip,vdec_mmu";
 803                 reg = <0x0 0xff9b0480 0x0 0x40>,
 804                       <0x0 0xff9b04c0 0x0 0x40>;
 805                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 806                 interrupt-names = "vdec_mmu";
 807                 status = "disabled";
 808         };
 809
 810         dsihost0: mipi@ff960000 {
 811                 compatible = "rockchip,rk3368-dsi";
 812                 rockchip,prop = <0>;
 813                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 814                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 815                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 816                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 817                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 818                 status = "disabled";
 819         };
 820
 821         lvds: lvds@ff968000 {
 822                 compatible = "rockchip,rk3366-lvds";
 823                 rockchip,grf = <&grf>;
 824                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 825                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 826                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 827                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 828                 status = "disabled";
 829         };
 830
 831         hdmi: hdmi@ff980000 {
 832                 compatible = "rockchip,rk3366-hdmi";
 833                 reg = <0x0 0xff980000 0x0 0x20000>;
 834                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 835                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 836                 clocks = <&cru PCLK_HDMI_CTRL>,
 837                          <&cru SCLK_HDMI_HDCP>,
 838                          <&cru SCLK_HDMI_CEC>,
 839                          <&cru DCLK_HDMIPHY>;
 840                 clock-names = "pclk_hdmi",
 841                               "hdcp_clk_hdmi",
 842                               "cec_clk_hdmi",
 843                               "dclk_hdmi_phy";
 844                 resets = <&cru SRST_HDMI>;
 845                 reset-names = "hdmi";
 846                 pinctrl-names = "default", "gpio";
 847                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 848                 pinctrl-1 = <&i2c5_gpio>;
 849                 status = "disabled";
 850         };
 851
 852         vpu: vpu_service@ff9a0000 {
 853                 compatible = "rockchip,vpu_service";
 854                 rockchip,grf = <&grf>;
 855                 iommu_enabled = <1>;
 856                 reg = <0x0 0xff9a0000 0x0 0x800>;
 857                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 858                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 859                 interrupt-names = "irq_dec", "irq_enc";
 860                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
 861                 clock-names = "aclk_vcodec", "hclk_vcodec";
 862                 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
 863                 reset-names = "video_h", "video_a";
 864                 name = "vpu_service";
 865                 dev_mode = <0>;
 866                 status = "disabled";
 867         };
 868
 869         rkvdec: rkvdec@ff9b0000 {
 870                 compatible = "rockchip,rkvdec";
 871                 rockchip,grf = <&grf>;
 872                 iommu_enabled = <1>;
 873                 reg = <0x0 0xff9b0000 0x0 0x400>;
 874                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 875                 interrupt-names = "irq_dec";
 876                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
 877                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
 878                 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
 879                 reset-names = "video_h", "video_a";
 880                 dev_mode = <2>;
 881                 name = "rkvdec";
 882                 status = "disabled";
 883         };
 884
 885         pinctrl: pinctrl {
 886                 compatible = "rockchip,rk3366-pinctrl";
 887                 rockchip,grf = <&grf>;
 888                 rockchip,pmu = <&pmugrf>;
 889                 #address-cells = <0x2>;
 890                 #size-cells = <0x2>;
 891                 ranges;
 892
 893                 gpio0: gpio0@ff750000 {
 894                         compatible = "rockchip,gpio-bank";
 895                         reg = <0x0 0xff750000 0x0 0x100>;
 896                         clocks = <&cru PCLK_GPIO0>;
 897                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 898
 899                         gpio-controller;
 900                         #gpio-cells = <0x2>;
 901
 902                         interrupt-controller;
 903                         #interrupt-cells = <0x2>;
 904                 };
 905
 906                 gpio1: gpio1@ff780000 {
 907                         compatible = "rockchip,gpio-bank";
 908                         reg = <0x0 0xff758000 0x0 0x100>;
 909                         clocks = <&cru PCLK_GPIO1>;
 910                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 911
 912                         gpio-controller;
 913                         #gpio-cells = <0x2>;
 914
 915                         interrupt-controller;
 916                         #interrupt-cells = <0x2>;
 917                 };
 918
 919                 gpio2: gpio2@ff790000 {
 920                         compatible = "rockchip,gpio-bank";
 921                         reg = <0x0 0xff790000 0x0 0x100>;
 922                         clocks = <&cru PCLK_GPIO2>;
 923                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 924
 925                         gpio-controller;
 926                         #gpio-cells = <0x2>;
 927
 928                         interrupt-controller;
 929                         #interrupt-cells = <0x2>;
 930                 };
 931
 932                 gpio3: gpio3@ff7a0000 {
 933                         compatible = "rockchip,gpio-bank";
 934                         reg = <0x0 0xff7a0000 0x0 0x100>;
 935                         clocks = <&cru PCLK_GPIO3>;
 936                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 937
 938                         gpio-controller;
 939                         #gpio-cells = <0x2>;
 940
 941                         interrupt-controller;
 942                         #interrupt-cells = <0x2>;
 943                 };
 944
 945                 gpio4: gpio4@ff7b0000 {
 946                         compatible = "rockchip,gpio-bank";
 947                         reg = <0x0 0xff7b0000 0x0 0x100>;
 948                         clocks = <&cru PCLK_GPIO4>;
 949                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 950
 951                         gpio-controller;
 952                         #gpio-cells = <0x2>;
 953
 954                         interrupt-controller;
 955                         #interrupt-cells = <0x2>;
 956                 };
 957
 958                 gpio5: gpio5@ff7c0000 {
 959                         compatible = "rockchip,gpio-bank";
 960                         reg = <0x0 0xff7c0000 0x0 0x100>;
 961                         clocks = <&cru PCLK_GPIO5>;
 962                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 963
 964                         gpio-controller;
 965                         #gpio-cells = <0x2>;
 966
 967                         interrupt-controller;
 968                         #interrupt-cells = <0x2>;
 969                 };
 970
 971                 pcfg_pull_up: pcfg-pull-up {
 972                         bias-pull-up;
 973                 };
 974
 975                 pcfg_pull_down: pcfg-pull-down {
 976                         bias-pull-down;
 977                 };
 978
 979                 pcfg_pull_none: pcfg-pull-none {
 980                         bias-disable;
 981                 };
 982
 983                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 984                         bias-disable;
 985                         drive-strength = <12>;
 986                 };
 987
 988                 emmc {
 989                         emmc_clk: emmc-clk {
 990                                 rockchip,pins =
 991                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
 992                         };
 993
 994                         emmc_cmd: emmc-cmd {
 995                                 rockchip,pins =
 996                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
 997                         };
 998
 999                         emmc_pwr: emmc-pwr {
1000                                 rockchip,pins =
1001                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
1002                         };
1003
1004                         emmc_bus1: emmc-bus1 {
1005                                 rockchip,pins =
1006                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
1007                         };
1008
1009                         emmc_bus4: emmc-bus4 {
1010                                 rockchip,pins =
1011                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1012                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1013                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1014                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1015                         };
1016
1017                         emmc_bus8: emmc-bus8 {
1018                                 rockchip,pins =
1019                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1020                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1021                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1022                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
1023                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
1024                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
1025                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
1026                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
1027                         };
1028                 };
1029
1030                 sdmmc {
1031                         sdmmc_cd: sdmmc-cd {
1032                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1033                         };
1034
1035                         sdmmc_bus1: sdmmc-bus1 {
1036                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1037                         };
1038
1039                         sdmmc_bus4: sdmmc-bus4 {
1040                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1041                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1042                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1043                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1044                         };
1045
1046                         sdmmc_clk: sdmmc-clk {
1047                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1048                         };
1049
1050                         sdmmc_cmd: sdmmc-cmd {
1051                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1052                         };
1053                 };
1054
1055                 sdio {
1056                         sdio_bus1: sdio-bus1 {
1057                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1058                         };
1059
1060                         sdio_bus4: sdio-bus4 {
1061                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1062                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1063                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1064                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1065                         };
1066
1067                         sdio_cmd: sdio-cmd {
1068                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1069                         };
1070
1071                         sdio_clk: sdio-clk {
1072                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1073                         };
1074
1075                         sdio_cd: sdio-cd {
1076                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1077                         };
1078
1079                         sdio_wp: sdio-wp {
1080                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1081                         };
1082
1083                         sdio_int: sdio-int {
1084                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1085                         };
1086
1087                         sdio_pwr: sdio-pwr {
1088                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1089                         };
1090                 };
1091
1092                 hdmi_i2c {
1093                         hdmii2c_xfer: hdmii2c-xfer {
1094                                 rockchip,pins =
1095                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1096                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1097                         };
1098                 };
1099
1100                 hdmi_pin {
1101                         hdmi_cec: hdmi-cec {
1102                                 rockchip,pins =
1103                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1104                         };
1105                 };
1106
1107                 i2c0 {
1108                         i2c0_xfer: i2c0-xfer {
1109                                 rockchip,pins =
1110                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1111                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1112                         };
1113                 };
1114
1115                 i2c1 {
1116                         i2c1_xfer: i2c1-xfer {
1117                                 rockchip,pins =
1118                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1119                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1120                         };
1121                 };
1122
1123                 i2c2 {
1124                         i2c2_xfer: i2c2-xfer {
1125                                 rockchip,pins =
1126                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1127                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1128                         };
1129
1130                         i2c2_gpio: i2c2-gpio {
1131                                 rockchip,pins =
1132                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1133                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1134                         };
1135                 };
1136
1137                 i2c3 {
1138                         i2c3_xfer: i2c3-xfer {
1139                                 rockchip,pins =
1140                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1141                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1142                         };
1143                 };
1144
1145                 i2c4 {
1146                         i2c4_xfer: i2c4-xfer {
1147                                 rockchip,pins =
1148                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1149                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1150                         };
1151
1152                         i2c4_gpio: i2c4-gpio {
1153                                 rockchip,pins =
1154                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1155                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1156                         };
1157                 };
1158
1159                 i2c5 {
1160                         i2c5_xfer: i2c5-xfer {
1161                                 rockchip,pins =
1162                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1163                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1164                         };
1165                         i2c5_gpio: i2c5-gpio {
1166                                 rockchip,pins =
1167                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1168                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1169                         };
1170                 };
1171
1172                 i2s {
1173                         i2s_8ch_bus: i2s-8ch-bus {
1174                                 rockchip,pins =
1175                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1176                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1177                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1178                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1179                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1180                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1181                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1182                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1183                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1184                         };
1185                 };
1186
1187                 spdif {
1188                         spdif_bus: spdif-bus {
1189                                 rockchip,pins =
1190                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1191                         };
1192                 };
1193
1194                 spi0 {
1195                         spi0_clk: spi0-clk {
1196                                 rockchip,pins =
1197                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1198                         };
1199                         spi0_cs0: spi0-cs0 {
1200                                 rockchip,pins =
1201                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1202                         };
1203                         spi0_cs1: spi0-cs1 {
1204                                 rockchip,pins =
1205                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1206                         };
1207                         spi0_tx: spi0-tx {
1208                                 rockchip,pins =
1209                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1210                         };
1211                         spi0_rx: spi0-rx {
1212                                 rockchip,pins =
1213                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1214                         };
1215                 };
1216
1217                 spi1 {
1218                         spi1_clk: spi1-clk {
1219                                 rockchip,pins =
1220                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1221                         };
1222                         spi1_cs0: spi1-cs0 {
1223                                 rockchip,pins =
1224                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1225                         };
1226                         spi1_tx: spi1-tx {
1227                                 rockchip,pins =
1228                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1229                         };
1230                         spi1_rx: spi1-rx {
1231                                 rockchip,pins =
1232                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1233                         };
1234                 };
1235
1236                 uart0 {
1237                         uart0_xfer: uart0-xfer {
1238                                 rockchip,pins =
1239                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1240                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1241                         };
1242
1243                         uart0_cts: uart0-cts {
1244                                 rockchip,pins =
1245                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1246                         };
1247
1248                         uart0_rts: uart0-rts {
1249                                 rockchip,pins =
1250                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1251                         };
1252                 };
1253
1254                 uart2_t0 {
1255                         uart2_t0_xfer: uart2_t0-xfer {
1256                                 rockchip,pins =
1257                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1258                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1259                         };
1260                         /* no rts / cts for uart2 */
1261                 };
1262
1263                 uart2_t1 {
1264                         uart2_t1_xfer: uart2_t1-xfer {
1265                                 rockchip,pins =
1266                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1267                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1268                         };
1269                         /* no rts / cts for uart2 */
1270                 };
1271
1272                 uart2_t2 {
1273                         uart2_t2_xfer: uart2_t2-xfer {
1274                                 rockchip,pins =
1275                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1276                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1277                         };
1278                         /* no rts / cts for uart2 */
1279                 };
1280
1281                 uart3 {
1282                         uart3_xfer: uart3-xfer {
1283                                 rockchip,pins =
1284                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1285                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1286                         };
1287
1288                         uart3_cts: uart3-cts {
1289                                 rockchip,pins =
1290                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1291                         };
1292
1293                         uart3_rts: uart3-rts {
1294                                 rockchip,pins =
1295                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1296                         };
1297                 };
1298
1299                 pwm0 {
1300                         pwm0_pin: pwm0-pin {
1301                                 rockchip,pins =
1302                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1303                         };
1304                 };
1305
1306                 pwm1 {
1307                         pwm1_pin: pwm1-pin {
1308                                 rockchip,pins =
1309                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1310                         };
1311                 };
1312
1313                 pwm2_t0 {
1314                         pwm2_t0_pin: pwm2_t0-pin {
1315                                 rockchip,pins =
1316                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1317                         };
1318                 };
1319
1320                 pwm2_t1 {
1321                         pwm2_t1_pin: pwm2_t1-pin {
1322                                 rockchip,pins =
1323                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1324                         };
1325                 };
1326
1327                 pwm3_t0 {
1328                         pwm3_t0_pin: pwm3_t0-pin {
1329                                 rockchip,pins =
1330                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1331                         };
1332                 };
1333
1334                 pwm3_t1 {
1335                         pwm3_t1_pin: pwm3_t1-pin {
1336                                 rockchip,pins =
1337                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1338                         };
1339                 };
1340
1341                 pwm3_t2 {
1342                         pwm3_t2_pin: pwm3_t2-pin {
1343                                 rockchip,pins =
1344                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1345                         };
1346                 };
1347
1348                 lcdc {
1349                         lcdc_lcdc: lcdc-lcdc {
1350                                 rockchip,pins =
1351                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1352                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1353                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1354                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1355                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1356                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1357                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1358                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1359                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1360                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1361                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1362                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1363                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1364                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1365                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1366                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1367                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1368                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1369                         };
1370
1371                         lcdc_gpio: lcdc-gpio {
1372                                 rockchip,pins =
1373                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1374                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1375                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1376                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1377                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1378                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1379                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1380                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1381                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1382                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1383                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1384                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1385                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1386                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1387                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1388                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1389                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1390                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1391                         };
1392                 };
1393
1394                 gmac {
1395                         rgmii_pins: rgmii-pins {
1396                                 rockchip,pins =
1397                                         /* mac_rxd3 */
1398                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1399                                         /* mac_rxd2 */
1400                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1401                                         /* mac_txd3 */
1402                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1403                                         /* mac_txd2 */
1404                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1405                                         /* mac_rxd1 */
1406                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1407                                         /* mac_rxd0 */
1408                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1409                                         /* mac_txd1 */
1410                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1411                                         /* mac_txd0 */
1412                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1413                                         /* mac_txclkout */
1414                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1415                                         /* mac_crs */
1416                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1417                                         /* mac_rxclkin */
1418                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1419                                         /* mac_mdio */
1420                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1421                                         /* mac_txen */
1422                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1423                                         /* mac_clk */
1424                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1425                                         /* mac_rxer */
1426                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1427                                         /* mac_rxdv */
1428                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1429                                         /* mac_mdc */
1430                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1431                         };
1432
1433                         rmii_pins: rmii-pins {
1434                                 rockchip,pins =
1435                                         /* mac_rxd1 */
1436                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1437                                         /* mac_rxd0 */
1438                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1439                                         /* mac_txd1 */
1440                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1441                                         /* mac_txd0 */
1442                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1443                                         /* mac_crs */
1444                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1445                                         /* mac_rxclkin */
1446                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1447                                         /* mac_mdio */
1448                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1449                                         /* mac_txen */
1450                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1451                                         /* mac_clk */
1452                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1453                                         /* mac_rxer */
1454                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1455                                         /* mac_rxdv */
1456                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1457                                         /* mac_mdc */
1458                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1459                         };
1460                 };
1461
1462                 eth_phy {
1463                         eth_phy_pwr: eth-phy-pwr {
1464                                 rockchip,pins =
1465                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1466                         };
1467                 };
1468         };
1469
1470         gpu: gpu@ffa30000 {
1471                 compatible = "arm,malit764",
1472                              "arm,malit76x",
1473                              "arm,malit7xx",
1474                              "arm,mali-midgard";
1475
1476                 reg = <0x0 0xffa30000 0 0x10000>;
1477
1478                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1479                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1480                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1481                 interrupt-names = "GPU", "MMU", "JOB";
1482
1483                 clocks = <&cru ACLK_GPU>;
1484                 clock-names = "clk_mali";
1485                 operating-points-v2 = <&gpu_opp_table>;
1486                 status = "disabled";
1487         };
1488
1489         gpu_opp_table: gpu_opp_table {
1490                 compatible = "operating-points-v2";
1491                 opp-shared;
1492
1493                 opp00 {
1494                         opp-hz = /bits/ 64 <96000000>;
1495                         opp-microvolt = <1150000>;
1496                 };
1497                 opp01 {
1498                         opp-hz = /bits/ 64 <192000000>;
1499                         opp-microvolt = <1150000>;
1500                 };
1501                 opp02 {
1502                         opp-hz = /bits/ 64 <288000000>;
1503                         opp-microvolt = <1150000>;
1504                 };
1505                 opp03 {
1506                         opp-hz = /bits/ 64 <375000000>;
1507                         opp-microvolt = <1150000>;
1508                 };
1509                 opp04 {
1510                         opp-hz = /bits/ 64 <480000000>;
1511                         opp-microvolt = <1150000>;
1512                 };
1513         };
1514 };