arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/power/rk3366-power.h>
  50 #include <dt-bindings/soc/rockchip_boot-mode.h>
  51
  52 / {
  53         compatible = "rockchip,rk3366";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 serial0 = &uart0;
  66                 serial2 = &uart2;
  67                 serial3 = &uart3;
  68                 spi0 = &spi0;
  69                 spi1 = &spi1;
  70         };
  71
  72         cpus {
  73                 #address-cells = <0x2>;
  74                 #size-cells = <0x0>;
  75
  76                 cpu0: cpu@0 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53","arm,armv8";
  79                         reg = <0x0 0x0>;
  80                         enable-method = "psci";
  81                 };
  82
  83                 cpu1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53","arm,armv8";
  86                         reg = <0x0 0x1>;
  87                         enable-method = "psci";
  88                 };
  89
  90                 cpu2: cpu@2 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53","arm,armv8";
  93                         reg = <0x0 0x2>;
  94                         enable-method = "psci";
  95                 };
  96
  97                 cpu3: cpu@3 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a53","arm,armv8";
 100                         reg = <0x0 0x3>;
 101                         enable-method = "psci";
 102                 };
 103         };
 104
 105         psci {
 106                 compatible = "arm,psci-1.0";
 107                 method = "smc";
 108         };
 109
 110         timer {
 111                 compatible = "arm,armv8-timer";
 112                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 113                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 114                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 115                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 116         };
 117
 118         xin24m: xin24m {
 119                 compatible = "fixed-clock";
 120                 #clock-cells = <0>;
 121                 clock-frequency = <24000000>;
 122                 clock-output-names = "xin24m";
 123         };
 124
 125         gic: interrupt-controller@ffb71000 {
 126                 compatible = "arm,gic-400";
 127                 interrupt-controller;
 128                 #interrupt-cells = <3>;
 129                 #address-cells = <0>;
 130
 131                 reg = <0x0 0xffb71000 0x0 0x1000>,
 132                       <0x0 0xffb72000 0x0 0x1000>,
 133                       <0x0 0xffb74000 0x0 0x2000>,
 134                       <0x0 0xffb76000 0x0 0x2000>;
 135                 interrupts = <GIC_PPI 9
 136                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 137         };
 138
 139         nandc0: nandc@ff0c0000 {
 140                 compatible = "rockchip,rk-nandc";
 141                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 142                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 143                 nandc_id = <0>;
 144                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 145                 clock-names = "clk_nandc", "hclk_nandc";
 146                 status = "disabled";
 147         };
 148
 149         saradc: saradc@ff100000 {
 150                 compatible = "rockchip,saradc";
 151                 reg = <0x0 0xff100000 0x0 0x100>;
 152                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 153                 #io-channel-cells = <1>;
 154                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 155                 clock-names = "saradc", "apb_pclk";
 156                 status = "disabled";
 157         };
 158
 159         spi0: spi@ff110000 {
 160                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 161                 reg = <0x0 0xff110000 0x0 0x1000>;
 162                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 163                 clock-names = "spiclk", "apb_pclk";
 164                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 165                 pinctrl-names = "default";
 166                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 167                 #address-cells = <1>;
 168                 #size-cells = <0>;
 169                 status = "disabled";
 170         };
 171
 172         spi1: spi@ff120000 {
 173                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 174                 reg = <0x0 0xff120000 0x0 0x1000>;
 175                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 176                 clock-names = "spiclk", "apb_pclk";
 177                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 178                 pinctrl-names = "default";
 179                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 status = "disabled";
 183         };
 184
 185         sdmmc: rksdmmc@ff400000 {
 186                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 187                 clock-freq-min-max = <400000 150000000>;
 188                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 189                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 190                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 191                 fifo-depth = <0x100>;
 192                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 193                 reg = <0x0 0xff400000 0x0 0x4000>;
 194                 status = "disabled";
 195         };
 196
 197         sdio: rksdmmc@ff410000 {
 198                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 199                 clock-freq-min-max = <400000 150000000>;
 200                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 201                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 202                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 203                 fifo-depth = <0x100>;
 204                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 205                 reg = <0x0 0xff410000 0x0 0x4000>;
 206                 status = "disabled";
 207         };
 208
 209         emmc: rksdmmc@ff420000 {
 210                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 211                 clock-freq-min-max = <400000 150000000>;
 212                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 213                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 214                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 215                 fifo-depth = <0x100>;
 216                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 217                 reg = <0x0 0xff420000 0x0 0x4000>;
 218                 status = "disabled";
 219         };
 220
 221         gmac: eth@ff440000 {
 222                 compatible = "rockchip,rk3366-gmac";
 223                 reg = <0x0 0xff440000 0x0 0x10000>;
 224                 rockchip,grf = <&grf>;
 225                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 226                 interrupt-names = "macirq";
 227                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 228                          <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>,
 229                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 230                          <&cru PCLK_GMAC>;
 231                 clock-names = "stmmaceth", "mac_clk_rx",
 232                               "mac_clk_tx", "clk_mac_ref",
 233                               "clk_mac_refout", "aclk_mac",
 234                               "pclk_mac";
 235                 resets = <&cru SRST_MAC>;
 236                 reset-names = "stmmaceth";
 237                 status = "disabled";
 238         };
 239
 240         i2c0: i2c@ff650000 {
 241                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 242                 reg = <0x0 0xff728000 0x0 0x1000>;
 243                 clocks = <&cru PCLK_I2C0>;
 244                 clock-names = "i2c";
 245                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 246                 pinctrl-names = "default";
 247                 pinctrl-0 = <&i2c0_xfer>;
 248                 #address-cells = <1>;
 249                 #size-cells = <0>;
 250                 status = "disabled";
 251         };
 252
 253         i2c2: i2c@ff140000 {
 254                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 255                 reg = <0x0 0xff140000 0x0 0x1000>;
 256                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 257                 #address-cells = <1>;
 258                 #size-cells = <0>;
 259                 clock-names = "i2c";
 260                 clocks = <&cru PCLK_I2C2>;
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&i2c2_xfer>;
 263                 status = "disabled";
 264         };
 265
 266         i2c3: i2c@ff150000 {
 267                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 268                 reg = <0x0 0xff150000 0x0 0x1000>;
 269                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 270                 #address-cells = <1>;
 271                 #size-cells = <0>;
 272                 clock-names = "i2c";
 273                 clocks = <&cru PCLK_I2C3>;
 274                 pinctrl-names = "default";
 275                 pinctrl-0 = <&i2c3_xfer>;
 276                 status = "disabled";
 277         };
 278
 279         i2c4: i2c@ff160000 {
 280                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 281                 reg = <0x0 0xff160000 0x0 0x1000>;
 282                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285                 clock-names = "i2c";
 286                 clocks = <&cru PCLK_I2C4>;
 287                 pinctrl-names = "default";
 288                 pinctrl-0 = <&i2c4_xfer>;
 289                 status = "disabled";
 290         };
 291
 292         i2c5: i2c@ff170000 {
 293                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 294                 reg = <0x0 0xff170000 0x0 0x1000>;
 295                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 296                 #address-cells = <1>;
 297                 #size-cells = <0>;
 298                 clock-names = "i2c";
 299                 clocks = <&cru PCLK_I2C5>;
 300                 pinctrl-names = "default";
 301                 pinctrl-0 = <&i2c5_xfer>;
 302                 status = "disabled";
 303         };
 304
 305         uart0: serial@ff180000 {
 306                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 307                 reg = <0x0 0xff180000 0x0 0x100>;
 308                 clock-frequency = <24000000>;
 309                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 310                 clock-names = "baudclk", "apb_pclk";
 311                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 312                 reg-shift = <2>;
 313                 reg-io-width = <4>;
 314                 pinctrl-names = "default";
 315                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 316                 status = "disabled";
 317         };
 318
 319         uart3: serial@ff1b0000 {
 320                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 321                 reg = <0x0 0xff1b0000 0x0 0x100>;
 322                 clock-frequency = <24000000>;
 323                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 324                 clock-names = "baudclk", "apb_pclk";
 325                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 326                 reg-shift = <2>;
 327                 reg-io-width = <4>;
 328                 pinctrl-names = "default";
 329                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 330                 status = "disabled";
 331         };
 332
 333         usb_otg: usb@ff4c0000 {
 334                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 335                              "snps,dwc2";
 336                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 337                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 338                 clocks = <&cru HCLK_OTG>;
 339                 clock-names = "otg";
 340                 dr_mode = "otg";
 341                 g-np-tx-fifo-size = <16>;
 342                 g-rx-fifo-size = <275>;
 343                 g-tx-fifo-size = <256 128 128 64 64 32>;
 344                 g-use-dma;
 345                 status = "disabled";
 346         };
 347
 348         i2c1: i2c@ff660000 {
 349                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 350                 reg = <0x0 0xff660000 0x0 0x1000>;
 351                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 clock-names = "i2c";
 355                 clocks = <&cru PCLK_I2C1>;
 356                 pinctrl-names = "default";
 357                 pinctrl-0 = <&i2c1_xfer>;
 358                 status = "disabled";
 359         };
 360
 361         pwm0: pwm@ff680000 {
 362                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 363                 reg = <0x0 0xff680000 0x0 0x10>;
 364                 #pwm-cells = <3>;
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&pwm0_pin>;
 367                 clocks = <&cru PCLK_RKPWM>;
 368                 clock-names = "pwm";
 369                 status = "disabled";
 370         };
 371
 372         pwm1: pwm@ff680010 {
 373                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 374                 reg = <0x0 0xff680010 0x0 0x10>;
 375                 #pwm-cells = <3>;
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&pwm1_pin>;
 378                 clocks = <&cru PCLK_RKPWM>;
 379                 clock-names = "pwm";
 380                 status = "disabled";
 381         };
 382
 383         pwm2: pwm@ff680020 {
 384                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 385                 reg = <0x0 0xff680020 0x0 0x10>;
 386                 #pwm-cells = <3>;
 387                 clocks = <&cru PCLK_RKPWM>;
 388                 clock-names = "pwm";
 389                 status = "disabled";
 390         };
 391
 392         pwm3: pwm@ff680030 {
 393                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 394                 reg = <0x0 0xff680030 0x0 0x10>;
 395                 #pwm-cells = <3>;
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&pwm3_t2_pin>;
 398                 clocks = <&cru PCLK_RKPWM>;
 399                 clock-names = "pwm";
 400                 status = "disabled";
 401         };
 402
 403         uart2: serial@ff690000 {
 404                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 405                 reg = <0x0 0xff690000 0x0 0x100>;
 406                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 407                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 408                 clock-names = "baudclk", "apb_pclk";
 409                 reg-shift = <2>;
 410                 reg-io-width = <4>;
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&uart2_t1_xfer>;
 413                 status = "disabled";
 414         };
 415
 416         pmu: power-management@ff730000 {
 417                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 418                 reg = <0x0 0xff730000 0x0 0x1000>;
 419
 420                 power: power-controller {
 421                         status = "disabled";
 422                         compatible = "rockchip,rk3366-power-controller";
 423                         #power-domain-cells = <1>;
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426
 427                         /*
 428                          * Note: Although SCLK_* are the working clocks
 429                          * of device without including on the NOC, needed for
 430                          * synchronous reset.
 431                          *
 432                          * The clocks on the which NOC:
 433                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 434                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 435                          * ACLK_ISP is on ACLK_ISP_NIU.
 436                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 437                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 438                          *
 439                          * Which clock are device clocks:
 440                          *      clocks          devices
 441                          *      *_IEP           IEP:Image Enhancement Processor
 442                          *      *_ISP           ISP:Image Signal Processing
 443                          *      *_VOP*          VOP:Visual Output Processor
 444                          *      *_RGA           RGA
 445                          *      *_DPHY*         LVDS
 446                          *      *_HDMI          HDMI
 447                          *      *_MIPI_*        MIPI
 448                          */
 449                         pd_vio {
 450                                 reg = <RK3366_PD_VIO>;
 451                                 clocks = <&cru ACLK_IEP>,
 452                                          <&cru ACLK_ISP>,
 453                                          <&cru ACLK_RGA>,
 454                                          <&cru ACLK_HDCP>,
 455                                          <&cru ACLK_VOP_FULL>,
 456                                          <&cru ACLK_VOP_LITE>,
 457                                          <&cru ACLK_VOP_IEP>,
 458                                          <&cru DCLK_VOP_FULL>,
 459                                          <&cru DCLK_VOP_LITE>,
 460                                          <&cru HCLK_IEP>,
 461                                          <&cru HCLK_ISP>,
 462                                          <&cru HCLK_RGA>,
 463                                          <&cru HCLK_VOP_FULL>,
 464                                          <&cru HCLK_VOP_LITE>,
 465                                          <&cru HCLK_VIO_HDCPMMU>,
 466                                          <&cru PCLK_HDMI_CTRL>,
 467                                          <&cru PCLK_HDCP>,
 468                                          <&cru PCLK_MIPI_DSI0>,
 469                                          <&cru SCLK_VOP_FULL_PWM>,
 470                                          <&cru SCLK_HDCP>,
 471                                          <&cru SCLK_ISP>,
 472                                          <&cru SCLK_RGA>,
 473                                          <&cru SCLK_HDMI_CEC>,
 474                                          <&cru SCLK_HDMI_HDCP>;
 475                         };
 476
 477                         /*
 478                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 479                          * (video endecoder & decoder) clocks that on the
 480                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 481                          */
 482                         pd_vpu {
 483                                 reg = <RK3366_PD_VPU>;
 484                                 clocks = <&cru ACLK_VIDEO>,
 485                                          <&cru HCLK_VIDEO>;
 486                         };
 487
 488                         /*
 489                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 490                          * (video decoder) clocks that on the
 491                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 492                          */
 493                         pd_rkvdec {
 494                                 reg = <RK3366_PD_RKVDEC>;
 495                                 clocks = <&cru ACLK_RKVDEC>,
 496                                          <&cru HCLK_RKVDEC>;
 497                         };
 498
 499                         pd_video {
 500                                 reg = <RK3366_PD_VIDEO>;
 501                                 clocks = <&cru ACLK_VIDEO>,
 502                                          <&cru ACLK_RKVDEC>,
 503                                          <&cru HCLK_VIDEO>,
 504                                          <&cru HCLK_RKVDEC>,
 505                                          <&cru SCLK_HEVC_CABAC>,
 506                                          <&cru SCLK_HEVC_CORE>;
 507                         };
 508
 509                         /*
 510                          * Note: ACLK_GPU is the GPU clock,
 511                          * and on the ACLK_GPU_NIU (NOC).
 512                          */
 513                         pd_gpu {
 514                                 reg = <RK3366_PD_GPU>;
 515                                 clocks = <&cru ACLK_GPU>;
 516                         };
 517                 };
 518         };
 519
 520         pmugrf: syscon@ff738000 {
 521                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 522                 reg = <0x0 0xff738000 0x0 0x1000>;
 523
 524                 reboot-mode {
 525                         compatible = "syscon-reboot-mode";
 526                         offset = <0x200>;
 527                         mode-normal = <BOOT_NORMAL>;
 528                         mode-recovery = <BOOT_RECOVERY>;
 529                         mode-fastboot = <BOOT_FASTBOOT>;
 530                         mode-loader = <BOOT_LOADER>;
 531                 };
 532         };
 533
 534         amba {
 535                 compatible = "arm,amba-bus";
 536                 #address-cells = <2>;
 537                 #size-cells = <2>;
 538                 ranges;
 539
 540                 dmac_peri: dma-controller@ff250000 {
 541                         compatible = "arm,pl330", "arm,primecell";
 542                         reg = <0x0 0xff250000 0x0 0x4000>;
 543                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 544                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 545                         #dma-cells = <1>;
 546                         clocks = <&cru ACLK_DMAC_PERI>;
 547                         clock-names = "apb_pclk";
 548                 };
 549
 550                 dmac_bus: dma-controller@ff600000 {
 551                         compatible = "arm,pl330", "arm,primecell";
 552                         reg = <0x0 0xff600000 0x0 0x4000>;
 553                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 554                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 555                         #dma-cells = <1>;
 556                         clocks = <&cru ACLK_DMAC_BUS>;
 557                         clock-names = "apb_pclk";
 558                 };
 559         };
 560
 561         cru: clock-controller@ff760000 {
 562                 compatible = "rockchip,rk3366-cru";
 563                 reg = <0x0 0xff760000 0x0 0x1000>;
 564                 rockchip,grf = <&grf>;
 565                 #clock-cells = <1>;
 566                 #reset-cells = <1>;
 567                 assigned-clocks =
 568                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 569                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 570                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 571                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 572                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
 573                 assigned-clock-rates =
 574                         <750000000>, <576000000>,
 575                         <594000000>, <594000000>,
 576                         <480000000>, <520000000>,
 577                         <375000000>, <288000000>,
 578                         <100000000>, <100000000>;
 579         };
 580
 581         grf: syscon@ff770000 {
 582                 compatible = "rockchip,rk3366-grf", "syscon";
 583                 reg = <0x0 0xff770000 0x0 0x1000>;
 584         };
 585
 586         i2s_2ch: i2s-2ch@ff890000 {
 587                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 588                 reg = <0x0 0xff890000 0x0 0x1000>;
 589                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 590                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 591                 dma-names = "tx", "rx";
 592                 clock-names = "i2s_hclk", "i2s_clk";
 593                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 594                 status = "disabled";
 595         };
 596
 597         i2s_8ch: i2s-8ch@ff898000 {
 598                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 599                 reg = <0x0 0xff898000 0x0 0x1000>;
 600                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 601                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 602                 dma-names = "tx", "rx";
 603                 clock-names = "i2s_hclk", "i2s_clk";
 604                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&i2s_8ch_bus>;
 607                 status = "disabled";
 608         };
 609
 610         fb: fb {
 611                 compatible = "rockchip,rk-fb";
 612                 rockchip,disp-mode = <DUAL>;
 613                 status = "disabled";
 614         };
 615
 616         rk_screen: screen {
 617                 compatible = "rockchip,screen";
 618                 status = "disabled";
 619         };
 620
 621         vop_lite: vop@ff8f0000 {
 622                 compatible = "rockchip,rk3366-lcdc-lite";
 623                 rockchip,grf = <&grf>;
 624                 rockchip,pwr18 = <0>;
 625                 rockchip,iommu-enabled = <1>;
 626                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 627                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 628                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 629                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 630                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 631                 reset-names = "axi", "ahb", "dclk";
 632                 status = "disabled";
 633         };
 634
 635         vopl_mmu: vopl-mmu {
 636                 dbgname = "vop";
 637                 compatible = "rockchip,vopl_mmu";
 638                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 639                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 640                 interrupt-names = "vopl_mmu";
 641                 status = "disabled";
 642         };
 643
 644         rga: rga@ff920000 {
 645                 compatible = "rockchip,rga2";
 646                 dev_mode = <1>;
 647                 reg = <0x0 0xff920000 0x0 0x1000>;
 648                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 649                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 650                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 651                 status = "disabled";
 652         };
 653
 654         vop_big: vop@ff930000 {
 655                 compatible = "rockchip,rk3366-lcdc-big";
 656                 rockchip,grf = <&grf>;
 657                 rockchip,prop = <PRMRY>;
 658                 rockchip,pwr18 = <0>;
 659                 rockchip,iommu-enabled = <1>;
 660                 reg = <0x0 0xff930000 0x0 0x23f0>;
 661                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 662                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 663                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 664                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 665                 reset-names = "axi", "ahb", "dclk";
 666                 status = "disabled";
 667         };
 668
 669         vopb_mmu: vopb-mmu {
 670                 dbgname = "vop";
 671                 compatible = "rockchip,vopb_mmu";
 672                 reg = <0x0 0xff932400 0x0 0x100>;
 673                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 674                 interrupt-names = "vop_mmu";
 675                 status = "disabled";
 676         };
 677
 678         dsihost0: mipi@ff960000 {
 679                 compatible = "rockchip,rk3368-dsi";
 680                 rockchip,prop = <0>;
 681                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 682                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 683                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 684                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 685                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 686                 status = "disabled";
 687         };
 688
 689         lvds: lvds@ff968000 {
 690                 compatible = "rockchip,rk3366-lvds";
 691                 rockchip,grf = <&grf>;
 692                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 693                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 694                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 695                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 696                 status = "disabled";
 697         };
 698
 699         hdmi: hdmi@ff980000 {
 700                 compatible = "rockchip,rk3366-hdmi";
 701                 reg = <0x0 0xff980000 0x0 0x20000>;
 702                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 703                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 704                 clocks = <&cru PCLK_HDMI_CTRL>,
 705                          <&cru SCLK_HDMI_HDCP>,
 706                          <&cru SCLK_HDMI_CEC>,
 707                          <&cru DCLK_HDMIPHY>;
 708                 clock-names = "pclk_hdmi",
 709                               "hdcp_clk_hdmi",
 710                               "cec_clk_hdmi",
 711                               "dclk_hdmi_phy";
 712                 resets = <&cru SRST_HDMI>;
 713                 reset-names = "hdmi";
 714                 pinctrl-names = "default", "gpio";
 715                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 716                 pinctrl-1 = <&i2c5_gpio>;
 717                 status = "disabled";
 718         };
 719
 720         pinctrl: pinctrl {
 721                 compatible = "rockchip,rk3366-pinctrl";
 722                 rockchip,grf = <&grf>;
 723                 rockchip,pmu = <&pmugrf>;
 724                 #address-cells = <0x2>;
 725                 #size-cells = <0x2>;
 726                 ranges;
 727
 728                 gpio0: gpio0@ff750000 {
 729                         compatible = "rockchip,gpio-bank";
 730                         reg = <0x0 0xff750000 0x0 0x100>;
 731                         clocks = <&cru PCLK_GPIO0>;
 732                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 733
 734                         gpio-controller;
 735                         #gpio-cells = <0x2>;
 736
 737                         interrupt-controller;
 738                         #interrupt-cells = <0x2>;
 739                 };
 740
 741                 gpio1: gpio1@ff780000 {
 742                         compatible = "rockchip,gpio-bank";
 743                         reg = <0x0 0xff758000 0x0 0x100>;
 744                         clocks = <&cru PCLK_GPIO1>;
 745                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 746
 747                         gpio-controller;
 748                         #gpio-cells = <0x2>;
 749
 750                         interrupt-controller;
 751                         #interrupt-cells = <0x2>;
 752                 };
 753
 754                 gpio2: gpio2@ff790000 {
 755                         compatible = "rockchip,gpio-bank";
 756                         reg = <0x0 0xff790000 0x0 0x100>;
 757                         clocks = <&cru PCLK_GPIO2>;
 758                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 759
 760                         gpio-controller;
 761                         #gpio-cells = <0x2>;
 762
 763                         interrupt-controller;
 764                         #interrupt-cells = <0x2>;
 765                 };
 766
 767                 gpio3: gpio3@ff7a0000 {
 768                         compatible = "rockchip,gpio-bank";
 769                         reg = <0x0 0xff7a0000 0x0 0x100>;
 770                         clocks = <&cru PCLK_GPIO3>;
 771                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 772
 773                         gpio-controller;
 774                         #gpio-cells = <0x2>;
 775
 776                         interrupt-controller;
 777                         #interrupt-cells = <0x2>;
 778                 };
 779
 780                 gpio4: gpio4@ff7b0000 {
 781                         compatible = "rockchip,gpio-bank";
 782                         reg = <0x0 0xff7b0000 0x0 0x100>;
 783                         clocks = <&cru PCLK_GPIO4>;
 784                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 785
 786                         gpio-controller;
 787                         #gpio-cells = <0x2>;
 788
 789                         interrupt-controller;
 790                         #interrupt-cells = <0x2>;
 791                 };
 792
 793                 gpio5: gpio5@ff7c0000 {
 794                         compatible = "rockchip,gpio-bank";
 795                         reg = <0x0 0xff7c0000 0x0 0x100>;
 796                         clocks = <&cru PCLK_GPIO5>;
 797                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 798
 799                         gpio-controller;
 800                         #gpio-cells = <0x2>;
 801
 802                         interrupt-controller;
 803                         #interrupt-cells = <0x2>;
 804                 };
 805
 806                 pcfg_pull_up: pcfg-pull-up {
 807                         bias-pull-up;
 808                 };
 809
 810                 pcfg_pull_down: pcfg-pull-down {
 811                         bias-pull-down;
 812                 };
 813
 814                 pcfg_pull_none: pcfg-pull-none {
 815                         bias-disable;
 816                 };
 817
 818                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 819                         bias-disable;
 820                         drive-strength = <12>;
 821                 };
 822
 823                 emmc {
 824                         emmc_clk: emmc-clk {
 825                                 rockchip,pins =
 826                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
 827                         };
 828
 829                         emmc_cmd: emmc-cmd {
 830                                 rockchip,pins =
 831                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
 832                         };
 833
 834                         emmc_pwr: emmc-pwr {
 835                                 rockchip,pins =
 836                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
 837                         };
 838
 839                         emmc_bus1: emmc-bus1 {
 840                                 rockchip,pins =
 841                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
 842                         };
 843
 844                         emmc_bus4: emmc-bus4 {
 845                                 rockchip,pins =
 846                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 847                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 848                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 849                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
 850                         };
 851
 852                         emmc_bus8: emmc-bus8 {
 853                                 rockchip,pins =
 854                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 855                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 856                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 857                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
 858                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
 859                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
 860                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
 861                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
 862                         };
 863                 };
 864
 865                 sdmmc {
 866                         sdmmc_cd: sdmmc-cd {
 867                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
 868                         };
 869
 870                         sdmmc_bus1: sdmmc-bus1 {
 871                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
 872                         };
 873
 874                         sdmmc_bus4: sdmmc-bus4 {
 875                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
 876                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
 877                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
 878                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
 879                         };
 880
 881                         sdmmc_clk: sdmmc-clk {
 882                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
 883                         };
 884
 885                         sdmmc_cmd: sdmmc-cmd {
 886                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
 887                         };
 888                 };
 889
 890                 sdio {
 891                         sdio_bus1: sdio-bus1 {
 892                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
 893                         };
 894
 895                         sdio_bus4: sdio-bus4 {
 896                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
 897                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
 898                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
 899                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
 900                         };
 901
 902                         sdio_cmd: sdio-cmd {
 903                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
 904                         };
 905
 906                         sdio_clk: sdio-clk {
 907                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
 908                         };
 909
 910                         sdio_cd: sdio-cd {
 911                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
 912                         };
 913
 914                         sdio_wp: sdio-wp {
 915                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
 916                         };
 917
 918                         sdio_int: sdio-int {
 919                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
 920                         };
 921
 922                         sdio_pwr: sdio-pwr {
 923                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
 924                         };
 925                 };
 926
 927                 hdmi_i2c {
 928                         hdmii2c_xfer: hdmii2c-xfer {
 929                                 rockchip,pins =
 930                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
 931                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
 932                         };
 933                 };
 934
 935                 hdmi_pin {
 936                         hdmi_cec: hdmi-cec {
 937                                 rockchip,pins =
 938                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
 939                         };
 940                 };
 941
 942                 i2c0 {
 943                         i2c0_xfer: i2c0-xfer {
 944                                 rockchip,pins =
 945                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
 946                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
 947                         };
 948                 };
 949
 950                 i2c1 {
 951                         i2c1_xfer: i2c1-xfer {
 952                                 rockchip,pins =
 953                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
 954                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
 955                         };
 956                 };
 957
 958                 i2c2 {
 959                         i2c2_xfer: i2c2-xfer {
 960                                 rockchip,pins =
 961                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
 962                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
 963                         };
 964                 };
 965
 966                 i2c3 {
 967                         i2c3_xfer: i2c3-xfer {
 968                                 rockchip,pins =
 969                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
 970                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
 971                         };
 972                 };
 973
 974                 i2c4 {
 975                         i2c4_xfer: i2c4-xfer {
 976                                 rockchip,pins =
 977                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
 978                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
 979                         };
 980                 };
 981
 982                 i2c5 {
 983                         i2c5_xfer: i2c5-xfer {
 984                                 rockchip,pins =
 985                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
 986                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
 987                         };
 988                         i2c5_gpio: i2c5-gpio {
 989                                 rockchip,pins =
 990                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
 991                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
 992                         };
 993                 };
 994
 995                 i2s {
 996                         i2s_8ch_bus: i2s-8ch-bus {
 997                                 rockchip,pins =
 998                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
 999                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1000                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1001                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1002                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1003                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1004                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1005                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1006                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1007                         };
1008                 };
1009
1010                 spi0 {
1011                         spi0_clk: spi0-clk {
1012                                 rockchip,pins =
1013                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1014                         };
1015                         spi0_cs0: spi0-cs0 {
1016                                 rockchip,pins =
1017                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1018                         };
1019                         spi0_cs1: spi0-cs1 {
1020                                 rockchip,pins =
1021                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1022                         };
1023                         spi0_tx: spi0-tx {
1024                                 rockchip,pins =
1025                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1026                         };
1027                         spi0_rx: spi0-rx {
1028                                 rockchip,pins =
1029                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1030                         };
1031                 };
1032
1033                 spi1 {
1034                         spi1_clk: spi1-clk {
1035                                 rockchip,pins =
1036                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1037                         };
1038                         spi1_cs0: spi1-cs0 {
1039                                 rockchip,pins =
1040                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1041                         };
1042                         spi1_tx: spi1-tx {
1043                                 rockchip,pins =
1044                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1045                         };
1046                         spi1_rx: spi1-rx {
1047                                 rockchip,pins =
1048                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1049                         };
1050                 };
1051
1052                 uart0 {
1053                         uart0_xfer: uart0-xfer {
1054                                 rockchip,pins =
1055                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1056                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1057                         };
1058
1059                         uart0_cts: uart0-cts {
1060                                 rockchip,pins =
1061                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1062                         };
1063
1064                         uart0_rts: uart0-rts {
1065                                 rockchip,pins =
1066                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1067                         };
1068                 };
1069
1070                 uart2_t0 {
1071                         uart2_t0_xfer: uart2_t0-xfer {
1072                                 rockchip,pins =
1073                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1074                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1075                         };
1076                         /* no rts / cts for uart2 */
1077                 };
1078
1079                 uart2_t1 {
1080                         uart2_t1_xfer: uart2_t1-xfer {
1081                                 rockchip,pins =
1082                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1083                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1084                         };
1085                         /* no rts / cts for uart2 */
1086                 };
1087
1088                 uart2_t2 {
1089                         uart2_t2_xfer: uart2_t2-xfer {
1090                                 rockchip,pins =
1091                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1092                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1093                         };
1094                         /* no rts / cts for uart2 */
1095                 };
1096
1097                 uart3 {
1098                         uart3_xfer: uart3-xfer {
1099                                 rockchip,pins =
1100                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1101                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1102                         };
1103
1104                         uart3_cts: uart3-cts {
1105                                 rockchip,pins =
1106                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1107                         };
1108
1109                         uart3_rts: uart3-rts {
1110                                 rockchip,pins =
1111                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1112                         };
1113                 };
1114
1115                 pwm0 {
1116                         pwm0_pin: pwm0-pin {
1117                                 rockchip,pins =
1118                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1119                         };
1120                 };
1121
1122                 pwm1 {
1123                         pwm1_pin: pwm1-pin {
1124                                 rockchip,pins =
1125                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1126                         };
1127                 };
1128
1129                 pwm2_t0 {
1130                         pwm2_t0_pin: pwm2_t0-pin {
1131                                 rockchip,pins =
1132                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1133                         };
1134                 };
1135
1136                 pwm2_t1 {
1137                         pwm2_t1_pin: pwm2_t1-pin {
1138                                 rockchip,pins =
1139                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1140                         };
1141                 };
1142
1143                 pwm3_t0 {
1144                         pwm3_t0_pin: pwm3_t0-pin {
1145                                 rockchip,pins =
1146                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1147                         };
1148                 };
1149
1150                 pwm3_t1 {
1151                         pwm3_t1_pin: pwm3_t1-pin {
1152                                 rockchip,pins =
1153                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1154                         };
1155                 };
1156
1157                 pwm3_t2 {
1158                         pwm3_t2_pin: pwm3_t2-pin {
1159                                 rockchip,pins =
1160                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1161                         };
1162                 };
1163
1164                 lcdc {
1165                         lcdc_lcdc: lcdc-lcdc {
1166                                 rockchip,pins =
1167                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1168                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1169                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1170                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1171                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1172                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1173                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1174                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1175                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1176                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1177                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1178                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1179                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1180                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1181                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1182                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1183                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1184                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1185                         };
1186
1187                         lcdc_gpio: lcdc-gpio {
1188                                 rockchip,pins =
1189                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1190                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1191                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1192                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1193                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1194                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1195                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1196                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1197                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1198                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1199                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1200                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1201                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1202                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1203                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1204                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1205                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1206                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1207                         };
1208                 };
1209
1210                 gmac {
1211                         rgmii_pins: rgmii-pins {
1212                                 rockchip,pins =
1213                                         /* mac_rxd3 */
1214                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1215                                         /* mac_rxd2 */
1216                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1217                                         /* mac_txd3 */
1218                                         <2 5  RK_FUNC_1 &pcfg_pull_none>,
1219                                         /* mac_txd2 */
1220                                         <2 4  RK_FUNC_1 &pcfg_pull_none>,
1221                                         /* mac_rxd1 */
1222                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1223                                         /* mac_rxd0 */
1224                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1225                                         /* mac_txd1 */
1226                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1227                                         /* mac_txd0 */
1228                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1229                                         /* mac_crs */
1230                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1231                                         /* mac_rxclkin */
1232                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1233                                         /* mac_mdio */
1234                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1235                                         /* mac_txen */
1236                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1237                                         /* mac_clk */
1238                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1239                                         /* mac_rxer */
1240                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1241                                         /* mac_rxdv */
1242                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1243                                         /* mac_mdc */
1244                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1245                         };
1246
1247                         rmii_pins: rmii-pins {
1248                                 rockchip,pins =
1249                                         /* mac_rxd1 */
1250                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1251                                         /* mac_rxd0 */
1252                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1253                                         /* mac_txd1 */
1254                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1255                                         /* mac_txd0 */
1256                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1257                                         /* mac_crs */
1258                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1259                                         /* mac_rxclkin */
1260                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1261                                         /* mac_mdio */
1262                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1263                                         /* mac_txen */
1264                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1265                                         /* mac_clk */
1266                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1267                                         /* mac_rxer */
1268                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1269                                         /* mac_rxdv */
1270                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1271                                         /* mac_mdc */
1272                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1273                         };
1274                 };
1275
1276                 eth_phy {
1277                         eth_phy_pwr: eth-phy-pwr {
1278                                 rockchip,pins =
1279                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
1280                         };
1281                 };
1282         };
1283 };