arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/power/rk3366-power.h>
  50
  51 / {
  52         compatible = "rockchip,rk3366";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 serial0 = &uart0;
  65                 serial2 = &uart2;
  66                 serial3 = &uart3;
  67                 spi0 = &spi0;
  68                 spi1 = &spi1;
  69         };
  70
  71         cpus {
  72                 #address-cells = <0x2>;
  73                 #size-cells = <0x0>;
  74
  75                 cpu0: cpu@0 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a53","arm,armv8";
  78                         reg = <0x0 0x0>;
  79                         enable-method = "psci";
  80                 };
  81
  82                 cpu1: cpu@1 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53","arm,armv8";
  85                         reg = <0x0 0x1>;
  86                         enable-method = "psci";
  87                 };
  88
  89                 cpu2: cpu@2 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a53","arm,armv8";
  92                         reg = <0x0 0x2>;
  93                         enable-method = "psci";
  94                 };
  95
  96                 cpu3: cpu@3 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a53","arm,armv8";
  99                         reg = <0x0 0x3>;
 100                         enable-method = "psci";
 101                 };
 102         };
 103
 104         psci {
 105                 compatible = "arm,psci-1.0";
 106                 method = "smc";
 107         };
 108
 109         timer {
 110                 compatible = "arm,armv8-timer";
 111                 interrupts = <
 112                                 GIC_PPI 13
 113                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 114                                 <GIC_PPI 14
 115                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 116                                 <GIC_PPI 11
 117                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 118                                 <GIC_PPI 10
 119                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 120                 clock-frequency = <24000000>;
 121         };
 122
 123         xin24m: xin24m {
 124                 compatible = "fixed-clock";
 125                 #clock-cells = <0>;
 126                 clock-frequency = <24000000>;
 127                 clock-output-names = "xin24m";
 128         };
 129
 130         gic: interrupt-controller@ffb71000 {
 131                 compatible = "arm,gic-400";
 132                 interrupt-controller;
 133                 #interrupt-cells = <3>;
 134                 #address-cells = <0>;
 135
 136                 reg = <0x0 0xffb71000 0x0 0x1000>,
 137                       <0x0 0xffb72000 0x0 0x1000>,
 138                       <0x0 0xffb74000 0x0 0x2000>,
 139                       <0x0 0xffb76000 0x0 0x2000>;
 140                 interrupts = <GIC_PPI 9
 141                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 142         };
 143
 144         nandc0: nandc@ff0c0000 {
 145                 compatible = "rockchip,rk-nandc";
 146                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 147                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 148                 nandc_id = <0>;
 149                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 150                 clock-names = "clk_nandc", "hclk_nandc";
 151                 status = "disabled";
 152         };
 153
 154         saradc: saradc@ff100000 {
 155                 compatible = "rockchip,saradc";
 156                 reg = <0x0 0xff100000 0x0 0x100>;
 157                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 158                 #io-channel-cells = <1>;
 159                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 160                 clock-names = "saradc", "apb_pclk";
 161                 status = "disabled";
 162         };
 163
 164         spi0: spi@ff110000 {
 165                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 166                 reg = <0x0 0xff110000 0x0 0x1000>;
 167                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 168                 clock-names = "spiclk", "apb_pclk";
 169                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 170                 pinctrl-names = "default";
 171                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 172                 #address-cells = <1>;
 173                 #size-cells = <0>;
 174                 status = "disabled";
 175         };
 176
 177         spi1: spi@ff120000 {
 178                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 179                 reg = <0x0 0xff120000 0x0 0x1000>;
 180                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 181                 clock-names = "spiclk", "apb_pclk";
 182                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 183                 pinctrl-names = "default";
 184                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 185                 #address-cells = <1>;
 186                 #size-cells = <0>;
 187                 status = "disabled";
 188         };
 189
 190         sdmmc: rksdmmc@ff400000 {
 191                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 192                 clock-freq-min-max = <400000 150000000>;
 193                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 194                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 195                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 196                 fifo-depth = <0x100>;
 197                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 198                 reg = <0x0 0xff400000 0x0 0x4000>;
 199                 status = "disabled";
 200         };
 201
 202         sdio: rksdmmc@ff410000 {
 203                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 204                 clock-freq-min-max = <400000 150000000>;
 205                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 206                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 207                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 208                 fifo-depth = <0x100>;
 209                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 210                 reg = <0x0 0xff410000 0x0 0x4000>;
 211                 status = "disabled";
 212         };
 213
 214         emmc: rksdmmc@ff420000 {
 215                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 216                 clock-freq-min-max = <400000 150000000>;
 217                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 218                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 219                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 220                 fifo-depth = <0x100>;
 221                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 222                 reg = <0x0 0xff420000 0x0 0x4000>;
 223                 status = "disabled";
 224         };
 225
 226         gmac: eth@ff440000 {
 227                 compatible = "rockchip,rk3366-gmac";
 228                 reg = <0x0 0xff440000 0x0 0x10000>;
 229                 rockchip,grf = <&grf>;
 230                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 231                 interrupt-names = "macirq";
 232                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 233                          <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>,
 234                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 235                          <&cru PCLK_GMAC>;
 236                 clock-names = "stmmaceth", "mac_clk_rx",
 237                               "mac_clk_tx", "clk_mac_ref",
 238                               "clk_mac_refout", "aclk_mac",
 239                               "pclk_mac";
 240                 resets = <&cru SRST_MAC>;
 241                 reset-names = "stmmaceth";
 242                 status = "disabled";
 243         };
 244
 245         i2c0: i2c@ff650000 {
 246                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 247                 reg = <0x0 0xff728000 0x0 0x1000>;
 248                 clocks = <&cru PCLK_I2C0>;
 249                 clock-names = "i2c";
 250                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 251                 pinctrl-names = "default";
 252                 pinctrl-0 = <&i2c0_xfer>;
 253                 #address-cells = <1>;
 254                 #size-cells = <0>;
 255                 status = "disabled";
 256         };
 257
 258         i2c2: i2c@ff140000 {
 259                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 260                 reg = <0x0 0xff140000 0x0 0x1000>;
 261                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 262                 #address-cells = <1>;
 263                 #size-cells = <0>;
 264                 clock-names = "i2c";
 265                 clocks = <&cru PCLK_I2C2>;
 266                 pinctrl-names = "default";
 267                 pinctrl-0 = <&i2c2_xfer>;
 268                 status = "disabled";
 269         };
 270
 271         i2c3: i2c@ff150000 {
 272                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 273                 reg = <0x0 0xff150000 0x0 0x1000>;
 274                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 275                 #address-cells = <1>;
 276                 #size-cells = <0>;
 277                 clock-names = "i2c";
 278                 clocks = <&cru PCLK_I2C3>;
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&i2c3_xfer>;
 281                 status = "disabled";
 282         };
 283
 284         i2c4: i2c@ff160000 {
 285                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 286                 reg = <0x0 0xff160000 0x0 0x1000>;
 287                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 288                 #address-cells = <1>;
 289                 #size-cells = <0>;
 290                 clock-names = "i2c";
 291                 clocks = <&cru PCLK_I2C4>;
 292                 pinctrl-names = "default";
 293                 pinctrl-0 = <&i2c4_xfer>;
 294                 status = "disabled";
 295         };
 296
 297         i2c5: i2c@ff170000 {
 298                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 299                 reg = <0x0 0xff170000 0x0 0x1000>;
 300                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 clock-names = "i2c";
 304                 clocks = <&cru PCLK_I2C5>;
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&i2c5_xfer>;
 307                 status = "disabled";
 308         };
 309
 310         uart0: serial@ff180000 {
 311                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 312                 reg = <0x0 0xff180000 0x0 0x100>;
 313                 clock-frequency = <24000000>;
 314                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 315                 clock-names = "baudclk", "apb_pclk";
 316                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 317                 reg-shift = <2>;
 318                 reg-io-width = <4>;
 319                 pinctrl-names = "default";
 320                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 321                 status = "disabled";
 322         };
 323
 324         uart3: serial@ff1b0000 {
 325                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 326                 reg = <0x0 0xff1b0000 0x0 0x100>;
 327                 clock-frequency = <24000000>;
 328                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 329                 clock-names = "baudclk", "apb_pclk";
 330                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 331                 reg-shift = <2>;
 332                 reg-io-width = <4>;
 333                 pinctrl-names = "default";
 334                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 335                 status = "disabled";
 336         };
 337
 338         usb_otg: usb@ff4c0000 {
 339                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 340                              "snps,dwc2";
 341                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 342                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&cru HCLK_OTG>;
 344                 clock-names = "otg";
 345                 dr_mode = "otg";
 346                 g-np-tx-fifo-size = <16>;
 347                 g-rx-fifo-size = <275>;
 348                 g-tx-fifo-size = <256 128 128 64 64 32>;
 349                 g-use-dma;
 350                 status = "disabled";
 351         };
 352
 353         i2c1: i2c@ff660000 {
 354                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 355                 reg = <0x0 0xff660000 0x0 0x1000>;
 356                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 357                 #address-cells = <1>;
 358                 #size-cells = <0>;
 359                 clock-names = "i2c";
 360                 clocks = <&cru PCLK_I2C1>;
 361                 pinctrl-names = "default";
 362                 pinctrl-0 = <&i2c1_xfer>;
 363                 status = "disabled";
 364         };
 365
 366         pwm0: pwm@ff680000 {
 367                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 368                 reg = <0x0 0xff680000 0x0 0x10>;
 369                 #pwm-cells = <3>;
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&pwm0_pin>;
 372                 clocks = <&cru PCLK_RKPWM>;
 373                 clock-names = "pwm";
 374                 status = "disabled";
 375         };
 376
 377         pwm1: pwm@ff680010 {
 378                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 379                 reg = <0x0 0xff680010 0x0 0x10>;
 380                 #pwm-cells = <3>;
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&pwm1_pin>;
 383                 clocks = <&cru PCLK_RKPWM>;
 384                 clock-names = "pwm";
 385                 status = "disabled";
 386         };
 387
 388         pwm2: pwm@ff680020 {
 389                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 390                 reg = <0x0 0xff680020 0x0 0x10>;
 391                 #pwm-cells = <3>;
 392                 clocks = <&cru PCLK_RKPWM>;
 393                 clock-names = "pwm";
 394                 status = "disabled";
 395         };
 396
 397         pwm3: pwm@ff680030 {
 398                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 399                 reg = <0x0 0xff680030 0x0 0x10>;
 400                 #pwm-cells = <3>;
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&pwm3_t2_pin>;
 403                 clocks = <&cru PCLK_RKPWM>;
 404                 clock-names = "pwm";
 405                 status = "disabled";
 406         };
 407
 408         uart2: serial@ff690000 {
 409                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 410                 reg = <0x0 0xff690000 0x0 0x100>;
 411                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 412                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 413                 clock-names = "baudclk", "apb_pclk";
 414                 reg-shift = <2>;
 415                 reg-io-width = <4>;
 416                 pinctrl-names = "default";
 417                 pinctrl-0 = <&uart2_t1_xfer>;
 418                 status = "disabled";
 419         };
 420
 421         pmu: power-management@ff730000 {
 422                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 423                 reg = <0x0 0xff730000 0x0 0x1000>;
 424
 425                 power: power-controller {
 426                         status = "disabled";
 427                         compatible = "rockchip,rk3366-power-controller";
 428                         #power-domain-cells = <1>;
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431
 432                         /*
 433                          * Note: Although SCLK_* are the working clocks
 434                          * of device without including on the NOC, needed for
 435                          * synchronous reset.
 436                          *
 437                          * The clocks on the which NOC:
 438                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 439                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 440                          * ACLK_ISP is on ACLK_ISP_NIU.
 441                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 442                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 443                          *
 444                          * Which clock are device clocks:
 445                          *      clocks          devices
 446                          *      *_IEP           IEP:Image Enhancement Processor
 447                          *      *_ISP           ISP:Image Signal Processing
 448                          *      *_VOP*          VOP:Visual Output Processor
 449                          *      *_RGA           RGA
 450                          *      *_DPHY*         LVDS
 451                          *      *_HDMI          HDMI
 452                          *      *_MIPI_*        MIPI
 453                          */
 454                         pd_vio {
 455                                 reg = <RK3366_PD_VIO>;
 456                                 clocks = <&cru ACLK_IEP>,
 457                                          <&cru ACLK_ISP>,
 458                                          <&cru ACLK_RGA>,
 459                                          <&cru ACLK_HDCP>,
 460                                          <&cru ACLK_VOP_FULL>,
 461                                          <&cru ACLK_VOP_LITE>,
 462                                          <&cru ACLK_VOP_IEP>,
 463                                          <&cru DCLK_VOP_FULL>,
 464                                          <&cru DCLK_VOP_LITE>,
 465                                          <&cru HCLK_IEP>,
 466                                          <&cru HCLK_ISP>,
 467                                          <&cru HCLK_RGA>,
 468                                          <&cru HCLK_VOP_FULL>,
 469                                          <&cru HCLK_VOP_LITE>,
 470                                          <&cru HCLK_VIO_HDCPMMU>,
 471                                          <&cru PCLK_HDMI_CTRL>,
 472                                          <&cru PCLK_HDCP>,
 473                                          <&cru PCLK_MIPI_DSI0>,
 474                                          <&cru SCLK_VOP_FULL_PWM>,
 475                                          <&cru SCLK_HDCP>,
 476                                          <&cru SCLK_ISP>,
 477                                          <&cru SCLK_RGA>,
 478                                          <&cru SCLK_HDMI_CEC>,
 479                                          <&cru SCLK_HDMI_HDCP>;
 480                         };
 481
 482                         /*
 483                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 484                          * (video endecoder & decoder) clocks that on the
 485                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 486                          */
 487                         pd_vpu {
 488                                 reg = <RK3366_PD_VPU>;
 489                                 clocks = <&cru ACLK_VIDEO>,
 490                                          <&cru HCLK_VIDEO>;
 491                         };
 492
 493                         /*
 494                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 495                          * (video decoder) clocks that on the
 496                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 497                          */
 498                         pd_rkvdec {
 499                                 reg = <RK3366_PD_RKVDEC>;
 500                                 clocks = <&cru ACLK_RKVDEC>,
 501                                          <&cru HCLK_RKVDEC>;
 502                         };
 503
 504                         pd_video {
 505                                 reg = <RK3366_PD_VIDEO>;
 506                                 clocks = <&cru ACLK_VIDEO>,
 507                                          <&cru ACLK_RKVDEC>,
 508                                          <&cru HCLK_VIDEO>,
 509                                          <&cru HCLK_RKVDEC>,
 510                                          <&cru SCLK_HEVC_CABAC>,
 511                                          <&cru SCLK_HEVC_CORE>;
 512                         };
 513
 514                         /*
 515                          * Note: ACLK_GPU is the GPU clock,
 516                          * and on the ACLK_GPU_NIU (NOC).
 517                          */
 518                         pd_gpu {
 519                                 reg = <RK3366_PD_GPU>;
 520                                 clocks = <&cru ACLK_GPU>;
 521                         };
 522                 };
 523         };
 524
 525         pmugrf: syscon@ff738000 {
 526                 compatible = "rockchip,rk3366-pmugrf", "syscon";
 527                 reg = <0x0 0xff738000 0x0 0x1000>;
 528         };
 529
 530         amba {
 531                 compatible = "arm,amba-bus";
 532                 #address-cells = <2>;
 533                 #size-cells = <2>;
 534                 ranges;
 535
 536                 dmac_peri: dma-controller@ff250000 {
 537                         compatible = "arm,pl330", "arm,primecell";
 538                         reg = <0x0 0xff250000 0x0 0x4000>;
 539                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 540                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 541                         #dma-cells = <1>;
 542                         clocks = <&cru ACLK_DMAC_PERI>;
 543                         clock-names = "apb_pclk";
 544                 };
 545
 546                 dmac_bus: dma-controller@ff600000 {
 547                         compatible = "arm,pl330", "arm,primecell";
 548                         reg = <0x0 0xff600000 0x0 0x4000>;
 549                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 550                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 551                         #dma-cells = <1>;
 552                         clocks = <&cru ACLK_DMAC_BUS>;
 553                         clock-names = "apb_pclk";
 554                 };
 555         };
 556
 557         cru: clock-controller@ff760000 {
 558                 compatible = "rockchip,rk3366-cru";
 559                 reg = <0x0 0xff760000 0x0 0x1000>;
 560                 rockchip,grf = <&grf>;
 561                 #clock-cells = <1>;
 562                 #reset-cells = <1>;
 563                 assigned-clocks =
 564                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 565                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 566                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 567                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 568                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
 569                 assigned-clock-rates =
 570                         <750000000>, <576000000>,
 571                         <594000000>, <594000000>,
 572                         <480000000>, <520000000>,
 573                         <375000000>, <288000000>,
 574                         <100000000>, <100000000>;
 575         };
 576
 577         grf: syscon@ff770000 {
 578                 compatible = "rockchip,rk3366-grf", "syscon";
 579                 reg = <0x0 0xff770000 0x0 0x1000>;
 580         };
 581
 582         i2s_2ch: i2s-2ch@ff890000 {
 583                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 584                 reg = <0x0 0xff890000 0x0 0x1000>;
 585                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 586                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 587                 dma-names = "tx", "rx";
 588                 clock-names = "i2s_hclk", "i2s_clk";
 589                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 590                 status = "disabled";
 591         };
 592
 593         i2s_8ch: i2s-8ch@ff898000 {
 594                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 595                 reg = <0x0 0xff898000 0x0 0x1000>;
 596                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 597                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 598                 dma-names = "tx", "rx";
 599                 clock-names = "i2s_hclk", "i2s_clk";
 600                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 601                 pinctrl-names = "default";
 602                 pinctrl-0 = <&i2s_8ch_bus>;
 603                 status = "disabled";
 604         };
 605
 606         fb: fb {
 607                 compatible = "rockchip,rk-fb";
 608                 rockchip,disp-mode = <DUAL>;
 609                 status = "disabled";
 610         };
 611
 612         rk_screen: screen {
 613                 compatible = "rockchip,screen";
 614                 status = "disabled";
 615         };
 616
 617         vop_lite: vop@ff8f0000 {
 618                 compatible = "rockchip,rk3366-lcdc-lite";
 619                 rockchip,grf = <&grf>;
 620                 rockchip,pwr18 = <0>;
 621                 rockchip,iommu-enabled = <1>;
 622                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 623                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 624                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 625                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 626                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 627                 reset-names = "axi", "ahb", "dclk";
 628                 status = "disabled";
 629         };
 630
 631         vopl_mmu: vopl-mmu {
 632                 dbgname = "vop";
 633                 compatible = "rockchip,vopl_mmu";
 634                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 635                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 636                 interrupt-names = "vopl_mmu";
 637                 status = "disabled";
 638         };
 639
 640         rga: rga@ff920000 {
 641                 compatible = "rockchip,rga2";
 642                 dev_mode = <1>;
 643                 reg = <0x0 0xff920000 0x0 0x1000>;
 644                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 645                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 646                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 647                 status = "disabled";
 648         };
 649
 650         vop_big: vop@ff930000 {
 651                 compatible = "rockchip,rk3366-lcdc-big";
 652                 rockchip,grf = <&grf>;
 653                 rockchip,prop = <PRMRY>;
 654                 rockchip,pwr18 = <0>;
 655                 rockchip,iommu-enabled = <1>;
 656                 reg = <0x0 0xff930000 0x0 0x23f0>;
 657                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 658                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 659                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 660                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 661                 reset-names = "axi", "ahb", "dclk";
 662                 status = "disabled";
 663         };
 664
 665         vopb_mmu: vopb-mmu {
 666                 dbgname = "vop";
 667                 compatible = "rockchip,vopb_mmu";
 668                 reg = <0x0 0xff932400 0x0 0x100>;
 669                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 670                 interrupt-names = "vop_mmu";
 671                 status = "disabled";
 672         };
 673
 674         dsihost0: mipi@ff960000 {
 675                 compatible = "rockchip,rk3368-dsi";
 676                 rockchip,prop = <0>;
 677                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 678                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 679                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 680                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 681                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 682                 status = "disabled";
 683         };
 684
 685         lvds: lvds@ff968000 {
 686                 compatible = "rockchip,rk3366-lvds";
 687                 rockchip,grf = <&grf>;
 688                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 689                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 690                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 691                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 692                 status = "disabled";
 693         };
 694
 695         hdmi: hdmi@ff980000 {
 696                 compatible = "rockchip,rk3366-hdmi";
 697                 reg = <0x0 0xff980000 0x0 0x20000>;
 698                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 699                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 700                 clocks = <&cru PCLK_HDMI_CTRL>,
 701                          <&cru SCLK_HDMI_HDCP>,
 702                          <&cru SCLK_HDMI_CEC>,
 703                          <&cru DCLK_HDMIPHY>;
 704                 clock-names = "pclk_hdmi",
 705                               "hdcp_clk_hdmi",
 706                               "cec_clk_hdmi",
 707                               "dclk_hdmi_phy";
 708                 resets = <&cru SRST_HDMI>;
 709                 reset-names = "hdmi";
 710                 pinctrl-names = "default", "gpio";
 711                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 712                 pinctrl-1 = <&i2c5_gpio>;
 713                 status = "disabled";
 714         };
 715
 716         pinctrl: pinctrl {
 717                 compatible = "rockchip,rk3366-pinctrl";
 718                 rockchip,grf = <&grf>;
 719                 rockchip,pmu = <&pmugrf>;
 720                 #address-cells = <0x2>;
 721                 #size-cells = <0x2>;
 722                 ranges;
 723
 724                 gpio0: gpio0@ff750000 {
 725                         compatible = "rockchip,gpio-bank";
 726                         reg = <0x0 0xff750000 0x0 0x100>;
 727                         clocks = <&cru PCLK_GPIO0>;
 728                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 729
 730                         gpio-controller;
 731                         #gpio-cells = <0x2>;
 732
 733                         interrupt-controller;
 734                         #interrupt-cells = <0x2>;
 735                 };
 736
 737                 gpio1: gpio1@ff780000 {
 738                         compatible = "rockchip,gpio-bank";
 739                         reg = <0x0 0xff758000 0x0 0x100>;
 740                         clocks = <&cru PCLK_GPIO1>;
 741                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 742
 743                         gpio-controller;
 744                         #gpio-cells = <0x2>;
 745
 746                         interrupt-controller;
 747                         #interrupt-cells = <0x2>;
 748                 };
 749
 750                 gpio2: gpio2@ff790000 {
 751                         compatible = "rockchip,gpio-bank";
 752                         reg = <0x0 0xff790000 0x0 0x100>;
 753                         clocks = <&cru PCLK_GPIO2>;
 754                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 755
 756                         gpio-controller;
 757                         #gpio-cells = <0x2>;
 758
 759                         interrupt-controller;
 760                         #interrupt-cells = <0x2>;
 761                 };
 762
 763                 gpio3: gpio3@ff7a0000 {
 764                         compatible = "rockchip,gpio-bank";
 765                         reg = <0x0 0xff7a0000 0x0 0x100>;
 766                         clocks = <&cru PCLK_GPIO3>;
 767                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 768
 769                         gpio-controller;
 770                         #gpio-cells = <0x2>;
 771
 772                         interrupt-controller;
 773                         #interrupt-cells = <0x2>;
 774                 };
 775
 776                 gpio4: gpio4@ff7b0000 {
 777                         compatible = "rockchip,gpio-bank";
 778                         reg = <0x0 0xff7b0000 0x0 0x100>;
 779                         clocks = <&cru PCLK_GPIO4>;
 780                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 781
 782                         gpio-controller;
 783                         #gpio-cells = <0x2>;
 784
 785                         interrupt-controller;
 786                         #interrupt-cells = <0x2>;
 787                 };
 788
 789                 gpio5: gpio5@ff7c0000 {
 790                         compatible = "rockchip,gpio-bank";
 791                         reg = <0x0 0xff7c0000 0x0 0x100>;
 792                         clocks = <&cru PCLK_GPIO5>;
 793                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 794
 795                         gpio-controller;
 796                         #gpio-cells = <0x2>;
 797
 798                         interrupt-controller;
 799                         #interrupt-cells = <0x2>;
 800                 };
 801
 802                 pcfg_pull_up: pcfg-pull-up {
 803                         bias-pull-up;
 804                 };
 805
 806                 pcfg_pull_down: pcfg-pull-down {
 807                         bias-pull-down;
 808                 };
 809
 810                 pcfg_pull_none: pcfg-pull-none {
 811                         bias-disable;
 812                 };
 813
 814                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 815                         bias-disable;
 816                         drive-strength = <12>;
 817                 };
 818
 819                 emmc {
 820                         emmc_clk: emmc-clk {
 821                                 rockchip,pins =
 822                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
 823                         };
 824
 825                         emmc_cmd: emmc-cmd {
 826                                 rockchip,pins =
 827                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
 828                         };
 829
 830                         emmc_pwr: emmc-pwr {
 831                                 rockchip,pins =
 832                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
 833                         };
 834
 835                         emmc_bus1: emmc-bus1 {
 836                                 rockchip,pins =
 837                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
 838                         };
 839
 840                         emmc_bus4: emmc-bus4 {
 841                                 rockchip,pins =
 842                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 843                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 844                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 845                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
 846                         };
 847
 848                         emmc_bus8: emmc-bus8 {
 849                                 rockchip,pins =
 850                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 851                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 852                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 853                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
 854                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
 855                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
 856                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
 857                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
 858                         };
 859                 };
 860
 861                 sdmmc {
 862                         sdmmc_cd: sdmmc-cd {
 863                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
 864                         };
 865
 866                         sdmmc_bus1: sdmmc-bus1 {
 867                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
 868                         };
 869
 870                         sdmmc_bus4: sdmmc-bus4 {
 871                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
 872                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
 873                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
 874                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
 875                         };
 876
 877                         sdmmc_clk: sdmmc-clk {
 878                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
 879                         };
 880
 881                         sdmmc_cmd: sdmmc-cmd {
 882                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
 883                         };
 884                 };
 885
 886                 sdio {
 887                         sdio_bus1: sdio-bus1 {
 888                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
 889                         };
 890
 891                         sdio_bus4: sdio-bus4 {
 892                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
 893                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
 894                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
 895                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
 896                         };
 897
 898                         sdio_cmd: sdio-cmd {
 899                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
 900                         };
 901
 902                         sdio_clk: sdio-clk {
 903                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
 904                         };
 905
 906                         sdio_cd: sdio-cd {
 907                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
 908                         };
 909
 910                         sdio_wp: sdio-wp {
 911                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
 912                         };
 913
 914                         sdio_int: sdio-int {
 915                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
 916                         };
 917
 918                         sdio_pwr: sdio-pwr {
 919                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
 920                         };
 921                 };
 922
 923                 hdmi_i2c {
 924                         hdmii2c_xfer: hdmii2c-xfer {
 925                                 rockchip,pins =
 926                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
 927                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
 928                         };
 929                 };
 930
 931                 hdmi_pin {
 932                         hdmi_cec: hdmi-cec {
 933                                 rockchip,pins =
 934                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
 935                         };
 936                 };
 937
 938                 i2c0 {
 939                         i2c0_xfer: i2c0-xfer {
 940                                 rockchip,pins =
 941                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
 942                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
 943                         };
 944                 };
 945
 946                 i2c1 {
 947                         i2c1_xfer: i2c1-xfer {
 948                                 rockchip,pins =
 949                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
 950                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
 951                         };
 952                 };
 953
 954                 i2c2 {
 955                         i2c2_xfer: i2c2-xfer {
 956                                 rockchip,pins =
 957                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
 958                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
 959                         };
 960                 };
 961
 962                 i2c3 {
 963                         i2c3_xfer: i2c3-xfer {
 964                                 rockchip,pins =
 965                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
 966                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
 967                         };
 968                 };
 969
 970                 i2c4 {
 971                         i2c4_xfer: i2c4-xfer {
 972                                 rockchip,pins =
 973                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
 974                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
 975                         };
 976                 };
 977
 978                 i2c5 {
 979                         i2c5_xfer: i2c5-xfer {
 980                                 rockchip,pins =
 981                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
 982                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
 983                         };
 984                         i2c5_gpio: i2c5-gpio {
 985                                 rockchip,pins =
 986                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
 987                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
 988                         };
 989                 };
 990
 991                 i2s {
 992                         i2s_8ch_bus: i2s-8ch-bus {
 993                                 rockchip,pins =
 994                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
 995                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 996                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
 997                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
 998                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
 999                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1000                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1001                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1002                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1003                         };
1004                 };
1005
1006                 spi0 {
1007                         spi0_clk: spi0-clk {
1008                                 rockchip,pins =
1009                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1010                         };
1011                         spi0_cs0: spi0-cs0 {
1012                                 rockchip,pins =
1013                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1014                         };
1015                         spi0_cs1: spi0-cs1 {
1016                                 rockchip,pins =
1017                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1018                         };
1019                         spi0_tx: spi0-tx {
1020                                 rockchip,pins =
1021                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1022                         };
1023                         spi0_rx: spi0-rx {
1024                                 rockchip,pins =
1025                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1026                         };
1027                 };
1028
1029                 spi1 {
1030                         spi1_clk: spi1-clk {
1031                                 rockchip,pins =
1032                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1033                         };
1034                         spi1_cs0: spi1-cs0 {
1035                                 rockchip,pins =
1036                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1037                         };
1038                         spi1_tx: spi1-tx {
1039                                 rockchip,pins =
1040                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1041                         };
1042                         spi1_rx: spi1-rx {
1043                                 rockchip,pins =
1044                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1045                         };
1046                 };
1047
1048                 uart0 {
1049                         uart0_xfer: uart0-xfer {
1050                                 rockchip,pins =
1051                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1052                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1053                         };
1054
1055                         uart0_cts: uart0-cts {
1056                                 rockchip,pins =
1057                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1058                         };
1059
1060                         uart0_rts: uart0-rts {
1061                                 rockchip,pins =
1062                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1063                         };
1064                 };
1065
1066                 uart2_t0 {
1067                         uart2_t0_xfer: uart2_t0-xfer {
1068                                 rockchip,pins =
1069                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1070                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1071                         };
1072                         /* no rts / cts for uart2 */
1073                 };
1074
1075                 uart2_t1 {
1076                         uart2_t1_xfer: uart2_t1-xfer {
1077                                 rockchip,pins =
1078                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1079                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1080                         };
1081                         /* no rts / cts for uart2 */
1082                 };
1083
1084                 uart2_t2 {
1085                         uart2_t2_xfer: uart2_t2-xfer {
1086                                 rockchip,pins =
1087                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1088                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1089                         };
1090                         /* no rts / cts for uart2 */
1091                 };
1092
1093                 uart3 {
1094                         uart3_xfer: uart3-xfer {
1095                                 rockchip,pins =
1096                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1097                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1098                         };
1099
1100                         uart3_cts: uart3-cts {
1101                                 rockchip,pins =
1102                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1103                         };
1104
1105                         uart3_rts: uart3-rts {
1106                                 rockchip,pins =
1107                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1108                         };
1109                 };
1110
1111                 pwm0 {
1112                         pwm0_pin: pwm0-pin {
1113                                 rockchip,pins =
1114                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1115                         };
1116                 };
1117
1118                 pwm1 {
1119                         pwm1_pin: pwm1-pin {
1120                                 rockchip,pins =
1121                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1122                         };
1123                 };
1124
1125                 pwm2_t0 {
1126                         pwm2_t0_pin: pwm2_t0-pin {
1127                                 rockchip,pins =
1128                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1129                         };
1130                 };
1131
1132                 pwm2_t1 {
1133                         pwm2_t1_pin: pwm2_t1-pin {
1134                                 rockchip,pins =
1135                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1136                         };
1137                 };
1138
1139                 pwm3_t0 {
1140                         pwm3_t0_pin: pwm3_t0-pin {
1141                                 rockchip,pins =
1142                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1143                         };
1144                 };
1145
1146                 pwm3_t1 {
1147                         pwm3_t1_pin: pwm3_t1-pin {
1148                                 rockchip,pins =
1149                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1150                         };
1151                 };
1152
1153                 pwm3_t2 {
1154                         pwm3_t2_pin: pwm3_t2-pin {
1155                                 rockchip,pins =
1156                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1157                         };
1158                 };
1159
1160                 lcdc {
1161                         lcdc_lcdc: lcdc-lcdc {
1162                                 rockchip,pins =
1163                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1164                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1165                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1166                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1167                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1168                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1169                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1170                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1171                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1172                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1173                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1174                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1175                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1176                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1177                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1178                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1179                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1180                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1181                         };
1182
1183                         lcdc_gpio: lcdc-gpio {
1184                                 rockchip,pins =
1185                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1186                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1187                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1188                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1189                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1190                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1191                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1192                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1193                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1194                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1195                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1196                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1197                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1198                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1199                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1200                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1201                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1202                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1203                         };
1204                 };
1205
1206                 gmac {
1207                         rgmii_pins: rgmii-pins {
1208                                 rockchip,pins =
1209                                         /* mac_rxd3 */
1210                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1211                                         /* mac_rxd2 */
1212                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1213                                         /* mac_txd3 */
1214                                         <2 5  RK_FUNC_1 &pcfg_pull_none>,
1215                                         /* mac_txd2 */
1216                                         <2 4  RK_FUNC_1 &pcfg_pull_none>,
1217                                         /* mac_rxd1 */
1218                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1219                                         /* mac_rxd0 */
1220                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1221                                         /* mac_txd1 */
1222                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1223                                         /* mac_txd0 */
1224                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1225                                         /* mac_crs */
1226                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1227                                         /* mac_rxclkin */
1228                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1229                                         /* mac_mdio */
1230                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1231                                         /* mac_txen */
1232                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1233                                         /* mac_clk */
1234                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1235                                         /* mac_rxer */
1236                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1237                                         /* mac_rxdv */
1238                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1239                                         /* mac_mdc */
1240                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1241                         };
1242
1243                         rmii_pins: rmii-pins {
1244                                 rockchip,pins =
1245                                         /* mac_rxd1 */
1246                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1247                                         /* mac_rxd0 */
1248                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1249                                         /* mac_txd1 */
1250                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1251                                         /* mac_txd0 */
1252                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1253                                         /* mac_crs */
1254                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1255                                         /* mac_rxclkin */
1256                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1257                                         /* mac_mdio */
1258                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1259                                         /* mac_txen */
1260                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1261                                         /* mac_clk */
1262                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1263                                         /* mac_rxer */
1264                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1265                                         /* mac_rxdv */
1266                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1267                                         /* mac_mdc */
1268                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1269                         };
1270                 };
1271
1272                 eth_phy {
1273                         eth_phy_pwr: eth-phy-pwr {
1274                                 rockchip,pins =
1275                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
1276                         };
1277                 };
1278         };
1279 };