2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/power/rk3366-power.h>
50 #include <dt-bindings/soc/rockchip_boot-mode.h>
53 compatible = "rockchip,rk3366";
54 interrupt-parent = <&gic>;
73 #address-cells = <0x2>;
78 compatible = "arm,cortex-a53","arm,armv8";
80 enable-method = "psci";
81 clocks = <&cru ARMCLK>;
82 operating-points-v2 = <&cpu0_opp_table>;
87 compatible = "arm,cortex-a53","arm,armv8";
89 enable-method = "psci";
90 operating-points-v2 = <&cpu0_opp_table>;
95 compatible = "arm,cortex-a53","arm,armv8";
97 enable-method = "psci";
98 operating-points-v2 = <&cpu0_opp_table>;
103 compatible = "arm,cortex-a53","arm,armv8";
105 enable-method = "psci";
106 operating-points-v2 = <&cpu0_opp_table>;
110 cpu0_opp_table: opp_table0 {
111 compatible = "operating-points-v2";
115 opp-hz = /bits/ 64 <408000000>;
116 opp-microvolt = <1200000>;
117 clock-latency-ns = <40000>;
121 opp-hz = /bits/ 64 <600000000>;
122 opp-microvolt = <1200000>;
125 opp-hz = /bits/ 64 <816000000>;
126 opp-microvolt = <1200000>;
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1200000>;
133 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <1200000>;
139 compatible = "arm,psci-1.0";
144 compatible = "arm,armv8-timer";
145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
152 compatible = "arm,cortex-a53-pmu";
153 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
157 interrupt-affinity = <&cpu0>,
164 compatible = "fixed-clock";
166 clock-frequency = <24000000>;
167 clock-output-names = "xin24m";
170 gic: interrupt-controller@ffb71000 {
171 compatible = "arm,gic-400";
172 interrupt-controller;
173 #interrupt-cells = <3>;
174 #address-cells = <0>;
176 reg = <0x0 0xffb71000 0x0 0x1000>,
177 <0x0 0xffb72000 0x0 0x1000>,
178 <0x0 0xffb74000 0x0 0x2000>,
179 <0x0 0xffb76000 0x0 0x2000>;
180 interrupts = <GIC_PPI 9
181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
184 nandc0: nandc@ff0c0000 {
185 compatible = "rockchip,rk-nandc";
186 reg = <0x0 0xff0c0000 0x0 0x4000>;
187 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
190 clock-names = "clk_nandc", "hclk_nandc";
194 saradc: saradc@ff100000 {
195 compatible = "rockchip,saradc";
196 reg = <0x0 0xff100000 0x0 0x100>;
197 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
198 #io-channel-cells = <1>;
199 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
200 clock-names = "saradc", "apb_pclk";
205 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
206 reg = <0x0 0xff110000 0x0 0x1000>;
207 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
208 clock-names = "spiclk", "apb_pclk";
209 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
212 #address-cells = <1>;
218 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
219 reg = <0x0 0xff120000 0x0 0x1000>;
220 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
221 clock-names = "spiclk", "apb_pclk";
222 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
225 #address-cells = <1>;
230 scr: rkscr@ff1d0000 {
231 compatible = "rockchip-scr";
232 reg = <0x0 0xff1d0000 0x0 0x10000>;
233 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
234 #address-cells = <1>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
238 clocks = <&cru PCLK_SIM>;
239 clock-names = "g_pclk_sim_card";
243 sdmmc: rksdmmc@ff400000 {
244 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
245 clock-freq-min-max = <400000 150000000>;
246 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
247 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
248 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
249 fifo-depth = <0x100>;
250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
251 reg = <0x0 0xff400000 0x0 0x4000>;
255 sdio: rksdmmc@ff410000 {
256 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
257 clock-freq-min-max = <400000 150000000>;
258 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
259 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
260 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
261 fifo-depth = <0x100>;
262 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
263 reg = <0x0 0xff410000 0x0 0x4000>;
267 emmc: rksdmmc@ff420000 {
268 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
269 clock-freq-min-max = <400000 150000000>;
270 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
271 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
272 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
273 fifo-depth = <0x100>;
274 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
275 reg = <0x0 0xff420000 0x0 0x4000>;
280 compatible = "rockchip,rk3366-gmac";
281 reg = <0x0 0xff440000 0x0 0x10000>;
282 rockchip,grf = <&grf>;
283 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "macirq";
285 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
286 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
287 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
289 clock-names = "stmmaceth", "mac_clk_rx",
290 "mac_clk_tx", "clk_mac_ref",
291 "clk_mac_refout", "aclk_mac",
293 resets = <&cru SRST_MAC>;
294 reset-names = "stmmaceth";
299 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
300 reg = <0x0 0xff728000 0x0 0x1000>;
301 clocks = <&cru PCLK_I2C0>;
303 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&i2c0_xfer>;
306 #address-cells = <1>;
312 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
313 reg = <0x0 0xff140000 0x0 0x1000>;
314 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
318 clocks = <&cru PCLK_I2C2>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c2_xfer>;
325 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
326 reg = <0x0 0xff150000 0x0 0x1000>;
327 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
328 #address-cells = <1>;
331 clocks = <&cru PCLK_I2C3>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&i2c3_xfer>;
338 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
339 reg = <0x0 0xff160000 0x0 0x1000>;
340 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
341 #address-cells = <1>;
344 clocks = <&cru PCLK_I2C4>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&i2c4_xfer>;
351 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
352 reg = <0x0 0xff170000 0x0 0x1000>;
353 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
357 clocks = <&cru PCLK_I2C5>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&i2c5_xfer>;
363 uart0: serial@ff180000 {
364 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
365 reg = <0x0 0xff180000 0x0 0x100>;
366 clock-frequency = <24000000>;
367 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
368 clock-names = "baudclk", "apb_pclk";
369 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
377 uart3: serial@ff1b0000 {
378 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
379 reg = <0x0 0xff1b0000 0x0 0x100>;
380 clock-frequency = <24000000>;
381 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
382 clock-names = "baudclk", "apb_pclk";
383 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
392 compatible = "rockchip,rk336x-usb-phy";
393 rockchip,grf = <&grf>;
394 #address-cells = <1>;
410 usb_host0_echi: usb@ff480000 {
411 compatible = "generic-ehci";
412 reg = <0x0 0xff480000 0x0 0x20000>;
413 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
415 clock-names = "sclk_otgphy0", "hclk_host0";
421 usb_host0_ohci: usb@ff4a0000 {
422 compatible = "generic-ohci";
423 reg = <0x0 0xff4a0000 0x0 0x20000>;
424 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
426 clock-names = "sclk_otgphy0", "hclk_host0";
430 usb_otg: usb@ff4c0000 {
431 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
433 reg = <0x0 0xff4c0000 0x0 0x40000>;
434 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&cru HCLK_OTG>;
438 g-np-tx-fifo-size = <16>;
439 g-rx-fifo-size = <275>;
440 g-tx-fifo-size = <256 128 128 64 64 32>;
446 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
447 reg = <0x0 0xff660000 0x0 0x1000>;
448 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
449 #address-cells = <1>;
452 clocks = <&cru PCLK_I2C1>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&i2c1_xfer>;
459 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
460 reg = <0x0 0xff680000 0x0 0x10>;
462 pinctrl-names = "default";
463 pinctrl-0 = <&pwm0_pin>;
464 clocks = <&cru PCLK_RKPWM>;
470 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
471 reg = <0x0 0xff680010 0x0 0x10>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&pwm1_pin>;
475 clocks = <&cru PCLK_RKPWM>;
481 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
482 reg = <0x0 0xff680020 0x0 0x10>;
484 clocks = <&cru PCLK_RKPWM>;
490 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
491 reg = <0x0 0xff680030 0x0 0x10>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&pwm3_t2_pin>;
495 clocks = <&cru PCLK_RKPWM>;
500 uart2: serial@ff690000 {
501 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
502 reg = <0x0 0xff690000 0x0 0x100>;
503 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
505 clock-names = "baudclk", "apb_pclk";
508 pinctrl-names = "default";
509 pinctrl-0 = <&uart2_t1_xfer>;
513 pmu: power-management@ff730000 {
514 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
515 reg = <0x0 0xff730000 0x0 0x1000>;
517 power: power-controller {
519 compatible = "rockchip,rk3366-power-controller";
520 #power-domain-cells = <1>;
521 #address-cells = <1>;
525 * Note: Although SCLK_* are the working clocks
526 * of device without including on the NOC, needed for
529 * The clocks on the which NOC:
530 * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
531 * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
532 * ACLK_ISP is on ACLK_ISP_NIU.
533 * ACLK_HDCP is on ACLK_HDCP_NIU.
534 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
536 * Which clock are device clocks:
538 * *_IEP IEP:Image Enhancement Processor
539 * *_ISP ISP:Image Signal Processing
540 * *_VOP* VOP:Visual Output Processor
547 reg = <RK3366_PD_VIO>;
548 clocks = <&cru ACLK_IEP>,
552 <&cru ACLK_VOP_FULL>,
553 <&cru ACLK_VOP_LITE>,
555 <&cru DCLK_VOP_FULL>,
556 <&cru DCLK_VOP_LITE>,
560 <&cru HCLK_VOP_FULL>,
561 <&cru HCLK_VOP_LITE>,
562 <&cru HCLK_VIO_HDCPMMU>,
563 <&cru PCLK_HDMI_CTRL>,
565 <&cru PCLK_MIPI_DSI0>,
566 <&cru SCLK_VOP_FULL_PWM>,
570 <&cru SCLK_HDMI_CEC>,
571 <&cru SCLK_HDMI_HDCP>;
575 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
576 * (video endecoder & decoder) clocks that on the
577 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
580 reg = <RK3366_PD_VPU>;
581 clocks = <&cru ACLK_VIDEO>,
586 * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
587 * (video decoder) clocks that on the
588 * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
591 reg = <RK3366_PD_RKVDEC>;
592 clocks = <&cru ACLK_RKVDEC>,
597 reg = <RK3366_PD_VIDEO>;
598 clocks = <&cru ACLK_VIDEO>,
602 <&cru SCLK_HEVC_CABAC>,
603 <&cru SCLK_HEVC_CORE>;
607 * Note: ACLK_GPU is the GPU clock,
608 * and on the ACLK_GPU_NIU (NOC).
611 reg = <RK3366_PD_GPU>;
612 clocks = <&cru ACLK_GPU>;
617 pmugrf: syscon@ff738000 {
618 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
619 reg = <0x0 0xff738000 0x0 0x1000>;
622 compatible = "syscon-reboot-mode";
624 mode-normal = <BOOT_NORMAL>;
625 mode-recovery = <BOOT_RECOVERY>;
626 mode-fastboot = <BOOT_FASTBOOT>;
627 mode-loader = <BOOT_LOADER>;
632 compatible = "arm,amba-bus";
633 #address-cells = <2>;
637 dmac_peri: dma-controller@ff250000 {
638 compatible = "arm,pl330", "arm,primecell";
639 reg = <0x0 0xff250000 0x0 0x4000>;
640 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&cru ACLK_DMAC_PERI>;
644 clock-names = "apb_pclk";
647 dmac_bus: dma-controller@ff600000 {
648 compatible = "arm,pl330", "arm,primecell";
649 reg = <0x0 0xff600000 0x0 0x4000>;
650 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cru ACLK_DMAC_BUS>;
654 clock-names = "apb_pclk";
658 cru: clock-controller@ff760000 {
659 compatible = "rockchip,rk3366-cru";
660 reg = <0x0 0xff760000 0x0 0x1000>;
661 rockchip,grf = <&grf>;
665 <&cru PLL_CPLL>, <&cru PLL_GPLL>,
666 <&cru PLL_NPLL>, <&cru PLL_MPLL>,
667 <&cru PLL_WPLL>, <&cru PLL_BPLL>,
668 <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
669 <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
670 assigned-clock-rates =
671 <750000000>, <576000000>,
672 <594000000>, <594000000>,
673 <960000000>, <520000000>,
674 <375000000>, <288000000>,
675 <100000000>, <100000000>;
678 grf: syscon@ff770000 {
679 compatible = "rockchip,rk3366-grf", "syscon";
680 reg = <0x0 0xff770000 0x0 0x1000>;
683 wdt: watchdog@ff800000 {
684 compatible = "snps,dw-wdt";
685 reg = <0x0 0xff800000 0x0 0x100>;
686 clocks = <&cru PCLK_WDT>;
687 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
691 spdif: spdif@ff880000 {
692 compatible = "rockchip,rk3366-spdif";
693 reg = <0x0 0xff880000 0x0 0x1000>;
694 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
695 dmas = <&dmac_bus 3>;
697 clock-names = "hclk", "mclk";
698 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&spdif_bus>;
704 i2s_2ch: i2s-2ch@ff890000 {
705 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
706 reg = <0x0 0xff890000 0x0 0x1000>;
707 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
708 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
709 dma-names = "tx", "rx";
710 clock-names = "i2s_hclk", "i2s_clk";
711 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
715 i2s_8ch: i2s-8ch@ff898000 {
716 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
717 reg = <0x0 0xff898000 0x0 0x1000>;
718 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
719 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
720 dma-names = "tx", "rx";
721 clock-names = "i2s_hclk", "i2s_clk";
722 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&i2s_8ch_bus>;
729 compatible = "rockchip,rk-fb";
730 rockchip,disp-mode = <DUAL>;
735 compatible = "rockchip,screen";
739 vop_lite: vop@ff8f0000 {
740 compatible = "rockchip,rk3366-lcdc-lite";
741 rockchip,grf = <&grf>;
742 rockchip,pwr18 = <0>;
743 rockchip,iommu-enabled = <1>;
744 reg = <0x0 0xff8f0000 0x0 0x1000>;
745 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
747 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
748 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
749 reset-names = "axi", "ahb", "dclk";
755 compatible = "rockchip,vopl_mmu";
756 reg = <0x0 0xff8f0f00 0x0 0x100>;
757 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
758 interrupt-names = "vopl_mmu";
763 compatible = "rockchip,iep";
765 reg = <0x0 0xff900000 0x0 0x800>;
766 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
768 clock-names = "aclk_iep", "hclk_iep";
774 compatible = "rockchip,rga2";
776 reg = <0x0 0xff920000 0x0 0x1000>;
777 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
779 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
783 vop_big: vop@ff930000 {
784 compatible = "rockchip,rk3366-lcdc-big";
785 rockchip,grf = <&grf>;
786 rockchip,prop = <PRMRY>;
787 rockchip,pwr18 = <0>;
788 rockchip,iommu-enabled = <1>;
789 reg = <0x0 0xff930000 0x0 0x23f0>;
790 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
792 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
793 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
794 reset-names = "axi", "ahb", "dclk";
800 compatible = "rockchip,vopb_mmu";
801 reg = <0x0 0xff932400 0x0 0x100>;
802 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
803 interrupt-names = "vop_mmu";
809 compatible = "rockchip,iep_mmu";
810 reg = <0x0 0xff900800 0x0 0x100>;
811 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
812 interrupt-names = "iep_mmu";
818 compatible = "rockchip,vpu_mmu";
819 reg = <0x0 0xff9a0800 0x0 0x100>;
820 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
821 interrupt-names = "vpu_mmu";
827 compatible = "rockchip,vdec_mmu";
828 reg = <0x0 0xff9b0480 0x0 0x40>,
829 <0x0 0xff9b04c0 0x0 0x40>;
830 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
831 interrupt-names = "vdec_mmu";
835 dsihost0: mipi@ff960000 {
836 compatible = "rockchip,rk3368-dsi";
838 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
839 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
840 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
842 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
846 lvds: lvds@ff968000 {
847 compatible = "rockchip,rk3366-lvds";
848 rockchip,grf = <&grf>;
849 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
850 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
851 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
852 clock-names = "pclk_lvds", "pclk_lvds_ctl";
856 hdmi: hdmi@ff980000 {
857 compatible = "rockchip,rk3366-hdmi";
858 reg = <0x0 0xff980000 0x0 0x20000>;
859 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
860 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&cru PCLK_HDMI_CTRL>,
862 <&cru SCLK_HDMI_HDCP>,
863 <&cru SCLK_HDMI_CEC>,
865 clock-names = "pclk_hdmi",
869 resets = <&cru SRST_HDMI>;
870 reset-names = "hdmi";
871 pinctrl-names = "default", "gpio";
872 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
873 pinctrl-1 = <&i2c5_gpio>;
877 vpu: vpu_service@ff9a0000 {
878 compatible = "rockchip,vpu_service";
879 rockchip,grf = <&grf>;
881 reg = <0x0 0xff9a0000 0x0 0x800>;
882 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
884 interrupt-names = "irq_dec", "irq_enc";
885 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
886 clock-names = "aclk_vcodec", "hclk_vcodec";
887 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
888 reset-names = "video_h", "video_a";
889 name = "vpu_service";
894 rkvdec: rkvdec@ff9b0000 {
895 compatible = "rockchip,rkvdec";
896 rockchip,grf = <&grf>;
898 reg = <0x0 0xff9b0000 0x0 0x400>;
899 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
900 interrupt-names = "irq_dec";
901 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
902 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
903 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
904 reset-names = "video_h", "video_a";
911 compatible = "rockchip,rk3366-pinctrl";
912 rockchip,grf = <&grf>;
913 rockchip,pmu = <&pmugrf>;
914 #address-cells = <0x2>;
918 gpio0: gpio0@ff750000 {
919 compatible = "rockchip,gpio-bank";
920 reg = <0x0 0xff750000 0x0 0x100>;
921 clocks = <&cru PCLK_GPIO0>;
922 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
927 interrupt-controller;
928 #interrupt-cells = <0x2>;
931 gpio1: gpio1@ff780000 {
932 compatible = "rockchip,gpio-bank";
933 reg = <0x0 0xff758000 0x0 0x100>;
934 clocks = <&cru PCLK_GPIO1>;
935 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
940 interrupt-controller;
941 #interrupt-cells = <0x2>;
944 gpio2: gpio2@ff790000 {
945 compatible = "rockchip,gpio-bank";
946 reg = <0x0 0xff790000 0x0 0x100>;
947 clocks = <&cru PCLK_GPIO2>;
948 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
953 interrupt-controller;
954 #interrupt-cells = <0x2>;
957 gpio3: gpio3@ff7a0000 {
958 compatible = "rockchip,gpio-bank";
959 reg = <0x0 0xff7a0000 0x0 0x100>;
960 clocks = <&cru PCLK_GPIO3>;
961 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
966 interrupt-controller;
967 #interrupt-cells = <0x2>;
970 gpio4: gpio4@ff7b0000 {
971 compatible = "rockchip,gpio-bank";
972 reg = <0x0 0xff7b0000 0x0 0x100>;
973 clocks = <&cru PCLK_GPIO4>;
974 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
979 interrupt-controller;
980 #interrupt-cells = <0x2>;
983 gpio5: gpio5@ff7c0000 {
984 compatible = "rockchip,gpio-bank";
985 reg = <0x0 0xff7c0000 0x0 0x100>;
986 clocks = <&cru PCLK_GPIO5>;
987 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
992 interrupt-controller;
993 #interrupt-cells = <0x2>;
996 pcfg_pull_up: pcfg-pull-up {
1000 pcfg_pull_down: pcfg-pull-down {
1004 pcfg_pull_none: pcfg-pull-none {
1008 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1010 drive-strength = <12>;
1014 emmc_clk: emmc-clk {
1016 <3 4 RK_FUNC_2 &pcfg_pull_none>;
1019 emmc_cmd: emmc-cmd {
1021 <2 26 RK_FUNC_2 &pcfg_pull_up>;
1024 emmc_pwr: emmc-pwr {
1026 <2 27 RK_FUNC_2 &pcfg_pull_up>;
1029 emmc_bus1: emmc-bus1 {
1031 <2 18 RK_FUNC_2 &pcfg_pull_up>;
1034 emmc_bus4: emmc-bus4 {
1036 <2 18 RK_FUNC_2 &pcfg_pull_up>,
1037 <2 19 RK_FUNC_2 &pcfg_pull_up>,
1038 <2 20 RK_FUNC_2 &pcfg_pull_up>,
1039 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1042 emmc_bus8: emmc-bus8 {
1044 <2 18 RK_FUNC_2 &pcfg_pull_up>,
1045 <2 19 RK_FUNC_2 &pcfg_pull_up>,
1046 <2 20 RK_FUNC_2 &pcfg_pull_up>,
1047 <2 21 RK_FUNC_2 &pcfg_pull_up>,
1048 <2 22 RK_FUNC_2 &pcfg_pull_up>,
1049 <2 23 RK_FUNC_2 &pcfg_pull_up>,
1050 <2 24 RK_FUNC_2 &pcfg_pull_up>,
1051 <2 25 RK_FUNC_2 &pcfg_pull_up>;
1056 sdmmc_cd: sdmmc-cd {
1057 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1060 sdmmc_bus1: sdmmc-bus1 {
1061 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1064 sdmmc_bus4: sdmmc-bus4 {
1065 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1066 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1067 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1068 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1071 sdmmc_clk: sdmmc-clk {
1072 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1075 sdmmc_cmd: sdmmc-cmd {
1076 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1081 sdio_bus1: sdio-bus1 {
1082 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1085 sdio_bus4: sdio-bus4 {
1086 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1087 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1088 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1089 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1092 sdio_cmd: sdio-cmd {
1093 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1096 sdio_clk: sdio-clk {
1097 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1101 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1105 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1108 sdio_int: sdio-int {
1109 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1112 sdio_pwr: sdio-pwr {
1113 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1118 hdmii2c_xfer: hdmii2c-xfer {
1120 <5 13 RK_FUNC_2 &pcfg_pull_none>,
1121 <5 14 RK_FUNC_2 &pcfg_pull_none>;
1126 hdmi_cec: hdmi-cec {
1128 <5 12 RK_FUNC_1 &pcfg_pull_none>;
1133 i2c0_xfer: i2c0-xfer {
1135 <0 3 RK_FUNC_1 &pcfg_pull_none>,
1136 <0 4 RK_FUNC_1 &pcfg_pull_none>;
1141 i2c1_xfer: i2c1-xfer {
1143 <4 25 RK_FUNC_1 &pcfg_pull_none>,
1144 <4 26 RK_FUNC_1 &pcfg_pull_none>;
1149 i2c2_xfer: i2c2-xfer {
1151 <5 15 RK_FUNC_2 &pcfg_pull_none>,
1152 <5 16 RK_FUNC_2 &pcfg_pull_none>;
1155 i2c2_gpio: i2c2-gpio {
1157 <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1158 <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1163 i2c3_xfer: i2c3-xfer {
1165 <2 16 RK_FUNC_2 &pcfg_pull_none>,
1166 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1171 i2c4_xfer: i2c4-xfer {
1173 <5 8 RK_FUNC_1 &pcfg_pull_none>,
1174 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1177 i2c4_gpio: i2c4-gpio {
1179 <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1180 <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1185 i2c5_xfer: i2c5-xfer {
1187 <5 13 RK_FUNC_1 &pcfg_pull_none>,
1188 <5 14 RK_FUNC_1 &pcfg_pull_none>;
1190 i2c5_gpio: i2c5-gpio {
1192 <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1193 <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1198 i2s_8ch_bus: i2s-8ch-bus {
1200 <4 16 RK_FUNC_1 &pcfg_pull_none>,
1201 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1202 <4 18 RK_FUNC_1 &pcfg_pull_none>,
1203 <4 19 RK_FUNC_1 &pcfg_pull_none>,
1204 <4 20 RK_FUNC_1 &pcfg_pull_none>,
1205 <4 21 RK_FUNC_1 &pcfg_pull_none>,
1206 <4 22 RK_FUNC_1 &pcfg_pull_none>,
1207 <4 23 RK_FUNC_1 &pcfg_pull_none>,
1208 <4 24 RK_FUNC_1 &pcfg_pull_none>;
1213 spdif_bus: spdif-bus {
1215 <5 19 RK_FUNC_1 &pcfg_pull_none>;
1220 spi0_clk: spi0-clk {
1222 <2 29 RK_FUNC_2 &pcfg_pull_up>;
1224 spi0_cs0: spi0-cs0 {
1226 <2 24 RK_FUNC_3 &pcfg_pull_up>;
1228 spi0_cs1: spi0-cs1 {
1230 <2 25 RK_FUNC_3 &pcfg_pull_up>;
1234 <2 23 RK_FUNC_3 &pcfg_pull_up>;
1238 <2 22 RK_FUNC_3 &pcfg_pull_up>;
1243 spi1_clk: spi1-clk {
1245 <2 4 RK_FUNC_3 &pcfg_pull_up>;
1247 spi1_cs0: spi1-cs0 {
1249 <2 5 RK_FUNC_3 &pcfg_pull_up>;
1253 <2 6 RK_FUNC_3 &pcfg_pull_up>;
1257 <2 7 RK_FUNC_3 &pcfg_pull_up>;
1264 <5 8 RK_FUNC_2 &pcfg_pull_none>;
1269 <5 9 RK_FUNC_2 &pcfg_pull_up>;
1274 <5 10 RK_FUNC_1 &pcfg_pull_none>;
1277 scr_detect: scr-detect {
1279 <5 11 RK_FUNC_1 &pcfg_pull_none>;
1284 uart0_xfer: uart0-xfer {
1286 <3 8 RK_FUNC_1 &pcfg_pull_up>,
1287 <3 9 RK_FUNC_1 &pcfg_pull_none>;
1290 uart0_cts: uart0-cts {
1292 <3 10 RK_FUNC_1 &pcfg_pull_none>;
1295 uart0_rts: uart0-rts {
1297 <3 11 RK_FUNC_1 &pcfg_pull_none>;
1302 uart2_t0_xfer: uart2_t0-xfer {
1304 <0 22 RK_FUNC_1 &pcfg_pull_up>,
1305 <0 21 RK_FUNC_1 &pcfg_pull_none>;
1307 /* no rts / cts for uart2 */
1311 uart2_t1_xfer: uart2_t1-xfer {
1313 <5 0 RK_FUNC_2 &pcfg_pull_up>,
1314 <5 1 RK_FUNC_2 &pcfg_pull_none>;
1316 /* no rts / cts for uart2 */
1320 uart2_t2_xfer: uart2_t2-xfer {
1322 <5 14 RK_FUNC_3 &pcfg_pull_up>,
1323 <5 13 RK_FUNC_3 &pcfg_pull_none>;
1325 /* no rts / cts for uart2 */
1329 uart3_xfer: uart3-xfer {
1331 <5 15 RK_FUNC_1 &pcfg_pull_up>,
1332 <5 16 RK_FUNC_1 &pcfg_pull_none>;
1335 uart3_cts: uart3-cts {
1337 <5 17 RK_FUNC_1 &pcfg_pull_none>;
1340 uart3_rts: uart3-rts {
1342 <5 18 RK_FUNC_1 &pcfg_pull_none>;
1347 pwm0_pin: pwm0-pin {
1349 <0 8 RK_FUNC_1 &pcfg_pull_none>;
1354 pwm1_pin: pwm1-pin {
1356 <1 6 RK_FUNC_2 &pcfg_pull_none>;
1361 pwm2_t0_pin: pwm2_t0-pin {
1363 <2 15 RK_FUNC_3 &pcfg_pull_none>;
1368 pwm2_t1_pin: pwm2_t1-pin {
1370 <5 17 RK_FUNC_2 &pcfg_pull_none>;
1375 pwm3_t0_pin: pwm3_t0-pin {
1377 <1 0 RK_FUNC_2 &pcfg_pull_none>;
1382 pwm3_t1_pin: pwm3_t1-pin {
1384 <0 21 RK_FUNC_2 &pcfg_pull_none>;
1389 pwm3_t2_pin: pwm3_t2-pin {
1391 <5 18 RK_FUNC_2 &pcfg_pull_none>;
1396 lcdc_lcdc: lcdc-lcdc {
1398 <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1399 <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1400 <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1401 <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1402 <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1403 <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1404 <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1405 <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1406 <1 0 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1407 <1 1 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1408 <1 2 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1409 <1 3 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1410 <1 4 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1411 <1 5 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1412 <1 6 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1413 <1 7 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1414 <1 8 RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1415 <1 9 RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1418 lcdc_gpio: lcdc-gpio {
1420 <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1421 <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1422 <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1423 <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1424 <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1425 <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1426 <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1427 <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1428 <1 0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1429 <1 1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1430 <1 2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1431 <1 3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1432 <1 4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1433 <1 5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1434 <1 6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1435 <1 7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1436 <1 8 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1437 <1 9 RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1442 rgmii_pins: rgmii-pins {
1445 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1447 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1449 <2 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1451 <2 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1453 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1455 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1457 <2 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1459 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1461 <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1463 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1465 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1467 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1469 <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1471 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1473 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1475 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1477 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1480 rmii_pins: rmii-pins {
1483 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1485 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1487 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1489 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1491 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1493 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1495 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1497 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1499 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1501 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1503 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1505 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1510 eth_phy_pwr: eth-phy-pwr {
1512 <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1518 compatible = "arm,malit764",
1523 reg = <0x0 0xffa30000 0 0x10000>;
1525 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1526 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1528 interrupt-names = "GPU", "MMU", "JOB";
1530 clocks = <&cru ACLK_GPU>;
1531 clock-names = "clk_mali";
1532 operating-points-v2 = <&gpu_opp_table>;
1533 status = "disabled";
1536 gpu_opp_table: gpu_opp_table {
1537 compatible = "operating-points-v2";
1541 opp-hz = /bits/ 64 <96000000>;
1542 opp-microvolt = <1150000>;
1545 opp-hz = /bits/ 64 <192000000>;
1546 opp-microvolt = <1150000>;
1549 opp-hz = /bits/ 64 <288000000>;
1550 opp-microvolt = <1150000>;
1553 opp-hz = /bits/ 64 <375000000>;
1554 opp-microvolt = <1150000>;
1557 opp-hz = /bits/ 64 <480000000>;
1558 opp-microvolt = <1150000>;