2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
50 compatible = "rockchip,rk3366";
51 interrupt-parent = <&gic>;
70 #address-cells = <0x2>;
75 compatible = "arm,cortex-a53","arm,armv8";
77 enable-method = "psci";
82 compatible = "arm,cortex-a53","arm,armv8";
84 enable-method = "psci";
89 compatible = "arm,cortex-a53","arm,armv8";
91 enable-method = "psci";
96 compatible = "arm,cortex-a53","arm,armv8";
98 enable-method = "psci";
103 compatible = "arm,psci-1.0";
108 compatible = "arm,armv8-timer";
111 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
113 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
115 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
117 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
118 clock-frequency = <24000000>;
122 compatible = "fixed-clock";
124 clock-frequency = <24000000>;
125 clock-output-names = "xin24m";
128 gic: interrupt-controller@ffb71000 {
129 compatible = "arm,gic-400";
130 interrupt-controller;
131 #interrupt-cells = <3>;
132 #address-cells = <0>;
134 reg = <0x0 0xffb71000 0x0 0x1000>,
135 <0x0 0xffb72000 0x0 0x1000>,
136 <0x0 0xffb74000 0x0 0x2000>,
137 <0x0 0xffb76000 0x0 0x2000>;
138 interrupts = <GIC_PPI 9
139 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
142 nandc0: nandc@ff0c0000 {
143 compatible = "rockchip,rk-nandc";
144 reg = <0x0 0xff0c0000 0x0 0x4000>;
145 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
148 clock-names = "clk_nandc", "hclk_nandc";
152 saradc: saradc@ff100000 {
153 compatible = "rockchip,saradc";
154 reg = <0x0 0xff100000 0x0 0x100>;
155 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
156 #io-channel-cells = <1>;
157 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
158 clock-names = "saradc", "apb_pclk";
163 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
164 reg = <0x0 0xff110000 0x0 0x1000>;
165 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
166 clock-names = "spiclk", "apb_pclk";
167 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
170 #address-cells = <1>;
176 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
177 reg = <0x0 0xff120000 0x0 0x1000>;
178 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
179 clock-names = "spiclk", "apb_pclk";
180 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
183 #address-cells = <1>;
189 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
190 reg = <0x0 0xff728000 0x0 0x1000>;
191 clocks = <&cru PCLK_I2C0>;
193 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&i2c0_xfer>;
196 #address-cells = <1>;
202 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
203 reg = <0x0 0xff140000 0x0 0x1000>;
204 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
205 #address-cells = <1>;
208 clocks = <&cru PCLK_I2C2>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&i2c2_xfer>;
215 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
216 reg = <0x0 0xff150000 0x0 0x1000>;
217 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
218 #address-cells = <1>;
221 clocks = <&cru PCLK_I2C3>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&i2c3_xfer>;
228 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
229 reg = <0x0 0xff160000 0x0 0x1000>;
230 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
231 #address-cells = <1>;
234 clocks = <&cru PCLK_I2C4>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&i2c4_xfer>;
241 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
242 reg = <0x0 0xff170000 0x0 0x1000>;
243 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
244 #address-cells = <1>;
247 clocks = <&cru PCLK_I2C5>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&i2c5_xfer>;
253 uart0: serial@ff180000 {
254 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
255 reg = <0x0 0xff180000 0x0 0x100>;
256 clock-frequency = <24000000>;
257 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
258 clock-names = "baudclk", "apb_pclk";
259 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
267 uart3: serial@ff1b0000 {
268 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
269 reg = <0x0 0xff1b0000 0x0 0x100>;
270 clock-frequency = <24000000>;
271 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
272 clock-names = "baudclk", "apb_pclk";
273 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
282 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
283 reg = <0x0 0xff660000 0x0 0x1000>;
284 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
285 #address-cells = <1>;
288 clocks = <&cru PCLK_I2C1>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&i2c1_xfer>;
295 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
296 reg = <0x0 0xff680000 0x0 0x10>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pwm0_pin>;
300 clocks = <&cru PCLK_RKPWM>;
306 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
307 reg = <0x0 0xff680010 0x0 0x10>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pwm1_pin>;
311 clocks = <&cru PCLK_RKPWM>;
317 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
318 reg = <0x0 0xff680020 0x0 0x10>;
320 clocks = <&cru PCLK_RKPWM>;
326 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
327 reg = <0x0 0xff680030 0x0 0x10>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pwm3_t2_pin>;
331 clocks = <&cru PCLK_RKPWM>;
336 uart2: serial@ff690000 {
337 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
338 reg = <0x0 0xff690000 0x0 0x100>;
339 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
341 clock-names = "baudclk", "apb_pclk";
344 pinctrl-names = "default";
345 pinctrl-0 = <&uart2_t1_xfer>;
349 pmugrf: syscon@ff738000 {
350 compatible = "rockchip,rk3366-pmugrf", "syscon";
351 reg = <0x0 0xff738000 0x0 0x1000>;
354 cru: clock-controller@ff760000 {
355 compatible = "rockchip,rk3366-cru";
356 reg = <0x0 0xff760000 0x0 0x1000>;
357 rockchip,grf = <&grf>;
362 grf: syscon@ff770000 {
363 compatible = "rockchip,rk3366-grf", "syscon";
364 reg = <0x0 0xff770000 0x0 0x1000>;
368 compatible = "rockchip,rk3366-pinctrl";
369 rockchip,grf = <&grf>;
370 rockchip,pmu = <&pmugrf>;
371 #address-cells = <0x2>;
375 gpio0: gpio0@ff750000 {
376 compatible = "rockchip,gpio-bank";
377 reg = <0x0 0xff750000 0x0 0x100>;
378 clocks = <&cru PCLK_GPIO0>;
379 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
384 interrupt-controller;
385 #interrupt-cells = <0x2>;
388 gpio1: gpio1@ff780000 {
389 compatible = "rockchip,gpio-bank";
390 reg = <0x0 0xff758000 0x0 0x100>;
391 clocks = <&cru PCLK_GPIO1>;
392 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
397 interrupt-controller;
398 #interrupt-cells = <0x2>;
401 gpio2: gpio2@ff790000 {
402 compatible = "rockchip,gpio-bank";
403 reg = <0x0 0xff790000 0x0 0x100>;
404 clocks = <&cru PCLK_GPIO2>;
405 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
410 interrupt-controller;
411 #interrupt-cells = <0x2>;
414 gpio3: gpio3@ff7a0000 {
415 compatible = "rockchip,gpio-bank";
416 reg = <0x0 0xff7a0000 0x0 0x100>;
417 clocks = <&cru PCLK_GPIO3>;
418 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
423 interrupt-controller;
424 #interrupt-cells = <0x2>;
427 gpio4: gpio4@ff7b0000 {
428 compatible = "rockchip,gpio-bank";
429 reg = <0x0 0xff7b0000 0x0 0x100>;
430 clocks = <&cru PCLK_GPIO4>;
431 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
436 interrupt-controller;
437 #interrupt-cells = <0x2>;
440 gpio5: gpio5@ff7c0000 {
441 compatible = "rockchip,gpio-bank";
442 reg = <0x0 0xff7c0000 0x0 0x100>;
443 clocks = <&cru PCLK_GPIO5>;
444 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
449 interrupt-controller;
450 #interrupt-cells = <0x2>;
453 pcfg_pull_up: pcfg-pull-up {
457 pcfg_pull_down: pcfg-pull-down {
461 pcfg_pull_none: pcfg-pull-none {
465 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
467 drive-strength = <12>;
473 <3 4 RK_FUNC_2 &pcfg_pull_none>;
478 <2 26 RK_FUNC_2 &pcfg_pull_up>;
483 <2 27 RK_FUNC_2 &pcfg_pull_up>;
486 emmc_bus1: emmc-bus1 {
488 <2 18 RK_FUNC_2 &pcfg_pull_up>;
491 emmc_bus4: emmc-bus4 {
493 <2 18 RK_FUNC_2 &pcfg_pull_up>,
494 <2 19 RK_FUNC_2 &pcfg_pull_up>,
495 <2 20 RK_FUNC_2 &pcfg_pull_up>,
496 <2 21 RK_FUNC_2 &pcfg_pull_up>;
499 emmc_bus8: emmc-bus8 {
501 <2 18 RK_FUNC_2 &pcfg_pull_up>,
502 <2 19 RK_FUNC_2 &pcfg_pull_up>,
503 <2 20 RK_FUNC_2 &pcfg_pull_up>,
504 <2 21 RK_FUNC_2 &pcfg_pull_up>,
505 <2 22 RK_FUNC_2 &pcfg_pull_up>,
506 <2 23 RK_FUNC_2 &pcfg_pull_up>,
507 <2 24 RK_FUNC_2 &pcfg_pull_up>,
508 <2 25 RK_FUNC_2 &pcfg_pull_up>;
513 i2c0_xfer: i2c0-xfer {
515 <0 3 RK_FUNC_1 &pcfg_pull_none>,
516 <0 4 RK_FUNC_1 &pcfg_pull_none>;
521 i2c1_xfer: i2c1-xfer {
523 <4 19 RK_FUNC_1 &pcfg_pull_none>,
524 <4 20 RK_FUNC_1 &pcfg_pull_none>;
529 i2c2_xfer: i2c2-xfer {
531 <5 15 RK_FUNC_2 &pcfg_pull_none>,
532 <5 16 RK_FUNC_2 &pcfg_pull_none>;
537 i2c3_xfer: i2c3-xfer {
539 <2 16 RK_FUNC_2 &pcfg_pull_none>,
540 <2 17 RK_FUNC_2 &pcfg_pull_none>;
545 i2c4_xfer: i2c4-xfer {
547 <5 8 RK_FUNC_1 &pcfg_pull_none>,
548 <5 9 RK_FUNC_1 &pcfg_pull_none>;
553 i2c5_xfer: i2c5-xfer {
555 <5 13 RK_FUNC_1 &pcfg_pull_none>,
556 <5 14 RK_FUNC_1 &pcfg_pull_none>;
561 i2s_8ch_bus: i2s-8ch-bus {
563 <4 16 RK_FUNC_1 &pcfg_pull_none>,
564 <4 17 RK_FUNC_1 &pcfg_pull_none>,
565 <4 18 RK_FUNC_1 &pcfg_pull_none>,
566 <4 19 RK_FUNC_1 &pcfg_pull_none>,
567 <4 20 RK_FUNC_1 &pcfg_pull_none>,
568 <4 21 RK_FUNC_1 &pcfg_pull_none>,
569 <4 22 RK_FUNC_1 &pcfg_pull_none>,
570 <4 23 RK_FUNC_1 &pcfg_pull_none>,
571 <4 24 RK_FUNC_1 &pcfg_pull_none>;
578 <2 29 RK_FUNC_2 &pcfg_pull_up>;
582 <2 24 RK_FUNC_3 &pcfg_pull_up>;
586 <2 25 RK_FUNC_3 &pcfg_pull_up>;
590 <2 23 RK_FUNC_3 &pcfg_pull_up>;
594 <2 22 RK_FUNC_3 &pcfg_pull_up>;
601 <2 4 RK_FUNC_2 &pcfg_pull_up>;
605 <2 5 RK_FUNC_2 &pcfg_pull_up>;
609 <2 6 RK_FUNC_2 &pcfg_pull_up>;
613 <2 7 RK_FUNC_2 &pcfg_pull_up>;
618 uart0_xfer: uart0-xfer {
620 <3 8 RK_FUNC_1 &pcfg_pull_up>,
621 <3 9 RK_FUNC_1 &pcfg_pull_none>;
624 uart0_cts: uart0-cts {
626 <3 10 RK_FUNC_1 &pcfg_pull_none>;
629 uart0_rts: uart0-rts {
631 <3 11 RK_FUNC_1 &pcfg_pull_none>;
636 uart2_t0_xfer: uart2_t0-xfer {
638 <0 22 RK_FUNC_1 &pcfg_pull_up>,
639 <0 21 RK_FUNC_1 &pcfg_pull_none>;
641 /* no rts / cts for uart2 */
645 uart2_t1_xfer: uart2_t1-xfer {
647 <5 0 RK_FUNC_2 &pcfg_pull_up>,
648 <5 1 RK_FUNC_2 &pcfg_pull_none>;
650 /* no rts / cts for uart2 */
654 uart2_t2_xfer: uart2_t2-xfer {
656 <5 14 RK_FUNC_3 &pcfg_pull_up>,
657 <5 13 RK_FUNC_3 &pcfg_pull_none>;
659 /* no rts / cts for uart2 */
663 uart3_xfer: uart3-xfer {
665 <5 15 RK_FUNC_1 &pcfg_pull_up>,
666 <5 16 RK_FUNC_1 &pcfg_pull_none>;
669 uart3_cts: uart3-cts {
671 <5 17 RK_FUNC_1 &pcfg_pull_none>;
674 uart3_rts: uart3-rts {
676 <5 18 RK_FUNC_1 &pcfg_pull_none>;
683 <0 8 RK_FUNC_1 &pcfg_pull_none>;
690 <1 6 RK_FUNC_2 &pcfg_pull_none>;
695 pwm2_t0_pin: pwm2_t0-pin {
697 <2 15 RK_FUNC_3 &pcfg_pull_none>;
702 pwm2_t1_pin: pwm2_t1-pin {
704 <5 17 RK_FUNC_2 &pcfg_pull_none>;
709 pwm3_t0_pin: pwm3_t0-pin {
711 <1 0 RK_FUNC_2 &pcfg_pull_none>;
716 pwm3_t1_pin: pwm3_t1-pin {
718 <0 21 RK_FUNC_2 &pcfg_pull_none>;
723 pwm3_t2_pin: pwm3_t2-pin {
725 <5 18 RK_FUNC_2 &pcfg_pull_none>;