arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/power/rk3366-power.h>
  50 #include <dt-bindings/soc/rockchip_boot-mode.h>
  51
  52 / {
  53         compatible = "rockchip,rk3366";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 serial0 = &uart0;
  66                 serial2 = &uart2;
  67                 serial3 = &uart3;
  68                 spi0 = &spi0;
  69                 spi1 = &spi1;
  70         };
  71
  72         cpus {
  73                 #address-cells = <0x2>;
  74                 #size-cells = <0x0>;
  75
  76                 cpu0: cpu@0 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53","arm,armv8";
  79                         reg = <0x0 0x0>;
  80                         enable-method = "psci";
  81                         clocks = <&cru ARMCLK>;
  82                         operating-points-v2 = <&cpu0_opp_table>;
  83                         cpu-idle-states = <&cpu_sleep>;
  84                 };
  85
  86                 cpu1: cpu@1 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53","arm,armv8";
  89                         reg = <0x0 0x1>;
  90                         enable-method = "psci";
  91                         operating-points-v2 = <&cpu0_opp_table>;
  92                         cpu-idle-states = <&cpu_sleep>;
  93                 };
  94
  95                 cpu2: cpu@2 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a53","arm,armv8";
  98                         reg = <0x0 0x2>;
  99                         enable-method = "psci";
 100                         operating-points-v2 = <&cpu0_opp_table>;
 101                         cpu-idle-states = <&cpu_sleep>;
 102                 };
 103
 104                 cpu3: cpu@3 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a53","arm,armv8";
 107                         reg = <0x0 0x3>;
 108                         enable-method = "psci";
 109                         operating-points-v2 = <&cpu0_opp_table>;
 110                         cpu-idle-states = <&cpu_sleep>;
 111                 };
 112
 113                 idle-states {
 114                         entry-method = "psci";
 115                         cpu_sleep: cpu-sleep-0 {
 116                                 compatible = "arm,idle-state";
 117                                 local-timer-stop;
 118                                 arm,psci-suspend-param = <0x0010000>;
 119                                 entry-latency-us = <350>;
 120                                 exit-latency-us = <600>;
 121                                 min-residency-us = <1150>;
 122                         };
 123                 };
 124         };
 125
 126         cpu0_opp_table: opp_table0 {
 127                 compatible = "operating-points-v2";
 128                 opp-shared;
 129
 130                 opp00 {
 131                         opp-hz = /bits/ 64 <408000000>;
 132                         opp-microvolt = <950000>;
 133                         clock-latency-ns = <40000>;
 134                         opp-suspend;
 135                 };
 136                 opp01 {
 137                         opp-hz = /bits/ 64 <600000000>;
 138                         opp-microvolt = <950000>;
 139                 };
 140                 opp02 {
 141                         opp-hz = /bits/ 64 <816000000>;
 142                         opp-microvolt = <1000000>;
 143                 };
 144                 opp03 {
 145                         opp-hz = /bits/ 64 <1008000000>;
 146                         opp-microvolt = <1075000>;
 147                 };
 148                 opp04 {
 149                         opp-hz = /bits/ 64 <1200000000>;
 150                         opp-microvolt = <1175000>;
 151                 };
 152                 opp05 {
 153                         opp-hz = /bits/ 64 <1296000000>;
 154                         opp-microvolt = <1250000>;
 155                 };
 156         };
 157
 158         psci {
 159                 compatible = "arm,psci-1.0";
 160                 method = "smc";
 161         };
 162
 163         timer {
 164                 compatible = "arm,armv8-timer";
 165                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 166                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 167                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 168                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 169         };
 170
 171         arm-pmu {
 172                 compatible = "arm,cortex-a53-pmu";
 173                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 177                 interrupt-affinity = <&cpu0>,
 178                                      <&cpu1>,
 179                                      <&cpu2>,
 180                                      <&cpu3>;
 181         };
 182
 183         xin24m: xin24m {
 184                 compatible = "fixed-clock";
 185                 #clock-cells = <0>;
 186                 clock-frequency = <24000000>;
 187                 clock-output-names = "xin24m";
 188         };
 189
 190         gic: interrupt-controller@ffb71000 {
 191                 compatible = "arm,gic-400";
 192                 interrupt-controller;
 193                 #interrupt-cells = <3>;
 194                 #address-cells = <0>;
 195
 196                 reg = <0x0 0xffb71000 0x0 0x1000>,
 197                       <0x0 0xffb72000 0x0 0x1000>,
 198                       <0x0 0xffb74000 0x0 0x2000>,
 199                       <0x0 0xffb76000 0x0 0x2000>;
 200                 interrupts = <GIC_PPI 9
 201                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 202         };
 203
 204         nandc0: nandc@ff0c0000 {
 205                 compatible = "rockchip,rk-nandc";
 206                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 207                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 208                 nandc_id = <0>;
 209                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 210                 clock-names = "clk_nandc", "hclk_nandc";
 211                 status = "disabled";
 212         };
 213
 214         saradc: saradc@ff100000 {
 215                 compatible = "rockchip,saradc";
 216                 reg = <0x0 0xff100000 0x0 0x100>;
 217                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 218                 #io-channel-cells = <1>;
 219                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 220                 clock-names = "saradc", "apb_pclk";
 221                 status = "disabled";
 222         };
 223
 224         spi0: spi@ff110000 {
 225                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 226                 reg = <0x0 0xff110000 0x0 0x1000>;
 227                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 228                 clock-names = "spiclk", "apb_pclk";
 229                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 230                 pinctrl-names = "default";
 231                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 232                 #address-cells = <1>;
 233                 #size-cells = <0>;
 234                 status = "disabled";
 235         };
 236
 237         spi1: spi@ff120000 {
 238                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 239                 reg = <0x0 0xff120000 0x0 0x1000>;
 240                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 241                 clock-names = "spiclk", "apb_pclk";
 242                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 243                 pinctrl-names = "default";
 244                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 245                 #address-cells = <1>;
 246                 #size-cells = <0>;
 247                 status = "disabled";
 248         };
 249
 250         scr: rkscr@ff1d0000 {
 251                 compatible = "rockchip-scr";
 252                 reg = <0x0 0xff1d0000 0x0 0x10000>;
 253                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 254                 #address-cells = <1>;
 255                 #size-cells = <0>;
 256                 pinctrl-names = "default";
 257                 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
 258                 clocks = <&cru PCLK_SIM>;
 259                 clock-names = "g_pclk_sim_card";
 260                 status = "disabled";
 261         };
 262
 263         sdmmc: rksdmmc@ff400000 {
 264                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 265                 clock-freq-min-max = <400000 150000000>;
 266                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 267                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 268                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 269                 fifo-depth = <0x100>;
 270                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 271                 reg = <0x0 0xff400000 0x0 0x4000>;
 272                 status = "disabled";
 273         };
 274
 275         sdio: rksdmmc@ff410000 {
 276                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 277                 clock-freq-min-max = <400000 150000000>;
 278                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 279                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 280                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 281                 fifo-depth = <0x100>;
 282                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 283                 reg = <0x0 0xff410000 0x0 0x4000>;
 284                 status = "disabled";
 285         };
 286
 287         emmc: rksdmmc@ff420000 {
 288                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 289                 clock-freq-min-max = <400000 150000000>;
 290                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 291                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 292                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 293                 fifo-depth = <0x100>;
 294                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 295                 reg = <0x0 0xff420000 0x0 0x4000>;
 296                 status = "disabled";
 297         };
 298
 299         gmac: eth@ff440000 {
 300                 compatible = "rockchip,rk3366-gmac";
 301                 reg = <0x0 0xff440000 0x0 0x10000>;
 302                 rockchip,grf = <&grf>;
 303                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 304                 interrupt-names = "macirq";
 305                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 306                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 307                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 308                          <&cru PCLK_GMAC>;
 309                 clock-names = "stmmaceth", "mac_clk_rx",
 310                               "mac_clk_tx", "clk_mac_ref",
 311                               "clk_mac_refout", "aclk_mac",
 312                               "pclk_mac";
 313                 resets = <&cru SRST_MAC>;
 314                 reset-names = "stmmaceth";
 315                 status = "disabled";
 316         };
 317
 318         i2c0: i2c@ff650000 {
 319                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 320                 reg = <0x0 0xff728000 0x0 0x1000>;
 321                 clocks = <&cru PCLK_I2C0>;
 322                 clock-names = "i2c";
 323                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&i2c0_xfer>;
 326                 #address-cells = <1>;
 327                 #size-cells = <0>;
 328                 status = "disabled";
 329         };
 330
 331         i2c2: i2c@ff140000 {
 332                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 333                 reg = <0x0 0xff140000 0x0 0x1000>;
 334                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 335                 #address-cells = <1>;
 336                 #size-cells = <0>;
 337                 clock-names = "i2c";
 338                 clocks = <&cru PCLK_I2C2>;
 339                 pinctrl-names = "default";
 340                 pinctrl-0 = <&i2c2_xfer>;
 341                 status = "disabled";
 342         };
 343
 344         i2c3: i2c@ff150000 {
 345                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 346                 reg = <0x0 0xff150000 0x0 0x1000>;
 347                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 348                 #address-cells = <1>;
 349                 #size-cells = <0>;
 350                 clock-names = "i2c";
 351                 clocks = <&cru PCLK_I2C3>;
 352                 pinctrl-names = "default";
 353                 pinctrl-0 = <&i2c3_xfer>;
 354                 status = "disabled";
 355         };
 356
 357         i2c4: i2c@ff160000 {
 358                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 359                 reg = <0x0 0xff160000 0x0 0x1000>;
 360                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363                 clock-names = "i2c";
 364                 clocks = <&cru PCLK_I2C4>;
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&i2c4_xfer>;
 367                 status = "disabled";
 368         };
 369
 370         i2c5: i2c@ff170000 {
 371                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 372                 reg = <0x0 0xff170000 0x0 0x1000>;
 373                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376                 clock-names = "i2c";
 377                 clocks = <&cru PCLK_I2C5>;
 378                 pinctrl-names = "default";
 379                 pinctrl-0 = <&i2c5_xfer>;
 380                 status = "disabled";
 381         };
 382
 383         uart0: serial@ff180000 {
 384                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 385                 reg = <0x0 0xff180000 0x0 0x100>;
 386                 clock-frequency = <24000000>;
 387                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 388                 clock-names = "baudclk", "apb_pclk";
 389                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 390                 reg-shift = <2>;
 391                 reg-io-width = <4>;
 392                 pinctrl-names = "default";
 393                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 394                 status = "disabled";
 395         };
 396
 397         uart3: serial@ff1b0000 {
 398                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 399                 reg = <0x0 0xff1b0000 0x0 0x100>;
 400                 clock-frequency = <24000000>;
 401                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 402                 clock-names = "baudclk", "apb_pclk";
 403                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 404                 reg-shift = <2>;
 405                 reg-io-width = <4>;
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 408                 status = "disabled";
 409         };
 410
 411         usbphy: phy {
 412                 compatible = "rockchip,rk336x-usb-phy";
 413                 rockchip,grf = <&grf>;
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416
 417                 usbphy0: usb-phy0 {
 418                         #phy-cells = <0>;
 419                         #clock-cells = <0>;
 420                         reg = <0x700>;
 421                 };
 422
 423                 usbphy1: usb-phy1 {
 424                         #phy-cells = <0>;
 425                         #clock-cells = <0>;
 426                         reg = <0x728>;
 427                 };
 428         };
 429
 430         usb_host0_echi: usb@ff480000 {
 431                 compatible = "generic-ehci";
 432                 reg = <0x0 0xff480000 0x0 0x20000>;
 433                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 434                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 435                 clock-names = "sclk_otgphy0", "hclk_host0";
 436                 phys = <&usbphy1>;
 437                 phy-names = "usb";
 438                 status = "disabled";
 439         };
 440
 441         usb_host0_ohci: usb@ff4a0000 {
 442                 compatible = "generic-ohci";
 443                 reg = <0x0 0xff4a0000 0x0 0x20000>;
 444                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 445                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 446                 clock-names = "sclk_otgphy0", "hclk_host0";
 447                 status = "disabled";
 448         };
 449
 450         usb_otg: usb@ff4c0000 {
 451                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 452                              "snps,dwc2";
 453                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 454                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 455                 clocks = <&cru HCLK_OTG>;
 456                 clock-names = "otg";
 457                 dr_mode = "otg";
 458                 g-np-tx-fifo-size = <16>;
 459                 g-rx-fifo-size = <275>;
 460                 g-tx-fifo-size = <256 128 128 64 64 32>;
 461                 g-use-dma;
 462                 status = "disabled";
 463         };
 464
 465         i2c1: i2c@ff660000 {
 466                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 467                 reg = <0x0 0xff660000 0x0 0x1000>;
 468                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 469                 #address-cells = <1>;
 470                 #size-cells = <0>;
 471                 clock-names = "i2c";
 472                 clocks = <&cru PCLK_I2C1>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&i2c1_xfer>;
 475                 status = "disabled";
 476         };
 477
 478         pwm0: pwm@ff680000 {
 479                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 480                 reg = <0x0 0xff680000 0x0 0x10>;
 481                 #pwm-cells = <3>;
 482                 pinctrl-names = "default";
 483                 pinctrl-0 = <&pwm0_pin>;
 484                 clocks = <&cru PCLK_RKPWM>;
 485                 clock-names = "pwm";
 486                 status = "disabled";
 487         };
 488
 489         pwm1: pwm@ff680010 {
 490                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 491                 reg = <0x0 0xff680010 0x0 0x10>;
 492                 #pwm-cells = <3>;
 493                 pinctrl-names = "default";
 494                 pinctrl-0 = <&pwm1_pin>;
 495                 clocks = <&cru PCLK_RKPWM>;
 496                 clock-names = "pwm";
 497                 status = "disabled";
 498         };
 499
 500         pwm2: pwm@ff680020 {
 501                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 502                 reg = <0x0 0xff680020 0x0 0x10>;
 503                 #pwm-cells = <3>;
 504                 clocks = <&cru PCLK_RKPWM>;
 505                 clock-names = "pwm";
 506                 status = "disabled";
 507         };
 508
 509         pwm3: pwm@ff680030 {
 510                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 511                 reg = <0x0 0xff680030 0x0 0x10>;
 512                 #pwm-cells = <3>;
 513                 pinctrl-names = "default";
 514                 pinctrl-0 = <&pwm3_t2_pin>;
 515                 clocks = <&cru PCLK_RKPWM>;
 516                 clock-names = "pwm";
 517                 status = "disabled";
 518         };
 519
 520         uart2: serial@ff690000 {
 521                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 522                 reg = <0x0 0xff690000 0x0 0x100>;
 523                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 524                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 525                 clock-names = "baudclk", "apb_pclk";
 526                 reg-shift = <2>;
 527                 reg-io-width = <4>;
 528                 pinctrl-names = "default";
 529                 pinctrl-0 = <&uart2_t1_xfer>;
 530                 status = "disabled";
 531         };
 532
 533         pmu: power-management@ff730000 {
 534                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 535                 reg = <0x0 0xff730000 0x0 0x1000>;
 536
 537                 power: power-controller {
 538                         status = "disabled";
 539                         compatible = "rockchip,rk3366-power-controller";
 540                         #power-domain-cells = <1>;
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543
 544                         /*
 545                          * Note: Although SCLK_* are the working clocks
 546                          * of device without including on the NOC, needed for
 547                          * synchronous reset.
 548                          *
 549                          * The clocks on the which NOC:
 550                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 551                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 552                          * ACLK_ISP is on ACLK_ISP_NIU.
 553                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 554                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 555                          *
 556                          * Which clock are device clocks:
 557                          *      clocks          devices
 558                          *      *_IEP           IEP:Image Enhancement Processor
 559                          *      *_ISP           ISP:Image Signal Processing
 560                          *      *_VOP*          VOP:Visual Output Processor
 561                          *      *_RGA           RGA
 562                          *      *_DPHY*         LVDS
 563                          *      *_HDMI          HDMI
 564                          *      *_MIPI_*        MIPI
 565                          */
 566                         pd_vio {
 567                                 reg = <RK3366_PD_VIO>;
 568                                 clocks = <&cru ACLK_IEP>,
 569                                          <&cru ACLK_ISP>,
 570                                          <&cru ACLK_RGA>,
 571                                          <&cru ACLK_HDCP>,
 572                                          <&cru ACLK_VOP_FULL>,
 573                                          <&cru ACLK_VOP_LITE>,
 574                                          <&cru ACLK_VOP_IEP>,
 575                                          <&cru DCLK_VOP_FULL>,
 576                                          <&cru DCLK_VOP_LITE>,
 577                                          <&cru HCLK_IEP>,
 578                                          <&cru HCLK_ISP>,
 579                                          <&cru HCLK_RGA>,
 580                                          <&cru HCLK_VOP_FULL>,
 581                                          <&cru HCLK_VOP_LITE>,
 582                                          <&cru HCLK_VIO_HDCPMMU>,
 583                                          <&cru PCLK_HDMI_CTRL>,
 584                                          <&cru PCLK_HDCP>,
 585                                          <&cru PCLK_MIPI_DSI0>,
 586                                          <&cru SCLK_VOP_FULL_PWM>,
 587                                          <&cru SCLK_HDCP>,
 588                                          <&cru SCLK_ISP>,
 589                                          <&cru SCLK_RGA>,
 590                                          <&cru SCLK_HDMI_CEC>,
 591                                          <&cru SCLK_HDMI_HDCP>;
 592                         };
 593
 594                         /*
 595                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 596                          * (video endecoder & decoder) clocks that on the
 597                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 598                          */
 599                         pd_vpu {
 600                                 reg = <RK3366_PD_VPU>;
 601                                 clocks = <&cru ACLK_VIDEO>,
 602                                          <&cru HCLK_VIDEO>;
 603                         };
 604
 605                         /*
 606                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 607                          * (video decoder) clocks that on the
 608                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 609                          */
 610                         pd_rkvdec {
 611                                 reg = <RK3366_PD_RKVDEC>;
 612                                 clocks = <&cru ACLK_RKVDEC>,
 613                                          <&cru HCLK_RKVDEC>;
 614                         };
 615
 616                         pd_video {
 617                                 reg = <RK3366_PD_VIDEO>;
 618                                 clocks = <&cru ACLK_VIDEO>,
 619                                          <&cru ACLK_RKVDEC>,
 620                                          <&cru HCLK_VIDEO>,
 621                                          <&cru HCLK_RKVDEC>,
 622                                          <&cru SCLK_HEVC_CABAC>,
 623                                          <&cru SCLK_HEVC_CORE>;
 624                         };
 625
 626                         /*
 627                          * Note: ACLK_GPU is the GPU clock,
 628                          * and on the ACLK_GPU_NIU (NOC).
 629                          */
 630                         pd_gpu {
 631                                 reg = <RK3366_PD_GPU>;
 632                                 clocks = <&cru ACLK_GPU>;
 633                         };
 634                 };
 635         };
 636
 637         pmugrf: syscon@ff738000 {
 638                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 639                 reg = <0x0 0xff738000 0x0 0x1000>;
 640
 641                 reboot-mode {
 642                         compatible = "syscon-reboot-mode";
 643                         offset = <0x200>;
 644                         mode-normal = <BOOT_NORMAL>;
 645                         mode-recovery = <BOOT_RECOVERY>;
 646                         mode-fastboot = <BOOT_FASTBOOT>;
 647                         mode-loader = <BOOT_LOADER>;
 648                 };
 649         };
 650
 651         amba {
 652                 compatible = "arm,amba-bus";
 653                 #address-cells = <2>;
 654                 #size-cells = <2>;
 655                 ranges;
 656
 657                 dmac_peri: dma-controller@ff250000 {
 658                         compatible = "arm,pl330", "arm,primecell";
 659                         reg = <0x0 0xff250000 0x0 0x4000>;
 660                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 661                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 662                         #dma-cells = <1>;
 663                         clocks = <&cru ACLK_DMAC_PERI>;
 664                         clock-names = "apb_pclk";
 665                 };
 666
 667                 dmac_bus: dma-controller@ff600000 {
 668                         compatible = "arm,pl330", "arm,primecell";
 669                         reg = <0x0 0xff600000 0x0 0x4000>;
 670                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 671                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 672                         #dma-cells = <1>;
 673                         clocks = <&cru ACLK_DMAC_BUS>;
 674                         clock-names = "apb_pclk";
 675                 };
 676         };
 677
 678         cru: clock-controller@ff760000 {
 679                 compatible = "rockchip,rk3366-cru";
 680                 reg = <0x0 0xff760000 0x0 0x1000>;
 681                 rockchip,grf = <&grf>;
 682                 #clock-cells = <1>;
 683                 #reset-cells = <1>;
 684                 assigned-clocks =
 685                         <&cru SCLK_32K>,
 686                         <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
 687                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 688                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 689                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 690                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 691                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
 692                         <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
 693                         <&cru ACLK_PERI1>;
 694                 assigned-clock-rates =
 695                         <0>,
 696                         <0>, <0>,
 697                         <750000000>, <576000000>,
 698                         <594000000>, <594000000>,
 699                         <960000000>, <520000000>,
 700                         <375000000>, <288000000>,
 701                         <100000000>, <100000000>,
 702                         <288000000>, <288000000>,
 703                         <144000000>;
 704                 assigned-clock-parents =
 705                         <&cru SCLK_32K_INTR>,
 706                         <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
 707         };
 708
 709         grf: syscon@ff770000 {
 710                 compatible = "rockchip,rk3366-grf", "syscon";
 711                 reg = <0x0 0xff770000 0x0 0x1000>;
 712         };
 713
 714         wdt: watchdog@ff800000 {
 715                 compatible = "snps,dw-wdt";
 716                 reg = <0x0 0xff800000 0x0 0x100>;
 717                 clocks = <&cru PCLK_WDT>;
 718                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 719                 status = "disabled";
 720         };
 721
 722         spdif: spdif@ff880000 {
 723                 compatible = "rockchip,rk3366-spdif";
 724                 reg = <0x0 0xff880000 0x0 0x1000>;
 725                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 726                 dmas = <&dmac_bus 3>;
 727                 dma-names = "tx";
 728                 clock-names = "hclk", "mclk";
 729                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 730                 pinctrl-names = "default";
 731                 pinctrl-0 = <&spdif_bus>;
 732                 status = "disabled";
 733         };
 734
 735         i2s_2ch: i2s-2ch@ff890000 {
 736                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 737                 reg = <0x0 0xff890000 0x0 0x1000>;
 738                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 739                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 740                 dma-names = "tx", "rx";
 741                 clock-names = "i2s_hclk", "i2s_clk";
 742                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 743                 status = "disabled";
 744         };
 745
 746         i2s_8ch: i2s-8ch@ff898000 {
 747                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 748                 reg = <0x0 0xff898000 0x0 0x1000>;
 749                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 750                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 751                 dma-names = "tx", "rx";
 752                 clock-names = "i2s_hclk", "i2s_clk";
 753                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 754                 pinctrl-names = "default";
 755                 pinctrl-0 = <&i2s_8ch_bus>;
 756                 status = "disabled";
 757         };
 758
 759         fb: fb {
 760                 compatible = "rockchip,rk-fb";
 761                 rockchip,disp-mode = <DUAL>;
 762                 status = "disabled";
 763         };
 764
 765         rk_screen: screen {
 766                 compatible = "rockchip,screen";
 767                 status = "disabled";
 768         };
 769
 770         vop_lite: vop@ff8f0000 {
 771                 compatible = "rockchip,rk3366-lcdc-lite";
 772                 rockchip,grf = <&grf>;
 773                 rockchip,pwr18 = <0>;
 774                 rockchip,iommu-enabled = <1>;
 775                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 776                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 777                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 778                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 779                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 780                 reset-names = "axi", "ahb", "dclk";
 781                 status = "disabled";
 782         };
 783
 784         vopl_mmu: vopl-mmu {
 785                 dbgname = "vop";
 786                 compatible = "rockchip,vopl_mmu";
 787                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 788                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 789                 interrupt-names = "vopl_mmu";
 790                 status = "disabled";
 791         };
 792
 793         iep: iep@ff900000 {
 794                 compatible = "rockchip,iep";
 795                 iommu_enabled = <1>;
 796                 reg = <0x0 0xff900000 0x0 0x800>;
 797                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 798                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 799                 clock-names = "aclk_iep", "hclk_iep";
 800                 version = <2>;
 801                 status = "disabled";
 802         };
 803
 804         rga: rga@ff920000 {
 805                 compatible = "rockchip,rga2";
 806                 dev_mode = <1>;
 807                 reg = <0x0 0xff920000 0x0 0x1000>;
 808                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 809                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 810                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 811                 status = "disabled";
 812         };
 813
 814         vop_big: vop@ff930000 {
 815                 compatible = "rockchip,rk3366-lcdc-big";
 816                 rockchip,grf = <&grf>;
 817                 rockchip,prop = <PRMRY>;
 818                 rockchip,pwr18 = <0>;
 819                 rockchip,iommu-enabled = <1>;
 820                 reg = <0x0 0xff930000 0x0 0x23f0>;
 821                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 822                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 823                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 824                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 825                 reset-names = "axi", "ahb", "dclk";
 826                 status = "disabled";
 827         };
 828
 829         vopb_mmu: vopb-mmu {
 830                 dbgname = "vop";
 831                 compatible = "rockchip,vopb_mmu";
 832                 reg = <0x0 0xff932400 0x0 0x100>;
 833                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 834                 interrupt-names = "vop_mmu";
 835                 status = "disabled";
 836         };
 837
 838         iep_mmu: iep-mmu {
 839                 dbgname = "iep";
 840                 compatible = "rockchip,iep_mmu";
 841                 reg = <0x0 0xff900800 0x0 0x100>;
 842                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 843                 interrupt-names = "iep_mmu";
 844                 status = "disabled";
 845         };
 846
 847         vpu_mmu: vpu_mmu {
 848                 dbgname = "vpu";
 849                 compatible = "rockchip,vpu_mmu";
 850                 reg = <0x0 0xff9a0800 0x0 0x100>;
 851                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 852                 interrupt-names = "vpu_mmu";
 853                 status = "disabled";
 854         };
 855
 856         vdec_mmu: vdec_mmu {
 857                 dbgname = "vdec";
 858                 compatible = "rockchip,vdec_mmu";
 859                 reg = <0x0 0xff9b0480 0x0 0x40>,
 860                       <0x0 0xff9b04c0 0x0 0x40>;
 861                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 862                 interrupt-names = "vdec_mmu";
 863                 status = "disabled";
 864         };
 865
 866         dsihost0: mipi@ff960000 {
 867                 compatible = "rockchip,rk3366-dsi";
 868                 rockchip,prop = <0>;
 869                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 870                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 871                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 872                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 873                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 874                 status = "disabled";
 875         };
 876
 877         lvds: lvds@ff968000 {
 878                 compatible = "rockchip,rk3366-lvds";
 879                 rockchip,grf = <&grf>;
 880                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 881                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 882                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 883                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 884                 status = "disabled";
 885         };
 886
 887         hdmi: hdmi@ff980000 {
 888                 compatible = "rockchip,rk3366-hdmi";
 889                 reg = <0x0 0xff980000 0x0 0x20000>;
 890                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 891                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 892                 clocks = <&cru PCLK_HDMI_CTRL>,
 893                          <&cru SCLK_HDMI_HDCP>,
 894                          <&cru SCLK_HDMI_CEC>,
 895                          <&cru DCLK_HDMIPHY>;
 896                 clock-names = "pclk_hdmi",
 897                               "hdcp_clk_hdmi",
 898                               "cec_clk_hdmi",
 899                               "dclk_hdmi_phy";
 900                 resets = <&cru SRST_HDMI>;
 901                 reset-names = "hdmi";
 902                 pinctrl-names = "default", "gpio";
 903                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 904                 pinctrl-1 = <&i2c5_gpio>;
 905                 status = "disabled";
 906         };
 907
 908         vpu: vpu_service@ff9a0000 {
 909                 compatible = "rockchip,vpu_service";
 910                 rockchip,grf = <&grf>;
 911                 iommu_enabled = <1>;
 912                 reg = <0x0 0xff9a0000 0x0 0x800>;
 913                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 914                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 915                 interrupt-names = "irq_dec", "irq_enc";
 916                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
 917                 clock-names = "aclk_vcodec", "hclk_vcodec";
 918                 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
 919                 reset-names = "video_h", "video_a";
 920                 name = "vpu_service";
 921                 dev_mode = <0>;
 922                 status = "disabled";
 923         };
 924
 925         rkvdec: rkvdec@ff9b0000 {
 926                 compatible = "rockchip,rkvdec";
 927                 rockchip,grf = <&grf>;
 928                 iommu_enabled = <1>;
 929                 reg = <0x0 0xff9b0000 0x0 0x400>;
 930                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 931                 interrupt-names = "irq_dec";
 932                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
 933                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
 934                 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
 935                 reset-names = "video_h", "video_a";
 936                 dev_mode = <2>;
 937                 name = "rkvdec";
 938                 status = "disabled";
 939         };
 940
 941         pinctrl: pinctrl {
 942                 compatible = "rockchip,rk3366-pinctrl";
 943                 rockchip,grf = <&grf>;
 944                 rockchip,pmu = <&pmugrf>;
 945                 #address-cells = <0x2>;
 946                 #size-cells = <0x2>;
 947                 ranges;
 948
 949                 gpio0: gpio0@ff750000 {
 950                         compatible = "rockchip,gpio-bank";
 951                         reg = <0x0 0xff750000 0x0 0x100>;
 952                         clocks = <&cru PCLK_GPIO0>;
 953                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 954
 955                         gpio-controller;
 956                         #gpio-cells = <0x2>;
 957
 958                         interrupt-controller;
 959                         #interrupt-cells = <0x2>;
 960                 };
 961
 962                 gpio1: gpio1@ff780000 {
 963                         compatible = "rockchip,gpio-bank";
 964                         reg = <0x0 0xff758000 0x0 0x100>;
 965                         clocks = <&cru PCLK_GPIO1>;
 966                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 967
 968                         gpio-controller;
 969                         #gpio-cells = <0x2>;
 970
 971                         interrupt-controller;
 972                         #interrupt-cells = <0x2>;
 973                 };
 974
 975                 gpio2: gpio2@ff790000 {
 976                         compatible = "rockchip,gpio-bank";
 977                         reg = <0x0 0xff790000 0x0 0x100>;
 978                         clocks = <&cru PCLK_GPIO2>;
 979                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 980
 981                         gpio-controller;
 982                         #gpio-cells = <0x2>;
 983
 984                         interrupt-controller;
 985                         #interrupt-cells = <0x2>;
 986                 };
 987
 988                 gpio3: gpio3@ff7a0000 {
 989                         compatible = "rockchip,gpio-bank";
 990                         reg = <0x0 0xff7a0000 0x0 0x100>;
 991                         clocks = <&cru PCLK_GPIO3>;
 992                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 993
 994                         gpio-controller;
 995                         #gpio-cells = <0x2>;
 996
 997                         interrupt-controller;
 998                         #interrupt-cells = <0x2>;
 999                 };
1000
1001                 gpio4: gpio4@ff7b0000 {
1002                         compatible = "rockchip,gpio-bank";
1003                         reg = <0x0 0xff7b0000 0x0 0x100>;
1004                         clocks = <&cru PCLK_GPIO4>;
1005                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1006
1007                         gpio-controller;
1008                         #gpio-cells = <0x2>;
1009
1010                         interrupt-controller;
1011                         #interrupt-cells = <0x2>;
1012                 };
1013
1014                 gpio5: gpio5@ff7c0000 {
1015                         compatible = "rockchip,gpio-bank";
1016                         reg = <0x0 0xff7c0000 0x0 0x100>;
1017                         clocks = <&cru PCLK_GPIO5>;
1018                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1019
1020                         gpio-controller;
1021                         #gpio-cells = <0x2>;
1022
1023                         interrupt-controller;
1024                         #interrupt-cells = <0x2>;
1025                 };
1026
1027                 pcfg_pull_up: pcfg-pull-up {
1028                         bias-pull-up;
1029                 };
1030
1031                 pcfg_pull_down: pcfg-pull-down {
1032                         bias-pull-down;
1033                 };
1034
1035                 pcfg_pull_none: pcfg-pull-none {
1036                         bias-disable;
1037                 };
1038
1039                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1040                         bias-disable;
1041                         drive-strength = <12>;
1042                 };
1043
1044                 emmc {
1045                         emmc_clk: emmc-clk {
1046                                 rockchip,pins =
1047                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
1048                         };
1049
1050                         emmc_cmd: emmc-cmd {
1051                                 rockchip,pins =
1052                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
1053                         };
1054
1055                         emmc_pwr: emmc-pwr {
1056                                 rockchip,pins =
1057                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
1058                         };
1059
1060                         emmc_bus1: emmc-bus1 {
1061                                 rockchip,pins =
1062                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
1063                         };
1064
1065                         emmc_bus4: emmc-bus4 {
1066                                 rockchip,pins =
1067                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1068                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1069                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1070                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1071                         };
1072
1073                         emmc_bus8: emmc-bus8 {
1074                                 rockchip,pins =
1075                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1076                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1077                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1078                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
1079                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
1080                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
1081                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
1082                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
1083                         };
1084                 };
1085
1086                 sdmmc {
1087                         sdmmc_cd: sdmmc-cd {
1088                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1089                         };
1090
1091                         sdmmc_bus1: sdmmc-bus1 {
1092                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1093                         };
1094
1095                         sdmmc_bus4: sdmmc-bus4 {
1096                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1097                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1098                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1099                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1100                         };
1101
1102                         sdmmc_clk: sdmmc-clk {
1103                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1104                         };
1105
1106                         sdmmc_cmd: sdmmc-cmd {
1107                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1108                         };
1109                 };
1110
1111                 sdio {
1112                         sdio_bus1: sdio-bus1 {
1113                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1114                         };
1115
1116                         sdio_bus4: sdio-bus4 {
1117                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1118                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1119                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1120                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1121                         };
1122
1123                         sdio_cmd: sdio-cmd {
1124                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1125                         };
1126
1127                         sdio_clk: sdio-clk {
1128                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1129                         };
1130
1131                         sdio_cd: sdio-cd {
1132                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1133                         };
1134
1135                         sdio_wp: sdio-wp {
1136                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1137                         };
1138
1139                         sdio_int: sdio-int {
1140                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1141                         };
1142
1143                         sdio_pwr: sdio-pwr {
1144                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1145                         };
1146                 };
1147
1148                 hdmi_i2c {
1149                         hdmii2c_xfer: hdmii2c-xfer {
1150                                 rockchip,pins =
1151                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1152                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1153                         };
1154                 };
1155
1156                 hdmi_pin {
1157                         hdmi_cec: hdmi-cec {
1158                                 rockchip,pins =
1159                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1160                         };
1161                 };
1162
1163                 i2c0 {
1164                         i2c0_xfer: i2c0-xfer {
1165                                 rockchip,pins =
1166                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1167                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1168                         };
1169                 };
1170
1171                 i2c1 {
1172                         i2c1_xfer: i2c1-xfer {
1173                                 rockchip,pins =
1174                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1175                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1176                         };
1177                 };
1178
1179                 i2c2 {
1180                         i2c2_xfer: i2c2-xfer {
1181                                 rockchip,pins =
1182                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1183                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1184                         };
1185
1186                         i2c2_gpio: i2c2-gpio {
1187                                 rockchip,pins =
1188                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1189                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1190                         };
1191                 };
1192
1193                 i2c3 {
1194                         i2c3_xfer: i2c3-xfer {
1195                                 rockchip,pins =
1196                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1197                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1198                         };
1199                 };
1200
1201                 i2c4 {
1202                         i2c4_xfer: i2c4-xfer {
1203                                 rockchip,pins =
1204                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1205                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1206                         };
1207
1208                         i2c4_gpio: i2c4-gpio {
1209                                 rockchip,pins =
1210                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1211                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1212                         };
1213                 };
1214
1215                 i2c5 {
1216                         i2c5_xfer: i2c5-xfer {
1217                                 rockchip,pins =
1218                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1219                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1220                         };
1221                         i2c5_gpio: i2c5-gpio {
1222                                 rockchip,pins =
1223                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1224                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1225                         };
1226                 };
1227
1228                 i2s {
1229                         i2s_8ch_bus: i2s-8ch-bus {
1230                                 rockchip,pins =
1231                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1232                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1233                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1234                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1235                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1236                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1237                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1238                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1239                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1240                         };
1241                 };
1242
1243                 spdif {
1244                         spdif_bus: spdif-bus {
1245                                 rockchip,pins =
1246                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1247                         };
1248                 };
1249
1250                 spi0 {
1251                         spi0_clk: spi0-clk {
1252                                 rockchip,pins =
1253                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1254                         };
1255                         spi0_cs0: spi0-cs0 {
1256                                 rockchip,pins =
1257                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1258                         };
1259                         spi0_cs1: spi0-cs1 {
1260                                 rockchip,pins =
1261                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1262                         };
1263                         spi0_tx: spi0-tx {
1264                                 rockchip,pins =
1265                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1266                         };
1267                         spi0_rx: spi0-rx {
1268                                 rockchip,pins =
1269                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1270                         };
1271                 };
1272
1273                 spi1 {
1274                         spi1_clk: spi1-clk {
1275                                 rockchip,pins =
1276                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1277                         };
1278                         spi1_cs0: spi1-cs0 {
1279                                 rockchip,pins =
1280                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1281                         };
1282                         spi1_tx: spi1-tx {
1283                                 rockchip,pins =
1284                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1285                         };
1286                         spi1_rx: spi1-rx {
1287                                 rockchip,pins =
1288                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1289                         };
1290                 };
1291
1292                 scr {
1293                         scr_clk: scr-clk {
1294                                 rockchip,pins =
1295                                         <5 8 RK_FUNC_2 &pcfg_pull_none>;
1296                         };
1297
1298                         scr_io: scr-io {
1299                                 rockchip,pins =
1300                                         <5 9 RK_FUNC_2 &pcfg_pull_up>;
1301                         };
1302
1303                         scr_rst: scr-rst {
1304                                 rockchip,pins =
1305                                         <5 10 RK_FUNC_1 &pcfg_pull_none>;
1306                         };
1307
1308                         scr_detect: scr-detect {
1309                                 rockchip,pins =
1310                                         <5 11 RK_FUNC_1 &pcfg_pull_none>;
1311                         };
1312                 };
1313
1314                 uart0 {
1315                         uart0_xfer: uart0-xfer {
1316                                 rockchip,pins =
1317                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1318                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1319                         };
1320
1321                         uart0_cts: uart0-cts {
1322                                 rockchip,pins =
1323                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1324                         };
1325
1326                         uart0_rts: uart0-rts {
1327                                 rockchip,pins =
1328                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1329                         };
1330                 };
1331
1332                 uart2_t0 {
1333                         uart2_t0_xfer: uart2_t0-xfer {
1334                                 rockchip,pins =
1335                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1336                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1337                         };
1338                         /* no rts / cts for uart2 */
1339                 };
1340
1341                 uart2_t1 {
1342                         uart2_t1_xfer: uart2_t1-xfer {
1343                                 rockchip,pins =
1344                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1345                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1346                         };
1347                         /* no rts / cts for uart2 */
1348                 };
1349
1350                 uart2_t2 {
1351                         uart2_t2_xfer: uart2_t2-xfer {
1352                                 rockchip,pins =
1353                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1354                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1355                         };
1356                         /* no rts / cts for uart2 */
1357                 };
1358
1359                 uart3 {
1360                         uart3_xfer: uart3-xfer {
1361                                 rockchip,pins =
1362                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1363                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1364                         };
1365
1366                         uart3_cts: uart3-cts {
1367                                 rockchip,pins =
1368                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1369                         };
1370
1371                         uart3_rts: uart3-rts {
1372                                 rockchip,pins =
1373                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1374                         };
1375                 };
1376
1377                 pwm0 {
1378                         pwm0_pin: pwm0-pin {
1379                                 rockchip,pins =
1380                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1381                         };
1382                 };
1383
1384                 pwm1 {
1385                         pwm1_pin: pwm1-pin {
1386                                 rockchip,pins =
1387                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1388                         };
1389                 };
1390
1391                 pwm2_t0 {
1392                         pwm2_t0_pin: pwm2_t0-pin {
1393                                 rockchip,pins =
1394                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1395                         };
1396                 };
1397
1398                 pwm2_t1 {
1399                         pwm2_t1_pin: pwm2_t1-pin {
1400                                 rockchip,pins =
1401                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1402                         };
1403                 };
1404
1405                 pwm3_t0 {
1406                         pwm3_t0_pin: pwm3_t0-pin {
1407                                 rockchip,pins =
1408                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1409                         };
1410                 };
1411
1412                 pwm3_t1 {
1413                         pwm3_t1_pin: pwm3_t1-pin {
1414                                 rockchip,pins =
1415                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1416                         };
1417                 };
1418
1419                 pwm3_t2 {
1420                         pwm3_t2_pin: pwm3_t2-pin {
1421                                 rockchip,pins =
1422                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1423                         };
1424                 };
1425
1426                 lcdc {
1427                         lcdc_lcdc: lcdc-lcdc {
1428                                 rockchip,pins =
1429                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1430                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1431                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1432                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1433                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1434                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1435                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1436                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1437                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1438                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1439                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1440                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1441                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1442                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1443                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1444                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1445                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1446                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1447                         };
1448
1449                         lcdc_gpio: lcdc-gpio {
1450                                 rockchip,pins =
1451                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1452                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1453                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1454                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1455                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1456                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1457                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1458                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1459                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1460                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1461                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1462                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1463                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1464                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1465                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1466                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1467                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1468                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1469                         };
1470                 };
1471
1472                 gmac {
1473                         rgmii_pins: rgmii-pins {
1474                                 rockchip,pins =
1475                                         /* mac_rxd3 */
1476                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1477                                         /* mac_rxd2 */
1478                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1479                                         /* mac_txd3 */
1480                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1481                                         /* mac_txd2 */
1482                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1483                                         /* mac_rxd1 */
1484                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1485                                         /* mac_rxd0 */
1486                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1487                                         /* mac_txd1 */
1488                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1489                                         /* mac_txd0 */
1490                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1491                                         /* mac_txclkout */
1492                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1493                                         /* mac_crs */
1494                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1495                                         /* mac_rxclkin */
1496                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1497                                         /* mac_mdio */
1498                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1499                                         /* mac_txen */
1500                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1501                                         /* mac_clk */
1502                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1503                                         /* mac_rxer */
1504                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1505                                         /* mac_rxdv */
1506                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1507                                         /* mac_mdc */
1508                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1509                         };
1510
1511                         rmii_pins: rmii-pins {
1512                                 rockchip,pins =
1513                                         /* mac_rxd1 */
1514                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1515                                         /* mac_rxd0 */
1516                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1517                                         /* mac_txd1 */
1518                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1519                                         /* mac_txd0 */
1520                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1521                                         /* mac_crs */
1522                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1523                                         /* mac_rxclkin */
1524                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1525                                         /* mac_mdio */
1526                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1527                                         /* mac_txen */
1528                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1529                                         /* mac_clk */
1530                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1531                                         /* mac_rxer */
1532                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1533                                         /* mac_rxdv */
1534                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1535                                         /* mac_mdc */
1536                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1537                         };
1538                 };
1539
1540                 eth_phy {
1541                         eth_phy_pwr: eth-phy-pwr {
1542                                 rockchip,pins =
1543                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1544                         };
1545                 };
1546         };
1547
1548         gpu: gpu@ffa30000 {
1549                 compatible = "arm,malit764",
1550                              "arm,malit76x",
1551                              "arm,malit7xx",
1552                              "arm,mali-midgard";
1553
1554                 reg = <0x0 0xffa30000 0 0x10000>;
1555
1556                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1557                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1558                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1559                 interrupt-names = "GPU", "MMU", "JOB";
1560
1561                 clocks = <&cru ACLK_GPU>;
1562                 clock-names = "clk_mali";
1563                 operating-points-v2 = <&gpu_opp_table>;
1564                 status = "disabled";
1565         };
1566
1567         gpu_opp_table: gpu_opp_table {
1568                 compatible = "operating-points-v2";
1569                 opp-shared;
1570
1571                 opp00 {
1572                         opp-hz = /bits/ 64 <96000000>;
1573                         opp-microvolt = <1100000>;
1574                 };
1575                 opp01 {
1576                         opp-hz = /bits/ 64 <192000000>;
1577                         opp-microvolt = <1100000>;
1578                 };
1579                 opp02 {
1580                         opp-hz = /bits/ 64 <288000000>;
1581                         opp-microvolt = <1100000>;
1582                 };
1583                 opp03 {
1584                         opp-hz = /bits/ 64 <375000000>;
1585                         opp-microvolt = <1125000>;
1586                 };
1587                 opp04 {
1588                         opp-hz = /bits/ 64 <480000000>;
1589                         opp-microvolt = <1200000>;
1590                 };
1591         };
1592 };