arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/display/mipi_dsi.h>
  50 #include <dt-bindings/power/rk3366-power.h>
  51 #include <dt-bindings/soc/rockchip_boot-mode.h>
  52
  53 / {
  54         compatible = "rockchip,rk3366";
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 serial0 = &uart0;
  67                 serial2 = &uart2;
  68                 serial3 = &uart3;
  69                 spi0 = &spi0;
  70                 spi1 = &spi1;
  71         };
  72
  73         cpus {
  74                 #address-cells = <0x2>;
  75                 #size-cells = <0x0>;
  76
  77                 cpu0: cpu@0 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a53","arm,armv8";
  80                         reg = <0x0 0x0>;
  81                         enable-method = "psci";
  82                         clocks = <&cru ARMCLK>;
  83                         operating-points-v2 = <&cpu0_opp_table>;
  84                         cpu-idle-states = <&cpu_sleep>;
  85                 };
  86
  87                 cpu1: cpu@1 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53","arm,armv8";
  90                         reg = <0x0 0x1>;
  91                         enable-method = "psci";
  92                         operating-points-v2 = <&cpu0_opp_table>;
  93                         cpu-idle-states = <&cpu_sleep>;
  94                 };
  95
  96                 cpu2: cpu@2 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a53","arm,armv8";
  99                         reg = <0x0 0x2>;
 100                         enable-method = "psci";
 101                         operating-points-v2 = <&cpu0_opp_table>;
 102                         cpu-idle-states = <&cpu_sleep>;
 103                 };
 104
 105                 cpu3: cpu@3 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53","arm,armv8";
 108                         reg = <0x0 0x3>;
 109                         enable-method = "psci";
 110                         operating-points-v2 = <&cpu0_opp_table>;
 111                         cpu-idle-states = <&cpu_sleep>;
 112                 };
 113
 114                 idle-states {
 115                         entry-method = "psci";
 116                         cpu_sleep: cpu-sleep-0 {
 117                                 compatible = "arm,idle-state";
 118                                 local-timer-stop;
 119                                 arm,psci-suspend-param = <0x0010000>;
 120                                 entry-latency-us = <350>;
 121                                 exit-latency-us = <600>;
 122                                 min-residency-us = <1150>;
 123                         };
 124                 };
 125         };
 126
 127         cpu0_opp_table: opp_table0 {
 128                 compatible = "operating-points-v2";
 129                 opp-shared;
 130
 131                 opp00 {
 132                         opp-hz = /bits/ 64 <408000000>;
 133                         opp-microvolt = <950000>;
 134                         clock-latency-ns = <40000>;
 135                         opp-suspend;
 136                 };
 137                 opp01 {
 138                         opp-hz = /bits/ 64 <600000000>;
 139                         opp-microvolt = <950000>;
 140                 };
 141                 opp02 {
 142                         opp-hz = /bits/ 64 <816000000>;
 143                         opp-microvolt = <1000000>;
 144                 };
 145                 opp03 {
 146                         opp-hz = /bits/ 64 <1008000000>;
 147                         opp-microvolt = <1075000>;
 148                 };
 149                 opp04 {
 150                         opp-hz = /bits/ 64 <1200000000>;
 151                         opp-microvolt = <1175000>;
 152                 };
 153                 opp05 {
 154                         opp-hz = /bits/ 64 <1296000000>;
 155                         opp-microvolt = <1250000>;
 156                 };
 157         };
 158
 159         psci {
 160                 compatible = "arm,psci-1.0";
 161                 method = "smc";
 162         };
 163
 164         timer {
 165                 compatible = "arm,armv8-timer";
 166                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 167                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 168                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 169                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 170         };
 171
 172         arm-pmu {
 173                 compatible = "arm,cortex-a53-pmu";
 174                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 178                 interrupt-affinity = <&cpu0>,
 179                                      <&cpu1>,
 180                                      <&cpu2>,
 181                                      <&cpu3>;
 182         };
 183
 184         xin24m: xin24m {
 185                 compatible = "fixed-clock";
 186                 #clock-cells = <0>;
 187                 clock-frequency = <24000000>;
 188                 clock-output-names = "xin24m";
 189         };
 190
 191         gic: interrupt-controller@ffb71000 {
 192                 compatible = "arm,gic-400";
 193                 interrupt-controller;
 194                 #interrupt-cells = <3>;
 195                 #address-cells = <0>;
 196
 197                 reg = <0x0 0xffb71000 0x0 0x1000>,
 198                       <0x0 0xffb72000 0x0 0x1000>,
 199                       <0x0 0xffb74000 0x0 0x2000>,
 200                       <0x0 0xffb76000 0x0 0x2000>;
 201                 interrupts = <GIC_PPI 9
 202                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 203         };
 204
 205         nandc0: nandc@ff0c0000 {
 206                 compatible = "rockchip,rk-nandc";
 207                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 208                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 209                 nandc_id = <0>;
 210                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 211                 clock-names = "clk_nandc", "hclk_nandc";
 212                 status = "disabled";
 213         };
 214
 215         saradc: saradc@ff100000 {
 216                 compatible = "rockchip,saradc";
 217                 reg = <0x0 0xff100000 0x0 0x100>;
 218                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 219                 #io-channel-cells = <1>;
 220                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 221                 clock-names = "saradc", "apb_pclk";
 222                 status = "disabled";
 223         };
 224
 225         spi0: spi@ff110000 {
 226                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 227                 reg = <0x0 0xff110000 0x0 0x1000>;
 228                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 229                 clock-names = "spiclk", "apb_pclk";
 230                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 231                 pinctrl-names = "default";
 232                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 233                 #address-cells = <1>;
 234                 #size-cells = <0>;
 235                 status = "disabled";
 236         };
 237
 238         spi1: spi@ff120000 {
 239                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 240                 reg = <0x0 0xff120000 0x0 0x1000>;
 241                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 242                 clock-names = "spiclk", "apb_pclk";
 243                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 244                 pinctrl-names = "default";
 245                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 246                 #address-cells = <1>;
 247                 #size-cells = <0>;
 248                 status = "disabled";
 249         };
 250
 251         scr: rkscr@ff1d0000 {
 252                 compatible = "rockchip-scr";
 253                 reg = <0x0 0xff1d0000 0x0 0x10000>;
 254                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 255                 #address-cells = <1>;
 256                 #size-cells = <0>;
 257                 pinctrl-names = "default";
 258                 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
 259                 clocks = <&cru PCLK_SIM>;
 260                 clock-names = "g_pclk_sim_card";
 261                 status = "disabled";
 262         };
 263
 264         sdmmc: rksdmmc@ff400000 {
 265                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 266                 clock-freq-min-max = <400000 150000000>;
 267                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 268                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 269                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 270                 fifo-depth = <0x100>;
 271                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 272                 reg = <0x0 0xff400000 0x0 0x4000>;
 273                 status = "disabled";
 274         };
 275
 276         sdio: rksdmmc@ff410000 {
 277                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 278                 clock-freq-min-max = <400000 150000000>;
 279                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 280                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 281                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 282                 fifo-depth = <0x100>;
 283                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 284                 reg = <0x0 0xff410000 0x0 0x4000>;
 285                 status = "disabled";
 286         };
 287
 288         emmc: rksdmmc@ff420000 {
 289                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 290                 clock-freq-min-max = <400000 150000000>;
 291                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 292                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 293                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 294                 fifo-depth = <0x100>;
 295                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 296                 reg = <0x0 0xff420000 0x0 0x4000>;
 297                 status = "disabled";
 298         };
 299
 300         gmac: eth@ff440000 {
 301                 compatible = "rockchip,rk3366-gmac";
 302                 reg = <0x0 0xff440000 0x0 0x10000>;
 303                 rockchip,grf = <&grf>;
 304                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 305                 interrupt-names = "macirq";
 306                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 307                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 308                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 309                          <&cru PCLK_GMAC>;
 310                 clock-names = "stmmaceth", "mac_clk_rx",
 311                               "mac_clk_tx", "clk_mac_ref",
 312                               "clk_mac_refout", "aclk_mac",
 313                               "pclk_mac";
 314                 resets = <&cru SRST_MAC>;
 315                 reset-names = "stmmaceth";
 316                 status = "disabled";
 317         };
 318
 319         i2c0: i2c@ff650000 {
 320                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 321                 reg = <0x0 0xff728000 0x0 0x1000>;
 322                 clocks = <&cru PCLK_I2C0>;
 323                 clock-names = "i2c";
 324                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 325                 pinctrl-names = "default";
 326                 pinctrl-0 = <&i2c0_xfer>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 status = "disabled";
 330         };
 331
 332         i2c2: i2c@ff140000 {
 333                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 334                 reg = <0x0 0xff140000 0x0 0x1000>;
 335                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338                 clock-names = "i2c";
 339                 clocks = <&cru PCLK_I2C2>;
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&i2c2_xfer>;
 342                 status = "disabled";
 343         };
 344
 345         i2c3: i2c@ff150000 {
 346                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 347                 reg = <0x0 0xff150000 0x0 0x1000>;
 348                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351                 clock-names = "i2c";
 352                 clocks = <&cru PCLK_I2C3>;
 353                 pinctrl-names = "default";
 354                 pinctrl-0 = <&i2c3_xfer>;
 355                 status = "disabled";
 356         };
 357
 358         i2c4: i2c@ff160000 {
 359                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 360                 reg = <0x0 0xff160000 0x0 0x1000>;
 361                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 clock-names = "i2c";
 365                 clocks = <&cru PCLK_I2C4>;
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&i2c4_xfer>;
 368                 status = "disabled";
 369         };
 370
 371         i2c5: i2c@ff170000 {
 372                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 373                 reg = <0x0 0xff170000 0x0 0x1000>;
 374                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 clock-names = "i2c";
 378                 clocks = <&cru PCLK_I2C5>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&i2c5_xfer>;
 381                 status = "disabled";
 382         };
 383
 384         uart0: serial@ff180000 {
 385                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 386                 reg = <0x0 0xff180000 0x0 0x100>;
 387                 clock-frequency = <24000000>;
 388                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 389                 clock-names = "baudclk", "apb_pclk";
 390                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 391                 reg-shift = <2>;
 392                 reg-io-width = <4>;
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 395                 status = "disabled";
 396         };
 397
 398         uart3: serial@ff1b0000 {
 399                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 400                 reg = <0x0 0xff1b0000 0x0 0x100>;
 401                 clock-frequency = <24000000>;
 402                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 403                 clock-names = "baudclk", "apb_pclk";
 404                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 405                 reg-shift = <2>;
 406                 reg-io-width = <4>;
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 409                 status = "disabled";
 410         };
 411
 412         usbphy: phy {
 413                 compatible = "rockchip,rk336x-usb-phy";
 414                 rockchip,grf = <&grf>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417
 418                 usbphy0: usb-phy0 {
 419                         #phy-cells = <0>;
 420                         #clock-cells = <0>;
 421                         reg = <0x700>;
 422                 };
 423
 424                 usbphy1: usb-phy1 {
 425                         #phy-cells = <0>;
 426                         #clock-cells = <0>;
 427                         reg = <0x728>;
 428                 };
 429         };
 430
 431         usb_host0_echi: usb@ff480000 {
 432                 compatible = "generic-ehci";
 433                 reg = <0x0 0xff480000 0x0 0x20000>;
 434                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 436                 clock-names = "sclk_otgphy0", "hclk_host0";
 437                 phys = <&usbphy1>;
 438                 phy-names = "usb";
 439                 status = "disabled";
 440         };
 441
 442         usb_host0_ohci: usb@ff4a0000 {
 443                 compatible = "generic-ohci";
 444                 reg = <0x0 0xff4a0000 0x0 0x20000>;
 445                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 446                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 447                 clock-names = "sclk_otgphy0", "hclk_host0";
 448                 status = "disabled";
 449         };
 450
 451         usb_otg: usb@ff4c0000 {
 452                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 453                              "snps,dwc2";
 454                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 455                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 456                 clocks = <&cru HCLK_OTG>;
 457                 clock-names = "otg";
 458                 dr_mode = "otg";
 459                 g-np-tx-fifo-size = <16>;
 460                 g-rx-fifo-size = <275>;
 461                 g-tx-fifo-size = <256 128 128 64 64 32>;
 462                 g-use-dma;
 463                 status = "disabled";
 464         };
 465
 466         i2c1: i2c@ff660000 {
 467                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 468                 reg = <0x0 0xff660000 0x0 0x1000>;
 469                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 470                 #address-cells = <1>;
 471                 #size-cells = <0>;
 472                 clock-names = "i2c";
 473                 clocks = <&cru PCLK_I2C1>;
 474                 pinctrl-names = "default";
 475                 pinctrl-0 = <&i2c1_xfer>;
 476                 status = "disabled";
 477         };
 478
 479         pwm0: pwm@ff680000 {
 480                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 481                 reg = <0x0 0xff680000 0x0 0x10>;
 482                 #pwm-cells = <3>;
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&pwm0_pin>;
 485                 clocks = <&cru PCLK_RKPWM>;
 486                 clock-names = "pwm";
 487                 status = "disabled";
 488         };
 489
 490         pwm1: pwm@ff680010 {
 491                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 492                 reg = <0x0 0xff680010 0x0 0x10>;
 493                 #pwm-cells = <3>;
 494                 pinctrl-names = "default";
 495                 pinctrl-0 = <&pwm1_pin>;
 496                 clocks = <&cru PCLK_RKPWM>;
 497                 clock-names = "pwm";
 498                 status = "disabled";
 499         };
 500
 501         pwm2: pwm@ff680020 {
 502                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 503                 reg = <0x0 0xff680020 0x0 0x10>;
 504                 #pwm-cells = <3>;
 505                 clocks = <&cru PCLK_RKPWM>;
 506                 clock-names = "pwm";
 507                 status = "disabled";
 508         };
 509
 510         pwm3: pwm@ff680030 {
 511                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 512                 reg = <0x0 0xff680030 0x0 0x10>;
 513                 #pwm-cells = <3>;
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&pwm3_t2_pin>;
 516                 clocks = <&cru PCLK_RKPWM>;
 517                 clock-names = "pwm";
 518                 status = "disabled";
 519         };
 520
 521         uart2: serial@ff690000 {
 522                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 523                 reg = <0x0 0xff690000 0x0 0x100>;
 524                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 525                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 526                 clock-names = "baudclk", "apb_pclk";
 527                 reg-shift = <2>;
 528                 reg-io-width = <4>;
 529                 pinctrl-names = "default";
 530                 pinctrl-0 = <&uart2_t1_xfer>;
 531                 status = "disabled";
 532         };
 533
 534         pmu: power-management@ff730000 {
 535                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 536                 reg = <0x0 0xff730000 0x0 0x1000>;
 537
 538                 power: power-controller {
 539                         status = "disabled";
 540                         compatible = "rockchip,rk3366-power-controller";
 541                         #power-domain-cells = <1>;
 542                         #address-cells = <1>;
 543                         #size-cells = <0>;
 544
 545                         /*
 546                          * Note: Although SCLK_* are the working clocks
 547                          * of device without including on the NOC, needed for
 548                          * synchronous reset.
 549                          *
 550                          * The clocks on the which NOC:
 551                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 552                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 553                          * ACLK_ISP is on ACLK_ISP_NIU.
 554                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 555                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 556                          *
 557                          * Which clock are device clocks:
 558                          *      clocks          devices
 559                          *      *_IEP           IEP:Image Enhancement Processor
 560                          *      *_ISP           ISP:Image Signal Processing
 561                          *      *_VOP*          VOP:Visual Output Processor
 562                          *      *_RGA           RGA
 563                          *      *_DPHY*         LVDS
 564                          *      *_HDMI          HDMI
 565                          *      *_MIPI_*        MIPI
 566                          */
 567                         pd_vio {
 568                                 reg = <RK3366_PD_VIO>;
 569                                 clocks = <&cru ACLK_IEP>,
 570                                          <&cru ACLK_ISP>,
 571                                          <&cru ACLK_RGA>,
 572                                          <&cru ACLK_HDCP>,
 573                                          <&cru ACLK_VOP_FULL>,
 574                                          <&cru ACLK_VOP_LITE>,
 575                                          <&cru ACLK_VOP_IEP>,
 576                                          <&cru DCLK_VOP_FULL>,
 577                                          <&cru DCLK_VOP_LITE>,
 578                                          <&cru HCLK_IEP>,
 579                                          <&cru HCLK_ISP>,
 580                                          <&cru HCLK_RGA>,
 581                                          <&cru HCLK_VOP_FULL>,
 582                                          <&cru HCLK_VOP_LITE>,
 583                                          <&cru HCLK_VIO_HDCPMMU>,
 584                                          <&cru PCLK_HDMI_CTRL>,
 585                                          <&cru PCLK_HDCP>,
 586                                          <&cru PCLK_MIPI_DSI0>,
 587                                          <&cru SCLK_VOP_FULL_PWM>,
 588                                          <&cru SCLK_HDCP>,
 589                                          <&cru SCLK_ISP>,
 590                                          <&cru SCLK_RGA>,
 591                                          <&cru SCLK_HDMI_CEC>,
 592                                          <&cru SCLK_HDMI_HDCP>;
 593                         };
 594
 595                         /*
 596                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 597                          * (video endecoder & decoder) clocks that on the
 598                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 599                          */
 600                         pd_vpu {
 601                                 reg = <RK3366_PD_VPU>;
 602                                 clocks = <&cru ACLK_VIDEO>,
 603                                          <&cru HCLK_VIDEO>;
 604                         };
 605
 606                         /*
 607                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 608                          * (video decoder) clocks that on the
 609                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 610                          */
 611                         pd_rkvdec {
 612                                 reg = <RK3366_PD_RKVDEC>;
 613                                 clocks = <&cru ACLK_RKVDEC>,
 614                                          <&cru HCLK_RKVDEC>;
 615                         };
 616
 617                         pd_video {
 618                                 reg = <RK3366_PD_VIDEO>;
 619                                 clocks = <&cru ACLK_VIDEO>,
 620                                          <&cru ACLK_RKVDEC>,
 621                                          <&cru HCLK_VIDEO>,
 622                                          <&cru HCLK_RKVDEC>,
 623                                          <&cru SCLK_HEVC_CABAC>,
 624                                          <&cru SCLK_HEVC_CORE>;
 625                         };
 626
 627                         /*
 628                          * Note: ACLK_GPU is the GPU clock,
 629                          * and on the ACLK_GPU_NIU (NOC).
 630                          */
 631                         pd_gpu {
 632                                 reg = <RK3366_PD_GPU>;
 633                                 clocks = <&cru ACLK_GPU>;
 634                         };
 635                 };
 636         };
 637
 638         pmugrf: syscon@ff738000 {
 639                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 640                 reg = <0x0 0xff738000 0x0 0x1000>;
 641
 642                 reboot-mode {
 643                         compatible = "syscon-reboot-mode";
 644                         offset = <0x200>;
 645                         mode-normal = <BOOT_NORMAL>;
 646                         mode-recovery = <BOOT_RECOVERY>;
 647                         mode-fastboot = <BOOT_FASTBOOT>;
 648                         mode-loader = <BOOT_LOADER>;
 649                 };
 650         };
 651
 652         amba {
 653                 compatible = "arm,amba-bus";
 654                 #address-cells = <2>;
 655                 #size-cells = <2>;
 656                 ranges;
 657
 658                 dmac_peri: dma-controller@ff250000 {
 659                         compatible = "arm,pl330", "arm,primecell";
 660                         reg = <0x0 0xff250000 0x0 0x4000>;
 661                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 662                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 663                         #dma-cells = <1>;
 664                         clocks = <&cru ACLK_DMAC_PERI>;
 665                         clock-names = "apb_pclk";
 666                 };
 667
 668                 dmac_bus: dma-controller@ff600000 {
 669                         compatible = "arm,pl330", "arm,primecell";
 670                         reg = <0x0 0xff600000 0x0 0x4000>;
 671                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 672                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 673                         #dma-cells = <1>;
 674                         clocks = <&cru ACLK_DMAC_BUS>;
 675                         clock-names = "apb_pclk";
 676                 };
 677         };
 678
 679         cru: clock-controller@ff760000 {
 680                 compatible = "rockchip,rk3366-cru";
 681                 reg = <0x0 0xff760000 0x0 0x1000>;
 682                 rockchip,grf = <&grf>;
 683                 #clock-cells = <1>;
 684                 #reset-cells = <1>;
 685                 assigned-clocks =
 686                         <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
 687                         <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
 688                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 689                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 690                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 691                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 692                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
 693                         <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
 694                         <&cru ACLK_PERI1>;
 695                 assigned-clock-rates =
 696                         <0>, <0>,
 697                         <0>, <0>,
 698                         <750000000>, <576000000>,
 699                         <594000000>, <594000000>,
 700                         <960000000>, <520000000>,
 701                         <375000000>, <288000000>,
 702                         <100000000>, <100000000>,
 703                         <288000000>, <288000000>,
 704                         <144000000>;
 705                 assigned-clock-parents =
 706                         <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
 707                         <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
 708         };
 709
 710         grf: syscon@ff770000 {
 711                 compatible = "rockchip,rk3366-grf", "syscon";
 712                 reg = <0x0 0xff770000 0x0 0x1000>;
 713         };
 714
 715         wdt: watchdog@ff800000 {
 716                 compatible = "snps,dw-wdt";
 717                 reg = <0x0 0xff800000 0x0 0x100>;
 718                 clocks = <&cru PCLK_WDT>;
 719                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 720                 status = "disabled";
 721         };
 722
 723         spdif: spdif@ff880000 {
 724                 compatible = "rockchip,rk3366-spdif";
 725                 reg = <0x0 0xff880000 0x0 0x1000>;
 726                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 727                 dmas = <&dmac_bus 3>;
 728                 dma-names = "tx";
 729                 clock-names = "mclk", "hclk";
 730                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 731                 pinctrl-names = "default";
 732                 pinctrl-0 = <&spdif_bus>;
 733                 status = "disabled";
 734         };
 735
 736         i2s_2ch: i2s-2ch@ff890000 {
 737                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 738                 reg = <0x0 0xff890000 0x0 0x1000>;
 739                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 740                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 741                 dma-names = "tx", "rx";
 742                 clock-names = "i2s_clk", "i2s_hclk";
 743                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 744                 status = "disabled";
 745         };
 746
 747         i2s_8ch: i2s-8ch@ff898000 {
 748                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 749                 reg = <0x0 0xff898000 0x0 0x1000>;
 750                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 751                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 752                 dma-names = "tx", "rx";
 753                 clock-names = "i2s_clk", "i2s_hclk";
 754                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 755                 pinctrl-names = "default";
 756                 pinctrl-0 = <&i2s_8ch_bus>;
 757                 status = "disabled";
 758         };
 759
 760         fb: fb {
 761                 compatible = "rockchip,rk-fb";
 762                 rockchip,disp-mode = <DUAL>;
 763                 status = "disabled";
 764         };
 765
 766         rk_screen: screen {
 767                 compatible = "rockchip,screen";
 768                 status = "disabled";
 769         };
 770
 771         vop_lite: vop@ff8f0000 {
 772                 compatible = "rockchip,rk3366-lcdc-lite";
 773                 rockchip,grf = <&grf>;
 774                 rockchip,pwr18 = <0>;
 775                 rockchip,iommu-enabled = <1>;
 776                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 777                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 778                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 779                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 780                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 781                 reset-names = "axi", "ahb", "dclk";
 782                 status = "disabled";
 783         };
 784
 785         vopl_mmu: vopl-mmu {
 786                 dbgname = "vop";
 787                 compatible = "rockchip,vopl_mmu";
 788                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 789                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 790                 interrupt-names = "vopl_mmu";
 791                 status = "disabled";
 792         };
 793
 794         iep: iep@ff900000 {
 795                 compatible = "rockchip,iep";
 796                 iommu_enabled = <1>;
 797                 reg = <0x0 0xff900000 0x0 0x800>;
 798                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 799                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 800                 clock-names = "aclk_iep", "hclk_iep";
 801                 version = <2>;
 802                 status = "disabled";
 803         };
 804
 805         rga: rga@ff920000 {
 806                 compatible = "rockchip,rga2";
 807                 dev_mode = <1>;
 808                 reg = <0x0 0xff920000 0x0 0x1000>;
 809                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 810                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 811                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 812                 status = "disabled";
 813         };
 814
 815         vop_big: vop@ff930000 {
 816                 compatible = "rockchip,rk3366-lcdc-big";
 817                 rockchip,grf = <&grf>;
 818                 rockchip,prop = <PRMRY>;
 819                 rockchip,pwr18 = <0>;
 820                 rockchip,iommu-enabled = <1>;
 821                 reg = <0x0 0xff930000 0x0 0x23f0>;
 822                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 823                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 824                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 825                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 826                 reset-names = "axi", "ahb", "dclk";
 827                 status = "disabled";
 828         };
 829
 830         vopb_mmu: vopb-mmu {
 831                 dbgname = "vop";
 832                 compatible = "rockchip,vopb_mmu";
 833                 reg = <0x0 0xff932400 0x0 0x100>;
 834                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 835                 interrupt-names = "vop_mmu";
 836                 status = "disabled";
 837         };
 838
 839         iep_mmu: iep-mmu {
 840                 dbgname = "iep";
 841                 compatible = "rockchip,iep_mmu";
 842                 reg = <0x0 0xff900800 0x0 0x100>;
 843                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 844                 interrupt-names = "iep_mmu";
 845                 status = "disabled";
 846         };
 847
 848         vpu_mmu: vpu_mmu {
 849                 dbgname = "vpu";
 850                 compatible = "rockchip,vpu_mmu";
 851                 reg = <0x0 0xff9a0800 0x0 0x100>;
 852                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 853                 interrupt-names = "vpu_mmu";
 854                 status = "disabled";
 855         };
 856
 857         vdec_mmu: vdec_mmu {
 858                 dbgname = "vdec";
 859                 compatible = "rockchip,vdec_mmu";
 860                 reg = <0x0 0xff9b0480 0x0 0x40>,
 861                       <0x0 0xff9b04c0 0x0 0x40>;
 862                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 863                 interrupt-names = "vdec_mmu";
 864                 status = "disabled";
 865         };
 866
 867         dsihost0: mipi@ff960000 {
 868                 compatible = "rockchip,rk3366-dsi";
 869                 rockchip,prop = <0>;
 870                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 871                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 872                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 873                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 874                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 875                 status = "disabled";
 876         };
 877
 878         lvds: lvds@ff968000 {
 879                 compatible = "rockchip,rk3366-lvds";
 880                 rockchip,grf = <&grf>;
 881                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 882                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 883                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 884                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 885                 status = "disabled";
 886         };
 887
 888         hdmi: hdmi@ff980000 {
 889                 compatible = "rockchip,rk3366-hdmi";
 890                 reg = <0x0 0xff980000 0x0 0x20000>;
 891                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 892                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 893                 clocks = <&cru PCLK_HDMI_CTRL>,
 894                          <&cru SCLK_HDMI_HDCP>,
 895                          <&cru SCLK_HDMI_CEC>,
 896                          <&cru DCLK_HDMIPHY>;
 897                 clock-names = "pclk_hdmi",
 898                               "hdcp_clk_hdmi",
 899                               "cec_clk_hdmi",
 900                               "dclk_hdmi_phy";
 901                 resets = <&cru SRST_HDMI>;
 902                 reset-names = "hdmi";
 903                 pinctrl-names = "default", "gpio";
 904                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 905                 pinctrl-1 = <&i2c5_gpio>;
 906                 status = "disabled";
 907         };
 908
 909         vpu: vpu_service@ff9a0000 {
 910                 compatible = "rockchip,vpu_service";
 911                 rockchip,grf = <&grf>;
 912                 iommu_enabled = <1>;
 913                 reg = <0x0 0xff9a0000 0x0 0x800>;
 914                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 915                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 916                 interrupt-names = "irq_dec", "irq_enc";
 917                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
 918                 clock-names = "aclk_vcodec", "hclk_vcodec";
 919                 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
 920                 reset-names = "video_h", "video_a";
 921                 name = "vpu_service";
 922                 dev_mode = <0>;
 923                 status = "disabled";
 924         };
 925
 926         rkvdec: rkvdec@ff9b0000 {
 927                 compatible = "rockchip,rkvdec";
 928                 rockchip,grf = <&grf>;
 929                 iommu_enabled = <1>;
 930                 reg = <0x0 0xff9b0000 0x0 0x400>;
 931                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 932                 interrupt-names = "irq_dec";
 933                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
 934                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
 935                 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
 936                 reset-names = "video_h", "video_a";
 937                 dev_mode = <2>;
 938                 name = "rkvdec";
 939                 status = "disabled";
 940         };
 941
 942         pinctrl: pinctrl {
 943                 compatible = "rockchip,rk3366-pinctrl";
 944                 rockchip,grf = <&grf>;
 945                 rockchip,pmu = <&pmugrf>;
 946                 #address-cells = <0x2>;
 947                 #size-cells = <0x2>;
 948                 ranges;
 949
 950                 gpio0: gpio0@ff750000 {
 951                         compatible = "rockchip,gpio-bank";
 952                         reg = <0x0 0xff750000 0x0 0x100>;
 953                         clocks = <&cru PCLK_GPIO0>;
 954                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 955
 956                         gpio-controller;
 957                         #gpio-cells = <0x2>;
 958
 959                         interrupt-controller;
 960                         #interrupt-cells = <0x2>;
 961                 };
 962
 963                 gpio1: gpio1@ff780000 {
 964                         compatible = "rockchip,gpio-bank";
 965                         reg = <0x0 0xff758000 0x0 0x100>;
 966                         clocks = <&cru PCLK_GPIO1>;
 967                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 968
 969                         gpio-controller;
 970                         #gpio-cells = <0x2>;
 971
 972                         interrupt-controller;
 973                         #interrupt-cells = <0x2>;
 974                 };
 975
 976                 gpio2: gpio2@ff790000 {
 977                         compatible = "rockchip,gpio-bank";
 978                         reg = <0x0 0xff790000 0x0 0x100>;
 979                         clocks = <&cru PCLK_GPIO2>;
 980                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 981
 982                         gpio-controller;
 983                         #gpio-cells = <0x2>;
 984
 985                         interrupt-controller;
 986                         #interrupt-cells = <0x2>;
 987                 };
 988
 989                 gpio3: gpio3@ff7a0000 {
 990                         compatible = "rockchip,gpio-bank";
 991                         reg = <0x0 0xff7a0000 0x0 0x100>;
 992                         clocks = <&cru PCLK_GPIO3>;
 993                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 994
 995                         gpio-controller;
 996                         #gpio-cells = <0x2>;
 997
 998                         interrupt-controller;
 999                         #interrupt-cells = <0x2>;
1000                 };
1001
1002                 gpio4: gpio4@ff7b0000 {
1003                         compatible = "rockchip,gpio-bank";
1004                         reg = <0x0 0xff7b0000 0x0 0x100>;
1005                         clocks = <&cru PCLK_GPIO4>;
1006                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1007
1008                         gpio-controller;
1009                         #gpio-cells = <0x2>;
1010
1011                         interrupt-controller;
1012                         #interrupt-cells = <0x2>;
1013                 };
1014
1015                 gpio5: gpio5@ff7c0000 {
1016                         compatible = "rockchip,gpio-bank";
1017                         reg = <0x0 0xff7c0000 0x0 0x100>;
1018                         clocks = <&cru PCLK_GPIO5>;
1019                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1020
1021                         gpio-controller;
1022                         #gpio-cells = <0x2>;
1023
1024                         interrupt-controller;
1025                         #interrupt-cells = <0x2>;
1026                 };
1027
1028                 pcfg_pull_up: pcfg-pull-up {
1029                         bias-pull-up;
1030                 };
1031
1032                 pcfg_pull_down: pcfg-pull-down {
1033                         bias-pull-down;
1034                 };
1035
1036                 pcfg_pull_none: pcfg-pull-none {
1037                         bias-disable;
1038                 };
1039
1040                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1041                         bias-disable;
1042                         drive-strength = <12>;
1043                 };
1044
1045                 emmc {
1046                         emmc_clk: emmc-clk {
1047                                 rockchip,pins =
1048                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
1049                         };
1050
1051                         emmc_cmd: emmc-cmd {
1052                                 rockchip,pins =
1053                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
1054                         };
1055
1056                         emmc_pwr: emmc-pwr {
1057                                 rockchip,pins =
1058                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
1059                         };
1060
1061                         emmc_bus1: emmc-bus1 {
1062                                 rockchip,pins =
1063                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
1064                         };
1065
1066                         emmc_bus4: emmc-bus4 {
1067                                 rockchip,pins =
1068                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1069                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1070                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1071                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1072                         };
1073
1074                         emmc_bus8: emmc-bus8 {
1075                                 rockchip,pins =
1076                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1077                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1078                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1079                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
1080                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
1081                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
1082                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
1083                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
1084                         };
1085                 };
1086
1087                 sdmmc {
1088                         sdmmc_cd: sdmmc-cd {
1089                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1090                         };
1091
1092                         sdmmc_bus1: sdmmc-bus1 {
1093                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1094                         };
1095
1096                         sdmmc_bus4: sdmmc-bus4 {
1097                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1098                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1099                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1100                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1101                         };
1102
1103                         sdmmc_clk: sdmmc-clk {
1104                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1105                         };
1106
1107                         sdmmc_cmd: sdmmc-cmd {
1108                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1109                         };
1110                 };
1111
1112                 sdio {
1113                         sdio_bus1: sdio-bus1 {
1114                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1115                         };
1116
1117                         sdio_bus4: sdio-bus4 {
1118                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1119                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1120                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1121                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1122                         };
1123
1124                         sdio_cmd: sdio-cmd {
1125                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1126                         };
1127
1128                         sdio_clk: sdio-clk {
1129                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1130                         };
1131
1132                         sdio_cd: sdio-cd {
1133                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1134                         };
1135
1136                         sdio_wp: sdio-wp {
1137                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1138                         };
1139
1140                         sdio_int: sdio-int {
1141                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1142                         };
1143
1144                         sdio_pwr: sdio-pwr {
1145                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1146                         };
1147                 };
1148
1149                 hdmi_i2c {
1150                         hdmii2c_xfer: hdmii2c-xfer {
1151                                 rockchip,pins =
1152                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1153                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1154                         };
1155                 };
1156
1157                 hdmi_pin {
1158                         hdmi_cec: hdmi-cec {
1159                                 rockchip,pins =
1160                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1161                         };
1162                 };
1163
1164                 i2c0 {
1165                         i2c0_xfer: i2c0-xfer {
1166                                 rockchip,pins =
1167                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1168                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1169                         };
1170                 };
1171
1172                 i2c1 {
1173                         i2c1_xfer: i2c1-xfer {
1174                                 rockchip,pins =
1175                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1176                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1177                         };
1178                 };
1179
1180                 i2c2 {
1181                         i2c2_xfer: i2c2-xfer {
1182                                 rockchip,pins =
1183                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1184                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1185                         };
1186
1187                         i2c2_gpio: i2c2-gpio {
1188                                 rockchip,pins =
1189                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1190                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1191                         };
1192                 };
1193
1194                 i2c3 {
1195                         i2c3_xfer: i2c3-xfer {
1196                                 rockchip,pins =
1197                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1198                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1199                         };
1200                 };
1201
1202                 i2c4 {
1203                         i2c4_xfer: i2c4-xfer {
1204                                 rockchip,pins =
1205                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1206                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1207                         };
1208
1209                         i2c4_gpio: i2c4-gpio {
1210                                 rockchip,pins =
1211                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1212                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1213                         };
1214                 };
1215
1216                 i2c5 {
1217                         i2c5_xfer: i2c5-xfer {
1218                                 rockchip,pins =
1219                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1220                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1221                         };
1222                         i2c5_gpio: i2c5-gpio {
1223                                 rockchip,pins =
1224                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1225                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1226                         };
1227                 };
1228
1229                 i2s {
1230                         i2s_8ch_bus: i2s-8ch-bus {
1231                                 rockchip,pins =
1232                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1233                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1234                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1235                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1236                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1237                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1238                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1239                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1240                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1241                         };
1242                 };
1243
1244                 spdif {
1245                         spdif_bus: spdif-bus {
1246                                 rockchip,pins =
1247                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1248                         };
1249                 };
1250
1251                 spi0 {
1252                         spi0_clk: spi0-clk {
1253                                 rockchip,pins =
1254                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1255                         };
1256                         spi0_cs0: spi0-cs0 {
1257                                 rockchip,pins =
1258                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1259                         };
1260                         spi0_cs1: spi0-cs1 {
1261                                 rockchip,pins =
1262                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1263                         };
1264                         spi0_tx: spi0-tx {
1265                                 rockchip,pins =
1266                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1267                         };
1268                         spi0_rx: spi0-rx {
1269                                 rockchip,pins =
1270                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1271                         };
1272                 };
1273
1274                 spi1 {
1275                         spi1_clk: spi1-clk {
1276                                 rockchip,pins =
1277                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1278                         };
1279                         spi1_cs0: spi1-cs0 {
1280                                 rockchip,pins =
1281                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1282                         };
1283                         spi1_tx: spi1-tx {
1284                                 rockchip,pins =
1285                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1286                         };
1287                         spi1_rx: spi1-rx {
1288                                 rockchip,pins =
1289                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1290                         };
1291                 };
1292
1293                 scr {
1294                         scr_clk: scr-clk {
1295                                 rockchip,pins =
1296                                         <5 8 RK_FUNC_2 &pcfg_pull_none>;
1297                         };
1298
1299                         scr_io: scr-io {
1300                                 rockchip,pins =
1301                                         <5 9 RK_FUNC_2 &pcfg_pull_up>;
1302                         };
1303
1304                         scr_rst: scr-rst {
1305                                 rockchip,pins =
1306                                         <5 10 RK_FUNC_1 &pcfg_pull_none>;
1307                         };
1308
1309                         scr_detect: scr-detect {
1310                                 rockchip,pins =
1311                                         <5 11 RK_FUNC_1 &pcfg_pull_none>;
1312                         };
1313                 };
1314
1315                 uart0 {
1316                         uart0_xfer: uart0-xfer {
1317                                 rockchip,pins =
1318                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1319                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1320                         };
1321
1322                         uart0_cts: uart0-cts {
1323                                 rockchip,pins =
1324                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1325                         };
1326
1327                         uart0_rts: uart0-rts {
1328                                 rockchip,pins =
1329                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1330                         };
1331                 };
1332
1333                 uart2_t0 {
1334                         uart2_t0_xfer: uart2_t0-xfer {
1335                                 rockchip,pins =
1336                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1337                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1338                         };
1339                         /* no rts / cts for uart2 */
1340                 };
1341
1342                 uart2_t1 {
1343                         uart2_t1_xfer: uart2_t1-xfer {
1344                                 rockchip,pins =
1345                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1346                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1347                         };
1348                         /* no rts / cts for uart2 */
1349                 };
1350
1351                 uart2_t2 {
1352                         uart2_t2_xfer: uart2_t2-xfer {
1353                                 rockchip,pins =
1354                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1355                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1356                         };
1357                         /* no rts / cts for uart2 */
1358                 };
1359
1360                 uart3 {
1361                         uart3_xfer: uart3-xfer {
1362                                 rockchip,pins =
1363                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1364                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1365                         };
1366
1367                         uart3_cts: uart3-cts {
1368                                 rockchip,pins =
1369                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1370                         };
1371
1372                         uart3_rts: uart3-rts {
1373                                 rockchip,pins =
1374                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1375                         };
1376                 };
1377
1378                 pwm0 {
1379                         pwm0_pin: pwm0-pin {
1380                                 rockchip,pins =
1381                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1382                         };
1383                 };
1384
1385                 pwm1 {
1386                         pwm1_pin: pwm1-pin {
1387                                 rockchip,pins =
1388                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1389                         };
1390                 };
1391
1392                 pwm2_t0 {
1393                         pwm2_t0_pin: pwm2_t0-pin {
1394                                 rockchip,pins =
1395                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1396                         };
1397                 };
1398
1399                 pwm2_t1 {
1400                         pwm2_t1_pin: pwm2_t1-pin {
1401                                 rockchip,pins =
1402                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1403                         };
1404                 };
1405
1406                 pwm3_t0 {
1407                         pwm3_t0_pin: pwm3_t0-pin {
1408                                 rockchip,pins =
1409                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1410                         };
1411                 };
1412
1413                 pwm3_t1 {
1414                         pwm3_t1_pin: pwm3_t1-pin {
1415                                 rockchip,pins =
1416                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1417                         };
1418                 };
1419
1420                 pwm3_t2 {
1421                         pwm3_t2_pin: pwm3_t2-pin {
1422                                 rockchip,pins =
1423                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1424                         };
1425                 };
1426
1427                 lcdc {
1428                         lcdc_lcdc: lcdc-lcdc {
1429                                 rockchip,pins =
1430                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1431                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1432                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1433                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1434                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1435                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1436                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1437                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1438                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1439                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1440                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1441                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1442                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1443                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1444                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1445                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1446                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1447                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1448                         };
1449
1450                         lcdc_gpio: lcdc-gpio {
1451                                 rockchip,pins =
1452                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1453                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1454                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1455                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1456                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1457                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1458                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1459                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1460                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1461                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1462                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1463                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1464                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1465                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1466                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1467                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1468                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1469                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1470                         };
1471                 };
1472
1473                 gmac {
1474                         rgmii_pins: rgmii-pins {
1475                                 rockchip,pins =
1476                                         /* mac_rxd3 */
1477                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1478                                         /* mac_rxd2 */
1479                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1480                                         /* mac_txd3 */
1481                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1482                                         /* mac_txd2 */
1483                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1484                                         /* mac_rxd1 */
1485                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1486                                         /* mac_rxd0 */
1487                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1488                                         /* mac_txd1 */
1489                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1490                                         /* mac_txd0 */
1491                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1492                                         /* mac_txclkout */
1493                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1494                                         /* mac_crs */
1495                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1496                                         /* mac_rxclkin */
1497                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1498                                         /* mac_mdio */
1499                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1500                                         /* mac_txen */
1501                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1502                                         /* mac_clk */
1503                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1504                                         /* mac_rxer */
1505                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1506                                         /* mac_rxdv */
1507                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1508                                         /* mac_mdc */
1509                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1510                         };
1511
1512                         rmii_pins: rmii-pins {
1513                                 rockchip,pins =
1514                                         /* mac_rxd1 */
1515                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1516                                         /* mac_rxd0 */
1517                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1518                                         /* mac_txd1 */
1519                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1520                                         /* mac_txd0 */
1521                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1522                                         /* mac_crs */
1523                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1524                                         /* mac_rxclkin */
1525                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1526                                         /* mac_mdio */
1527                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1528                                         /* mac_txen */
1529                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1530                                         /* mac_clk */
1531                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1532                                         /* mac_rxer */
1533                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1534                                         /* mac_rxdv */
1535                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1536                                         /* mac_mdc */
1537                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1538                         };
1539                 };
1540
1541                 eth_phy {
1542                         eth_phy_pwr: eth-phy-pwr {
1543                                 rockchip,pins =
1544                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1545                         };
1546                 };
1547         };
1548
1549         gpu: gpu@ffa30000 {
1550                 compatible = "arm,malit764",
1551                              "arm,malit76x",
1552                              "arm,malit7xx",
1553                              "arm,mali-midgard";
1554
1555                 reg = <0x0 0xffa30000 0 0x10000>;
1556
1557                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1558                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1559                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1560                 interrupt-names = "GPU", "MMU", "JOB";
1561
1562                 clocks = <&cru ACLK_GPU>;
1563                 clock-names = "clk_mali";
1564                 operating-points-v2 = <&gpu_opp_table>;
1565                 status = "disabled";
1566         };
1567
1568         gpu_opp_table: gpu_opp_table {
1569                 compatible = "operating-points-v2";
1570                 opp-shared;
1571
1572                 opp00 {
1573                         opp-hz = /bits/ 64 <96000000>;
1574                         opp-microvolt = <1100000>;
1575                 };
1576                 opp01 {
1577                         opp-hz = /bits/ 64 <192000000>;
1578                         opp-microvolt = <1100000>;
1579                 };
1580                 opp02 {
1581                         opp-hz = /bits/ 64 <288000000>;
1582                         opp-microvolt = <1100000>;
1583                 };
1584                 opp03 {
1585                         opp-hz = /bits/ 64 <375000000>;
1586                         opp-microvolt = <1125000>;
1587                 };
1588                 opp04 {
1589                         opp-hz = /bits/ 64 <480000000>;
1590                         opp-microvolt = <1200000>;
1591                 };
1592         };
1593 };