arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/power/rk3366-power.h>
  50 #include <dt-bindings/soc/rockchip_boot-mode.h>
  51
  52 / {
  53         compatible = "rockchip,rk3366";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 serial0 = &uart0;
  66                 serial2 = &uart2;
  67                 serial3 = &uart3;
  68                 spi0 = &spi0;
  69                 spi1 = &spi1;
  70         };
  71
  72         cpus {
  73                 #address-cells = <0x2>;
  74                 #size-cells = <0x0>;
  75
  76                 cpu0: cpu@0 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53","arm,armv8";
  79                         reg = <0x0 0x0>;
  80                         enable-method = "psci";
  81                         clocks = <&cru ARMCLK>;
  82                         operating-points-v2 = <&cpu0_opp_table>;
  83                 };
  84
  85                 cpu1: cpu@1 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a53","arm,armv8";
  88                         reg = <0x0 0x1>;
  89                         enable-method = "psci";
  90                         operating-points-v2 = <&cpu0_opp_table>;
  91                 };
  92
  93                 cpu2: cpu@2 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53","arm,armv8";
  96                         reg = <0x0 0x2>;
  97                         enable-method = "psci";
  98                         operating-points-v2 = <&cpu0_opp_table>;
  99                 };
 100
 101                 cpu3: cpu@3 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53","arm,armv8";
 104                         reg = <0x0 0x3>;
 105                         enable-method = "psci";
 106                         operating-points-v2 = <&cpu0_opp_table>;
 107                 };
 108         };
 109
 110         cpu0_opp_table: opp_table0 {
 111                 compatible = "operating-points-v2";
 112                 opp-shared;
 113
 114                 opp00 {
 115                         opp-hz = /bits/ 64 <408000000>;
 116                         opp-microvolt = <1200000>;
 117                         clock-latency-ns = <40000>;
 118                         opp-suspend;
 119                 };
 120                 opp01 {
 121                         opp-hz = /bits/ 64 <600000000>;
 122                         opp-microvolt = <1200000>;
 123                 };
 124                 opp02 {
 125                         opp-hz = /bits/ 64 <816000000>;
 126                         opp-microvolt = <1200000>;
 127                 };
 128                 opp03 {
 129                         opp-hz = /bits/ 64 <1008000000>;
 130                         opp-microvolt = <1200000>;
 131                 };
 132                 opp04 {
 133                         opp-hz = /bits/ 64 <1200000000>;
 134                         opp-microvolt = <1200000>;
 135                 };
 136         };
 137
 138         psci {
 139                 compatible = "arm,psci-1.0";
 140                 method = "smc";
 141         };
 142
 143         timer {
 144                 compatible = "arm,armv8-timer";
 145                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 146                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 147                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 148                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 149         };
 150
 151         arm-pmu {
 152                 compatible = "arm,cortex-a53-pmu";
 153                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 155                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 156                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 157                 interrupt-affinity = <&cpu0>,
 158                                      <&cpu1>,
 159                                      <&cpu2>,
 160                                      <&cpu3>;
 161         };
 162
 163         xin24m: xin24m {
 164                 compatible = "fixed-clock";
 165                 #clock-cells = <0>;
 166                 clock-frequency = <24000000>;
 167                 clock-output-names = "xin24m";
 168         };
 169
 170         gic: interrupt-controller@ffb71000 {
 171                 compatible = "arm,gic-400";
 172                 interrupt-controller;
 173                 #interrupt-cells = <3>;
 174                 #address-cells = <0>;
 175
 176                 reg = <0x0 0xffb71000 0x0 0x1000>,
 177                       <0x0 0xffb72000 0x0 0x1000>,
 178                       <0x0 0xffb74000 0x0 0x2000>,
 179                       <0x0 0xffb76000 0x0 0x2000>;
 180                 interrupts = <GIC_PPI 9
 181                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 182         };
 183
 184         nandc0: nandc@ff0c0000 {
 185                 compatible = "rockchip,rk-nandc";
 186                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 187                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 188                 nandc_id = <0>;
 189                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 190                 clock-names = "clk_nandc", "hclk_nandc";
 191                 status = "disabled";
 192         };
 193
 194         saradc: saradc@ff100000 {
 195                 compatible = "rockchip,saradc";
 196                 reg = <0x0 0xff100000 0x0 0x100>;
 197                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 198                 #io-channel-cells = <1>;
 199                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 200                 clock-names = "saradc", "apb_pclk";
 201                 status = "disabled";
 202         };
 203
 204         spi0: spi@ff110000 {
 205                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 206                 reg = <0x0 0xff110000 0x0 0x1000>;
 207                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 208                 clock-names = "spiclk", "apb_pclk";
 209                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 210                 pinctrl-names = "default";
 211                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214                 status = "disabled";
 215         };
 216
 217         spi1: spi@ff120000 {
 218                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 219                 reg = <0x0 0xff120000 0x0 0x1000>;
 220                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 221                 clock-names = "spiclk", "apb_pclk";
 222                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 223                 pinctrl-names = "default";
 224                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227                 status = "disabled";
 228         };
 229
 230         scr: rkscr@ff1d0000 {
 231                 compatible = "rockchip-scr";
 232                 reg = <0x0 0xff1d0000 0x0 0x10000>;
 233                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 pinctrl-names = "default";
 237                 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
 238                 clocks = <&cru PCLK_SIM>;
 239                 clock-names = "g_pclk_sim_card";
 240                 status = "disabled";
 241         };
 242
 243         sdmmc: rksdmmc@ff400000 {
 244                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 245                 clock-freq-min-max = <400000 150000000>;
 246                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 247                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 248                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 249                 fifo-depth = <0x100>;
 250                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 251                 reg = <0x0 0xff400000 0x0 0x4000>;
 252                 status = "disabled";
 253         };
 254
 255         sdio: rksdmmc@ff410000 {
 256                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 257                 clock-freq-min-max = <400000 150000000>;
 258                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 259                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 260                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 261                 fifo-depth = <0x100>;
 262                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 263                 reg = <0x0 0xff410000 0x0 0x4000>;
 264                 status = "disabled";
 265         };
 266
 267         emmc: rksdmmc@ff420000 {
 268                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 269                 clock-freq-min-max = <400000 150000000>;
 270                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 271                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 272                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 273                 fifo-depth = <0x100>;
 274                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 275                 reg = <0x0 0xff420000 0x0 0x4000>;
 276                 status = "disabled";
 277         };
 278
 279         gmac: eth@ff440000 {
 280                 compatible = "rockchip,rk3366-gmac";
 281                 reg = <0x0 0xff440000 0x0 0x10000>;
 282                 rockchip,grf = <&grf>;
 283                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 284                 interrupt-names = "macirq";
 285                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 286                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 287                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 288                          <&cru PCLK_GMAC>;
 289                 clock-names = "stmmaceth", "mac_clk_rx",
 290                               "mac_clk_tx", "clk_mac_ref",
 291                               "clk_mac_refout", "aclk_mac",
 292                               "pclk_mac";
 293                 resets = <&cru SRST_MAC>;
 294                 reset-names = "stmmaceth";
 295                 status = "disabled";
 296         };
 297
 298         i2c0: i2c@ff650000 {
 299                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 300                 reg = <0x0 0xff728000 0x0 0x1000>;
 301                 clocks = <&cru PCLK_I2C0>;
 302                 clock-names = "i2c";
 303                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&i2c0_xfer>;
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308                 status = "disabled";
 309         };
 310
 311         i2c2: i2c@ff140000 {
 312                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 313                 reg = <0x0 0xff140000 0x0 0x1000>;
 314                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 clock-names = "i2c";
 318                 clocks = <&cru PCLK_I2C2>;
 319                 pinctrl-names = "default";
 320                 pinctrl-0 = <&i2c2_xfer>;
 321                 status = "disabled";
 322         };
 323
 324         i2c3: i2c@ff150000 {
 325                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 326                 reg = <0x0 0xff150000 0x0 0x1000>;
 327                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330                 clock-names = "i2c";
 331                 clocks = <&cru PCLK_I2C3>;
 332                 pinctrl-names = "default";
 333                 pinctrl-0 = <&i2c3_xfer>;
 334                 status = "disabled";
 335         };
 336
 337         i2c4: i2c@ff160000 {
 338                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 339                 reg = <0x0 0xff160000 0x0 0x1000>;
 340                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 341                 #address-cells = <1>;
 342                 #size-cells = <0>;
 343                 clock-names = "i2c";
 344                 clocks = <&cru PCLK_I2C4>;
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&i2c4_xfer>;
 347                 status = "disabled";
 348         };
 349
 350         i2c5: i2c@ff170000 {
 351                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 352                 reg = <0x0 0xff170000 0x0 0x1000>;
 353                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 clock-names = "i2c";
 357                 clocks = <&cru PCLK_I2C5>;
 358                 pinctrl-names = "default";
 359                 pinctrl-0 = <&i2c5_xfer>;
 360                 status = "disabled";
 361         };
 362
 363         uart0: serial@ff180000 {
 364                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 365                 reg = <0x0 0xff180000 0x0 0x100>;
 366                 clock-frequency = <24000000>;
 367                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 368                 clock-names = "baudclk", "apb_pclk";
 369                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 370                 reg-shift = <2>;
 371                 reg-io-width = <4>;
 372                 pinctrl-names = "default";
 373                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 374                 status = "disabled";
 375         };
 376
 377         uart3: serial@ff1b0000 {
 378                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 379                 reg = <0x0 0xff1b0000 0x0 0x100>;
 380                 clock-frequency = <24000000>;
 381                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 382                 clock-names = "baudclk", "apb_pclk";
 383                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 384                 reg-shift = <2>;
 385                 reg-io-width = <4>;
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 388                 status = "disabled";
 389         };
 390
 391         usbphy: phy {
 392                 compatible = "rockchip,rk336x-usb-phy";
 393                 rockchip,grf = <&grf>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396
 397                 usbphy0: usb-phy0 {
 398                         #phy-cells = <0>;
 399                         #clock-cells = <0>;
 400                         reg = <0x700>;
 401                 };
 402
 403                 usbphy1: usb-phy1 {
 404                         #phy-cells = <0>;
 405                         #clock-cells = <0>;
 406                         reg = <0x728>;
 407                 };
 408         };
 409
 410         usb_host0_echi: usb@ff480000 {
 411                 compatible = "generic-ehci";
 412                 reg = <0x0 0xff480000 0x0 0x20000>;
 413                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 414                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 415                 clock-names = "sclk_otgphy0", "hclk_host0";
 416                 phys = <&usbphy1>;
 417                 phy-names = "usb";
 418                 status = "disabled";
 419         };
 420
 421         usb_host0_ohci: usb@ff4a0000 {
 422                 compatible = "generic-ohci";
 423                 reg = <0x0 0xff4a0000 0x0 0x20000>;
 424                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 425                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 426                 clock-names = "sclk_otgphy0", "hclk_host0";
 427                 status = "disabled";
 428         };
 429
 430         usb_otg: usb@ff4c0000 {
 431                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 432                              "snps,dwc2";
 433                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 434                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&cru HCLK_OTG>;
 436                 clock-names = "otg";
 437                 dr_mode = "otg";
 438                 g-np-tx-fifo-size = <16>;
 439                 g-rx-fifo-size = <275>;
 440                 g-tx-fifo-size = <256 128 128 64 64 32>;
 441                 g-use-dma;
 442                 status = "disabled";
 443         };
 444
 445         i2c1: i2c@ff660000 {
 446                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 447                 reg = <0x0 0xff660000 0x0 0x1000>;
 448                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 clock-names = "i2c";
 452                 clocks = <&cru PCLK_I2C1>;
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&i2c1_xfer>;
 455                 status = "disabled";
 456         };
 457
 458         pwm0: pwm@ff680000 {
 459                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 460                 reg = <0x0 0xff680000 0x0 0x10>;
 461                 #pwm-cells = <3>;
 462                 pinctrl-names = "default";
 463                 pinctrl-0 = <&pwm0_pin>;
 464                 clocks = <&cru PCLK_RKPWM>;
 465                 clock-names = "pwm";
 466                 status = "disabled";
 467         };
 468
 469         pwm1: pwm@ff680010 {
 470                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 471                 reg = <0x0 0xff680010 0x0 0x10>;
 472                 #pwm-cells = <3>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&pwm1_pin>;
 475                 clocks = <&cru PCLK_RKPWM>;
 476                 clock-names = "pwm";
 477                 status = "disabled";
 478         };
 479
 480         pwm2: pwm@ff680020 {
 481                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 482                 reg = <0x0 0xff680020 0x0 0x10>;
 483                 #pwm-cells = <3>;
 484                 clocks = <&cru PCLK_RKPWM>;
 485                 clock-names = "pwm";
 486                 status = "disabled";
 487         };
 488
 489         pwm3: pwm@ff680030 {
 490                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 491                 reg = <0x0 0xff680030 0x0 0x10>;
 492                 #pwm-cells = <3>;
 493                 pinctrl-names = "default";
 494                 pinctrl-0 = <&pwm3_t2_pin>;
 495                 clocks = <&cru PCLK_RKPWM>;
 496                 clock-names = "pwm";
 497                 status = "disabled";
 498         };
 499
 500         uart2: serial@ff690000 {
 501                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 502                 reg = <0x0 0xff690000 0x0 0x100>;
 503                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 504                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 505                 clock-names = "baudclk", "apb_pclk";
 506                 reg-shift = <2>;
 507                 reg-io-width = <4>;
 508                 pinctrl-names = "default";
 509                 pinctrl-0 = <&uart2_t1_xfer>;
 510                 status = "disabled";
 511         };
 512
 513         pmu: power-management@ff730000 {
 514                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 515                 reg = <0x0 0xff730000 0x0 0x1000>;
 516
 517                 power: power-controller {
 518                         status = "disabled";
 519                         compatible = "rockchip,rk3366-power-controller";
 520                         #power-domain-cells = <1>;
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523
 524                         /*
 525                          * Note: Although SCLK_* are the working clocks
 526                          * of device without including on the NOC, needed for
 527                          * synchronous reset.
 528                          *
 529                          * The clocks on the which NOC:
 530                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 531                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 532                          * ACLK_ISP is on ACLK_ISP_NIU.
 533                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 534                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 535                          *
 536                          * Which clock are device clocks:
 537                          *      clocks          devices
 538                          *      *_IEP           IEP:Image Enhancement Processor
 539                          *      *_ISP           ISP:Image Signal Processing
 540                          *      *_VOP*          VOP:Visual Output Processor
 541                          *      *_RGA           RGA
 542                          *      *_DPHY*         LVDS
 543                          *      *_HDMI          HDMI
 544                          *      *_MIPI_*        MIPI
 545                          */
 546                         pd_vio {
 547                                 reg = <RK3366_PD_VIO>;
 548                                 clocks = <&cru ACLK_IEP>,
 549                                          <&cru ACLK_ISP>,
 550                                          <&cru ACLK_RGA>,
 551                                          <&cru ACLK_HDCP>,
 552                                          <&cru ACLK_VOP_FULL>,
 553                                          <&cru ACLK_VOP_LITE>,
 554                                          <&cru ACLK_VOP_IEP>,
 555                                          <&cru DCLK_VOP_FULL>,
 556                                          <&cru DCLK_VOP_LITE>,
 557                                          <&cru HCLK_IEP>,
 558                                          <&cru HCLK_ISP>,
 559                                          <&cru HCLK_RGA>,
 560                                          <&cru HCLK_VOP_FULL>,
 561                                          <&cru HCLK_VOP_LITE>,
 562                                          <&cru HCLK_VIO_HDCPMMU>,
 563                                          <&cru PCLK_HDMI_CTRL>,
 564                                          <&cru PCLK_HDCP>,
 565                                          <&cru PCLK_MIPI_DSI0>,
 566                                          <&cru SCLK_VOP_FULL_PWM>,
 567                                          <&cru SCLK_HDCP>,
 568                                          <&cru SCLK_ISP>,
 569                                          <&cru SCLK_RGA>,
 570                                          <&cru SCLK_HDMI_CEC>,
 571                                          <&cru SCLK_HDMI_HDCP>;
 572                         };
 573
 574                         /*
 575                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 576                          * (video endecoder & decoder) clocks that on the
 577                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 578                          */
 579                         pd_vpu {
 580                                 reg = <RK3366_PD_VPU>;
 581                                 clocks = <&cru ACLK_VIDEO>,
 582                                          <&cru HCLK_VIDEO>;
 583                         };
 584
 585                         /*
 586                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 587                          * (video decoder) clocks that on the
 588                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 589                          */
 590                         pd_rkvdec {
 591                                 reg = <RK3366_PD_RKVDEC>;
 592                                 clocks = <&cru ACLK_RKVDEC>,
 593                                          <&cru HCLK_RKVDEC>;
 594                         };
 595
 596                         pd_video {
 597                                 reg = <RK3366_PD_VIDEO>;
 598                                 clocks = <&cru ACLK_VIDEO>,
 599                                          <&cru ACLK_RKVDEC>,
 600                                          <&cru HCLK_VIDEO>,
 601                                          <&cru HCLK_RKVDEC>,
 602                                          <&cru SCLK_HEVC_CABAC>,
 603                                          <&cru SCLK_HEVC_CORE>;
 604                         };
 605
 606                         /*
 607                          * Note: ACLK_GPU is the GPU clock,
 608                          * and on the ACLK_GPU_NIU (NOC).
 609                          */
 610                         pd_gpu {
 611                                 reg = <RK3366_PD_GPU>;
 612                                 clocks = <&cru ACLK_GPU>;
 613                         };
 614                 };
 615         };
 616
 617         pmugrf: syscon@ff738000 {
 618                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 619                 reg = <0x0 0xff738000 0x0 0x1000>;
 620
 621                 reboot-mode {
 622                         compatible = "syscon-reboot-mode";
 623                         offset = <0x200>;
 624                         mode-normal = <BOOT_NORMAL>;
 625                         mode-recovery = <BOOT_RECOVERY>;
 626                         mode-fastboot = <BOOT_FASTBOOT>;
 627                         mode-loader = <BOOT_LOADER>;
 628                 };
 629         };
 630
 631         amba {
 632                 compatible = "arm,amba-bus";
 633                 #address-cells = <2>;
 634                 #size-cells = <2>;
 635                 ranges;
 636
 637                 dmac_peri: dma-controller@ff250000 {
 638                         compatible = "arm,pl330", "arm,primecell";
 639                         reg = <0x0 0xff250000 0x0 0x4000>;
 640                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 641                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 642                         #dma-cells = <1>;
 643                         clocks = <&cru ACLK_DMAC_PERI>;
 644                         clock-names = "apb_pclk";
 645                 };
 646
 647                 dmac_bus: dma-controller@ff600000 {
 648                         compatible = "arm,pl330", "arm,primecell";
 649                         reg = <0x0 0xff600000 0x0 0x4000>;
 650                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 651                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 652                         #dma-cells = <1>;
 653                         clocks = <&cru ACLK_DMAC_BUS>;
 654                         clock-names = "apb_pclk";
 655                 };
 656         };
 657
 658         cru: clock-controller@ff760000 {
 659                 compatible = "rockchip,rk3366-cru";
 660                 reg = <0x0 0xff760000 0x0 0x1000>;
 661                 rockchip,grf = <&grf>;
 662                 #clock-cells = <1>;
 663                 #reset-cells = <1>;
 664                 assigned-clocks =
 665                         <&cru SCLK_32K>,
 666                         <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
 667                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 668                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 669                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 670                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 671                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
 672                         <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
 673                         <&cru ACLK_PERI1>;
 674                 assigned-clock-rates =
 675                         <0>,
 676                         <0>, <0>,
 677                         <750000000>, <576000000>,
 678                         <594000000>, <594000000>,
 679                         <960000000>, <520000000>,
 680                         <375000000>, <288000000>,
 681                         <100000000>, <100000000>,
 682                         <288000000>, <288000000>,
 683                         <144000000>;
 684                 assigned-clock-parents =
 685                         <&cru SCLK_32K_INTR>,
 686                         <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
 687         };
 688
 689         grf: syscon@ff770000 {
 690                 compatible = "rockchip,rk3366-grf", "syscon";
 691                 reg = <0x0 0xff770000 0x0 0x1000>;
 692         };
 693
 694         wdt: watchdog@ff800000 {
 695                 compatible = "snps,dw-wdt";
 696                 reg = <0x0 0xff800000 0x0 0x100>;
 697                 clocks = <&cru PCLK_WDT>;
 698                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 699                 status = "disabled";
 700         };
 701
 702         spdif: spdif@ff880000 {
 703                 compatible = "rockchip,rk3366-spdif";
 704                 reg = <0x0 0xff880000 0x0 0x1000>;
 705                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 706                 dmas = <&dmac_bus 3>;
 707                 dma-names = "tx";
 708                 clock-names = "hclk", "mclk";
 709                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 710                 pinctrl-names = "default";
 711                 pinctrl-0 = <&spdif_bus>;
 712                 status = "disabled";
 713         };
 714
 715         i2s_2ch: i2s-2ch@ff890000 {
 716                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 717                 reg = <0x0 0xff890000 0x0 0x1000>;
 718                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 719                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 720                 dma-names = "tx", "rx";
 721                 clock-names = "i2s_hclk", "i2s_clk";
 722                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 723                 status = "disabled";
 724         };
 725
 726         i2s_8ch: i2s-8ch@ff898000 {
 727                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 728                 reg = <0x0 0xff898000 0x0 0x1000>;
 729                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 730                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 731                 dma-names = "tx", "rx";
 732                 clock-names = "i2s_hclk", "i2s_clk";
 733                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 734                 pinctrl-names = "default";
 735                 pinctrl-0 = <&i2s_8ch_bus>;
 736                 status = "disabled";
 737         };
 738
 739         fb: fb {
 740                 compatible = "rockchip,rk-fb";
 741                 rockchip,disp-mode = <DUAL>;
 742                 status = "disabled";
 743         };
 744
 745         rk_screen: screen {
 746                 compatible = "rockchip,screen";
 747                 status = "disabled";
 748         };
 749
 750         vop_lite: vop@ff8f0000 {
 751                 compatible = "rockchip,rk3366-lcdc-lite";
 752                 rockchip,grf = <&grf>;
 753                 rockchip,pwr18 = <0>;
 754                 rockchip,iommu-enabled = <1>;
 755                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 756                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 757                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 758                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 759                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 760                 reset-names = "axi", "ahb", "dclk";
 761                 status = "disabled";
 762         };
 763
 764         vopl_mmu: vopl-mmu {
 765                 dbgname = "vop";
 766                 compatible = "rockchip,vopl_mmu";
 767                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 768                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 769                 interrupt-names = "vopl_mmu";
 770                 status = "disabled";
 771         };
 772
 773         iep: iep@ff900000 {
 774                 compatible = "rockchip,iep";
 775                 iommu_enabled = <1>;
 776                 reg = <0x0 0xff900000 0x0 0x800>;
 777                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 778                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 779                 clock-names = "aclk_iep", "hclk_iep";
 780                 version = <2>;
 781                 status = "disabled";
 782         };
 783
 784         rga: rga@ff920000 {
 785                 compatible = "rockchip,rga2";
 786                 dev_mode = <1>;
 787                 reg = <0x0 0xff920000 0x0 0x1000>;
 788                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 789                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 790                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 791                 status = "disabled";
 792         };
 793
 794         vop_big: vop@ff930000 {
 795                 compatible = "rockchip,rk3366-lcdc-big";
 796                 rockchip,grf = <&grf>;
 797                 rockchip,prop = <PRMRY>;
 798                 rockchip,pwr18 = <0>;
 799                 rockchip,iommu-enabled = <1>;
 800                 reg = <0x0 0xff930000 0x0 0x23f0>;
 801                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 802                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 803                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 804                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 805                 reset-names = "axi", "ahb", "dclk";
 806                 status = "disabled";
 807         };
 808
 809         vopb_mmu: vopb-mmu {
 810                 dbgname = "vop";
 811                 compatible = "rockchip,vopb_mmu";
 812                 reg = <0x0 0xff932400 0x0 0x100>;
 813                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 814                 interrupt-names = "vop_mmu";
 815                 status = "disabled";
 816         };
 817
 818         iep_mmu: iep-mmu {
 819                 dbgname = "iep";
 820                 compatible = "rockchip,iep_mmu";
 821                 reg = <0x0 0xff900800 0x0 0x100>;
 822                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 823                 interrupt-names = "iep_mmu";
 824                 status = "disabled";
 825         };
 826
 827         vpu_mmu: vpu_mmu {
 828                 dbgname = "vpu";
 829                 compatible = "rockchip,vpu_mmu";
 830                 reg = <0x0 0xff9a0800 0x0 0x100>;
 831                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 832                 interrupt-names = "vpu_mmu";
 833                 status = "disabled";
 834         };
 835
 836         vdec_mmu: vdec_mmu {
 837                 dbgname = "vdec";
 838                 compatible = "rockchip,vdec_mmu";
 839                 reg = <0x0 0xff9b0480 0x0 0x40>,
 840                       <0x0 0xff9b04c0 0x0 0x40>;
 841                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 842                 interrupt-names = "vdec_mmu";
 843                 status = "disabled";
 844         };
 845
 846         dsihost0: mipi@ff960000 {
 847                 compatible = "rockchip,rk3366-dsi";
 848                 rockchip,prop = <0>;
 849                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 850                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 851                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 852                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 853                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 854                 status = "disabled";
 855         };
 856
 857         lvds: lvds@ff968000 {
 858                 compatible = "rockchip,rk3366-lvds";
 859                 rockchip,grf = <&grf>;
 860                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 861                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 862                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 863                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 864                 status = "disabled";
 865         };
 866
 867         hdmi: hdmi@ff980000 {
 868                 compatible = "rockchip,rk3366-hdmi";
 869                 reg = <0x0 0xff980000 0x0 0x20000>;
 870                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 871                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 872                 clocks = <&cru PCLK_HDMI_CTRL>,
 873                          <&cru SCLK_HDMI_HDCP>,
 874                          <&cru SCLK_HDMI_CEC>,
 875                          <&cru DCLK_HDMIPHY>;
 876                 clock-names = "pclk_hdmi",
 877                               "hdcp_clk_hdmi",
 878                               "cec_clk_hdmi",
 879                               "dclk_hdmi_phy";
 880                 resets = <&cru SRST_HDMI>;
 881                 reset-names = "hdmi";
 882                 pinctrl-names = "default", "gpio";
 883                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 884                 pinctrl-1 = <&i2c5_gpio>;
 885                 status = "disabled";
 886         };
 887
 888         vpu: vpu_service@ff9a0000 {
 889                 compatible = "rockchip,vpu_service";
 890                 rockchip,grf = <&grf>;
 891                 iommu_enabled = <1>;
 892                 reg = <0x0 0xff9a0000 0x0 0x800>;
 893                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 894                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 895                 interrupt-names = "irq_dec", "irq_enc";
 896                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
 897                 clock-names = "aclk_vcodec", "hclk_vcodec";
 898                 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
 899                 reset-names = "video_h", "video_a";
 900                 name = "vpu_service";
 901                 dev_mode = <0>;
 902                 status = "disabled";
 903         };
 904
 905         rkvdec: rkvdec@ff9b0000 {
 906                 compatible = "rockchip,rkvdec";
 907                 rockchip,grf = <&grf>;
 908                 iommu_enabled = <1>;
 909                 reg = <0x0 0xff9b0000 0x0 0x400>;
 910                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 911                 interrupt-names = "irq_dec";
 912                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
 913                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
 914                 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
 915                 reset-names = "video_h", "video_a";
 916                 dev_mode = <2>;
 917                 name = "rkvdec";
 918                 status = "disabled";
 919         };
 920
 921         pinctrl: pinctrl {
 922                 compatible = "rockchip,rk3366-pinctrl";
 923                 rockchip,grf = <&grf>;
 924                 rockchip,pmu = <&pmugrf>;
 925                 #address-cells = <0x2>;
 926                 #size-cells = <0x2>;
 927                 ranges;
 928
 929                 gpio0: gpio0@ff750000 {
 930                         compatible = "rockchip,gpio-bank";
 931                         reg = <0x0 0xff750000 0x0 0x100>;
 932                         clocks = <&cru PCLK_GPIO0>;
 933                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 934
 935                         gpio-controller;
 936                         #gpio-cells = <0x2>;
 937
 938                         interrupt-controller;
 939                         #interrupt-cells = <0x2>;
 940                 };
 941
 942                 gpio1: gpio1@ff780000 {
 943                         compatible = "rockchip,gpio-bank";
 944                         reg = <0x0 0xff758000 0x0 0x100>;
 945                         clocks = <&cru PCLK_GPIO1>;
 946                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 947
 948                         gpio-controller;
 949                         #gpio-cells = <0x2>;
 950
 951                         interrupt-controller;
 952                         #interrupt-cells = <0x2>;
 953                 };
 954
 955                 gpio2: gpio2@ff790000 {
 956                         compatible = "rockchip,gpio-bank";
 957                         reg = <0x0 0xff790000 0x0 0x100>;
 958                         clocks = <&cru PCLK_GPIO2>;
 959                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 960
 961                         gpio-controller;
 962                         #gpio-cells = <0x2>;
 963
 964                         interrupt-controller;
 965                         #interrupt-cells = <0x2>;
 966                 };
 967
 968                 gpio3: gpio3@ff7a0000 {
 969                         compatible = "rockchip,gpio-bank";
 970                         reg = <0x0 0xff7a0000 0x0 0x100>;
 971                         clocks = <&cru PCLK_GPIO3>;
 972                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 973
 974                         gpio-controller;
 975                         #gpio-cells = <0x2>;
 976
 977                         interrupt-controller;
 978                         #interrupt-cells = <0x2>;
 979                 };
 980
 981                 gpio4: gpio4@ff7b0000 {
 982                         compatible = "rockchip,gpio-bank";
 983                         reg = <0x0 0xff7b0000 0x0 0x100>;
 984                         clocks = <&cru PCLK_GPIO4>;
 985                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 986
 987                         gpio-controller;
 988                         #gpio-cells = <0x2>;
 989
 990                         interrupt-controller;
 991                         #interrupt-cells = <0x2>;
 992                 };
 993
 994                 gpio5: gpio5@ff7c0000 {
 995                         compatible = "rockchip,gpio-bank";
 996                         reg = <0x0 0xff7c0000 0x0 0x100>;
 997                         clocks = <&cru PCLK_GPIO5>;
 998                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 999
1000                         gpio-controller;
1001                         #gpio-cells = <0x2>;
1002
1003                         interrupt-controller;
1004                         #interrupt-cells = <0x2>;
1005                 };
1006
1007                 pcfg_pull_up: pcfg-pull-up {
1008                         bias-pull-up;
1009                 };
1010
1011                 pcfg_pull_down: pcfg-pull-down {
1012                         bias-pull-down;
1013                 };
1014
1015                 pcfg_pull_none: pcfg-pull-none {
1016                         bias-disable;
1017                 };
1018
1019                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1020                         bias-disable;
1021                         drive-strength = <12>;
1022                 };
1023
1024                 emmc {
1025                         emmc_clk: emmc-clk {
1026                                 rockchip,pins =
1027                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
1028                         };
1029
1030                         emmc_cmd: emmc-cmd {
1031                                 rockchip,pins =
1032                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
1033                         };
1034
1035                         emmc_pwr: emmc-pwr {
1036                                 rockchip,pins =
1037                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
1038                         };
1039
1040                         emmc_bus1: emmc-bus1 {
1041                                 rockchip,pins =
1042                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
1043                         };
1044
1045                         emmc_bus4: emmc-bus4 {
1046                                 rockchip,pins =
1047                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1048                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1049                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1050                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1051                         };
1052
1053                         emmc_bus8: emmc-bus8 {
1054                                 rockchip,pins =
1055                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1056                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1057                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1058                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
1059                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
1060                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
1061                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
1062                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
1063                         };
1064                 };
1065
1066                 sdmmc {
1067                         sdmmc_cd: sdmmc-cd {
1068                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1069                         };
1070
1071                         sdmmc_bus1: sdmmc-bus1 {
1072                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1073                         };
1074
1075                         sdmmc_bus4: sdmmc-bus4 {
1076                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1077                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1078                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1079                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1080                         };
1081
1082                         sdmmc_clk: sdmmc-clk {
1083                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1084                         };
1085
1086                         sdmmc_cmd: sdmmc-cmd {
1087                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1088                         };
1089                 };
1090
1091                 sdio {
1092                         sdio_bus1: sdio-bus1 {
1093                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1094                         };
1095
1096                         sdio_bus4: sdio-bus4 {
1097                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1098                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1099                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1100                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1101                         };
1102
1103                         sdio_cmd: sdio-cmd {
1104                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1105                         };
1106
1107                         sdio_clk: sdio-clk {
1108                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1109                         };
1110
1111                         sdio_cd: sdio-cd {
1112                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1113                         };
1114
1115                         sdio_wp: sdio-wp {
1116                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1117                         };
1118
1119                         sdio_int: sdio-int {
1120                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1121                         };
1122
1123                         sdio_pwr: sdio-pwr {
1124                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1125                         };
1126                 };
1127
1128                 hdmi_i2c {
1129                         hdmii2c_xfer: hdmii2c-xfer {
1130                                 rockchip,pins =
1131                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1132                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1133                         };
1134                 };
1135
1136                 hdmi_pin {
1137                         hdmi_cec: hdmi-cec {
1138                                 rockchip,pins =
1139                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1140                         };
1141                 };
1142
1143                 i2c0 {
1144                         i2c0_xfer: i2c0-xfer {
1145                                 rockchip,pins =
1146                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1147                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1148                         };
1149                 };
1150
1151                 i2c1 {
1152                         i2c1_xfer: i2c1-xfer {
1153                                 rockchip,pins =
1154                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1155                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1156                         };
1157                 };
1158
1159                 i2c2 {
1160                         i2c2_xfer: i2c2-xfer {
1161                                 rockchip,pins =
1162                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1163                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1164                         };
1165
1166                         i2c2_gpio: i2c2-gpio {
1167                                 rockchip,pins =
1168                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1169                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1170                         };
1171                 };
1172
1173                 i2c3 {
1174                         i2c3_xfer: i2c3-xfer {
1175                                 rockchip,pins =
1176                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1177                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1178                         };
1179                 };
1180
1181                 i2c4 {
1182                         i2c4_xfer: i2c4-xfer {
1183                                 rockchip,pins =
1184                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1185                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1186                         };
1187
1188                         i2c4_gpio: i2c4-gpio {
1189                                 rockchip,pins =
1190                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1191                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1192                         };
1193                 };
1194
1195                 i2c5 {
1196                         i2c5_xfer: i2c5-xfer {
1197                                 rockchip,pins =
1198                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1199                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1200                         };
1201                         i2c5_gpio: i2c5-gpio {
1202                                 rockchip,pins =
1203                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1204                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1205                         };
1206                 };
1207
1208                 i2s {
1209                         i2s_8ch_bus: i2s-8ch-bus {
1210                                 rockchip,pins =
1211                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1212                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1213                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1214                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1215                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1216                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1217                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1218                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1219                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1220                         };
1221                 };
1222
1223                 spdif {
1224                         spdif_bus: spdif-bus {
1225                                 rockchip,pins =
1226                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1227                         };
1228                 };
1229
1230                 spi0 {
1231                         spi0_clk: spi0-clk {
1232                                 rockchip,pins =
1233                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1234                         };
1235                         spi0_cs0: spi0-cs0 {
1236                                 rockchip,pins =
1237                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1238                         };
1239                         spi0_cs1: spi0-cs1 {
1240                                 rockchip,pins =
1241                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1242                         };
1243                         spi0_tx: spi0-tx {
1244                                 rockchip,pins =
1245                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1246                         };
1247                         spi0_rx: spi0-rx {
1248                                 rockchip,pins =
1249                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1250                         };
1251                 };
1252
1253                 spi1 {
1254                         spi1_clk: spi1-clk {
1255                                 rockchip,pins =
1256                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1257                         };
1258                         spi1_cs0: spi1-cs0 {
1259                                 rockchip,pins =
1260                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1261                         };
1262                         spi1_tx: spi1-tx {
1263                                 rockchip,pins =
1264                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1265                         };
1266                         spi1_rx: spi1-rx {
1267                                 rockchip,pins =
1268                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1269                         };
1270                 };
1271
1272                 scr {
1273                         scr_clk: scr-clk {
1274                                 rockchip,pins =
1275                                         <5 8 RK_FUNC_2 &pcfg_pull_none>;
1276                         };
1277
1278                         scr_io: scr-io {
1279                                 rockchip,pins =
1280                                         <5 9 RK_FUNC_2 &pcfg_pull_up>;
1281                         };
1282
1283                         scr_rst: scr-rst {
1284                                 rockchip,pins =
1285                                         <5 10 RK_FUNC_1 &pcfg_pull_none>;
1286                         };
1287
1288                         scr_detect: scr-detect {
1289                                 rockchip,pins =
1290                                         <5 11 RK_FUNC_1 &pcfg_pull_none>;
1291                         };
1292                 };
1293
1294                 uart0 {
1295                         uart0_xfer: uart0-xfer {
1296                                 rockchip,pins =
1297                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1298                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1299                         };
1300
1301                         uart0_cts: uart0-cts {
1302                                 rockchip,pins =
1303                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1304                         };
1305
1306                         uart0_rts: uart0-rts {
1307                                 rockchip,pins =
1308                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1309                         };
1310                 };
1311
1312                 uart2_t0 {
1313                         uart2_t0_xfer: uart2_t0-xfer {
1314                                 rockchip,pins =
1315                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1316                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1317                         };
1318                         /* no rts / cts for uart2 */
1319                 };
1320
1321                 uart2_t1 {
1322                         uart2_t1_xfer: uart2_t1-xfer {
1323                                 rockchip,pins =
1324                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1325                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1326                         };
1327                         /* no rts / cts for uart2 */
1328                 };
1329
1330                 uart2_t2 {
1331                         uart2_t2_xfer: uart2_t2-xfer {
1332                                 rockchip,pins =
1333                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1334                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1335                         };
1336                         /* no rts / cts for uart2 */
1337                 };
1338
1339                 uart3 {
1340                         uart3_xfer: uart3-xfer {
1341                                 rockchip,pins =
1342                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1343                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1344                         };
1345
1346                         uart3_cts: uart3-cts {
1347                                 rockchip,pins =
1348                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1349                         };
1350
1351                         uart3_rts: uart3-rts {
1352                                 rockchip,pins =
1353                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1354                         };
1355                 };
1356
1357                 pwm0 {
1358                         pwm0_pin: pwm0-pin {
1359                                 rockchip,pins =
1360                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1361                         };
1362                 };
1363
1364                 pwm1 {
1365                         pwm1_pin: pwm1-pin {
1366                                 rockchip,pins =
1367                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1368                         };
1369                 };
1370
1371                 pwm2_t0 {
1372                         pwm2_t0_pin: pwm2_t0-pin {
1373                                 rockchip,pins =
1374                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1375                         };
1376                 };
1377
1378                 pwm2_t1 {
1379                         pwm2_t1_pin: pwm2_t1-pin {
1380                                 rockchip,pins =
1381                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1382                         };
1383                 };
1384
1385                 pwm3_t0 {
1386                         pwm3_t0_pin: pwm3_t0-pin {
1387                                 rockchip,pins =
1388                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1389                         };
1390                 };
1391
1392                 pwm3_t1 {
1393                         pwm3_t1_pin: pwm3_t1-pin {
1394                                 rockchip,pins =
1395                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1396                         };
1397                 };
1398
1399                 pwm3_t2 {
1400                         pwm3_t2_pin: pwm3_t2-pin {
1401                                 rockchip,pins =
1402                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1403                         };
1404                 };
1405
1406                 lcdc {
1407                         lcdc_lcdc: lcdc-lcdc {
1408                                 rockchip,pins =
1409                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1410                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1411                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1412                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1413                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1414                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1415                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1416                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1417                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1418                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1419                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1420                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1421                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1422                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1423                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1424                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1425                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1426                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1427                         };
1428
1429                         lcdc_gpio: lcdc-gpio {
1430                                 rockchip,pins =
1431                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1432                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1433                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1434                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1435                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1436                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1437                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1438                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1439                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1440                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1441                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1442                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1443                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1444                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1445                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1446                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1447                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1448                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1449                         };
1450                 };
1451
1452                 gmac {
1453                         rgmii_pins: rgmii-pins {
1454                                 rockchip,pins =
1455                                         /* mac_rxd3 */
1456                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1457                                         /* mac_rxd2 */
1458                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1459                                         /* mac_txd3 */
1460                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1461                                         /* mac_txd2 */
1462                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1463                                         /* mac_rxd1 */
1464                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1465                                         /* mac_rxd0 */
1466                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1467                                         /* mac_txd1 */
1468                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1469                                         /* mac_txd0 */
1470                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1471                                         /* mac_txclkout */
1472                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1473                                         /* mac_crs */
1474                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1475                                         /* mac_rxclkin */
1476                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1477                                         /* mac_mdio */
1478                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1479                                         /* mac_txen */
1480                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1481                                         /* mac_clk */
1482                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1483                                         /* mac_rxer */
1484                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1485                                         /* mac_rxdv */
1486                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1487                                         /* mac_mdc */
1488                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1489                         };
1490
1491                         rmii_pins: rmii-pins {
1492                                 rockchip,pins =
1493                                         /* mac_rxd1 */
1494                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1495                                         /* mac_rxd0 */
1496                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1497                                         /* mac_txd1 */
1498                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1499                                         /* mac_txd0 */
1500                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1501                                         /* mac_crs */
1502                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1503                                         /* mac_rxclkin */
1504                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1505                                         /* mac_mdio */
1506                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1507                                         /* mac_txen */
1508                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1509                                         /* mac_clk */
1510                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1511                                         /* mac_rxer */
1512                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1513                                         /* mac_rxdv */
1514                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1515                                         /* mac_mdc */
1516                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1517                         };
1518                 };
1519
1520                 eth_phy {
1521                         eth_phy_pwr: eth-phy-pwr {
1522                                 rockchip,pins =
1523                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1524                         };
1525                 };
1526         };
1527
1528         gpu: gpu@ffa30000 {
1529                 compatible = "arm,malit764",
1530                              "arm,malit76x",
1531                              "arm,malit7xx",
1532                              "arm,mali-midgard";
1533
1534                 reg = <0x0 0xffa30000 0 0x10000>;
1535
1536                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1537                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1538                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1539                 interrupt-names = "GPU", "MMU", "JOB";
1540
1541                 clocks = <&cru ACLK_GPU>;
1542                 clock-names = "clk_mali";
1543                 operating-points-v2 = <&gpu_opp_table>;
1544                 status = "disabled";
1545         };
1546
1547         gpu_opp_table: gpu_opp_table {
1548                 compatible = "operating-points-v2";
1549                 opp-shared;
1550
1551                 opp00 {
1552                         opp-hz = /bits/ 64 <96000000>;
1553                         opp-microvolt = <1150000>;
1554                 };
1555                 opp01 {
1556                         opp-hz = /bits/ 64 <192000000>;
1557                         opp-microvolt = <1150000>;
1558                 };
1559                 opp02 {
1560                         opp-hz = /bits/ 64 <288000000>;
1561                         opp-microvolt = <1150000>;
1562                 };
1563                 opp03 {
1564                         opp-hz = /bits/ 64 <375000000>;
1565                         opp-microvolt = <1150000>;
1566                 };
1567                 opp04 {
1568                         opp-hz = /bits/ 64 <480000000>;
1569                         opp-microvolt = <1150000>;
1570                 };
1571         };
1572 };