arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/display/mipi_dsi.h>
  50 #include <dt-bindings/power/rk3366-power.h>
  51 #include <dt-bindings/soc/rockchip_boot-mode.h>
  52 #include <dt-bindings/thermal/thermal.h>
  53
  54 / {
  55         compatible = "rockchip,rk3366";
  56         interrupt-parent = <&gic>;
  57         #address-cells = <2>;
  58         #size-cells = <2>;
  59
  60         aliases {
  61                 i2c0 = &i2c0;
  62                 i2c1 = &i2c1;
  63                 i2c2 = &i2c2;
  64                 i2c3 = &i2c3;
  65                 i2c4 = &i2c4;
  66                 i2c5 = &i2c5;
  67                 serial0 = &uart0;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 spi0 = &spi0;
  71                 spi1 = &spi1;
  72         };
  73
  74         cpus {
  75                 #address-cells = <0x2>;
  76                 #size-cells = <0x0>;
  77
  78                 cpu0: cpu@0 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53","arm,armv8";
  81                         reg = <0x0 0x0>;
  82                         enable-method = "psci";
  83                         clocks = <&cru ARMCLK>;
  84                         operating-points-v2 = <&cpu0_opp_table>;
  85                         cpu-idle-states = <&cpu_sleep>;
  86                         #cooling-cells = <2>; /* min followed by max */
  87                         dynamic-power-coefficient = <166>;
  88                 };
  89
  90                 cpu1: cpu@1 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53","arm,armv8";
  93                         reg = <0x0 0x1>;
  94                         enable-method = "psci";
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                         cpu-idle-states = <&cpu_sleep>;
  97                 };
  98
  99                 cpu2: cpu@2 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a53","arm,armv8";
 102                         reg = <0x0 0x2>;
 103                         enable-method = "psci";
 104                         operating-points-v2 = <&cpu0_opp_table>;
 105                         cpu-idle-states = <&cpu_sleep>;
 106                 };
 107
 108                 cpu3: cpu@3 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53","arm,armv8";
 111                         reg = <0x0 0x3>;
 112                         enable-method = "psci";
 113                         operating-points-v2 = <&cpu0_opp_table>;
 114                         cpu-idle-states = <&cpu_sleep>;
 115                 };
 116
 117                 idle-states {
 118                         entry-method = "psci";
 119                         cpu_sleep: cpu-sleep-0 {
 120                                 compatible = "arm,idle-state";
 121                                 local-timer-stop;
 122                                 arm,psci-suspend-param = <0x0010000>;
 123                                 entry-latency-us = <350>;
 124                                 exit-latency-us = <600>;
 125                                 min-residency-us = <1150>;
 126                         };
 127                 };
 128         };
 129
 130         cpu0_opp_table: opp_table0 {
 131                 compatible = "operating-points-v2";
 132                 opp-shared;
 133
 134                 opp@408000000 {
 135                         opp-hz = /bits/ 64 <408000000>;
 136                         opp-microvolt = <950000>;
 137                         clock-latency-ns = <40000>;
 138                         opp-suspend;
 139                 };
 140                 opp@600000000 {
 141                         opp-hz = /bits/ 64 <600000000>;
 142                         opp-microvolt = <950000>;
 143                 };
 144                 opp@816000000 {
 145                         opp-hz = /bits/ 64 <816000000>;
 146                         opp-microvolt = <1000000>;
 147                 };
 148                 opp@1008000000 {
 149                         opp-hz = /bits/ 64 <1008000000>;
 150                         opp-microvolt = <1075000>;
 151                 };
 152                 opp@1200000000 {
 153                         opp-hz = /bits/ 64 <1200000000>;
 154                         opp-microvolt = <1175000>;
 155                 };
 156                 opp@1296000000 {
 157                         opp-hz = /bits/ 64 <1296000000>;
 158                         opp-microvolt = <1250000>;
 159                 };
 160         };
 161
 162         psci {
 163                 compatible = "arm,psci-1.0";
 164                 method = "smc";
 165         };
 166
 167         timer {
 168                 compatible = "arm,armv8-timer";
 169                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 170                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 171                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 172                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 173         };
 174
 175         arm-pmu {
 176                 compatible = "arm,cortex-a53-pmu";
 177                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 181                 interrupt-affinity = <&cpu0>,
 182                                      <&cpu1>,
 183                                      <&cpu2>,
 184                                      <&cpu3>;
 185         };
 186
 187         xin24m: xin24m {
 188                 compatible = "fixed-clock";
 189                 #clock-cells = <0>;
 190                 clock-frequency = <24000000>;
 191                 clock-output-names = "xin24m";
 192         };
 193
 194         gic: interrupt-controller@ffb71000 {
 195                 compatible = "arm,gic-400";
 196                 interrupt-controller;
 197                 #interrupt-cells = <3>;
 198                 #address-cells = <0>;
 199
 200                 reg = <0x0 0xffb71000 0x0 0x1000>,
 201                       <0x0 0xffb72000 0x0 0x1000>,
 202                       <0x0 0xffb74000 0x0 0x2000>,
 203                       <0x0 0xffb76000 0x0 0x2000>;
 204                 interrupts = <GIC_PPI 9
 205                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 206         };
 207
 208         nandc0: nandc@ff0c0000 {
 209                 compatible = "rockchip,rk-nandc";
 210                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 211                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 212                 nandc_id = <0>;
 213                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 214                 clock-names = "clk_nandc", "hclk_nandc";
 215                 status = "disabled";
 216         };
 217
 218         saradc: saradc@ff100000 {
 219                 compatible = "rockchip,saradc";
 220                 reg = <0x0 0xff100000 0x0 0x100>;
 221                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 222                 #io-channel-cells = <1>;
 223                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 224                 clock-names = "saradc", "apb_pclk";
 225                 status = "disabled";
 226         };
 227
 228         spi0: spi@ff110000 {
 229                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 230                 reg = <0x0 0xff110000 0x0 0x1000>;
 231                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 232                 clock-names = "spiclk", "apb_pclk";
 233                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 234                 pinctrl-names = "default";
 235                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 236                 #address-cells = <1>;
 237                 #size-cells = <0>;
 238                 status = "disabled";
 239         };
 240
 241         spi1: spi@ff120000 {
 242                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 243                 reg = <0x0 0xff120000 0x0 0x1000>;
 244                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 245                 clock-names = "spiclk", "apb_pclk";
 246                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 247                 pinctrl-names = "default";
 248                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 status = "disabled";
 252         };
 253
 254         scr: rkscr@ff1d0000 {
 255                 compatible = "rockchip-scr";
 256                 reg = <0x0 0xff1d0000 0x0 0x10000>;
 257                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 pinctrl-names = "default";
 261                 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
 262                 clocks = <&cru PCLK_SIM>;
 263                 clock-names = "g_pclk_sim_card";
 264                 status = "disabled";
 265         };
 266
 267         thermal-zones {
 268                 soc_thermal: soc-thermal {
 269                         polling-delay-passive = <100>; /* milliseconds */
 270                         polling-delay = <1000>; /* milliseconds */
 271                         sustainable-power = <1600>; /* milliwatts */
 272
 273                         thermal-sensors = <&tsadc 0>;
 274
 275                         trips {
 276                                 threshold: trip-point@0 {
 277                                         temperature = <70000>; /* millicelsius */
 278                                         hysteresis = <2000>; /* millicelsius */
 279                                         type = "passive";
 280                                 };
 281                                 target: trip-point@1 {
 282                                         temperature = <85000>; /* millicelsius */
 283                                         hysteresis = <2000>; /* millicelsius */
 284                                         type = "passive";
 285                                 };
 286                                 soc_crit: soc-crit {
 287                                         temperature = <95000>; /* millicelsius */
 288                                         hysteresis = <2000>; /* millicelsius */
 289                                         type = "critical";
 290                                 };
 291                         };
 292
 293                         cooling-maps {
 294                                 map0 {
 295                                         trip = <&target>;
 296                                         cooling-device =
 297                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 298                                 };
 299                                 map1 {
 300                                         trip = <&target>;
 301                                         cooling-device =
 302                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 303                                 };
 304                         };
 305                 };
 306
 307                 gpu_thermal: gpu-thermal {
 308                         polling-delay-passive = <100>; /* milliseconds */
 309                         polling-delay = <1000>; /* milliseconds */
 310
 311                         thermal-sensors = <&tsadc 1>;
 312                 };
 313         };
 314
 315         tsadc: tsadc@ff260000 {
 316                 compatible = "rockchip,rk3366-tsadc";
 317                 reg = <0x0 0xff260000 0x0 0x100>;
 318                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 320                 clock-names = "tsadc", "apb_pclk";
 321                 resets = <&cru SRST_TSADC>;
 322                 reset-names = "tsadc-apb";
 323                 pinctrl-names = "default";
 324                 pinctrl-0 = <&tsadc_gpio>;
 325                 #thermal-sensor-cells = <1>;
 326                 rockchip,hw-tshut-temp = <95000>;
 327                 status = "disabled";
 328         };
 329
 330         sdmmc: rksdmmc@ff400000 {
 331                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 332                 clock-freq-min-max = <400000 150000000>;
 333                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 334                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 335                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 336                 fifo-depth = <0x100>;
 337                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 338                 reg = <0x0 0xff400000 0x0 0x4000>;
 339                 status = "disabled";
 340         };
 341
 342         sdio: rksdmmc@ff410000 {
 343                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 344                 clock-freq-min-max = <400000 150000000>;
 345                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 346                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 347                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 348                 fifo-depth = <0x100>;
 349                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 350                 reg = <0x0 0xff410000 0x0 0x4000>;
 351                 status = "disabled";
 352         };
 353
 354         emmc: rksdmmc@ff420000 {
 355                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 356                 clock-freq-min-max = <400000 150000000>;
 357                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 358                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 359                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 360                 fifo-depth = <0x100>;
 361                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 362                 reg = <0x0 0xff420000 0x0 0x4000>;
 363                 status = "disabled";
 364         };
 365
 366         gmac: eth@ff440000 {
 367                 compatible = "rockchip,rk3366-gmac";
 368                 reg = <0x0 0xff440000 0x0 0x10000>;
 369                 rockchip,grf = <&grf>;
 370                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 371                 interrupt-names = "macirq";
 372                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 373                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 374                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 375                          <&cru PCLK_GMAC>;
 376                 clock-names = "stmmaceth", "mac_clk_rx",
 377                               "mac_clk_tx", "clk_mac_ref",
 378                               "clk_mac_refout", "aclk_mac",
 379                               "pclk_mac";
 380                 resets = <&cru SRST_MAC>;
 381                 reset-names = "stmmaceth";
 382                 status = "disabled";
 383         };
 384
 385         i2c0: i2c@ff650000 {
 386                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 387                 reg = <0x0 0xff728000 0x0 0x1000>;
 388                 clocks = <&cru PCLK_I2C0>;
 389                 clock-names = "i2c";
 390                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&i2c0_xfer>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 status = "disabled";
 396         };
 397
 398         i2c2: i2c@ff140000 {
 399                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 400                 reg = <0x0 0xff140000 0x0 0x1000>;
 401                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 clock-names = "i2c";
 405                 clocks = <&cru PCLK_I2C2>;
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&i2c2_xfer>;
 408                 status = "disabled";
 409         };
 410
 411         i2c3: i2c@ff150000 {
 412                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 413                 reg = <0x0 0xff150000 0x0 0x1000>;
 414                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 clock-names = "i2c";
 418                 clocks = <&cru PCLK_I2C3>;
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&i2c3_xfer>;
 421                 status = "disabled";
 422         };
 423
 424         i2c4: i2c@ff160000 {
 425                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 426                 reg = <0x0 0xff160000 0x0 0x1000>;
 427                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 428                 #address-cells = <1>;
 429                 #size-cells = <0>;
 430                 clock-names = "i2c";
 431                 clocks = <&cru PCLK_I2C4>;
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&i2c4_xfer>;
 434                 status = "disabled";
 435         };
 436
 437         i2c5: i2c@ff170000 {
 438                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 439                 reg = <0x0 0xff170000 0x0 0x1000>;
 440                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 441                 #address-cells = <1>;
 442                 #size-cells = <0>;
 443                 clock-names = "i2c";
 444                 clocks = <&cru PCLK_I2C5>;
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&i2c5_xfer>;
 447                 status = "disabled";
 448         };
 449
 450         uart0: serial@ff180000 {
 451                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 452                 reg = <0x0 0xff180000 0x0 0x100>;
 453                 clock-frequency = <24000000>;
 454                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 455                 clock-names = "baudclk", "apb_pclk";
 456                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 457                 reg-shift = <2>;
 458                 reg-io-width = <4>;
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 461                 status = "disabled";
 462         };
 463
 464         uart3: serial@ff1b0000 {
 465                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 466                 reg = <0x0 0xff1b0000 0x0 0x100>;
 467                 clock-frequency = <24000000>;
 468                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 469                 clock-names = "baudclk", "apb_pclk";
 470                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 475                 status = "disabled";
 476         };
 477
 478         usb_host0_ehci: usb@ff480000 {
 479                 compatible = "generic-ehci";
 480                 reg = <0x0 0xff480000 0x0 0x20000>;
 481                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 482                 clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
 483                 clock-names = "usbphy_480m", "hclk_host0";
 484                 phys = <&u2phy_host>;
 485                 phy-names = "usb";
 486                 status = "disabled";
 487         };
 488
 489         usb_host0_ohci: usb@ff4a0000 {
 490                 compatible = "generic-ohci";
 491                 reg = <0x0 0xff4a0000 0x0 0x20000>;
 492                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 493                 clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
 494                 clock-names = "usbphy_480m", "hclk_host0";
 495                 phys = <&u2phy_host>;
 496                 phy-names = "usb";
 497                 status = "disabled";
 498         };
 499
 500         usb_otg: usb@ff4c0000 {
 501                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 502                              "snps,dwc2";
 503                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 504                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 505                 clocks = <&cru HCLK_OTG>;
 506                 clock-names = "otg";
 507                 dr_mode = "otg";
 508                 g-np-tx-fifo-size = <16>;
 509                 g-rx-fifo-size = <275>;
 510                 g-tx-fifo-size = <256 128 128 64 64 32>;
 511                 g-use-dma;
 512                 status = "disabled";
 513         };
 514
 515         i2c1: i2c@ff660000 {
 516                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 517                 reg = <0x0 0xff660000 0x0 0x1000>;
 518                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 519                 #address-cells = <1>;
 520                 #size-cells = <0>;
 521                 clock-names = "i2c";
 522                 clocks = <&cru PCLK_I2C1>;
 523                 pinctrl-names = "default";
 524                 pinctrl-0 = <&i2c1_xfer>;
 525                 status = "disabled";
 526         };
 527
 528         pwm0: pwm@ff680000 {
 529                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 530                 reg = <0x0 0xff680000 0x0 0x10>;
 531                 #pwm-cells = <3>;
 532                 pinctrl-names = "default";
 533                 pinctrl-0 = <&pwm0_pin>;
 534                 clocks = <&cru PCLK_RKPWM>;
 535                 clock-names = "pwm";
 536                 status = "disabled";
 537         };
 538
 539         pwm1: pwm@ff680010 {
 540                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 541                 reg = <0x0 0xff680010 0x0 0x10>;
 542                 #pwm-cells = <3>;
 543                 pinctrl-names = "default";
 544                 pinctrl-0 = <&pwm1_pin>;
 545                 clocks = <&cru PCLK_RKPWM>;
 546                 clock-names = "pwm";
 547                 status = "disabled";
 548         };
 549
 550         pwm2: pwm@ff680020 {
 551                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 552                 reg = <0x0 0xff680020 0x0 0x10>;
 553                 #pwm-cells = <3>;
 554                 clocks = <&cru PCLK_RKPWM>;
 555                 clock-names = "pwm";
 556                 status = "disabled";
 557         };
 558
 559         pwm3: pwm@ff680030 {
 560                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 561                 reg = <0x0 0xff680030 0x0 0x10>;
 562                 #pwm-cells = <3>;
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&pwm3_t2_pin>;
 565                 clocks = <&cru PCLK_RKPWM>;
 566                 clock-names = "pwm";
 567                 status = "disabled";
 568         };
 569
 570         uart2: serial@ff690000 {
 571                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 572                 reg = <0x0 0xff690000 0x0 0x100>;
 573                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 574                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 575                 clock-names = "baudclk", "apb_pclk";
 576                 reg-shift = <2>;
 577                 reg-io-width = <4>;
 578                 pinctrl-names = "default";
 579                 pinctrl-0 = <&uart2_t1_xfer>;
 580                 status = "disabled";
 581         };
 582
 583         pmu: power-management@ff730000 {
 584                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 585                 reg = <0x0 0xff730000 0x0 0x1000>;
 586
 587                 power: power-controller {
 588                         status = "disabled";
 589                         compatible = "rockchip,rk3366-power-controller";
 590                         #power-domain-cells = <1>;
 591                         #address-cells = <1>;
 592                         #size-cells = <0>;
 593
 594                         /*
 595                          * Note: Although SCLK_* are the working clocks
 596                          * of device without including on the NOC, needed for
 597                          * synchronous reset.
 598                          *
 599                          * The clocks on the which NOC:
 600                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 601                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 602                          * ACLK_ISP is on ACLK_ISP_NIU.
 603                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 604                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 605                          *
 606                          * Which clock are device clocks:
 607                          *      clocks          devices
 608                          *      *_IEP           IEP:Image Enhancement Processor
 609                          *      *_ISP           ISP:Image Signal Processing
 610                          *      *_VOP*          VOP:Visual Output Processor
 611                          *      *_RGA           RGA
 612                          *      *_DPHY*         LVDS
 613                          *      *_HDMI          HDMI
 614                          *      *_MIPI_*        MIPI
 615                          */
 616                         pd_vio {
 617                                 reg = <RK3366_PD_VIO>;
 618                                 clocks = <&cru ACLK_IEP>,
 619                                          <&cru ACLK_ISP>,
 620                                          <&cru ACLK_RGA>,
 621                                          <&cru ACLK_HDCP>,
 622                                          <&cru ACLK_VOP_FULL>,
 623                                          <&cru ACLK_VOP_LITE>,
 624                                          <&cru ACLK_VOP_IEP>,
 625                                          <&cru DCLK_VOP_FULL>,
 626                                          <&cru DCLK_VOP_LITE>,
 627                                          <&cru HCLK_IEP>,
 628                                          <&cru HCLK_ISP>,
 629                                          <&cru HCLK_RGA>,
 630                                          <&cru HCLK_VOP_FULL>,
 631                                          <&cru HCLK_VOP_LITE>,
 632                                          <&cru HCLK_VIO_HDCPMMU>,
 633                                          <&cru PCLK_HDMI_CTRL>,
 634                                          <&cru PCLK_HDCP>,
 635                                          <&cru PCLK_MIPI_DSI0>,
 636                                          <&cru SCLK_VOP_FULL_PWM>,
 637                                          <&cru SCLK_HDCP>,
 638                                          <&cru SCLK_ISP>,
 639                                          <&cru SCLK_RGA>,
 640                                          <&cru SCLK_HDMI_CEC>,
 641                                          <&cru SCLK_HDMI_HDCP>;
 642                         };
 643
 644                         /*
 645                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 646                          * (video endecoder & decoder) clocks that on the
 647                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 648                          */
 649                         pd_vpu {
 650                                 reg = <RK3366_PD_VPU>;
 651                                 clocks = <&cru ACLK_VIDEO>,
 652                                          <&cru HCLK_VIDEO>;
 653                         };
 654
 655                         /*
 656                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 657                          * (video decoder) clocks that on the
 658                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 659                          */
 660                         pd_rkvdec {
 661                                 reg = <RK3366_PD_RKVDEC>;
 662                                 clocks = <&cru ACLK_RKVDEC>,
 663                                          <&cru HCLK_RKVDEC>;
 664                         };
 665
 666                         pd_video {
 667                                 reg = <RK3366_PD_VIDEO>;
 668                                 clocks = <&cru ACLK_VIDEO>,
 669                                          <&cru ACLK_RKVDEC>,
 670                                          <&cru HCLK_VIDEO>,
 671                                          <&cru HCLK_RKVDEC>,
 672                                          <&cru SCLK_HEVC_CABAC>,
 673                                          <&cru SCLK_HEVC_CORE>;
 674                         };
 675
 676                         /*
 677                          * Note: ACLK_GPU is the GPU clock,
 678                          * and on the ACLK_GPU_NIU (NOC).
 679                          */
 680                         pd_gpu {
 681                                 reg = <RK3366_PD_GPU>;
 682                                 clocks = <&cru ACLK_GPU>;
 683                         };
 684                 };
 685         };
 686
 687         pmugrf: syscon@ff738000 {
 688                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 689                 reg = <0x0 0xff738000 0x0 0x1000>;
 690
 691                 reboot-mode {
 692                         compatible = "syscon-reboot-mode";
 693                         offset = <0x200>;
 694                         mode-normal = <BOOT_NORMAL>;
 695                         mode-recovery = <BOOT_RECOVERY>;
 696                         mode-fastboot = <BOOT_FASTBOOT>;
 697                         mode-loader = <BOOT_LOADER>;
 698                 };
 699
 700                 pmu_pvtm: pmu-pvtm {
 701                         compatible = "rockchip,rk3366-pmu-pvtm";
 702                         clocks = <&cru SCLK_PVTM_PMU>;
 703                         clock-names = "pmu";
 704                         status = "disabled";
 705                 };
 706         };
 707
 708         amba {
 709                 compatible = "arm,amba-bus";
 710                 #address-cells = <2>;
 711                 #size-cells = <2>;
 712                 ranges;
 713
 714                 dmac_peri: dma-controller@ff250000 {
 715                         compatible = "arm,pl330", "arm,primecell";
 716                         reg = <0x0 0xff250000 0x0 0x4000>;
 717                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 718                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 719                         #dma-cells = <1>;
 720                         clocks = <&cru ACLK_DMAC_PERI>;
 721                         clock-names = "apb_pclk";
 722                         peripherals-req-type-burst;
 723                 };
 724
 725                 dmac_bus: dma-controller@ff600000 {
 726                         compatible = "arm,pl330", "arm,primecell";
 727                         reg = <0x0 0xff600000 0x0 0x4000>;
 728                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 729                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 730                         #dma-cells = <1>;
 731                         clocks = <&cru ACLK_DMAC_BUS>;
 732                         clock-names = "apb_pclk";
 733                         peripherals-req-type-burst;
 734                 };
 735         };
 736
 737         cru: clock-controller@ff760000 {
 738                 compatible = "rockchip,rk3366-cru";
 739                 reg = <0x0 0xff760000 0x0 0x1000>;
 740                 rockchip,grf = <&grf>;
 741                 #clock-cells = <1>;
 742                 #reset-cells = <1>;
 743                 assigned-clocks =
 744                         <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
 745                         <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
 746                         <&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>,
 747                         <&cru SCLK_SPDIF_8CH_SRC>,
 748                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 749                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 750                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 751                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 752                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
 753                         <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
 754                         <&cru ACLK_PERI1>;
 755                 assigned-clock-rates =
 756                         <0>, <0>,
 757                         <0>, <0>,
 758                         <0>, <0>,
 759                         <0>,
 760                         <750000000>, <576000000>,
 761                         <594000000>, <594000000>,
 762                         <960000000>, <520000000>,
 763                         <375000000>, <288000000>,
 764                         <100000000>, <100000000>,
 765                         <288000000>, <288000000>,
 766                         <144000000>;
 767                 assigned-clock-parents =
 768                         <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
 769                         <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>,
 770                         <&cru PLL_GPLL>, <&cru PLL_GPLL>,
 771                         <&cru PLL_GPLL>;
 772         };
 773
 774         grf: syscon@ff770000 {
 775                 compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";
 776                 reg = <0x0 0xff770000 0x0 0x1000>;
 777                 #address-cells = <1>;
 778                 #size-cells = <1>;
 779
 780                 u2phy: usb2-phy@700 {
 781                         compatible = "rockchip,rk3366-usb2phy";
 782                         reg = <0x700 0x2c>;
 783                         clocks = <&cru SCLK_OTG_PHY0>;
 784                         clock-names = "phyclk";
 785                         #clock-cells = <0>;
 786                         clock-output-names = "sclk_otgphy0_480m";
 787
 788                         u2phy_host: host-port {
 789                                 #phy-cells = <0>;
 790                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 791                                 interrupt-names = "linestate";
 792                                 status = "okay";
 793                         };
 794                 };
 795
 796                 pvtm: pvtm {
 797                         compatible = "rockchip,rk3366-pvtm";
 798                         clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>;
 799                         clock-names = "core", "gpu";
 800                         status = "disabled";
 801                 };
 802         };
 803
 804         wdt: watchdog@ff800000 {
 805                 compatible = "snps,dw-wdt";
 806                 reg = <0x0 0xff800000 0x0 0x100>;
 807                 clocks = <&cru PCLK_WDT>;
 808                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 809                 status = "disabled";
 810         };
 811
 812         spdif: spdif@ff880000 {
 813                 compatible = "rockchip,rk3366-spdif";
 814                 reg = <0x0 0xff880000 0x0 0x1000>;
 815                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 816                 dmas = <&dmac_bus 3>;
 817                 dma-names = "tx";
 818                 clock-names = "mclk", "hclk";
 819                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 820                 pinctrl-names = "default";
 821                 pinctrl-0 = <&spdif_bus>;
 822                 status = "disabled";
 823         };
 824
 825         i2s_2ch: i2s-2ch@ff890000 {
 826                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 827                 reg = <0x0 0xff890000 0x0 0x1000>;
 828                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 829                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 830                 dma-names = "tx", "rx";
 831                 clock-names = "i2s_clk", "i2s_hclk";
 832                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 833                 status = "disabled";
 834         };
 835
 836         i2s_8ch: i2s-8ch@ff898000 {
 837                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 838                 reg = <0x0 0xff898000 0x0 0x1000>;
 839                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 840                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 841                 dma-names = "tx", "rx";
 842                 clock-names = "i2s_clk", "i2s_hclk";
 843                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 844                 pinctrl-names = "default";
 845                 pinctrl-0 = <&i2s_8ch_bus>;
 846                 status = "disabled";
 847         };
 848
 849         fb: fb {
 850                 compatible = "rockchip,rk-fb";
 851                 rockchip,disp-mode = <DUAL>;
 852                 status = "disabled";
 853         };
 854
 855         rk_screen: screen {
 856                 compatible = "rockchip,screen";
 857                 status = "disabled";
 858         };
 859
 860         vop_lite: vop@ff8f0000 {
 861                 compatible = "rockchip,rk3366-lcdc-lite";
 862                 rockchip,grf = <&grf>;
 863                 rockchip,pwr18 = <0>;
 864                 rockchip,iommu-enabled = <1>;
 865                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 866                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 867                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 868                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 869                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 870                 reset-names = "axi", "ahb", "dclk";
 871                 status = "disabled";
 872         };
 873
 874         vopl_mmu: vopl-mmu {
 875                 dbgname = "vop";
 876                 compatible = "rockchip,vopl_mmu";
 877                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 878                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 879                 interrupt-names = "vopl_mmu";
 880                 status = "disabled";
 881         };
 882
 883         iep: iep@ff900000 {
 884                 compatible = "rockchip,iep";
 885                 iommu_enabled = <1>;
 886                 reg = <0x0 0xff900000 0x0 0x800>;
 887                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 888                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 889                 clock-names = "aclk_iep", "hclk_iep";
 890                 version = <2>;
 891                 status = "disabled";
 892         };
 893
 894         rga: rga@ff920000 {
 895                 compatible = "rockchip,rga2";
 896                 dev_mode = <1>;
 897                 reg = <0x0 0xff920000 0x0 0x1000>;
 898                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 899                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 900                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 901                 status = "disabled";
 902         };
 903
 904         vop_big: vop@ff930000 {
 905                 compatible = "rockchip,rk3366-lcdc-big";
 906                 rockchip,grf = <&grf>;
 907                 rockchip,prop = <PRMRY>;
 908                 rockchip,pwr18 = <0>;
 909                 rockchip,iommu-enabled = <1>;
 910                 reg = <0x0 0xff930000 0x0 0x23f0>;
 911                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 912                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 913                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 914                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 915                 reset-names = "axi", "ahb", "dclk";
 916                 status = "disabled";
 917         };
 918
 919         vopb_mmu: vopb-mmu {
 920                 dbgname = "vop";
 921                 compatible = "rockchip,vopb_mmu";
 922                 reg = <0x0 0xff932400 0x0 0x100>;
 923                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 924                 interrupt-names = "vop_mmu";
 925                 status = "disabled";
 926         };
 927
 928         iep_mmu: iep-mmu {
 929                 dbgname = "iep";
 930                 compatible = "rockchip,iep_mmu";
 931                 reg = <0x0 0xff900800 0x0 0x100>;
 932                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 933                 interrupt-names = "iep_mmu";
 934                 status = "disabled";
 935         };
 936
 937         vpu_mmu: vpu_mmu {
 938                 dbgname = "vpu";
 939                 compatible = "rockchip,vpu_mmu";
 940                 reg = <0x0 0xff9a0800 0x0 0x100>;
 941                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 942                 interrupt-names = "vpu_mmu";
 943                 status = "disabled";
 944         };
 945
 946         vdec_mmu: vdec_mmu {
 947                 dbgname = "vdec";
 948                 compatible = "rockchip,vdec_mmu";
 949                 reg = <0x0 0xff9b0480 0x0 0x40>,
 950                       <0x0 0xff9b04c0 0x0 0x40>;
 951                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 952                 interrupt-names = "vdec_mmu";
 953                 status = "disabled";
 954         };
 955
 956         dsihost0: mipi@ff960000 {
 957                 compatible = "rockchip,rk3366-dsi";
 958                 rockchip,prop = <0>;
 959                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 960                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 961                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 962                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 963                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 964                 status = "disabled";
 965         };
 966
 967         lvds: lvds@ff968000 {
 968                 compatible = "rockchip,rk3366-lvds";
 969                 rockchip,grf = <&grf>;
 970                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 971                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 972                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 973                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 974                 status = "disabled";
 975         };
 976
 977         hdmi: hdmi@ff980000 {
 978                 compatible = "rockchip,rk3366-hdmi";
 979                 reg = <0x0 0xff980000 0x0 0x20000>;
 980                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 981                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 982                 clocks = <&cru PCLK_HDMI_CTRL>,
 983                          <&cru SCLK_HDMI_HDCP>,
 984                          <&cru SCLK_HDMI_CEC>,
 985                          <&cru DCLK_HDMIPHY>;
 986                 clock-names = "pclk_hdmi",
 987                               "hdcp_clk_hdmi",
 988                               "cec_clk_hdmi",
 989                               "dclk_hdmi_phy";
 990                 resets = <&cru SRST_HDMI>;
 991                 reset-names = "hdmi";
 992                 pinctrl-names = "default", "gpio";
 993                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 994                 pinctrl-1 = <&i2c5_gpio>;
 995                 status = "disabled";
 996         };
 997
 998         vpu: vpu_service@ff9a0000 {
 999                 compatible = "rockchip,vpu_service";
1000                 rockchip,grf = <&grf>;
1001                 iommu_enabled = <1>;
1002                 reg = <0x0 0xff9a0000 0x0 0x800>;
1003                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1004                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1005                 interrupt-names = "irq_dec", "irq_enc";
1006                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1007                 clock-names = "aclk_vcodec", "hclk_vcodec";
1008                 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
1009                 reset-names = "video_h", "video_a";
1010                 name = "vpu_service";
1011                 dev_mode = <0>;
1012                 status = "disabled";
1013         };
1014
1015         rkvdec: rkvdec@ff9b0000 {
1016                 compatible = "rockchip,rkvdec";
1017                 rockchip,grf = <&grf>;
1018                 iommu_enabled = <1>;
1019                 reg = <0x0 0xff9b0000 0x0 0x400>;
1020                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1021                 interrupt-names = "irq_dec";
1022                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
1023                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
1024                 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
1025                 reset-names = "video_h", "video_a";
1026                 dev_mode = <2>;
1027                 name = "rkvdec";
1028                 status = "disabled";
1029         };
1030
1031         pinctrl: pinctrl {
1032                 compatible = "rockchip,rk3366-pinctrl";
1033                 rockchip,grf = <&grf>;
1034                 rockchip,pmu = <&pmugrf>;
1035                 #address-cells = <0x2>;
1036                 #size-cells = <0x2>;
1037                 ranges;
1038
1039                 gpio0: gpio0@ff750000 {
1040                         compatible = "rockchip,gpio-bank";
1041                         reg = <0x0 0xff750000 0x0 0x100>;
1042                         clocks = <&cru PCLK_GPIO0>;
1043                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1044
1045                         gpio-controller;
1046                         #gpio-cells = <0x2>;
1047
1048                         interrupt-controller;
1049                         #interrupt-cells = <0x2>;
1050                 };
1051
1052                 gpio1: gpio1@ff780000 {
1053                         compatible = "rockchip,gpio-bank";
1054                         reg = <0x0 0xff758000 0x0 0x100>;
1055                         clocks = <&cru PCLK_GPIO1>;
1056                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1057
1058                         gpio-controller;
1059                         #gpio-cells = <0x2>;
1060
1061                         interrupt-controller;
1062                         #interrupt-cells = <0x2>;
1063                 };
1064
1065                 gpio2: gpio2@ff790000 {
1066                         compatible = "rockchip,gpio-bank";
1067                         reg = <0x0 0xff790000 0x0 0x100>;
1068                         clocks = <&cru PCLK_GPIO2>;
1069                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1070
1071                         gpio-controller;
1072                         #gpio-cells = <0x2>;
1073
1074                         interrupt-controller;
1075                         #interrupt-cells = <0x2>;
1076                 };
1077
1078                 gpio3: gpio3@ff7a0000 {
1079                         compatible = "rockchip,gpio-bank";
1080                         reg = <0x0 0xff7a0000 0x0 0x100>;
1081                         clocks = <&cru PCLK_GPIO3>;
1082                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1083
1084                         gpio-controller;
1085                         #gpio-cells = <0x2>;
1086
1087                         interrupt-controller;
1088                         #interrupt-cells = <0x2>;
1089                 };
1090
1091                 gpio4: gpio4@ff7b0000 {
1092                         compatible = "rockchip,gpio-bank";
1093                         reg = <0x0 0xff7b0000 0x0 0x100>;
1094                         clocks = <&cru PCLK_GPIO4>;
1095                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1096
1097                         gpio-controller;
1098                         #gpio-cells = <0x2>;
1099
1100                         interrupt-controller;
1101                         #interrupt-cells = <0x2>;
1102                 };
1103
1104                 gpio5: gpio5@ff7c0000 {
1105                         compatible = "rockchip,gpio-bank";
1106                         reg = <0x0 0xff7c0000 0x0 0x100>;
1107                         clocks = <&cru PCLK_GPIO5>;
1108                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1109
1110                         gpio-controller;
1111                         #gpio-cells = <0x2>;
1112
1113                         interrupt-controller;
1114                         #interrupt-cells = <0x2>;
1115                 };
1116
1117                 pcfg_pull_up: pcfg-pull-up {
1118                         bias-pull-up;
1119                 };
1120
1121                 pcfg_pull_down: pcfg-pull-down {
1122                         bias-pull-down;
1123                 };
1124
1125                 pcfg_pull_none: pcfg-pull-none {
1126                         bias-disable;
1127                 };
1128
1129                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1130                         bias-disable;
1131                         drive-strength = <12>;
1132                 };
1133
1134                 emmc {
1135                         emmc_clk: emmc-clk {
1136                                 rockchip,pins =
1137                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
1138                         };
1139
1140                         emmc_cmd: emmc-cmd {
1141                                 rockchip,pins =
1142                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
1143                         };
1144
1145                         emmc_pwr: emmc-pwr {
1146                                 rockchip,pins =
1147                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
1148                         };
1149
1150                         emmc_bus1: emmc-bus1 {
1151                                 rockchip,pins =
1152                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
1153                         };
1154
1155                         emmc_bus4: emmc-bus4 {
1156                                 rockchip,pins =
1157                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1158                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1159                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1160                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1161                         };
1162
1163                         emmc_bus8: emmc-bus8 {
1164                                 rockchip,pins =
1165                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1166                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1167                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1168                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
1169                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
1170                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
1171                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
1172                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
1173                         };
1174                 };
1175
1176                 sdmmc {
1177                         sdmmc_cd: sdmmc-cd {
1178                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1179                         };
1180
1181                         sdmmc_bus1: sdmmc-bus1 {
1182                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1183                         };
1184
1185                         sdmmc_bus4: sdmmc-bus4 {
1186                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1187                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1188                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1189                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1190                         };
1191
1192                         sdmmc_clk: sdmmc-clk {
1193                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1194                         };
1195
1196                         sdmmc_cmd: sdmmc-cmd {
1197                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1198                         };
1199                 };
1200
1201                 sdio {
1202                         sdio_bus1: sdio-bus1 {
1203                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1204                         };
1205
1206                         sdio_bus4: sdio-bus4 {
1207                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1208                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1209                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1210                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1211                         };
1212
1213                         sdio_cmd: sdio-cmd {
1214                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1215                         };
1216
1217                         sdio_clk: sdio-clk {
1218                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1219                         };
1220
1221                         sdio_cd: sdio-cd {
1222                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1223                         };
1224
1225                         sdio_wp: sdio-wp {
1226                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1227                         };
1228
1229                         sdio_int: sdio-int {
1230                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1231                         };
1232
1233                         sdio_pwr: sdio-pwr {
1234                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1235                         };
1236                 };
1237
1238                 hdmi_i2c {
1239                         hdmii2c_xfer: hdmii2c-xfer {
1240                                 rockchip,pins =
1241                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1242                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1243                         };
1244                 };
1245
1246                 hdmi_pin {
1247                         hdmi_cec: hdmi-cec {
1248                                 rockchip,pins =
1249                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1250                         };
1251                 };
1252
1253                 i2c0 {
1254                         i2c0_xfer: i2c0-xfer {
1255                                 rockchip,pins =
1256                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1257                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1258                         };
1259                 };
1260
1261                 i2c1 {
1262                         i2c1_xfer: i2c1-xfer {
1263                                 rockchip,pins =
1264                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1265                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1266                         };
1267                 };
1268
1269                 i2c2 {
1270                         i2c2_xfer: i2c2-xfer {
1271                                 rockchip,pins =
1272                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1273                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1274                         };
1275
1276                         i2c2_gpio: i2c2-gpio {
1277                                 rockchip,pins =
1278                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1279                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1280                         };
1281                 };
1282
1283                 i2c3 {
1284                         i2c3_xfer: i2c3-xfer {
1285                                 rockchip,pins =
1286                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1287                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1288                         };
1289                 };
1290
1291                 i2c4 {
1292                         i2c4_xfer: i2c4-xfer {
1293                                 rockchip,pins =
1294                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1295                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1296                         };
1297
1298                         i2c4_gpio: i2c4-gpio {
1299                                 rockchip,pins =
1300                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1301                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1302                         };
1303                 };
1304
1305                 i2c5 {
1306                         i2c5_xfer: i2c5-xfer {
1307                                 rockchip,pins =
1308                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1309                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1310                         };
1311                         i2c5_gpio: i2c5-gpio {
1312                                 rockchip,pins =
1313                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1314                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1315                         };
1316                 };
1317
1318                 i2s {
1319                         i2s_8ch_bus: i2s-8ch-bus {
1320                                 rockchip,pins =
1321                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1322                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1323                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1324                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1325                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1326                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1327                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1328                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1329                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1330                         };
1331                 };
1332
1333                 spdif {
1334                         spdif_bus: spdif-bus {
1335                                 rockchip,pins =
1336                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1337                         };
1338                 };
1339
1340                 spi0 {
1341                         spi0_clk: spi0-clk {
1342                                 rockchip,pins =
1343                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1344                         };
1345                         spi0_cs0: spi0-cs0 {
1346                                 rockchip,pins =
1347                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1348                         };
1349                         spi0_cs1: spi0-cs1 {
1350                                 rockchip,pins =
1351                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1352                         };
1353                         spi0_tx: spi0-tx {
1354                                 rockchip,pins =
1355                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1356                         };
1357                         spi0_rx: spi0-rx {
1358                                 rockchip,pins =
1359                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1360                         };
1361                 };
1362
1363                 spi1 {
1364                         spi1_clk: spi1-clk {
1365                                 rockchip,pins =
1366                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1367                         };
1368                         spi1_cs0: spi1-cs0 {
1369                                 rockchip,pins =
1370                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1371                         };
1372                         spi1_tx: spi1-tx {
1373                                 rockchip,pins =
1374                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1375                         };
1376                         spi1_rx: spi1-rx {
1377                                 rockchip,pins =
1378                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1379                         };
1380                 };
1381
1382                 scr {
1383                         scr_clk: scr-clk {
1384                                 rockchip,pins =
1385                                         <5 8 RK_FUNC_2 &pcfg_pull_none>;
1386                         };
1387
1388                         scr_io: scr-io {
1389                                 rockchip,pins =
1390                                         <5 9 RK_FUNC_2 &pcfg_pull_up>;
1391                         };
1392
1393                         scr_rst: scr-rst {
1394                                 rockchip,pins =
1395                                         <5 10 RK_FUNC_1 &pcfg_pull_none>;
1396                         };
1397
1398                         scr_detect: scr-detect {
1399                                 rockchip,pins =
1400                                         <5 11 RK_FUNC_1 &pcfg_pull_none>;
1401                         };
1402                 };
1403
1404                 uart0 {
1405                         uart0_xfer: uart0-xfer {
1406                                 rockchip,pins =
1407                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1408                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1409                         };
1410
1411                         uart0_cts: uart0-cts {
1412                                 rockchip,pins =
1413                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1414                         };
1415
1416                         uart0_rts: uart0-rts {
1417                                 rockchip,pins =
1418                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1419                         };
1420                 };
1421
1422                 uart2_t0 {
1423                         uart2_t0_xfer: uart2_t0-xfer {
1424                                 rockchip,pins =
1425                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1426                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1427                         };
1428                         /* no rts / cts for uart2 */
1429                 };
1430
1431                 uart2_t1 {
1432                         uart2_t1_xfer: uart2_t1-xfer {
1433                                 rockchip,pins =
1434                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1435                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1436                         };
1437                         /* no rts / cts for uart2 */
1438                 };
1439
1440                 uart2_t2 {
1441                         uart2_t2_xfer: uart2_t2-xfer {
1442                                 rockchip,pins =
1443                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1444                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1445                         };
1446                         /* no rts / cts for uart2 */
1447                 };
1448
1449                 uart3 {
1450                         uart3_xfer: uart3-xfer {
1451                                 rockchip,pins =
1452                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1453                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1454                         };
1455
1456                         uart3_cts: uart3-cts {
1457                                 rockchip,pins =
1458                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1459                         };
1460
1461                         uart3_rts: uart3-rts {
1462                                 rockchip,pins =
1463                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1464                         };
1465                 };
1466
1467                 pwm0 {
1468                         pwm0_pin: pwm0-pin {
1469                                 rockchip,pins =
1470                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1471                         };
1472                 };
1473
1474                 pwm1 {
1475                         pwm1_pin: pwm1-pin {
1476                                 rockchip,pins =
1477                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1478                         };
1479                 };
1480
1481                 pwm2_t0 {
1482                         pwm2_t0_pin: pwm2_t0-pin {
1483                                 rockchip,pins =
1484                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1485                         };
1486                 };
1487
1488                 pwm2_t1 {
1489                         pwm2_t1_pin: pwm2_t1-pin {
1490                                 rockchip,pins =
1491                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1492                         };
1493                 };
1494
1495                 pwm3_t0 {
1496                         pwm3_t0_pin: pwm3_t0-pin {
1497                                 rockchip,pins =
1498                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1499                         };
1500                 };
1501
1502                 pwm3_t1 {
1503                         pwm3_t1_pin: pwm3_t1-pin {
1504                                 rockchip,pins =
1505                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1506                         };
1507                 };
1508
1509                 pwm3_t2 {
1510                         pwm3_t2_pin: pwm3_t2-pin {
1511                                 rockchip,pins =
1512                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1513                         };
1514                 };
1515
1516                 lcdc {
1517                         lcdc_lcdc: lcdc-lcdc {
1518                                 rockchip,pins =
1519                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1520                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1521                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1522                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1523                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1524                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1525                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1526                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1527                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1528                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1529                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1530                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1531                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1532                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1533                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1534                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1535                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1536                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1537                         };
1538
1539                         lcdc_gpio: lcdc-gpio {
1540                                 rockchip,pins =
1541                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1542                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1543                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1544                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1545                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1546                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1547                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1548                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1549                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1550                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1551                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1552                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1553                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1554                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1555                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1556                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1557                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1558                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1559                         };
1560                 };
1561
1562                 gmac {
1563                         rgmii_pins: rgmii-pins {
1564                                 rockchip,pins =
1565                                         /* mac_rxd3 */
1566                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1567                                         /* mac_rxd2 */
1568                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1569                                         /* mac_txd3 */
1570                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1571                                         /* mac_txd2 */
1572                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1573                                         /* mac_rxd1 */
1574                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1575                                         /* mac_rxd0 */
1576                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1577                                         /* mac_txd1 */
1578                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1579                                         /* mac_txd0 */
1580                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1581                                         /* mac_txclkout */
1582                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1583                                         /* mac_crs */
1584                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1585                                         /* mac_rxclkin */
1586                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1587                                         /* mac_mdio */
1588                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1589                                         /* mac_txen */
1590                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1591                                         /* mac_clk */
1592                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1593                                         /* mac_rxer */
1594                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1595                                         /* mac_rxdv */
1596                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1597                                         /* mac_mdc */
1598                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1599                         };
1600
1601                         rmii_pins: rmii-pins {
1602                                 rockchip,pins =
1603                                         /* mac_rxd1 */
1604                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1605                                         /* mac_rxd0 */
1606                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1607                                         /* mac_txd1 */
1608                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1609                                         /* mac_txd0 */
1610                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1611                                         /* mac_crs */
1612                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1613                                         /* mac_rxclkin */
1614                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1615                                         /* mac_mdio */
1616                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1617                                         /* mac_txen */
1618                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1619                                         /* mac_clk */
1620                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1621                                         /* mac_rxer */
1622                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1623                                         /* mac_rxdv */
1624                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1625                                         /* mac_mdc */
1626                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1627                         };
1628                 };
1629
1630                 eth_phy {
1631                         eth_phy_pwr: eth-phy-pwr {
1632                                 rockchip,pins =
1633                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1634                         };
1635                 };
1636
1637                 tsadc_pin {
1638                         tsadc_gpio: tsadc-gpio {
1639                                 rockchip,pins =
1640                                         <0 22 RK_FUNC_GPIO &pcfg_pull_none>;
1641                         };
1642
1643                         tsadc_int: tsadc-int {
1644                                 rockchip,pins =
1645                                         <0 22 RK_FUNC_2 &pcfg_pull_none>;
1646                         };
1647                 };
1648
1649                 usb2 {
1650                         host_vbus_drv: host-vbus-drv {
1651                                 rockchip,pins =
1652                                         <0 16 RK_FUNC_GPIO &pcfg_pull_none>;
1653                         };
1654                 };
1655
1656         };
1657
1658         gpu: gpu@ffa30000 {
1659                 compatible = "arm,malit764",
1660                              "arm,malit76x",
1661                              "arm,malit7xx",
1662                              "arm,mali-midgard";
1663
1664                 reg = <0x0 0xffa30000 0 0x10000>;
1665
1666                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1667                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1668                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1669                 interrupt-names = "GPU", "MMU", "JOB";
1670
1671                 clocks = <&cru ACLK_GPU>;
1672                 clock-names = "clk_mali";
1673                 #cooling-cells = <2>; /* min followed by max */
1674                 operating-points-v2 = <&gpu_opp_table>;
1675                 status = "disabled";
1676
1677                 power_model {
1678                         compatible = "arm,mali-simple-power-model";
1679                         voltage = <900>;
1680                         frequency = <500>;
1681                         static-power = <300>;
1682                         dynamic-power = <1780>;
1683                         ts = <32000 4700 (-80) 2>;
1684                         thermal-zone = "gpu-thermal";
1685                 };
1686         };
1687
1688         gpu_opp_table: gpu_opp_table {
1689                 compatible = "operating-points-v2";
1690                 opp-shared;
1691
1692                 opp@96000000 {
1693                         opp-hz = /bits/ 64 <96000000>;
1694                         opp-microvolt = <1100000>;
1695                 };
1696                 opp@192000000 {
1697                         opp-hz = /bits/ 64 <192000000>;
1698                         opp-microvolt = <1100000>;
1699                 };
1700                 opp@288000000 {
1701                         opp-hz = /bits/ 64 <288000000>;
1702                         opp-microvolt = <1100000>;
1703                 };
1704                 opp@375000000 {
1705                         opp-hz = /bits/ 64 <375000000>;
1706                         opp-microvolt = <1125000>;
1707                 };
1708                 opp@480000000 {
1709                         opp-hz = /bits/ 64 <480000000>;
1710                         opp-microvolt = <1200000>;
1711                 };
1712         };
1713 };