arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/display/mipi_dsi.h>
  50 #include <dt-bindings/power/rk3366-power.h>
  51 #include <dt-bindings/soc/rockchip_boot-mode.h>
  52 #include <dt-bindings/thermal/thermal.h>
  53
  54 / {
  55         compatible = "rockchip,rk3366";
  56         interrupt-parent = <&gic>;
  57         #address-cells = <2>;
  58         #size-cells = <2>;
  59
  60         aliases {
  61                 i2c0 = &i2c0;
  62                 i2c1 = &i2c1;
  63                 i2c2 = &i2c2;
  64                 i2c3 = &i2c3;
  65                 i2c4 = &i2c4;
  66                 i2c5 = &i2c5;
  67                 serial0 = &uart0;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 spi0 = &spi0;
  71                 spi1 = &spi1;
  72         };
  73
  74         cpus {
  75                 #address-cells = <0x2>;
  76                 #size-cells = <0x0>;
  77
  78                 cpu0: cpu@0 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53","arm,armv8";
  81                         reg = <0x0 0x0>;
  82                         enable-method = "psci";
  83                         clocks = <&cru ARMCLK>;
  84                         operating-points-v2 = <&cpu0_opp_table>;
  85                         cpu-idle-states = <&cpu_sleep>;
  86                         #cooling-cells = <2>; /* min followed by max */
  87                         dynamic-power-coefficient = <166>;
  88                 };
  89
  90                 cpu1: cpu@1 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53","arm,armv8";
  93                         reg = <0x0 0x1>;
  94                         enable-method = "psci";
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                         cpu-idle-states = <&cpu_sleep>;
  97                 };
  98
  99                 cpu2: cpu@2 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a53","arm,armv8";
 102                         reg = <0x0 0x2>;
 103                         enable-method = "psci";
 104                         operating-points-v2 = <&cpu0_opp_table>;
 105                         cpu-idle-states = <&cpu_sleep>;
 106                 };
 107
 108                 cpu3: cpu@3 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53","arm,armv8";
 111                         reg = <0x0 0x3>;
 112                         enable-method = "psci";
 113                         operating-points-v2 = <&cpu0_opp_table>;
 114                         cpu-idle-states = <&cpu_sleep>;
 115                 };
 116
 117                 idle-states {
 118                         entry-method = "psci";
 119                         cpu_sleep: cpu-sleep-0 {
 120                                 compatible = "arm,idle-state";
 121                                 local-timer-stop;
 122                                 arm,psci-suspend-param = <0x0010000>;
 123                                 entry-latency-us = <350>;
 124                                 exit-latency-us = <600>;
 125                                 min-residency-us = <1150>;
 126                         };
 127                 };
 128         };
 129
 130         cpu0_opp_table: opp_table0 {
 131                 compatible = "operating-points-v2";
 132                 opp-shared;
 133
 134                 opp@408000000 {
 135                         opp-hz = /bits/ 64 <408000000>;
 136                         opp-microvolt = <950000>;
 137                         clock-latency-ns = <40000>;
 138                         opp-suspend;
 139                 };
 140                 opp@600000000 {
 141                         opp-hz = /bits/ 64 <600000000>;
 142                         opp-microvolt = <950000>;
 143                 };
 144                 opp@816000000 {
 145                         opp-hz = /bits/ 64 <816000000>;
 146                         opp-microvolt = <1000000>;
 147                 };
 148                 opp@1008000000 {
 149                         opp-hz = /bits/ 64 <1008000000>;
 150                         opp-microvolt = <1075000>;
 151                 };
 152                 opp@1200000000 {
 153                         opp-hz = /bits/ 64 <1200000000>;
 154                         opp-microvolt = <1175000>;
 155                 };
 156                 opp@1296000000 {
 157                         opp-hz = /bits/ 64 <1296000000>;
 158                         opp-microvolt = <1250000>;
 159                 };
 160         };
 161
 162         psci {
 163                 compatible = "arm,psci-1.0";
 164                 method = "smc";
 165         };
 166
 167         timer {
 168                 compatible = "arm,armv8-timer";
 169                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 170                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 171                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 172                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 173         };
 174
 175         arm-pmu {
 176                 compatible = "arm,cortex-a53-pmu";
 177                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 181                 interrupt-affinity = <&cpu0>,
 182                                      <&cpu1>,
 183                                      <&cpu2>,
 184                                      <&cpu3>;
 185         };
 186
 187         xin24m: xin24m {
 188                 compatible = "fixed-clock";
 189                 #clock-cells = <0>;
 190                 clock-frequency = <24000000>;
 191                 clock-output-names = "xin24m";
 192         };
 193
 194         gic: interrupt-controller@ffb71000 {
 195                 compatible = "arm,gic-400";
 196                 interrupt-controller;
 197                 #interrupt-cells = <3>;
 198                 #address-cells = <0>;
 199
 200                 reg = <0x0 0xffb71000 0x0 0x1000>,
 201                       <0x0 0xffb72000 0x0 0x1000>,
 202                       <0x0 0xffb74000 0x0 0x2000>,
 203                       <0x0 0xffb76000 0x0 0x2000>;
 204                 interrupts = <GIC_PPI 9
 205                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 206         };
 207
 208         nandc0: nandc@ff0c0000 {
 209                 compatible = "rockchip,rk-nandc";
 210                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 211                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 212                 nandc_id = <0>;
 213                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 214                 clock-names = "clk_nandc", "hclk_nandc";
 215                 status = "disabled";
 216         };
 217
 218         saradc: saradc@ff100000 {
 219                 compatible = "rockchip,saradc";
 220                 reg = <0x0 0xff100000 0x0 0x100>;
 221                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 222                 #io-channel-cells = <1>;
 223                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 224                 clock-names = "saradc", "apb_pclk";
 225                 status = "disabled";
 226         };
 227
 228         spi0: spi@ff110000 {
 229                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 230                 reg = <0x0 0xff110000 0x0 0x1000>;
 231                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 232                 clock-names = "spiclk", "apb_pclk";
 233                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 234                 pinctrl-names = "default";
 235                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 236                 #address-cells = <1>;
 237                 #size-cells = <0>;
 238                 status = "disabled";
 239         };
 240
 241         spi1: spi@ff120000 {
 242                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 243                 reg = <0x0 0xff120000 0x0 0x1000>;
 244                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 245                 clock-names = "spiclk", "apb_pclk";
 246                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 247                 pinctrl-names = "default";
 248                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 status = "disabled";
 252         };
 253
 254         scr: rkscr@ff1d0000 {
 255                 compatible = "rockchip-scr";
 256                 reg = <0x0 0xff1d0000 0x0 0x10000>;
 257                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 pinctrl-names = "default";
 261                 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
 262                 clocks = <&cru PCLK_SIM>;
 263                 clock-names = "g_pclk_sim_card";
 264                 status = "disabled";
 265         };
 266
 267         thermal-zones {
 268                 soc_thermal: soc-thermal {
 269                         polling-delay-passive = <100>; /* milliseconds */
 270                         polling-delay = <1000>; /* milliseconds */
 271                         sustainable-power = <1600>; /* milliwatts */
 272
 273                         thermal-sensors = <&tsadc 0>;
 274
 275                         trips {
 276                                 threshold: trip-point@0 {
 277                                         temperature = <70000>; /* millicelsius */
 278                                         hysteresis = <2000>; /* millicelsius */
 279                                         type = "passive";
 280                                 };
 281                                 target: trip-point@1 {
 282                                         temperature = <85000>; /* millicelsius */
 283                                         hysteresis = <2000>; /* millicelsius */
 284                                         type = "passive";
 285                                 };
 286                                 soc_crit: soc-crit {
 287                                         temperature = <95000>; /* millicelsius */
 288                                         hysteresis = <2000>; /* millicelsius */
 289                                         type = "critical";
 290                                 };
 291                         };
 292
 293                         cooling-maps {
 294                                 map0 {
 295                                         trip = <&target>;
 296                                         cooling-device =
 297                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 298                                 };
 299                                 map1 {
 300                                         trip = <&target>;
 301                                         cooling-device =
 302                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 303                                 };
 304                         };
 305                 };
 306
 307                 gpu_thermal: gpu-thermal {
 308                         polling-delay-passive = <100>; /* milliseconds */
 309                         polling-delay = <1000>; /* milliseconds */
 310
 311                         thermal-sensors = <&tsadc 1>;
 312                 };
 313         };
 314
 315         tsadc: tsadc@ff260000 {
 316                 compatible = "rockchip,rk3366-tsadc";
 317                 reg = <0x0 0xff260000 0x0 0x100>;
 318                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 320                 clock-names = "tsadc", "apb_pclk";
 321                 resets = <&cru SRST_TSADC>;
 322                 reset-names = "tsadc-apb";
 323                 pinctrl-names = "default";
 324                 pinctrl-0 = <&tsadc_gpio>;
 325                 #thermal-sensor-cells = <1>;
 326                 rockchip,hw-tshut-temp = <95000>;
 327                 status = "disabled";
 328         };
 329
 330         sdmmc: rksdmmc@ff400000 {
 331                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 332                 clock-freq-min-max = <400000 150000000>;
 333                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 334                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 335                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 336                 fifo-depth = <0x100>;
 337                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 338                 reg = <0x0 0xff400000 0x0 0x4000>;
 339                 status = "disabled";
 340         };
 341
 342         sdio: rksdmmc@ff410000 {
 343                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 344                 clock-freq-min-max = <400000 150000000>;
 345                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 346                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 347                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 348                 fifo-depth = <0x100>;
 349                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 350                 reg = <0x0 0xff410000 0x0 0x4000>;
 351                 status = "disabled";
 352         };
 353
 354         emmc: rksdmmc@ff420000 {
 355                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 356                 clock-freq-min-max = <400000 150000000>;
 357                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 358                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 359                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 360                 fifo-depth = <0x100>;
 361                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 362                 reg = <0x0 0xff420000 0x0 0x4000>;
 363                 status = "disabled";
 364         };
 365
 366         gmac: eth@ff440000 {
 367                 compatible = "rockchip,rk3366-gmac";
 368                 reg = <0x0 0xff440000 0x0 0x10000>;
 369                 rockchip,grf = <&grf>;
 370                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 371                 interrupt-names = "macirq";
 372                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 373                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 374                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 375                          <&cru PCLK_GMAC>;
 376                 clock-names = "stmmaceth", "mac_clk_rx",
 377                               "mac_clk_tx", "clk_mac_ref",
 378                               "clk_mac_refout", "aclk_mac",
 379                               "pclk_mac";
 380                 resets = <&cru SRST_MAC>;
 381                 reset-names = "stmmaceth";
 382                 status = "disabled";
 383         };
 384
 385         i2c0: i2c@ff650000 {
 386                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 387                 reg = <0x0 0xff728000 0x0 0x1000>;
 388                 clocks = <&cru PCLK_I2C0>;
 389                 clock-names = "i2c";
 390                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&i2c0_xfer>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 status = "disabled";
 396         };
 397
 398         i2c2: i2c@ff140000 {
 399                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 400                 reg = <0x0 0xff140000 0x0 0x1000>;
 401                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 clock-names = "i2c";
 405                 clocks = <&cru PCLK_I2C2>;
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&i2c2_xfer>;
 408                 status = "disabled";
 409         };
 410
 411         i2c3: i2c@ff150000 {
 412                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 413                 reg = <0x0 0xff150000 0x0 0x1000>;
 414                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 clock-names = "i2c";
 418                 clocks = <&cru PCLK_I2C3>;
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&i2c3_xfer>;
 421                 status = "disabled";
 422         };
 423
 424         i2c4: i2c@ff160000 {
 425                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 426                 reg = <0x0 0xff160000 0x0 0x1000>;
 427                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 428                 #address-cells = <1>;
 429                 #size-cells = <0>;
 430                 clock-names = "i2c";
 431                 clocks = <&cru PCLK_I2C4>;
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&i2c4_xfer>;
 434                 status = "disabled";
 435         };
 436
 437         i2c5: i2c@ff170000 {
 438                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 439                 reg = <0x0 0xff170000 0x0 0x1000>;
 440                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 441                 #address-cells = <1>;
 442                 #size-cells = <0>;
 443                 clock-names = "i2c";
 444                 clocks = <&cru PCLK_I2C5>;
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&i2c5_xfer>;
 447                 status = "disabled";
 448         };
 449
 450         uart0: serial@ff180000 {
 451                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 452                 reg = <0x0 0xff180000 0x0 0x100>;
 453                 clock-frequency = <24000000>;
 454                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 455                 clock-names = "baudclk", "apb_pclk";
 456                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 457                 reg-shift = <2>;
 458                 reg-io-width = <4>;
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 461                 status = "disabled";
 462         };
 463
 464         uart3: serial@ff1b0000 {
 465                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 466                 reg = <0x0 0xff1b0000 0x0 0x100>;
 467                 clock-frequency = <24000000>;
 468                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 469                 clock-names = "baudclk", "apb_pclk";
 470                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 475                 status = "disabled";
 476         };
 477
 478         usb_host0_ehci: usb@ff480000 {
 479                 compatible = "generic-ehci";
 480                 reg = <0x0 0xff480000 0x0 0x20000>;
 481                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 482                 clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
 483                 clock-names = "usbphy_480m", "hclk_host0";
 484                 phys = <&u2phy_host>;
 485                 phy-names = "usb";
 486                 status = "disabled";
 487         };
 488
 489         usb_host0_ohci: usb@ff4a0000 {
 490                 compatible = "generic-ohci";
 491                 reg = <0x0 0xff4a0000 0x0 0x20000>;
 492                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 493                 clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
 494                 clock-names = "usbphy_480m", "hclk_host0";
 495                 phys = <&u2phy_host>;
 496                 phy-names = "usb";
 497                 status = "disabled";
 498         };
 499
 500         usb_otg: usb@ff4c0000 {
 501                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 502                              "snps,dwc2";
 503                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 504                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 505                 clocks = <&cru HCLK_OTG>;
 506                 clock-names = "otg";
 507                 dr_mode = "otg";
 508                 g-np-tx-fifo-size = <16>;
 509                 g-rx-fifo-size = <275>;
 510                 g-tx-fifo-size = <256 128 128 64 64 32>;
 511                 g-use-dma;
 512                 status = "disabled";
 513         };
 514
 515         i2c1: i2c@ff660000 {
 516                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 517                 reg = <0x0 0xff660000 0x0 0x1000>;
 518                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 519                 #address-cells = <1>;
 520                 #size-cells = <0>;
 521                 clock-names = "i2c";
 522                 clocks = <&cru PCLK_I2C1>;
 523                 pinctrl-names = "default";
 524                 pinctrl-0 = <&i2c1_xfer>;
 525                 status = "disabled";
 526         };
 527
 528         efuse: efuse@ff670000 {
 529                 compatible = "rockchip,rk3366-efuse";
 530                 reg = <0x0 0xff670000 0x0 0x20>;
 531                 #address-cells = <1>;
 532                 #size-cells = <1>;
 533                 clocks = <&cru PCLK_EFUSE_256>;
 534                 clock-names = "pclk_efuse";
 535
 536                 /* Data cells */
 537                 cpu_leakage: cpu-leakage {
 538                         reg = <0x17 0x1>;
 539                 };
 540                 gpu_leakage: gpu-leakage {
 541                         reg = <0x18 0x1>;
 542                 };
 543                 logic_leakage: logic-leakage {
 544                         reg = <0x19 0x1>;
 545                 };
 546                 wafer_info: wafer-info {
 547                         reg = <0x1c 0x1>;
 548                 };
 549         };
 550
 551         pwm0: pwm@ff680000 {
 552                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 553                 reg = <0x0 0xff680000 0x0 0x10>;
 554                 #pwm-cells = <3>;
 555                 pinctrl-names = "default";
 556                 pinctrl-0 = <&pwm0_pin>;
 557                 clocks = <&cru PCLK_RKPWM>;
 558                 clock-names = "pwm";
 559                 status = "disabled";
 560         };
 561
 562         pwm1: pwm@ff680010 {
 563                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 564                 reg = <0x0 0xff680010 0x0 0x10>;
 565                 #pwm-cells = <3>;
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&pwm1_pin>;
 568                 clocks = <&cru PCLK_RKPWM>;
 569                 clock-names = "pwm";
 570                 status = "disabled";
 571         };
 572
 573         pwm2: pwm@ff680020 {
 574                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 575                 reg = <0x0 0xff680020 0x0 0x10>;
 576                 #pwm-cells = <3>;
 577                 clocks = <&cru PCLK_RKPWM>;
 578                 clock-names = "pwm";
 579                 status = "disabled";
 580         };
 581
 582         pwm3: pwm@ff680030 {
 583                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 584                 reg = <0x0 0xff680030 0x0 0x10>;
 585                 #pwm-cells = <3>;
 586                 pinctrl-names = "default";
 587                 pinctrl-0 = <&pwm3_t2_pin>;
 588                 clocks = <&cru PCLK_RKPWM>;
 589                 clock-names = "pwm";
 590                 status = "disabled";
 591         };
 592
 593         uart2: serial@ff690000 {
 594                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 595                 reg = <0x0 0xff690000 0x0 0x100>;
 596                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 597                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 598                 clock-names = "baudclk", "apb_pclk";
 599                 reg-shift = <2>;
 600                 reg-io-width = <4>;
 601                 pinctrl-names = "default";
 602                 pinctrl-0 = <&uart2_t1_xfer>;
 603                 status = "disabled";
 604         };
 605
 606         pmu: power-management@ff730000 {
 607                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 608                 reg = <0x0 0xff730000 0x0 0x1000>;
 609
 610                 power: power-controller {
 611                         status = "disabled";
 612                         compatible = "rockchip,rk3366-power-controller";
 613                         #power-domain-cells = <1>;
 614                         #address-cells = <1>;
 615                         #size-cells = <0>;
 616
 617                         /*
 618                          * Note: Although SCLK_* are the working clocks
 619                          * of device without including on the NOC, needed for
 620                          * synchronous reset.
 621                          *
 622                          * The clocks on the which NOC:
 623                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 624                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 625                          * ACLK_ISP is on ACLK_ISP_NIU.
 626                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 627                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 628                          *
 629                          * Which clock are device clocks:
 630                          *      clocks          devices
 631                          *      *_IEP           IEP:Image Enhancement Processor
 632                          *      *_ISP           ISP:Image Signal Processing
 633                          *      *_VOP*          VOP:Visual Output Processor
 634                          *      *_RGA           RGA
 635                          *      *_DPHY*         LVDS
 636                          *      *_HDMI          HDMI
 637                          *      *_MIPI_*        MIPI
 638                          */
 639                         pd_vio {
 640                                 reg = <RK3366_PD_VIO>;
 641                                 clocks = <&cru ACLK_IEP>,
 642                                          <&cru ACLK_ISP>,
 643                                          <&cru ACLK_RGA>,
 644                                          <&cru ACLK_HDCP>,
 645                                          <&cru ACLK_VOP_FULL>,
 646                                          <&cru ACLK_VOP_LITE>,
 647                                          <&cru ACLK_VOP_IEP>,
 648                                          <&cru DCLK_VOP_FULL>,
 649                                          <&cru DCLK_VOP_LITE>,
 650                                          <&cru HCLK_IEP>,
 651                                          <&cru HCLK_ISP>,
 652                                          <&cru HCLK_RGA>,
 653                                          <&cru HCLK_VOP_FULL>,
 654                                          <&cru HCLK_VOP_LITE>,
 655                                          <&cru HCLK_VIO_HDCPMMU>,
 656                                          <&cru PCLK_HDMI_CTRL>,
 657                                          <&cru PCLK_HDCP>,
 658                                          <&cru PCLK_MIPI_DSI0>,
 659                                          <&cru SCLK_VOP_FULL_PWM>,
 660                                          <&cru SCLK_HDCP>,
 661                                          <&cru SCLK_ISP>,
 662                                          <&cru SCLK_RGA>,
 663                                          <&cru SCLK_HDMI_CEC>,
 664                                          <&cru SCLK_HDMI_HDCP>;
 665                         };
 666
 667                         /*
 668                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 669                          * (video endecoder & decoder) clocks that on the
 670                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 671                          */
 672                         pd_vpu {
 673                                 reg = <RK3366_PD_VPU>;
 674                                 clocks = <&cru ACLK_VIDEO>,
 675                                          <&cru HCLK_VIDEO>;
 676                         };
 677
 678                         /*
 679                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 680                          * (video decoder) clocks that on the
 681                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 682                          */
 683                         pd_rkvdec {
 684                                 reg = <RK3366_PD_RKVDEC>;
 685                                 clocks = <&cru ACLK_RKVDEC>,
 686                                          <&cru HCLK_RKVDEC>;
 687                         };
 688
 689                         pd_video {
 690                                 reg = <RK3366_PD_VIDEO>;
 691                                 clocks = <&cru ACLK_VIDEO>,
 692                                          <&cru ACLK_RKVDEC>,
 693                                          <&cru HCLK_VIDEO>,
 694                                          <&cru HCLK_RKVDEC>,
 695                                          <&cru SCLK_HEVC_CABAC>,
 696                                          <&cru SCLK_HEVC_CORE>;
 697                         };
 698
 699                         /*
 700                          * Note: ACLK_GPU is the GPU clock,
 701                          * and on the ACLK_GPU_NIU (NOC).
 702                          */
 703                         pd_gpu {
 704                                 reg = <RK3366_PD_GPU>;
 705                                 clocks = <&cru ACLK_GPU>;
 706                         };
 707                 };
 708         };
 709
 710         pmugrf: syscon@ff738000 {
 711                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 712                 reg = <0x0 0xff738000 0x0 0x1000>;
 713
 714                 reboot-mode {
 715                         compatible = "syscon-reboot-mode";
 716                         offset = <0x200>;
 717                         mode-normal = <BOOT_NORMAL>;
 718                         mode-recovery = <BOOT_RECOVERY>;
 719                         mode-fastboot = <BOOT_FASTBOOT>;
 720                         mode-loader = <BOOT_LOADER>;
 721                 };
 722
 723                 pmu_pvtm: pmu-pvtm {
 724                         compatible = "rockchip,rk3366-pmu-pvtm";
 725                         clocks = <&cru SCLK_PVTM_PMU>;
 726                         clock-names = "pmu";
 727                         status = "disabled";
 728                 };
 729         };
 730
 731         amba {
 732                 compatible = "arm,amba-bus";
 733                 #address-cells = <2>;
 734                 #size-cells = <2>;
 735                 ranges;
 736
 737                 dmac_peri: dma-controller@ff250000 {
 738                         compatible = "arm,pl330", "arm,primecell";
 739                         reg = <0x0 0xff250000 0x0 0x4000>;
 740                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 741                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 742                         #dma-cells = <1>;
 743                         clocks = <&cru ACLK_DMAC_PERI>;
 744                         clock-names = "apb_pclk";
 745                         peripherals-req-type-burst;
 746                 };
 747
 748                 dmac_bus: dma-controller@ff600000 {
 749                         compatible = "arm,pl330", "arm,primecell";
 750                         reg = <0x0 0xff600000 0x0 0x4000>;
 751                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 752                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 753                         #dma-cells = <1>;
 754                         clocks = <&cru ACLK_DMAC_BUS>;
 755                         clock-names = "apb_pclk";
 756                         peripherals-req-type-burst;
 757                 };
 758         };
 759
 760         cru: clock-controller@ff760000 {
 761                 compatible = "rockchip,rk3366-cru";
 762                 reg = <0x0 0xff760000 0x0 0x1000>;
 763                 rockchip,grf = <&grf>;
 764                 #clock-cells = <1>;
 765                 #reset-cells = <1>;
 766                 assigned-clocks =
 767                         <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
 768                         <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
 769                         <&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>,
 770                         <&cru SCLK_SPDIF_8CH_SRC>,
 771                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 772                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 773                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 774                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 775                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
 776                         <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
 777                         <&cru ACLK_PERI1>;
 778                 assigned-clock-rates =
 779                         <0>, <0>,
 780                         <0>, <0>,
 781                         <0>, <0>,
 782                         <0>,
 783                         <750000000>, <576000000>,
 784                         <594000000>, <594000000>,
 785                         <960000000>, <520000000>,
 786                         <375000000>, <288000000>,
 787                         <100000000>, <100000000>,
 788                         <288000000>, <288000000>,
 789                         <144000000>;
 790                 assigned-clock-parents =
 791                         <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
 792                         <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>,
 793                         <&cru PLL_GPLL>, <&cru PLL_GPLL>,
 794                         <&cru PLL_GPLL>;
 795         };
 796
 797         grf: syscon@ff770000 {
 798                 compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";
 799                 reg = <0x0 0xff770000 0x0 0x1000>;
 800                 #address-cells = <1>;
 801                 #size-cells = <1>;
 802
 803                 u2phy: usb2-phy@700 {
 804                         compatible = "rockchip,rk3366-usb2phy";
 805                         reg = <0x700 0x2c>;
 806                         clocks = <&cru SCLK_OTG_PHY0>;
 807                         clock-names = "phyclk";
 808                         #clock-cells = <0>;
 809                         clock-output-names = "sclk_otgphy0_480m";
 810
 811                         u2phy_host: host-port {
 812                                 #phy-cells = <0>;
 813                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 814                                 interrupt-names = "linestate";
 815                                 status = "okay";
 816                         };
 817                 };
 818
 819                 pvtm: pvtm {
 820                         compatible = "rockchip,rk3366-pvtm";
 821                         clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>;
 822                         clock-names = "core", "gpu";
 823                         status = "disabled";
 824                 };
 825         };
 826
 827         wdt: watchdog@ff800000 {
 828                 compatible = "snps,dw-wdt";
 829                 reg = <0x0 0xff800000 0x0 0x100>;
 830                 clocks = <&cru PCLK_WDT>;
 831                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 832                 status = "disabled";
 833         };
 834
 835         spdif: spdif@ff880000 {
 836                 compatible = "rockchip,rk3366-spdif";
 837                 reg = <0x0 0xff880000 0x0 0x1000>;
 838                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 839                 dmas = <&dmac_bus 3>;
 840                 dma-names = "tx";
 841                 clock-names = "mclk", "hclk";
 842                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 843                 pinctrl-names = "default";
 844                 pinctrl-0 = <&spdif_bus>;
 845                 status = "disabled";
 846         };
 847
 848         i2s_2ch: i2s-2ch@ff890000 {
 849                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 850                 reg = <0x0 0xff890000 0x0 0x1000>;
 851                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 852                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 853                 dma-names = "tx", "rx";
 854                 clock-names = "i2s_clk", "i2s_hclk";
 855                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 856                 status = "disabled";
 857         };
 858
 859         i2s_8ch: i2s-8ch@ff898000 {
 860                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 861                 reg = <0x0 0xff898000 0x0 0x1000>;
 862                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 863                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 864                 dma-names = "tx", "rx";
 865                 clock-names = "i2s_clk", "i2s_hclk";
 866                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 867                 pinctrl-names = "default";
 868                 pinctrl-0 = <&i2s_8ch_bus>;
 869                 status = "disabled";
 870         };
 871
 872         fb: fb {
 873                 compatible = "rockchip,rk-fb";
 874                 rockchip,disp-mode = <DUAL>;
 875                 status = "disabled";
 876         };
 877
 878         rk_screen: screen {
 879                 compatible = "rockchip,screen";
 880                 status = "disabled";
 881         };
 882
 883         vop_lite: vop@ff8f0000 {
 884                 compatible = "rockchip,rk3366-lcdc-lite";
 885                 rockchip,grf = <&grf>;
 886                 rockchip,pwr18 = <0>;
 887                 rockchip,iommu-enabled = <1>;
 888                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 889                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 890                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 891                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 892                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 893                 reset-names = "axi", "ahb", "dclk";
 894                 status = "disabled";
 895         };
 896
 897         vopl_mmu: vopl-mmu {
 898                 dbgname = "vop";
 899                 compatible = "rockchip,vopl_mmu";
 900                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 901                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 902                 interrupt-names = "vopl_mmu";
 903                 status = "disabled";
 904         };
 905
 906         iep: iep@ff900000 {
 907                 compatible = "rockchip,iep";
 908                 iommu_enabled = <1>;
 909                 reg = <0x0 0xff900000 0x0 0x800>;
 910                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 911                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 912                 clock-names = "aclk_iep", "hclk_iep";
 913                 version = <2>;
 914                 status = "disabled";
 915         };
 916
 917         rga: rga@ff920000 {
 918                 compatible = "rockchip,rga2";
 919                 dev_mode = <1>;
 920                 reg = <0x0 0xff920000 0x0 0x1000>;
 921                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 922                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 923                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 924                 status = "disabled";
 925         };
 926
 927         vop_big: vop@ff930000 {
 928                 compatible = "rockchip,rk3366-lcdc-big";
 929                 rockchip,grf = <&grf>;
 930                 rockchip,prop = <PRMRY>;
 931                 rockchip,pwr18 = <0>;
 932                 rockchip,iommu-enabled = <1>;
 933                 reg = <0x0 0xff930000 0x0 0x23f0>;
 934                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 935                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 936                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 937                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 938                 reset-names = "axi", "ahb", "dclk";
 939                 status = "disabled";
 940         };
 941
 942         vopb_mmu: vopb-mmu {
 943                 dbgname = "vop";
 944                 compatible = "rockchip,vopb_mmu";
 945                 reg = <0x0 0xff932400 0x0 0x100>;
 946                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 947                 interrupt-names = "vop_mmu";
 948                 status = "disabled";
 949         };
 950
 951         iep_mmu: iep-mmu {
 952                 dbgname = "iep";
 953                 compatible = "rockchip,iep_mmu";
 954                 reg = <0x0 0xff900800 0x0 0x100>;
 955                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 956                 interrupt-names = "iep_mmu";
 957                 status = "disabled";
 958         };
 959
 960         vpu_mmu: vpu_mmu {
 961                 dbgname = "vpu";
 962                 compatible = "rockchip,vpu_mmu";
 963                 reg = <0x0 0xff9a0800 0x0 0x100>;
 964                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 965                 interrupt-names = "vpu_mmu";
 966                 status = "disabled";
 967         };
 968
 969         vdec_mmu: vdec_mmu {
 970                 dbgname = "vdec";
 971                 compatible = "rockchip,vdec_mmu";
 972                 reg = <0x0 0xff9b0480 0x0 0x40>,
 973                       <0x0 0xff9b04c0 0x0 0x40>;
 974                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 975                 interrupt-names = "vdec_mmu";
 976                 status = "disabled";
 977         };
 978
 979         dsihost0: mipi@ff960000 {
 980                 compatible = "rockchip,rk3366-dsi";
 981                 rockchip,prop = <0>;
 982                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 983                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 984                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 985                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 986                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 987                 status = "disabled";
 988         };
 989
 990         lvds: lvds@ff968000 {
 991                 compatible = "rockchip,rk3366-lvds";
 992                 rockchip,grf = <&grf>;
 993                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 994                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 995                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 996                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 997                 status = "disabled";
 998         };
 999
1000         hdmi: hdmi@ff980000 {
1001                 compatible = "rockchip,rk3366-hdmi";
1002                 reg = <0x0 0xff980000 0x0 0x20000>;
1003                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1004                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1005                 clocks = <&cru PCLK_HDMI_CTRL>,
1006                          <&cru SCLK_HDMI_HDCP>,
1007                          <&cru SCLK_HDMI_CEC>,
1008                          <&cru DCLK_HDMIPHY>;
1009                 clock-names = "pclk_hdmi",
1010                               "hdcp_clk_hdmi",
1011                               "cec_clk_hdmi",
1012                               "dclk_hdmi_phy";
1013                 resets = <&cru SRST_HDMI>;
1014                 reset-names = "hdmi";
1015                 pinctrl-names = "default", "gpio";
1016                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1017                 pinctrl-1 = <&i2c5_gpio>;
1018                 status = "disabled";
1019         };
1020
1021         vpu: vpu_service@ff9a0000 {
1022                 compatible = "rockchip,vpu_service";
1023                 rockchip,grf = <&grf>;
1024                 iommu_enabled = <1>;
1025                 reg = <0x0 0xff9a0000 0x0 0x800>;
1026                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1027                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1028                 interrupt-names = "irq_dec", "irq_enc";
1029                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1030                 clock-names = "aclk_vcodec", "hclk_vcodec";
1031                 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
1032                 reset-names = "video_h", "video_a";
1033                 name = "vpu_service";
1034                 dev_mode = <0>;
1035                 status = "disabled";
1036         };
1037
1038         rkvdec: rkvdec@ff9b0000 {
1039                 compatible = "rockchip,rkvdec";
1040                 rockchip,grf = <&grf>;
1041                 iommu_enabled = <1>;
1042                 reg = <0x0 0xff9b0000 0x0 0x400>;
1043                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1044                 interrupt-names = "irq_dec";
1045                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
1046                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
1047                 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
1048                 reset-names = "video_h", "video_a";
1049                 dev_mode = <2>;
1050                 name = "rkvdec";
1051                 status = "disabled";
1052         };
1053
1054         pinctrl: pinctrl {
1055                 compatible = "rockchip,rk3366-pinctrl";
1056                 rockchip,grf = <&grf>;
1057                 rockchip,pmu = <&pmugrf>;
1058                 #address-cells = <0x2>;
1059                 #size-cells = <0x2>;
1060                 ranges;
1061
1062                 gpio0: gpio0@ff750000 {
1063                         compatible = "rockchip,gpio-bank";
1064                         reg = <0x0 0xff750000 0x0 0x100>;
1065                         clocks = <&cru PCLK_GPIO0>;
1066                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1067
1068                         gpio-controller;
1069                         #gpio-cells = <0x2>;
1070
1071                         interrupt-controller;
1072                         #interrupt-cells = <0x2>;
1073                 };
1074
1075                 gpio1: gpio1@ff780000 {
1076                         compatible = "rockchip,gpio-bank";
1077                         reg = <0x0 0xff758000 0x0 0x100>;
1078                         clocks = <&cru PCLK_GPIO1>;
1079                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1080
1081                         gpio-controller;
1082                         #gpio-cells = <0x2>;
1083
1084                         interrupt-controller;
1085                         #interrupt-cells = <0x2>;
1086                 };
1087
1088                 gpio2: gpio2@ff790000 {
1089                         compatible = "rockchip,gpio-bank";
1090                         reg = <0x0 0xff790000 0x0 0x100>;
1091                         clocks = <&cru PCLK_GPIO2>;
1092                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1093
1094                         gpio-controller;
1095                         #gpio-cells = <0x2>;
1096
1097                         interrupt-controller;
1098                         #interrupt-cells = <0x2>;
1099                 };
1100
1101                 gpio3: gpio3@ff7a0000 {
1102                         compatible = "rockchip,gpio-bank";
1103                         reg = <0x0 0xff7a0000 0x0 0x100>;
1104                         clocks = <&cru PCLK_GPIO3>;
1105                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1106
1107                         gpio-controller;
1108                         #gpio-cells = <0x2>;
1109
1110                         interrupt-controller;
1111                         #interrupt-cells = <0x2>;
1112                 };
1113
1114                 gpio4: gpio4@ff7b0000 {
1115                         compatible = "rockchip,gpio-bank";
1116                         reg = <0x0 0xff7b0000 0x0 0x100>;
1117                         clocks = <&cru PCLK_GPIO4>;
1118                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1119
1120                         gpio-controller;
1121                         #gpio-cells = <0x2>;
1122
1123                         interrupt-controller;
1124                         #interrupt-cells = <0x2>;
1125                 };
1126
1127                 gpio5: gpio5@ff7c0000 {
1128                         compatible = "rockchip,gpio-bank";
1129                         reg = <0x0 0xff7c0000 0x0 0x100>;
1130                         clocks = <&cru PCLK_GPIO5>;
1131                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1132
1133                         gpio-controller;
1134                         #gpio-cells = <0x2>;
1135
1136                         interrupt-controller;
1137                         #interrupt-cells = <0x2>;
1138                 };
1139
1140                 pcfg_pull_up: pcfg-pull-up {
1141                         bias-pull-up;
1142                 };
1143
1144                 pcfg_pull_down: pcfg-pull-down {
1145                         bias-pull-down;
1146                 };
1147
1148                 pcfg_pull_none: pcfg-pull-none {
1149                         bias-disable;
1150                 };
1151
1152                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1153                         bias-disable;
1154                         drive-strength = <12>;
1155                 };
1156
1157                 emmc {
1158                         emmc_clk: emmc-clk {
1159                                 rockchip,pins =
1160                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
1161                         };
1162
1163                         emmc_cmd: emmc-cmd {
1164                                 rockchip,pins =
1165                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
1166                         };
1167
1168                         emmc_pwr: emmc-pwr {
1169                                 rockchip,pins =
1170                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
1171                         };
1172
1173                         emmc_bus1: emmc-bus1 {
1174                                 rockchip,pins =
1175                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
1176                         };
1177
1178                         emmc_bus4: emmc-bus4 {
1179                                 rockchip,pins =
1180                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1181                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1182                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1183                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1184                         };
1185
1186                         emmc_bus8: emmc-bus8 {
1187                                 rockchip,pins =
1188                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1189                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1190                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1191                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
1192                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
1193                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
1194                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
1195                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
1196                         };
1197                 };
1198
1199                 sdmmc {
1200                         sdmmc_cd: sdmmc-cd {
1201                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1202                         };
1203
1204                         sdmmc_bus1: sdmmc-bus1 {
1205                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1206                         };
1207
1208                         sdmmc_bus4: sdmmc-bus4 {
1209                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1210                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1211                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1212                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1213                         };
1214
1215                         sdmmc_clk: sdmmc-clk {
1216                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1217                         };
1218
1219                         sdmmc_cmd: sdmmc-cmd {
1220                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1221                         };
1222                 };
1223
1224                 sdio {
1225                         sdio_bus1: sdio-bus1 {
1226                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1227                         };
1228
1229                         sdio_bus4: sdio-bus4 {
1230                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1231                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1232                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1233                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1234                         };
1235
1236                         sdio_cmd: sdio-cmd {
1237                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1238                         };
1239
1240                         sdio_clk: sdio-clk {
1241                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1242                         };
1243
1244                         sdio_cd: sdio-cd {
1245                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1246                         };
1247
1248                         sdio_wp: sdio-wp {
1249                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1250                         };
1251
1252                         sdio_int: sdio-int {
1253                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1254                         };
1255
1256                         sdio_pwr: sdio-pwr {
1257                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1258                         };
1259                 };
1260
1261                 hdmi_i2c {
1262                         hdmii2c_xfer: hdmii2c-xfer {
1263                                 rockchip,pins =
1264                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1265                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1266                         };
1267                 };
1268
1269                 hdmi_pin {
1270                         hdmi_cec: hdmi-cec {
1271                                 rockchip,pins =
1272                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1273                         };
1274                 };
1275
1276                 i2c0 {
1277                         i2c0_xfer: i2c0-xfer {
1278                                 rockchip,pins =
1279                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1280                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1281                         };
1282                 };
1283
1284                 i2c1 {
1285                         i2c1_xfer: i2c1-xfer {
1286                                 rockchip,pins =
1287                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1288                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1289                         };
1290                 };
1291
1292                 i2c2 {
1293                         i2c2_xfer: i2c2-xfer {
1294                                 rockchip,pins =
1295                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1296                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1297                         };
1298
1299                         i2c2_gpio: i2c2-gpio {
1300                                 rockchip,pins =
1301                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1302                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1303                         };
1304                 };
1305
1306                 i2c3 {
1307                         i2c3_xfer: i2c3-xfer {
1308                                 rockchip,pins =
1309                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1310                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1311                         };
1312                 };
1313
1314                 i2c4 {
1315                         i2c4_xfer: i2c4-xfer {
1316                                 rockchip,pins =
1317                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1318                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1319                         };
1320
1321                         i2c4_gpio: i2c4-gpio {
1322                                 rockchip,pins =
1323                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1324                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1325                         };
1326                 };
1327
1328                 i2c5 {
1329                         i2c5_xfer: i2c5-xfer {
1330                                 rockchip,pins =
1331                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1332                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1333                         };
1334                         i2c5_gpio: i2c5-gpio {
1335                                 rockchip,pins =
1336                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1337                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1338                         };
1339                 };
1340
1341                 i2s {
1342                         i2s_8ch_bus: i2s-8ch-bus {
1343                                 rockchip,pins =
1344                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1345                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1346                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1347                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1348                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1349                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1350                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1351                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1352                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1353                         };
1354                 };
1355
1356                 spdif {
1357                         spdif_bus: spdif-bus {
1358                                 rockchip,pins =
1359                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1360                         };
1361                 };
1362
1363                 spi0 {
1364                         spi0_clk: spi0-clk {
1365                                 rockchip,pins =
1366                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1367                         };
1368                         spi0_cs0: spi0-cs0 {
1369                                 rockchip,pins =
1370                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1371                         };
1372                         spi0_cs1: spi0-cs1 {
1373                                 rockchip,pins =
1374                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1375                         };
1376                         spi0_tx: spi0-tx {
1377                                 rockchip,pins =
1378                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1379                         };
1380                         spi0_rx: spi0-rx {
1381                                 rockchip,pins =
1382                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1383                         };
1384                 };
1385
1386                 spi1 {
1387                         spi1_clk: spi1-clk {
1388                                 rockchip,pins =
1389                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1390                         };
1391                         spi1_cs0: spi1-cs0 {
1392                                 rockchip,pins =
1393                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1394                         };
1395                         spi1_tx: spi1-tx {
1396                                 rockchip,pins =
1397                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1398                         };
1399                         spi1_rx: spi1-rx {
1400                                 rockchip,pins =
1401                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1402                         };
1403                 };
1404
1405                 scr {
1406                         scr_clk: scr-clk {
1407                                 rockchip,pins =
1408                                         <5 8 RK_FUNC_2 &pcfg_pull_none>;
1409                         };
1410
1411                         scr_io: scr-io {
1412                                 rockchip,pins =
1413                                         <5 9 RK_FUNC_2 &pcfg_pull_up>;
1414                         };
1415
1416                         scr_rst: scr-rst {
1417                                 rockchip,pins =
1418                                         <5 10 RK_FUNC_1 &pcfg_pull_none>;
1419                         };
1420
1421                         scr_detect: scr-detect {
1422                                 rockchip,pins =
1423                                         <5 11 RK_FUNC_1 &pcfg_pull_none>;
1424                         };
1425                 };
1426
1427                 uart0 {
1428                         uart0_xfer: uart0-xfer {
1429                                 rockchip,pins =
1430                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1431                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1432                         };
1433
1434                         uart0_cts: uart0-cts {
1435                                 rockchip,pins =
1436                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1437                         };
1438
1439                         uart0_rts: uart0-rts {
1440                                 rockchip,pins =
1441                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1442                         };
1443                 };
1444
1445                 uart2_t0 {
1446                         uart2_t0_xfer: uart2_t0-xfer {
1447                                 rockchip,pins =
1448                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1449                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1450                         };
1451                         /* no rts / cts for uart2 */
1452                 };
1453
1454                 uart2_t1 {
1455                         uart2_t1_xfer: uart2_t1-xfer {
1456                                 rockchip,pins =
1457                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1458                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1459                         };
1460                         /* no rts / cts for uart2 */
1461                 };
1462
1463                 uart2_t2 {
1464                         uart2_t2_xfer: uart2_t2-xfer {
1465                                 rockchip,pins =
1466                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1467                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1468                         };
1469                         /* no rts / cts for uart2 */
1470                 };
1471
1472                 uart3 {
1473                         uart3_xfer: uart3-xfer {
1474                                 rockchip,pins =
1475                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1476                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1477                         };
1478
1479                         uart3_cts: uart3-cts {
1480                                 rockchip,pins =
1481                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1482                         };
1483
1484                         uart3_rts: uart3-rts {
1485                                 rockchip,pins =
1486                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1487                         };
1488                 };
1489
1490                 pwm0 {
1491                         pwm0_pin: pwm0-pin {
1492                                 rockchip,pins =
1493                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1494                         };
1495                 };
1496
1497                 pwm1 {
1498                         pwm1_pin: pwm1-pin {
1499                                 rockchip,pins =
1500                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1501                         };
1502                 };
1503
1504                 pwm2_t0 {
1505                         pwm2_t0_pin: pwm2_t0-pin {
1506                                 rockchip,pins =
1507                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1508                         };
1509                 };
1510
1511                 pwm2_t1 {
1512                         pwm2_t1_pin: pwm2_t1-pin {
1513                                 rockchip,pins =
1514                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1515                         };
1516                 };
1517
1518                 pwm3_t0 {
1519                         pwm3_t0_pin: pwm3_t0-pin {
1520                                 rockchip,pins =
1521                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1522                         };
1523                 };
1524
1525                 pwm3_t1 {
1526                         pwm3_t1_pin: pwm3_t1-pin {
1527                                 rockchip,pins =
1528                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1529                         };
1530                 };
1531
1532                 pwm3_t2 {
1533                         pwm3_t2_pin: pwm3_t2-pin {
1534                                 rockchip,pins =
1535                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1536                         };
1537                 };
1538
1539                 lcdc {
1540                         lcdc_lcdc: lcdc-lcdc {
1541                                 rockchip,pins =
1542                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1543                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1544                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1545                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1546                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1547                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1548                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1549                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1550                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1551                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1552                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1553                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1554                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1555                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1556                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1557                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1558                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1559                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1560                         };
1561
1562                         lcdc_gpio: lcdc-gpio {
1563                                 rockchip,pins =
1564                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1565                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1566                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1567                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1568                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1569                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1570                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1571                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1572                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1573                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1574                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1575                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1576                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1577                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1578                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1579                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1580                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1581                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1582                         };
1583                 };
1584
1585                 gmac {
1586                         rgmii_pins: rgmii-pins {
1587                                 rockchip,pins =
1588                                         /* mac_rxd3 */
1589                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1590                                         /* mac_rxd2 */
1591                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1592                                         /* mac_txd3 */
1593                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1594                                         /* mac_txd2 */
1595                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1596                                         /* mac_rxd1 */
1597                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1598                                         /* mac_rxd0 */
1599                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1600                                         /* mac_txd1 */
1601                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1602                                         /* mac_txd0 */
1603                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1604                                         /* mac_txclkout */
1605                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1606                                         /* mac_crs */
1607                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1608                                         /* mac_rxclkin */
1609                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1610                                         /* mac_mdio */
1611                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1612                                         /* mac_txen */
1613                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1614                                         /* mac_clk */
1615                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1616                                         /* mac_rxer */
1617                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1618                                         /* mac_rxdv */
1619                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1620                                         /* mac_mdc */
1621                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1622                         };
1623
1624                         rmii_pins: rmii-pins {
1625                                 rockchip,pins =
1626                                         /* mac_rxd1 */
1627                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1628                                         /* mac_rxd0 */
1629                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1630                                         /* mac_txd1 */
1631                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1632                                         /* mac_txd0 */
1633                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1634                                         /* mac_crs */
1635                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1636                                         /* mac_rxclkin */
1637                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1638                                         /* mac_mdio */
1639                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1640                                         /* mac_txen */
1641                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1642                                         /* mac_clk */
1643                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1644                                         /* mac_rxer */
1645                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1646                                         /* mac_rxdv */
1647                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1648                                         /* mac_mdc */
1649                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1650                         };
1651                 };
1652
1653                 eth_phy {
1654                         eth_phy_pwr: eth-phy-pwr {
1655                                 rockchip,pins =
1656                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1657                         };
1658                 };
1659
1660                 tsadc_pin {
1661                         tsadc_gpio: tsadc-gpio {
1662                                 rockchip,pins =
1663                                         <0 22 RK_FUNC_GPIO &pcfg_pull_none>;
1664                         };
1665
1666                         tsadc_int: tsadc-int {
1667                                 rockchip,pins =
1668                                         <0 22 RK_FUNC_2 &pcfg_pull_none>;
1669                         };
1670                 };
1671
1672                 usb2 {
1673                         host_vbus_drv: host-vbus-drv {
1674                                 rockchip,pins =
1675                                         <0 16 RK_FUNC_GPIO &pcfg_pull_none>;
1676                         };
1677                 };
1678
1679         };
1680
1681         gpu: gpu@ffa30000 {
1682                 compatible = "arm,malit764",
1683                              "arm,malit76x",
1684                              "arm,malit7xx",
1685                              "arm,mali-midgard";
1686
1687                 reg = <0x0 0xffa30000 0 0x10000>;
1688
1689                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1690                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1691                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1692                 interrupt-names = "GPU", "MMU", "JOB";
1693
1694                 clocks = <&cru ACLK_GPU>;
1695                 clock-names = "clk_mali";
1696                 #cooling-cells = <2>; /* min followed by max */
1697                 operating-points-v2 = <&gpu_opp_table>;
1698                 status = "disabled";
1699
1700                 power_model {
1701                         compatible = "arm,mali-simple-power-model";
1702                         voltage = <900>;
1703                         frequency = <500>;
1704                         static-power = <300>;
1705                         dynamic-power = <1780>;
1706                         ts = <32000 4700 (-80) 2>;
1707                         thermal-zone = "gpu-thermal";
1708                 };
1709         };
1710
1711         gpu_opp_table: gpu_opp_table {
1712                 compatible = "operating-points-v2";
1713                 opp-shared;
1714
1715                 opp@96000000 {
1716                         opp-hz = /bits/ 64 <96000000>;
1717                         opp-microvolt = <1100000>;
1718                 };
1719                 opp@192000000 {
1720                         opp-hz = /bits/ 64 <192000000>;
1721                         opp-microvolt = <1100000>;
1722                 };
1723                 opp@288000000 {
1724                         opp-hz = /bits/ 64 <288000000>;
1725                         opp-microvolt = <1100000>;
1726                 };
1727                 opp@375000000 {
1728                         opp-hz = /bits/ 64 <375000000>;
1729                         opp-microvolt = <1125000>;
1730                 };
1731                 opp@480000000 {
1732                         opp-hz = /bits/ 64 <480000000>;
1733                         opp-microvolt = <1200000>;
1734                 };
1735         };
1736 };