arch/arm64/boot/dts/rockchip/rk3366-fpga.dts

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /dts-v1/;
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/display/rk_fb.h>
  47
  48 / {
  49         model = "rockchip,rk3366-fpga";
  50         compatible = "rockchip,rk3366";
  51
  52         interrupt-parent = <&gic>;
  53         #address-cells = <2>;
  54         #size-cells = <2>;
  55
  56         aliases {
  57                 serial2 = &uart2;
  58         };
  59
  60         chosen {
  61                 bootargs = "console=uart,mmio32,0xff690000 initrd=0x01FFFFF8,0x00800000";
  62         };
  63
  64         cpus {
  65                 #address-cells = <2>;
  66                 #size-cells = <0>;
  67
  68                 cpu0: cpu@0 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a53","arm,armv8";
  71                         reg = <0x0 0x0>;
  72                         enable-method = "psci";
  73                 };
  74
  75                 cpu1: cpu@1 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a53","arm,armv8";
  78                         reg = <0x0 0x1>;
  79                         enable-method = "psci";
  80                 };
  81
  82                 cpu2: cpu@2 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53","arm,armv8";
  85                         reg = <0x0 0x2>;
  86                         enable-method = "psci";
  87                 };
  88
  89                 cpu3: cpu@3 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a53","arm,armv8";
  92                         reg = <0x0 0x3>;
  93                         enable-method = "psci";
  94                 };
  95         };
  96
  97         psci {
  98                 compatible = "arm,psci";
  99                 method = "smc";
 100         };
 101
 102         memory@00000000 {
 103                 device_type = "memory";
 104                 reg = <0x0 0x00000000 0x0 0x20000000>;
 105         };
 106
 107         timer {
 108                 compatible = "arm,armv8-timer";
 109                 interrupts = <
 110                                 GIC_PPI 13
 111                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 112                                 <GIC_PPI 14
 113                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 114                                 <GIC_PPI 11
 115                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 116                                 <GIC_PPI 10
 117                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 118                 clock-frequency = <24000000>;
 119         };
 120
 121         xin24m: xin24m {
 122                 compatible = "fixed-clock";
 123                 #clock-cells = <0>;
 124                 clock-frequency = <24000000>;
 125                 clock-output-names = "xin24m";
 126         };
 127
 128         uart2: serial@ff690000 {
 129                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 130                 reg = <0x0 0xff690000 0x0 0x100>;
 131                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 132                 clocks = <&xin24m>, <&xin24m>;
 133                 clock-names = "baudclk", "apb_pclk";
 134                 reg-shift = <2>;
 135                 reg-io-width = <4>;
 136         };
 137
 138         ion {
 139                 compatible = "rockchip,ion";
 140                 #address-cells = <1>;
 141                 #size-cells = <0>;
 142
 143                 cma-heap {
 144                         reg = <0x00000000 0x01000000>;
 145                 };
 146
 147                 system-heap {
 148                 };
 149         };
 150
 151         grf: syscon@ff770000 {
 152                 compatible = "rockchip,rk3368-grf", "syscon";
 153                 reg = <0x0 0xff770000 0x0 0x1000>;
 154         };
 155
 156         fb: fb {
 157                 compatible = "rockchip,rk-fb";
 158                 rockchip,disp-mode = <NO_DUAL>;
 159                 status = "disabled";
 160         };
 161
 162         rk_screen: screen {
 163                 compatible = "rockchip,screen";
 164                 status = "disabled";
 165                 #include <dt-bindings/display/screen-timing/lcd-fpga-800x480-rgb.dtsi>
 166         };
 167
 168         lvds: lvds@ff968000 {
 169                 compatible = "rockchip,rk3366-lvds";
 170                 rockchip,grf = <&grf>;
 171                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 172                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 173                 /* clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 174                  * clock-names = "pclk_lvds", "pclk_lvds_ctl";
 175                  */
 176                 status = "disabled";
 177         };
 178
 179         vop_lite: vop@ff8f0000 {
 180                 compatible = "rockchip,rk3366-lcdc-lite";
 181                 rockchip,grf = <&grf>;
 182                 rockchip,prop = <EXTEND>;
 183                 rockchip,pwr18 = <0>;
 184                 rockchip,iommu-enabled = <1>;
 185                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 186                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 187                 /* clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 188                  * clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 189                  * resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 190                  * reset-names = "axi", "ahb", "dclk";
 191                  */
 192                 status = "disabled";
 193         };
 194
 195         vopl_mmu: vopl-mmu {
 196                 dbgname = "vop";
 197                 compatible = "rockchip,vopl_mmu";
 198                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 199                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 200                 interrupt-names = "vopl_mmu";
 201                 status = "disabled";
 202         };
 203
 204         vop_big: vop@ff930000 {
 205                 compatible = "rockchip,rk3366-lcdc-big";
 206                 rockchip,grf = <&grf>;
 207                 rockchip,prop = <PRMRY>;
 208                 rockchip,pwr18 = <0>;
 209                 rockchip,iommu-enabled = <1>;
 210                 reg = <0x0 0xff930000 0x0 0x23f0>;
 211                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 212                 /* clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 213                  * clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 214                  * resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 215                  * reset-names = "axi", "ahb", "dclk";
 216                  */
 217                 status = "disabled";
 218         };
 219
 220         vopb_mmu: vopb-mmu {
 221                 dbgname = "vop";
 222                 compatible = "rockchip,vopb_mmu";
 223                 reg = <0x0 0xff932400 0x0 0x100>;
 224                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 225                 interrupt-names = "vop_mmu";
 226                 status = "disabled";
 227         };
 228
 229         gic: interrupt-controller@ffb70000 {
 230                 compatible = "arm,gic-400";
 231                 #interrupt-cells = <3>;
 232                 #address-cells = <0>;
 233                 interrupt-controller;
 234                 reg = <0x0 0xffb71000 0x0 0x1000>,
 235                       <0x0 0xffb72000 0x0 0x1000>;
 236         };
 237 };