arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50
  51 / {
  52         compatible = "rockchip,rk3328";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 serial0 = &uart0;
  60                 serial1 = &uart1;
  61                 serial2 = &uart2;
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66         };
  67
  68         cpus {
  69                 #address-cells = <2>;
  70                 #size-cells = <0>;
  71
  72                 cpu0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x0>;
  76                         enable-method = "psci";
  77 //                      clocks = <&cru ARMCLK>;
  78                         operating-points-v2 = <&cpu0_opp_table>;
  79                 };
  80                 cpu1: cpu@1 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53", "arm,armv8";
  83                         reg = <0x0 0x1>;
  84                         enable-method = "psci";
  85                 };
  86                 cpu2: cpu@2 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x2>;
  90                         enable-method = "psci";
  91                 };
  92                 cpu3: cpu@3 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a53", "arm,armv8";
  95                         reg = <0x0 0x3>;
  96                         enable-method = "psci";
  97                 };
  98         };
  99
 100         cpu0_opp_table: opp_table0 {
 101                 compatible = "operating-points-v2";
 102                 opp-shared;
 103
 104                 opp@408000000 {
 105                         opp-hz = /bits/ 64 <408000000>;
 106                         opp-microvolt = <950000>;
 107                         clock-latency-ns = <40000>;
 108                         opp-suspend;
 109                 };
 110                 opp@600000000 {
 111                         opp-hz = /bits/ 64 <600000000>;
 112                         opp-microvolt = <950000>;
 113                         clock-latency-ns = <40000>;
 114                 };
 115                 opp@816000000 {
 116                         opp-hz = /bits/ 64 <816000000>;
 117                         opp-microvolt = <1000000>;
 118                         clock-latency-ns = <40000>;
 119                 };
 120                 opp@1008000000 {
 121                         opp-hz = /bits/ 64 <1008000000>;
 122                         opp-microvolt = <1100000>;
 123                         clock-latency-ns = <40000>;
 124                 };
 125                 opp@1200000000 {
 126                         opp-hz = /bits/ 64 <1200000000>;
 127                         opp-microvolt = <1225000>;
 128                         clock-latency-ns = <40000>;
 129                 };
 130                 opp@1296000000 {
 131                         opp-hz = /bits/ 64 <1296000000>;
 132                         opp-microvolt = <1300000>;
 133                         clock-latency-ns = <40000>;
 134                 };
 135         };
 136
 137         arm-pmu {
 138                 compatible = "arm,cortex-a53-pmu";
 139                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 141                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 142                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 143                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 144         };
 145
 146         psci {
 147                 compatible = "arm,psci-1.0";
 148                 method = "smc";
 149         };
 150
 151         timer {
 152                 compatible = "arm,armv8-timer";
 153                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 154                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 155                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 156                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 157         };
 158
 159         xin24m: xin24m {
 160                 compatible = "fixed-clock";
 161                 #clock-cells = <0>;
 162                 clock-frequency = <24000000>;
 163                 clock-output-names = "xin24m";
 164         };
 165
 166         i2s0: i2s@ff000000 {
 167                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 168                 reg = <0x0 0xff000000 0x0 0x1000>;
 169                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 170                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 171                 clock-names = "i2s_clk", "i2s_hclk";
 172                 dmas = <&dmac 11>, <&dmac 12>;
 173                 #dma-cells = <2>;
 174                 dma-names = "tx", "rx";
 175                 status = "disabled";
 176         };
 177
 178         i2s1: i2s@ff010000 {
 179                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 180                 reg = <0x0 0xff010000 0x0 0x1000>;
 181                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 182                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 183                 clock-names = "i2s_clk", "i2s_hclk";
 184                 dmas = <&dmac 14>, <&dmac 15>;
 185                 #dma-cells = <2>;
 186                 dma-names = "tx", "rx";
 187                 status = "disabled";
 188         };
 189
 190         i2s2: i2s@ff020000 {
 191                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 192                 reg = <0x0 0xff020000 0x0 0x1000>;
 193                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 194                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 195                 clock-names = "i2s_clk", "i2s_hclk";
 196                 dmas = <&dmac 0>, <&dmac 1>;
 197                 #dma-cells = <2>;
 198                 dma-names = "tx", "rx";
 199                 pinctrl-names = "default", "sleep";
 200                 pinctrl-0 = <&i2s2m0_mclk
 201                              &i2s2m0_sclk
 202                              &i2s2m0_lrcktx
 203                              &i2s2m0_lrckrx
 204                              &i2s2m0_sdo
 205                              &i2s2m0_sdi>;
 206                 pinctrl-1 = <&i2s2m0_sleep>;
 207                 status = "disabled";
 208         };
 209
 210         spdif: spdif@ff030000 {
 211                 compatible = "rockchip,rk3328-spdif";
 212                 reg = <0x0 0xff030000 0x0 0x1000>;
 213                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 215                 clock-names = "mclk", "hclk";
 216                 dmas = <&dmac 10>;
 217                 #dma-cells = <1>;
 218                 dma-names = "tx";
 219                 pinctrl-names = "default";
 220                 pinctrl-0 = <&spdifm2_tx>;
 221                 status = "disabled";
 222         };
 223
 224         grf: syscon@ff100000 {
 225                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 226                 reg = <0x0 0xff100000 0x0 0x1000>;
 227                 #address-cells = <1>;
 228                 #size-cells = <1>;
 229
 230                 io_domains: io-domains {
 231                         compatible = "rockchip,rk3328-io-voltage-domain";
 232                         status = "disabled";
 233                 };
 234
 235                 power: power-controller {
 236                         compatible = "rockchip,rk3328-power-controller";
 237                         #power-domain-cells = <1>;
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         status = "disabled";
 241
 242                         pd_hevc@RK3328_PD_HEVC {
 243                                 reg = <RK3328_PD_HEVC>;
 244                         };
 245                         pd_video@RK3328_PD_VIDEO {
 246                                 reg = <RK3328_PD_VIDEO>;
 247                         };
 248                         pd_vpu@RK3328_PD_VPU {
 249                                 reg = <RK3328_PD_VPU>;
 250                         };
 251                 };
 252
 253                 reboot-mode {
 254                         compatible = "syscon-reboot-mode";
 255                         offset = <0x5c8>;
 256                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 257                         mode-charge = <BOOT_CHARGING>;
 258                         mode-fastboot = <BOOT_FASTBOOT>;
 259                         mode-loader = <BOOT_BL_DOWNLOAD>;
 260                         mode-normal = <BOOT_NORMAL>;
 261                         mode-recovery = <BOOT_RECOVERY>;
 262                         mode-ums = <BOOT_UMS>;
 263                 };
 264         };
 265
 266         uart0: serial@ff110000 {
 267                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 268                 reg = <0x0 0xff110000 0x0 0x100>;
 269                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 271                 clock-names = "baudclk", "apb_pclk";
 272                 reg-shift = <2>;
 273                 reg-io-width = <4>;
 274                 dmas = <&dmac 2>, <&dmac 3>;
 275                 #dma-cells = <2>;
 276                 pinctrl-names = "default";
 277                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 278                 status = "disabled";
 279         };
 280
 281         uart1: serial@ff120000 {
 282                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 283                 reg = <0x0 0xff120000 0x0 0x100>;
 284                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 285                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 286                 clock-names = "sclk_uart", "pclk_uart";
 287                 reg-shift = <2>;
 288                 reg-io-width = <4>;
 289                 dmas = <&dmac 4>, <&dmac 5>;
 290                 #dma-cells = <2>;
 291                 pinctrl-names = "default";
 292                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 293                 status = "disabled";
 294         };
 295
 296         uart2: serial@ff130000 {
 297                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 298                 reg = <0x0 0xff130000 0x0 0x100>;
 299                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 300                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 301                 clock-names = "baudclk", "apb_pclk";
 302                 reg-shift = <2>;
 303                 reg-io-width = <4>;
 304                 dmas = <&dmac 6>, <&dmac 7>;
 305                 #dma-cells = <2>;
 306                 pinctrl-names = "default";
 307                 pinctrl-0 = <&uart2m1_xfer>;
 308                 status = "disabled";
 309         };
 310
 311         pmu: power-management@ff140000 {
 312                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 313                 reg = <0x0 0xff140000 0x0 0x1000>;
 314         };
 315
 316         i2c0: i2c@ff150000 {
 317                 compatible = "rockchip,rk3328-i2c";
 318                 reg = <0x0 0xff150000 0x0 0x1000>;
 319                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 320                 #address-cells = <1>;
 321                 #size-cells = <0>;
 322                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 323                 clock-names = "i2c", "pclk";
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&i2c0_xfer>;
 326                 status = "disabled";
 327         };
 328
 329         i2c1: i2c@ff160000 {
 330                 compatible = "rockchip,rk3328-i2c";
 331                 reg = <0x0 0xff160000 0x0 0x1000>;
 332                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 336                 clock-names = "i2c", "pclk";
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&i2c1_xfer>;
 339                 status = "disabled";
 340         };
 341
 342         i2c2: i2c@ff170000 {
 343                 compatible = "rockchip,rk3328-i2c";
 344                 reg = <0x0 0xff170000 0x0 0x1000>;
 345                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 349                 clock-names = "i2c", "pclk";
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&i2c2_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         i2c3: i2c@ff180000 {
 356                 compatible = "rockchip,rk3328-i2c";
 357                 reg = <0x0 0xff180000 0x0 0x1000>;
 358                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 362                 clock-names = "i2c", "pclk";
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&i2c3_xfer>;
 365                 status = "disabled";
 366         };
 367
 368         spi0: spi@ff190000 {
 369                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 370                 reg = <0x0 0xff190000 0x0 0x1000>;
 371                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 375                 clock-names = "spiclk", "apb_pclk";
 376                 dmas = <&dmac 8>, <&dmac 9>;
 377                 #dma-cells = <2>;
 378                 dma-names = "tx", "rx";
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 381                 status = "disabled";
 382         };
 383
 384         wdt: watchdog@ff1a0000 {
 385                 compatible = "snps,dw-wdt";
 386                 reg = <0x0 0xff1a0000 0x0 0x100>;
 387                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 388                 status = "disabled";
 389         };
 390
 391         amba {
 392                 compatible = "simple-bus";
 393                 #address-cells = <2>;
 394                 #size-cells = <2>;
 395                 ranges;
 396
 397                 dmac: dmac@ff1f0000 {
 398                         compatible = "arm,pl330", "arm,primecell";
 399                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 400                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 401                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 402                         clocks = <&cru ACLK_DMAC>;
 403                         clock-names = "apb_pclk";
 404                         #dma-cells = <1>;
 405                 };
 406         };
 407
 408         saradc: saradc@ff280000 {
 409                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 410                 reg = <0x0 0xff280000 0x0 0x100>;
 411                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 412                 #io-channel-cells = <1>;
 413                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 414                 clock-names = "saradc", "apb_pclk";
 415                 resets = <&cru SRST_SARADC_P>;
 416                 reset-names = "saradc-apb";
 417                 status = "disabled";
 418         };
 419
 420         cru: clock-controller@ff440000 {
 421                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 422                 reg = <0x0 0xff440000 0x0 0x1000>;
 423                 rockchip,grf = <&grf>;
 424                 #clock-cells = <1>;
 425                 #reset-cells = <1>;
 426                 assigned-clocks =
 427                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 428                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 429                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 430                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 431                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 432                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 433                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 434                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 435                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 436                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 437                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 438                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 439                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 440                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 441                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 442                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 443                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 444                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 445                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 446                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 447                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 448                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 449                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 450                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 451                 assigned-clock-parents =
 452                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 453                         <&cru PLL_GPLL>, <&xin24m>,
 454                         <&xin24m>, <&xin24m>;
 455                 assigned-clock-rates =
 456                         <0>, <61440000>,
 457                         <0>, <24000000>,
 458                         <24000000>, <24000000>,
 459                         <15000000>, <15000000>,
 460                         <100000000>, <100000000>,
 461                         <100000000>, <100000000>,
 462                         <50000000>, <100000000>,
 463                         <100000000>, <100000000>,
 464                         <50000000>, <50000000>,
 465                         <50000000>, <50000000>,
 466                         <24000000>, <600000000>,
 467                         <491520000>, <1200000000>,
 468                         <150000000>, <75000000>,
 469                         <75000000>, <150000000>,
 470                         <75000000>, <75000000>,
 471                         <300000000>, <100000000>,
 472                         <300000000>, <200000000>,
 473                         <400000000>, <500000000>,
 474                         <200000000>, <300000000>,
 475                         <300000000>, <250000000>,
 476                         <200000000>, <100000000>,
 477                         <24000000>, <100000000>,
 478                         <150000000>, <50000000>,
 479                         <32768>, <32768>;
 480         };
 481
 482         usb2phy_grf: syscon@ff450000 {
 483                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 484                              "simple-mfd";
 485                 reg = <0x0 0xff450000 0x0 0x10000>;
 486                 #address-cells = <1>;
 487                 #size-cells = <1>;
 488
 489                 u2phy: usb2-phy@100 {
 490                         compatible = "rockchip,rk3328-usb2phy";
 491                         reg = <0x100 0x10>;
 492                         clocks = <&xin24m>;
 493                         clock-names = "phyclk";
 494                         #clock-cells = <0>;
 495                         assigned-clocks = <&cru USB480M>;
 496                         assigned-clock-parents = <&u2phy>;
 497                         clock-output-names = "usb480m_phy";
 498                         status = "disabled";
 499
 500                         u2phy_host: host-port {
 501                                 #phy-cells = <0>;
 502                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 503                                 interrupt-names = "linestate";
 504                                 status = "disabled";
 505                         };
 506                 };
 507         };
 508
 509         sdmmc: rksdmmc@ff500000 {
 510                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 511                 reg = <0x0 0xff500000 0x0 0x4000>;
 512                 clock-freq-min-max = <400000 150000000>;
 513                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 514                 clock-names = "biu", "ciu";
 515                 fifo-depth = <0x100>;
 516                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 517                 status = "disabled";
 518         };
 519
 520         sdio: dwmmc@ff510000 {
 521                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 522                 reg = <0x0 0xff510000 0x0 0x4000>;
 523                 clock-freq-min-max = <400000 150000000>;
 524                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 525                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 526                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 527                 fifo-depth = <0x100>;
 528                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 529                 status = "disabled";
 530         };
 531
 532         emmc: rksdmmc@ff520000 {
 533                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 534                 reg = <0x0 0xff520000 0x0 0x4000>;
 535                 clock-freq-min-max = <400000 150000000>;
 536                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 537                 clock-names = "biu", "ciu";
 538                 fifo-depth = <0x100>;
 539                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 540                 status = "disabled";
 541         };
 542
 543         usb20_otg: usb@ff580000 {
 544                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 545                              "snps,dwc2";
 546                 reg = <0x0 0xff580000 0x0 0x40000>;
 547                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 548                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 549                 clock-names = "otg", "otg_pmu";
 550                 dr_mode = "otg";
 551                 g-np-tx-fifo-size = <16>;
 552                 g-rx-fifo-size = <275>;
 553                 g-tx-fifo-size = <256 128 128 64 64 32>;
 554                 g-use-dma;
 555                 status = "disabled";
 556         };
 557
 558         usb_host0_ehci: usb@ff5c0000 {
 559                 compatible = "generic-ehci";
 560                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 561                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 562                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 563                          <&u2phy>;
 564                 clock-names = "usbhost", "arbiter", "utmi";
 565                 phys = <&u2phy_host>;
 566                 phy-names = "usb";
 567                 status = "disabled";
 568         };
 569
 570         usb_host0_ohci: usb@ff5d0000 {
 571                 compatible = "generic-ohci";
 572                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 573                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 574                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 575                          <&u2phy>;
 576                 clock-names = "usbhost", "arbiter", "utmi";
 577                 phys = <&u2phy_host>;
 578                 phy-names = "usb";
 579                 status = "disabled";
 580         };
 581
 582         sdmmc_ext: rksdmmc@ff5f0000 {
 583                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 584                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 585                 clock-freq-min-max = <400000 150000000>;
 586                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 587                 clock-names = "biu", "ciu";
 588                 fifo-depth = <0x100>;
 589                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 590                 status = "disabled";
 591         };
 592
 593         gic: interrupt-controller@ff811000 {
 594                 compatible = "arm,gic-400";
 595                 #interrupt-cells = <3>;
 596                 #address-cells = <0>;
 597                 interrupt-controller;
 598                 reg = <0x0 0xff811000 0 0x1000>,
 599                       <0x0 0xff812000 0 0x2000>,
 600                       <0x0 0xff814000 0 0x2000>,
 601                       <0x0 0xff816000 0 0x2000>;
 602                 interrupts = <GIC_PPI 9
 603                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 604         };
 605
 606         pinctrl: pinctrl {
 607                 compatible = "rockchip,rk3328-pinctrl";
 608                 rockchip,grf = <&grf>;
 609                 #address-cells = <2>;
 610                 #size-cells = <2>;
 611                 ranges;
 612
 613                 gpio0: gpio0@ff210000 {
 614                         compatible = "rockchip,gpio-bank";
 615                         reg = <0x0 0xff210000 0x0 0x100>;
 616                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 617                         clocks = <&cru PCLK_GPIO0>;
 618
 619                         gpio-controller;
 620                         #gpio-cells = <2>;
 621
 622                         interrupt-controller;
 623                         #interrupt-cells = <2>;
 624                 };
 625
 626                 gpio1: gpio1@ff220000 {
 627                         compatible = "rockchip,gpio-bank";
 628                         reg = <0x0 0xff220000 0x0 0x100>;
 629                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 630                         clocks = <&cru PCLK_GPIO1>;
 631
 632                         gpio-controller;
 633                         #gpio-cells = <2>;
 634
 635                         interrupt-controller;
 636                         #interrupt-cells = <2>;
 637                 };
 638
 639                 gpio2: gpio2@ff230000 {
 640                         compatible = "rockchip,gpio-bank";
 641                         reg = <0x0 0xff230000 0x0 0x100>;
 642                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 643                         clocks = <&cru PCLK_GPIO2>;
 644
 645                         gpio-controller;
 646                         #gpio-cells = <2>;
 647
 648                         interrupt-controller;
 649                         #interrupt-cells = <2>;
 650                 };
 651
 652                 gpio3: gpio3@ff240000 {
 653                         compatible = "rockchip,gpio-bank";
 654                         reg = <0x0 0xff240000 0x0 0x100>;
 655                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 656                         clocks = <&cru PCLK_GPIO3>;
 657
 658                         gpio-controller;
 659                         #gpio-cells = <2>;
 660
 661                         interrupt-controller;
 662                         #interrupt-cells = <2>;
 663                 };
 664
 665                 pcfg_pull_up: pcfg-pull-up {
 666                         bias-pull-up;
 667                 };
 668
 669                 pcfg_pull_down: pcfg-pull-down {
 670                         bias-pull-down;
 671                 };
 672
 673                 pcfg_pull_none: pcfg-pull-none {
 674                         bias-disable;
 675                 };
 676
 677                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 678                         bias-disable;
 679                         drive-strength = <2>;
 680                 };
 681
 682                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 683                         bias-pull-up;
 684                         drive-strength = <2>;
 685                 };
 686
 687                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 688                         bias-pull-up;
 689                         drive-strength = <4>;
 690                 };
 691
 692                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 693                         bias-disable;
 694                         drive-strength = <4>;
 695                 };
 696
 697                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 698                         bias-pull-down;
 699                         drive-strength = <4>;
 700                 };
 701
 702                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 703                         bias-disable;
 704                         drive-strength = <8>;
 705                 };
 706
 707                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 708                         bias-pull-up;
 709                         drive-strength = <8>;
 710                 };
 711
 712                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 713                         bias-disable;
 714                         drive-strength = <12>;
 715                 };
 716
 717                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 718                         bias-pull-up;
 719                         drive-strength = <12>;
 720                 };
 721
 722                 pcfg_output_high: pcfg-output-high {
 723                         output-high;
 724                 };
 725
 726                 pcfg_output_low: pcfg-output-low {
 727                         output-low;
 728                 };
 729
 730                 pcfg_input_high: pcfg-input-high {
 731                         bias-pull-up;
 732                         input-enable;
 733                 };
 734
 735                 pcfg_input: pcfg-input {
 736                         input-enable;
 737                 };
 738
 739                 i2c0 {
 740                         i2c0_xfer: i2c0-xfer {
 741                                 rockchip,pins =
 742                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 743                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 744                         };
 745                 };
 746
 747                 i2c1 {
 748                         i2c1_xfer: i2c1-xfer {
 749                                 rockchip,pins =
 750                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 751                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 752                         };
 753                 };
 754
 755                 i2c2 {
 756                         i2c2_xfer: i2c2-xfer {
 757                                 rockchip,pins =
 758                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 759                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 760                         };
 761                 };
 762
 763                 i2c3 {
 764                         i2c3_xfer: i2c3-xfer {
 765                                 rockchip,pins =
 766                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 767                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 768                         };
 769                         i2c3_gpio: i2c3-gpio {
 770                                 rockchip,pins =
 771                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 772                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 773                         };
 774                 };
 775
 776                 hdmi_i2c {
 777                         hdmii2c_xfer: hdmii2c-xfer {
 778                                 rockchip,pins =
 779                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 780                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 781                         };
 782                 };
 783
 784                 uart0 {
 785                         uart0_xfer: uart0-xfer {
 786                                 rockchip,pins =
 787                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 788                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 789                         };
 790
 791                         uart0_cts: uart0-cts {
 792                                 rockchip,pins =
 793                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 794                         };
 795
 796                         uart0_rts: uart0-rts {
 797                                 rockchip,pins =
 798                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 799                         };
 800
 801                         uart0_rts_gpio: uart0-rts-gpio {
 802                                 rockchip,pins =
 803                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 804                         };
 805                 };
 806
 807                 uart1 {
 808                         uart1_xfer: uart1-xfer {
 809                                 rockchip,pins =
 810                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 811                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 812                         };
 813
 814                         uart1_cts: uart1-cts {
 815                                 rockchip,pins =
 816                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 817                         };
 818
 819                         uart1_rts: uart1-rts {
 820                                 rockchip,pins =
 821                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 822                         };
 823
 824                         uart1_rts_gpio: uart1-rts-gpio {
 825                                 rockchip,pins =
 826                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 827                         };
 828                 };
 829
 830                 uart2-0 {
 831                         uart2m0_xfer: uart2m0-xfer {
 832                                 rockchip,pins =
 833                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 834                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 835                         };
 836                 };
 837
 838                 uart2-1 {
 839                         uart2m1_xfer: uart2m1-xfer {
 840                                 rockchip,pins =
 841                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 842                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 843                         };
 844                 };
 845
 846                 spi0-0 {
 847                         spi0m0_clk: spi0m0-clk {
 848                                 rockchip,pins =
 849                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 850                         };
 851
 852                         spi0m0_cs0: spi0m0-cs0 {
 853                                 rockchip,pins =
 854                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 855                         };
 856
 857                         spi0m0_tx: spi0m0-tx {
 858                                 rockchip,pins =
 859                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 860                         };
 861
 862                         spi0m0_rx: spi0m0-rx {
 863                                 rockchip,pins =
 864                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 865                         };
 866
 867                         spi0m0_cs1: spi0m0-cs1 {
 868                                 rockchip,pins =
 869                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 870                         };
 871                 };
 872
 873                 spi0-1 {
 874                         spi0m1_clk: spi0m1-clk {
 875                                 rockchip,pins =
 876                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
 877                         };
 878
 879                         spi0m1_cs0: spi0m1-cs0 {
 880                                 rockchip,pins =
 881                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
 882                         };
 883
 884                         spi0m1_tx: spi0m1-tx {
 885                                 rockchip,pins =
 886                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
 887                         };
 888
 889                         spi0m1_rx: spi0m1-rx {
 890                                 rockchip,pins =
 891                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
 892                         };
 893
 894                         spi0m1_cs1: spi0m1-cs1 {
 895                                 rockchip,pins =
 896                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
 897                         };
 898                 };
 899
 900                 spi0-2 {
 901                         spi0m2_clk: spi0m2-clk {
 902                                 rockchip,pins =
 903                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
 904                         };
 905
 906                         spi0m2_cs0: spi0m2-cs0 {
 907                                 rockchip,pins =
 908                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
 909                         };
 910
 911                         spi0m2_tx: spi0m2-tx {
 912                                 rockchip,pins =
 913                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
 914                         };
 915
 916                         spi0m2_rx: spi0m2-rx {
 917                                 rockchip,pins =
 918                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
 919                         };
 920                 };
 921
 922                 i2s1 {
 923                         i2s1_mclk: i2s1-mclk {
 924                                 rockchip,pins =
 925                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
 926                         };
 927
 928                         i2s1_sclk: i2s1-sclk {
 929                                 rockchip,pins =
 930                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 931                         };
 932
 933                         i2s1_lrckrx: i2s1-lrckrx {
 934                                 rockchip,pins =
 935                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
 936                         };
 937
 938                         i2s1_lrcktx: i2s1-lrcktx {
 939                                 rockchip,pins =
 940                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 941                         };
 942
 943                         i2s1_sdi: i2s1-sdi {
 944                                 rockchip,pins =
 945                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 946                         };
 947
 948                         i2s1_sdo: i2s1-sdo {
 949                                 rockchip,pins =
 950                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
 951                         };
 952
 953                         i2s1_sdio1: i2s1-sdio1 {
 954                                 rockchip,pins =
 955                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
 956                         };
 957
 958                         i2s1_sdio2: i2s1-sdio2 {
 959                                 rockchip,pins =
 960                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
 961                         };
 962
 963                         i2s1_sdio3: i2s1-sdio3 {
 964                                 rockchip,pins =
 965                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
 966                         };
 967
 968                         i2s1_sleep: i2s1-sleep {
 969                                 rockchip,pins =
 970                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
 971                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
 972                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
 973                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
 974                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
 975                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
 976                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
 977                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
 978                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
 979                         };
 980                 };
 981
 982                 i2s2-0 {
 983                         i2s2m0_mclk: i2s2m0-mclk {
 984                                 rockchip,pins =
 985                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 986                         };
 987
 988                         i2s2m0_sclk: i2s2m0-sclk {
 989                                 rockchip,pins =
 990                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
 991                         };
 992
 993                         i2s2m0_lrckrx: i2s2m0-lrckrx {
 994                                 rockchip,pins =
 995                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
 996                         };
 997
 998                         i2s2m0_lrcktx: i2s2m0-lrcktx {
 999                                 rockchip,pins =
1000                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
1001                         };
1002
1003                         i2s2m0_sdi: i2s2m0-sdi {
1004                                 rockchip,pins =
1005                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
1006                         };
1007
1008                         i2s2m0_sdo: i2s2m0-sdo {
1009                                 rockchip,pins =
1010                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
1011                         };
1012
1013                         i2s2m0_sleep: i2s2m0-sleep {
1014                                 rockchip,pins =
1015                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1016                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
1017                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
1018                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
1019                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
1020                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
1021                         };
1022                 };
1023
1024                 i2s2-1 {
1025                         i2s2m1_mclk: i2s2m1-mclk {
1026                                 rockchip,pins =
1027                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1028                         };
1029
1030                         i2s2m1_sclk: i2s2m1-sclk {
1031                                 rockchip,pins =
1032                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
1033                         };
1034
1035                         i2s2m1_lrckrx: i2sm1-lrckrx {
1036                                 rockchip,pins =
1037                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
1038                         };
1039
1040                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1041                                 rockchip,pins =
1042                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
1043                         };
1044
1045                         i2s2m1_sdi: i2s2m1-sdi {
1046                                 rockchip,pins =
1047                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
1048                         };
1049
1050                         i2s2m1_sdo: i2s2m1-sdo {
1051                                 rockchip,pins =
1052                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
1053                         };
1054
1055                         i2s2m1_sleep: i2s2m1-sleep {
1056                                 rockchip,pins =
1057                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1058                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
1059                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
1060                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
1061                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
1062                         };
1063                 };
1064
1065                 spdif-0 {
1066                         spdifm0_tx: spdifm0-tx {
1067                                 rockchip,pins =
1068                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
1069                         };
1070                 };
1071
1072                 spdif-1 {
1073                         spdifm1_tx: spdifm1-tx {
1074                                 rockchip,pins =
1075                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1076                         };
1077                 };
1078
1079                 spdif-2 {
1080                         spdifm2_tx: spdifm2-tx {
1081                                 rockchip,pins =
1082                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
1083                         };
1084                 };
1085
1086                 sdmmc0-0 {
1087                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1088                                 rockchip,pins =
1089                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1090                         };
1091
1092                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1093                                 rockchip,pins =
1094                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1095                         };
1096                 };
1097
1098                 sdmmc0-1 {
1099                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1100                                 rockchip,pins =
1101                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1102                         };
1103
1104                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1105                                 rockchip,pins =
1106                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1107                         };
1108                 };
1109
1110                 sdmmc0 {
1111                         sdmmc0_clk: sdmmc0-clk {
1112                                 rockchip,pins =
1113                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1114                         };
1115
1116                         sdmmc0_cmd: sdmmc0-cmd {
1117                                 rockchip,pins =
1118                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1119                         };
1120
1121                         sdmmc0_dectn: sdmmc0-dectn {
1122                                 rockchip,pins =
1123                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1124                         };
1125
1126                         sdmmc0_wrprt: sdmmc0-wrprt {
1127                                 rockchip,pins =
1128                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1129                         };
1130
1131                         sdmmc0_bus1: sdmmc0-bus1 {
1132                                 rockchip,pins =
1133                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1134                         };
1135
1136                         sdmmc0_bus4: sdmmc0-bus4 {
1137                                 rockchip,pins =
1138                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1139                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1140                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1141                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1142                         };
1143
1144                         sdmmc0_gpio: sdmmc0-gpio {
1145                                 rockchip,pins =
1146                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1147                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1148                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1149                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1150                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1151                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1152                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1153                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1154                         };
1155                 };
1156
1157                 sdmmc0ext {
1158                         sdmmc0ext_clk: sdmmc0ext-clk {
1159                                 rockchip,pins =
1160                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1161                         };
1162
1163                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1164                                 rockchip,pins =
1165                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1166                         };
1167
1168                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1169                                 rockchip,pins =
1170                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1171                         };
1172
1173                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1174                                 rockchip,pins =
1175                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1176                         };
1177
1178                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1179                                 rockchip,pins =
1180                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1181                         };
1182
1183                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1184                                 rockchip,pins =
1185                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1186                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1187                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1188                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1189                         };
1190
1191                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1192                                 rockchip,pins =
1193                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1194                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1195                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1196                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1197                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1198                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1199                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1200                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1201                         };
1202                 };
1203
1204                 sdmmc1 {
1205                         sdmmc1_clk: sdmmc1-clk {
1206                                 rockchip,pins =
1207                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1208                         };
1209
1210                         sdmmc1_cmd: sdmmc1-cmd {
1211                                 rockchip,pins =
1212                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1213                         };
1214
1215                         sdmmc1_pwren: sdmmc1-pwren {
1216                                 rockchip,pins =
1217                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1218                         };
1219
1220                         sdmmc1_wrprt: sdmmc1-wrprt {
1221                                 rockchip,pins =
1222                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1223                         };
1224
1225                         sdmmc1_dectn: sdmmc1-dectn {
1226                                 rockchip,pins =
1227                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1228                         };
1229
1230                         sdmmc1_bus1: sdmmc1-bus1 {
1231                                 rockchip,pins =
1232                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1233                         };
1234
1235                         sdmmc1_bus4: sdmmc1-bus4 {
1236                                 rockchip,pins =
1237                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1238                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1239                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1240                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1241                         };
1242
1243                         sdmmc1_gpio: sdmmc1-gpio {
1244                                 rockchip,pins =
1245                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1246                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1247                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1248                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1249                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1250                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1251                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1252                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1253                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1254                         };
1255                 };
1256
1257                 emmc {
1258                         emmc_clk: emmc-clk {
1259                                 rockchip,pins =
1260                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1261                         };
1262
1263                         emmc_cmd: emmc-cmd {
1264                                 rockchip,pins =
1265                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1266                         };
1267
1268                         emmc_pwren: emmc-pwren {
1269                                 rockchip,pins =
1270                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1271                         };
1272
1273                         emmc_rstnout: emmc-rstnout {
1274                                 rockchip,pins =
1275                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1276                         };
1277
1278                         emmc_bus1: emmc-bus1 {
1279                                 rockchip,pins =
1280                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1281                         };
1282
1283                         emmc_bus4: emmc-bus4 {
1284                                 rockchip,pins =
1285                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1286                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1287                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1288                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1289                         };
1290
1291                         emmc_bus8: emmc-bus8 {
1292                                 rockchip,pins =
1293                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1294                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1295                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1296                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1297                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1298                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1299                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1300                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1301                         };
1302                 };
1303
1304                 pwm0 {
1305                         pwm0_pin: pwm0-pin {
1306                                 rockchip,pins =
1307                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1308                         };
1309                 };
1310
1311                 pwm1 {
1312                         pwm1_pin: pwm1-pin {
1313                                 rockchip,pins =
1314                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1315                         };
1316                 };
1317
1318                 pwm2 {
1319                         pwm2_pin: pwm2-pin {
1320                                 rockchip,pins =
1321                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1322                         };
1323                 };
1324
1325                 pwmir {
1326                         pwmir_pin: pwmir-pin {
1327                                 rockchip,pins =
1328                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1329                         };
1330                 };
1331
1332                 gmac-0 {
1333                         rgmiim0_pins: rgmiim0-pins {
1334                                 rockchip,pins =
1335                                         /* mac_txclk */
1336                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1337                                         /* mac_rxclk */
1338                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1339                                         /* mac_mdio */
1340                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1341                                         /* mac_txen */
1342                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1343                                         /* mac_clk */
1344                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1345                                         /* mac_rxdv */
1346                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1347                                         /* mac_mdc */
1348                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1349                                         /* mac_rxd1 */
1350                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1351                                         /* mac_rxd0 */
1352                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1353                                         /* mac_txd1 */
1354                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1355                                         /* mac_txd0 */
1356                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1357                                         /* mac_rxd3 */
1358                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1359                                         /* mac_rxd2 */
1360                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1361                                         /* mac_txd3 */
1362                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1363                                         /* mac_txd2 */
1364                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1365                         };
1366
1367                         rmiim0_pins: rmiim0-pins {
1368                                 rockchip,pins =
1369                                         /* mac_mdio */
1370                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1371                                         /* mac_txen */
1372                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1373                                         /* mac_clk */
1374                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1375                                         /* mac_rxer */
1376                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1377                                         /* mac_rxdv */
1378                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1379                                         /* mac_mdc */
1380                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1381                                         /* mac_rxd1 */
1382                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1383                                         /* mac_rxd0 */
1384                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1385                                         /* mac_txd1 */
1386                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1387                                         /* mac_txd0 */
1388                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1389                         };
1390                 };
1391
1392                 gmac-1 {
1393                         rgmiim1_pins: rgmiim1-pins {
1394                                 rockchip,pins =
1395                                         /* mac_txclk */
1396                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1397                                         /* mac_rxclk */
1398                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1399                                         /* mac_mdio */
1400                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1401                                         /* mac_txen */
1402                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1403                                         /* mac_clk */
1404                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1405                                         /* mac_rxdv */
1406                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1407                                         /* mac_mdc */
1408                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1409                                         /* mac_rxd1 */
1410                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1411                                         /* mac_rxd0 */
1412                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1413                                         /* mac_txd1 */
1414                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1415                                         /* mac_txd0 */
1416                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1417                                         /* mac_rxd3 */
1418                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1419                                         /* mac_rxd2 */
1420                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1421                                         /* mac_txd3 */
1422                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1423                                         /* mac_txd2 */
1424                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1425
1426                                         /* mac_txclk */
1427                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1428                                         /* mac_txen */
1429                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1430                                         /* mac_clk */
1431                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1432                                         /* mac_txd1 */
1433                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1434                                         /* mac_txd0 */
1435                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1436                                         /* mac_txd3 */
1437                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1438                                         /* mac_txd2 */
1439                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1440                         };
1441
1442                         rmiim1_pins: rmiim1-pins {
1443                                 rockchip,pins =
1444                                         /* mac_mdio */
1445                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1446                                         /* mac_txen */
1447                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1448                                         /* mac_clk */
1449                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1450                                         /* mac_rxer */
1451                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1452                                         /* mac_rxdv */
1453                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1454                                         /* mac_mdc */
1455                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1456                                         /* mac_rxd1 */
1457                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1458                                         /* mac_rxd0 */
1459                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1460                                         /* mac_txd1 */
1461                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1462                                         /* mac_txd0 */
1463                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1464
1465                                         /* mac_mdio */
1466                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1467                                         /* mac_txen */
1468                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1469                                         /* mac_clk */
1470                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1471                                         /* mac_mdc */
1472                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1473                                         /* mac_txd1 */
1474                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1475                                         /* mac_txd0 */
1476                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1477                         };
1478                 };
1479
1480                 gmac2phy {
1481                         fephyled_speed100: fephyled-speed100 {
1482                                 rockchip,pins =
1483                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1484                         };
1485
1486                         fephyled_speed10: fephyled-speed10 {
1487                                 rockchip,pins =
1488                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1489                         };
1490
1491                         fephyled_duplex: fephyled-duplex {
1492                                 rockchip,pins =
1493                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1494                         };
1495
1496                         fephyled_rxm0: fephyled-rxm0 {
1497                                 rockchip,pins =
1498                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1499                         };
1500
1501                         fephyled_txm0: fephyled-txm0 {
1502                                 rockchip,pins =
1503                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1504                         };
1505
1506                         fephyled_linkm0: fephyled-linkm0 {
1507                                 rockchip,pins =
1508                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1509                         };
1510
1511                         fephyled_rxm1: fephyled-rxm1 {
1512                                 rockchip,pins =
1513                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1514                         };
1515
1516                         fephyled_txm1: fephyled-txm1 {
1517                                 rockchip,pins =
1518                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1519                         };
1520
1521                         fephyled_linkm1: fephyled-linkm1 {
1522                                 rockchip,pins =
1523                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1524                         };
1525                 };
1526
1527                 tsadc_pin {
1528                         tsadc_int: tsadc-int {
1529                                 rockchip,pins =
1530                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1531                         };
1532                         tsadc_gpio: tsadc-gpio {
1533                                 rockchip,pins =
1534                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1535                         };
1536                 };
1537
1538                 hdmi_pin {
1539                         hdmi_cec: hdmi-cec {
1540                                 rockchip,pins =
1541                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1542                         };
1543
1544                         hdmi_hpd: hdmi-hpd {
1545                                 rockchip,pins =
1546                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1547                         };
1548                 };
1549
1550                 cif-0 {
1551                         dvp_d2d9_m0:dvp-d2d9-m0 {
1552                                 rockchip,pins =
1553                                         /* cif_d0 */
1554                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1555                                         /* cif_d1 */
1556                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1557                                         /* cif_d2 */
1558                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1559                                         /* cif_d3 */
1560                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1561                                         /* cif_d4 */
1562                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1563                                         /* cif_d5m0 */
1564                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1565                                         /* cif_d6m0 */
1566                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1567                                         /* cif_d7m0 */
1568                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1569                                         /* cif_href */
1570                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1571                                         /* cif_vsync */
1572                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1573                                         /* cif_clkoutm0 */
1574                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1575                                         /* cif_clkin */
1576                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1577                         };
1578                 };
1579
1580                 cif-1 {
1581                         dvp_d2d9_m1:dvp-d2d9-m1 {
1582                                 rockchip,pins =
1583                                         /* cif_d0 */
1584                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1585                                         /* cif_d1 */
1586                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1587                                         /* cif_d2 */
1588                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1589                                         /* cif_d3 */
1590                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1591                                         /* cif_d4 */
1592                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1593                                         /* cif_d5m1 */
1594                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1595                                         /* cif_d6m1 */
1596                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1597                                         /* cif_d7m1 */
1598                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1599                                         /* cif_href */
1600                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1601                                         /* cif_vsync */
1602                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1603                                         /* cif_clkoutm1 */
1604                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1605                                         /* cif_clkin */
1606                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1607                         };
1608                 };
1609         };
1610 };