arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3328";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67         };
  68
  69         cpus {
  70                 #address-cells = <2>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53", "arm,armv8";
  76                         reg = <0x0 0x0>;
  77                         enable-method = "psci";
  78                         clocks = <&cru ARMCLK>;
  79                         #cooling-cells = <2>; /* min followed by max */
  80                         dynamic-power-coefficient = <120>;
  81                         operating-points-v2 = <&cpu0_opp_table>;
  82                 };
  83                 cpu1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53", "arm,armv8";
  86                         reg = <0x0 0x1>;
  87                         enable-method = "psci";
  88                         operating-points-v2 = <&cpu0_opp_table>;
  89                 };
  90                 cpu2: cpu@2 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53", "arm,armv8";
  93                         reg = <0x0 0x2>;
  94                         enable-method = "psci";
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                 };
  97                 cpu3: cpu@3 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a53", "arm,armv8";
 100                         reg = <0x0 0x3>;
 101                         enable-method = "psci";
 102                         operating-points-v2 = <&cpu0_opp_table>;
 103                 };
 104         };
 105
 106         cpu0_opp_table: opp_table0 {
 107                 compatible = "operating-points-v2";
 108                 opp-shared;
 109
 110                 opp@408000000 {
 111                         opp-hz = /bits/ 64 <408000000>;
 112                         opp-microvolt = <950000>;
 113                         clock-latency-ns = <40000>;
 114                         opp-suspend;
 115                 };
 116                 opp@600000000 {
 117                         opp-hz = /bits/ 64 <600000000>;
 118                         opp-microvolt = <950000>;
 119                         clock-latency-ns = <40000>;
 120                 };
 121                 opp@816000000 {
 122                         opp-hz = /bits/ 64 <816000000>;
 123                         opp-microvolt = <1000000>;
 124                         clock-latency-ns = <40000>;
 125                 };
 126                 opp@1008000000 {
 127                         opp-hz = /bits/ 64 <1008000000>;
 128                         opp-microvolt = <1100000>;
 129                         clock-latency-ns = <40000>;
 130                 };
 131                 opp@1200000000 {
 132                         opp-hz = /bits/ 64 <1200000000>;
 133                         opp-microvolt = <1225000>;
 134                         clock-latency-ns = <40000>;
 135                 };
 136                 opp@1296000000 {
 137                         opp-hz = /bits/ 64 <1296000000>;
 138                         opp-microvolt = <1300000>;
 139                         clock-latency-ns = <40000>;
 140                 };
 141         };
 142
 143         arm-pmu {
 144                 compatible = "arm,cortex-a53-pmu";
 145                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 149                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 150         };
 151
 152         cpuinfo {
 153                 compatible = "rockchip,cpuinfo";
 154                 nvmem-cells = <&efuse_id>;
 155                 nvmem-cell-names = "id";
 156         };
 157
 158         psci {
 159                 compatible = "arm,psci-1.0";
 160                 method = "smc";
 161         };
 162
 163         timer {
 164                 compatible = "arm,armv8-timer";
 165                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 166                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 169         };
 170
 171         xin24m: xin24m {
 172                 compatible = "fixed-clock";
 173                 #clock-cells = <0>;
 174                 clock-frequency = <24000000>;
 175                 clock-output-names = "xin24m";
 176         };
 177
 178         i2s0: i2s@ff000000 {
 179                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 180                 reg = <0x0 0xff000000 0x0 0x1000>;
 181                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 182                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 183                 clock-names = "i2s_clk", "i2s_hclk";
 184                 dmas = <&dmac 11>, <&dmac 12>;
 185                 #dma-cells = <2>;
 186                 dma-names = "tx", "rx";
 187                 status = "disabled";
 188         };
 189
 190         i2s1: i2s@ff010000 {
 191                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 192                 reg = <0x0 0xff010000 0x0 0x1000>;
 193                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 194                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 195                 clock-names = "i2s_clk", "i2s_hclk";
 196                 dmas = <&dmac 14>, <&dmac 15>;
 197                 #dma-cells = <2>;
 198                 dma-names = "tx", "rx";
 199                 status = "disabled";
 200         };
 201
 202         i2s2: i2s@ff020000 {
 203                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 204                 reg = <0x0 0xff020000 0x0 0x1000>;
 205                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 206                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 207                 clock-names = "i2s_clk", "i2s_hclk";
 208                 dmas = <&dmac 0>, <&dmac 1>;
 209                 #dma-cells = <2>;
 210                 dma-names = "tx", "rx";
 211                 pinctrl-names = "default", "sleep";
 212                 pinctrl-0 = <&i2s2m0_mclk
 213                              &i2s2m0_sclk
 214                              &i2s2m0_lrcktx
 215                              &i2s2m0_lrckrx
 216                              &i2s2m0_sdo
 217                              &i2s2m0_sdi>;
 218                 pinctrl-1 = <&i2s2m0_sleep>;
 219                 status = "disabled";
 220         };
 221
 222         spdif: spdif@ff030000 {
 223                 compatible = "rockchip,rk3328-spdif";
 224                 reg = <0x0 0xff030000 0x0 0x1000>;
 225                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 226                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 227                 clock-names = "mclk", "hclk";
 228                 dmas = <&dmac 10>;
 229                 #dma-cells = <1>;
 230                 dma-names = "tx";
 231                 pinctrl-names = "default";
 232                 pinctrl-0 = <&spdifm2_tx>;
 233                 status = "disabled";
 234         };
 235
 236         pdm: pdm@ff040000 {
 237                 compatible = "rockchip,pdm";
 238                 reg = <0x0 0xff040000 0x0 0x1000>;
 239                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 240                 clock-names = "pdm_clk", "pdm_hclk";
 241                 dmas = <&dmac 16>;
 242                 #dma-cells = <1>;
 243                 dma-names = "rx";
 244                 pinctrl-names = "default", "sleep";
 245                 pinctrl-0 = <&pdmm0_clk
 246                              &pdmm0_fsync
 247                              &pdmm0_sdi0
 248                              &pdmm0_sdi1
 249                              &pdmm0_sdi2
 250                              &pdmm0_sdi3>;
 251                 pinctrl-1 = <&pdmm0_sleep>;
 252                 status = "disabled";
 253         };
 254
 255         grf: syscon@ff100000 {
 256                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 257                 reg = <0x0 0xff100000 0x0 0x1000>;
 258                 #address-cells = <1>;
 259                 #size-cells = <1>;
 260
 261                 io_domains: io-domains {
 262                         compatible = "rockchip,rk3328-io-voltage-domain";
 263                         status = "disabled";
 264                 };
 265
 266                 power: power-controller {
 267                         compatible = "rockchip,rk3328-power-controller";
 268                         #power-domain-cells = <1>;
 269                         #address-cells = <1>;
 270                         #size-cells = <0>;
 271                         status = "disabled";
 272
 273                         pd_hevc@RK3328_PD_HEVC {
 274                                 reg = <RK3328_PD_HEVC>;
 275                         };
 276                         pd_video@RK3328_PD_VIDEO {
 277                                 reg = <RK3328_PD_VIDEO>;
 278                         };
 279                         pd_vpu@RK3328_PD_VPU {
 280                                 reg = <RK3328_PD_VPU>;
 281                         };
 282                 };
 283
 284                 reboot-mode {
 285                         compatible = "syscon-reboot-mode";
 286                         offset = <0x5c8>;
 287                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 288                         mode-charge = <BOOT_CHARGING>;
 289                         mode-fastboot = <BOOT_FASTBOOT>;
 290                         mode-loader = <BOOT_BL_DOWNLOAD>;
 291                         mode-normal = <BOOT_NORMAL>;
 292                         mode-recovery = <BOOT_RECOVERY>;
 293                         mode-ums = <BOOT_UMS>;
 294                 };
 295         };
 296
 297         thermal-zones {
 298                 soc_thermal: soc-thermal {
 299                         polling-delay-passive = <20>; /* milliseconds */
 300                         polling-delay = <1000>; /* milliseconds */
 301                         sustainable-power = <1000>; /* milliwatts */
 302
 303                         thermal-sensors = <&tsadc 0>;
 304
 305                         trips {
 306                                 threshold: trip-point@0 {
 307                                         temperature = <70000>; /* millicelsius */
 308                                         hysteresis = <2000>; /* millicelsius */
 309                                         type = "passive";
 310                                 };
 311                                 target: trip-point@1 {
 312                                         temperature = <85000>; /* millicelsius */
 313                                         hysteresis = <2000>; /* millicelsius */
 314                                         type = "passive";
 315                                 };
 316                                 soc_crit: soc-crit {
 317                                         temperature = <95000>; /* millicelsius */
 318                                         hysteresis = <2000>; /* millicelsius */
 319                                         type = "critical";
 320                                 };
 321                         };
 322
 323                         cooling-maps {
 324                                 map0 {
 325                                         trip = <&target>;
 326                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 327                                         contribution = <4096>;
 328                                 };
 329                         };
 330                 };
 331
 332         };
 333
 334         tsadc: tsadc@ff250000 {
 335                 compatible = "rockchip,rk3328-tsadc";
 336                 reg = <0x0 0xff250000 0x0 0x100>;
 337                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
 338                 rockchip,grf = <&grf>;
 339                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 340                 clock-names = "tsadc", "apb_pclk";
 341                 assigned-clocks = <&cru SCLK_TSADC>;
 342                 assigned-clock-rates = <50000>;
 343                 resets = <&cru SRST_TSADC>;
 344                 reset-names = "tsadc-apb";
 345                 pinctrl-names = "init", "default", "sleep";
 346                 pinctrl-0 = <&otp_gpio>;
 347                 pinctrl-1 = <&otp_out>;
 348                 pinctrl-2 = <&otp_gpio>;
 349                 #thermal-sensor-cells = <1>;
 350                 rockchip,hw-tshut-temp = <100000>;
 351                 status = "disabled";
 352         };
 353
 354         uart0: serial@ff110000 {
 355                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 356                 reg = <0x0 0xff110000 0x0 0x100>;
 357                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 358                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 359                 clock-names = "baudclk", "apb_pclk";
 360                 reg-shift = <2>;
 361                 reg-io-width = <4>;
 362                 dmas = <&dmac 2>, <&dmac 3>;
 363                 #dma-cells = <2>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 366                 status = "disabled";
 367         };
 368
 369         uart1: serial@ff120000 {
 370                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 371                 reg = <0x0 0xff120000 0x0 0x100>;
 372                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 373                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 374                 clock-names = "sclk_uart", "pclk_uart";
 375                 reg-shift = <2>;
 376                 reg-io-width = <4>;
 377                 dmas = <&dmac 4>, <&dmac 5>;
 378                 #dma-cells = <2>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 381                 status = "disabled";
 382         };
 383
 384         uart2: serial@ff130000 {
 385                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 386                 reg = <0x0 0xff130000 0x0 0x100>;
 387                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 388                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 389                 clock-names = "baudclk", "apb_pclk";
 390                 reg-shift = <2>;
 391                 reg-io-width = <4>;
 392                 dmas = <&dmac 6>, <&dmac 7>;
 393                 #dma-cells = <2>;
 394                 pinctrl-names = "default";
 395                 pinctrl-0 = <&uart2m1_xfer>;
 396                 status = "disabled";
 397         };
 398
 399         pmu: power-management@ff140000 {
 400                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 401                 reg = <0x0 0xff140000 0x0 0x1000>;
 402         };
 403
 404         i2c0: i2c@ff150000 {
 405                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 406                 reg = <0x0 0xff150000 0x0 0x1000>;
 407                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 411                 clock-names = "i2c", "pclk";
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&i2c0_xfer>;
 414                 status = "disabled";
 415         };
 416
 417         i2c1: i2c@ff160000 {
 418                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 419                 reg = <0x0 0xff160000 0x0 0x1000>;
 420                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 421                 #address-cells = <1>;
 422                 #size-cells = <0>;
 423                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 424                 clock-names = "i2c", "pclk";
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&i2c1_xfer>;
 427                 status = "disabled";
 428         };
 429
 430         i2c2: i2c@ff170000 {
 431                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 432                 reg = <0x0 0xff170000 0x0 0x1000>;
 433                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 437                 clock-names = "i2c", "pclk";
 438                 pinctrl-names = "default";
 439                 pinctrl-0 = <&i2c2_xfer>;
 440                 status = "disabled";
 441         };
 442
 443         i2c3: i2c@ff180000 {
 444                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 445                 reg = <0x0 0xff180000 0x0 0x1000>;
 446                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 450                 clock-names = "i2c", "pclk";
 451                 pinctrl-names = "default";
 452                 pinctrl-0 = <&i2c3_xfer>;
 453                 status = "disabled";
 454         };
 455
 456         spi0: spi@ff190000 {
 457                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 458                 reg = <0x0 0xff190000 0x0 0x1000>;
 459                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 463                 clock-names = "spiclk", "apb_pclk";
 464                 dmas = <&dmac 8>, <&dmac 9>;
 465                 #dma-cells = <2>;
 466                 dma-names = "tx", "rx";
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 469                 status = "disabled";
 470         };
 471
 472         wdt: watchdog@ff1a0000 {
 473                 compatible = "snps,dw-wdt";
 474                 reg = <0x0 0xff1a0000 0x0 0x100>;
 475                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 476                 status = "disabled";
 477         };
 478
 479         pwm0: pwm@ff1b0000 {
 480                 compatible = "rockchip,rk3328-pwm";
 481                 reg = <0x0 0xff1b0000 0x0 0x10>;
 482                 #pwm-cells = <3>;
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&pwm0_pin>;
 485                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 486                 clock-names = "pwm", "pclk";
 487                 status = "disabled";
 488         };
 489
 490         pwm1: pwm@ff1b0010 {
 491                 compatible = "rockchip,rk3328-pwm";
 492                 reg = <0x0 0xff1b0010 0x0 0x10>;
 493                 #pwm-cells = <3>;
 494                 pinctrl-names = "default";
 495                 pinctrl-0 = <&pwm1_pin>;
 496                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 497                 clock-names = "pwm", "pclk";
 498                 status = "disabled";
 499         };
 500
 501         pwm2: pwm@ff1b0020 {
 502                 compatible = "rockchip,rk3328-pwm";
 503                 reg = <0x0 0xff1b0020 0x0 0x10>;
 504                 #pwm-cells = <3>;
 505                 pinctrl-names = "default";
 506                 pinctrl-0 = <&pwm2_pin>;
 507                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 508                 clock-names = "pwm", "pclk";
 509                 status = "disabled";
 510         };
 511
 512         pwm3: pwm@ff1b0030 {
 513                 compatible = "rockchip,rk3328-pwm";
 514                 reg = <0x0 0xff1b0030 0x0 0x10>;
 515                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 516                 #pwm-cells = <3>;
 517                 pinctrl-names = "default";
 518                 pinctrl-0 = <&pwmir_pin>;
 519                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 520                 clock-names = "pwm", "pclk";
 521                 status = "disabled";
 522         };
 523
 524         amba {
 525                 compatible = "simple-bus";
 526                 #address-cells = <2>;
 527                 #size-cells = <2>;
 528                 ranges;
 529
 530                 dmac: dmac@ff1f0000 {
 531                         compatible = "arm,pl330", "arm,primecell";
 532                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 533                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 534                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 535                         clocks = <&cru ACLK_DMAC>;
 536                         clock-names = "apb_pclk";
 537                         #dma-cells = <1>;
 538                 };
 539         };
 540
 541         efuse: efuse@ff260000 {
 542                 compatible = "rockchip,rk3328-efuse";
 543                 reg = <0x0 0xff260000 0x0 0x50>;
 544                 #address-cells = <1>;
 545                 #size-cells = <1>;
 546                 clocks = <&cru SCLK_EFUSE>;
 547                 clock-names = "pclk_efuse";
 548                 rockchip,efuse-size = <0x20>;
 549
 550                 /* Data cells */
 551                 efuse_id: id@7 {
 552                         reg = <0x07 0x10>;
 553                 };
 554                 cpu_leakage: cpu-leakage@17 {
 555                         reg = <0x17 0x1>;
 556                 };
 557                 logic_leakage: logic-leakage@19 {
 558                         reg = <0x19 0x1>;
 559                 };
 560         };
 561
 562         saradc: saradc@ff280000 {
 563                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 564                 reg = <0x0 0xff280000 0x0 0x100>;
 565                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 566                 #io-channel-cells = <1>;
 567                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 568                 clock-names = "saradc", "apb_pclk";
 569                 resets = <&cru SRST_SARADC_P>;
 570                 reset-names = "saradc-apb";
 571                 status = "disabled";
 572         };
 573
 574         gpu: gpu@ff300000 {
 575                 compatible = "arm,mali-450";
 576                 /* first item of 'reg' is dummy, to fit src code. */
 577                 reg = <0x0 0xff300000 0x0 0x40000>,
 578                       <0x0 0xff300000 0x0 0x40000>;
 579                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 580                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 581                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 582                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 583                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 584                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 585                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 586                 interrupt-names = "Mali_GP_IRQ",
 587                                   "Mali_GP_MMU_IRQ",
 588                                   "IRQPP",
 589                                   "Mali_PP0_IRQ",
 590                                   "Mali_PP0_MMU_IRQ",
 591                                   "Mali_PP1_IRQ",
 592                                   "Mali_PP1_MMU_IRQ";
 593                 clocks = <&cru ACLK_GPU>;
 594                 clock-names = "clk_mali";
 595                 operating-points-v2 = <&gpu_opp_table>;
 596                 status = "disabled";
 597         };
 598
 599         gpu_opp_table: opp-table2 {
 600                 compatible = "operating-points-v2";
 601
 602                 opp@200000000 {
 603                         opp-hz = /bits/ 64 <200000000>;
 604                         opp-microvolt = <1050000>;
 605                 };
 606                 opp@300000000 {
 607                         opp-hz = /bits/ 64 <300000000>;
 608                         opp-microvolt = <1050000>;
 609                 };
 610                 opp@400000000 {
 611                         opp-hz = /bits/ 64 <400000000>;
 612                         opp-microvolt = <1050000>;
 613                 };
 614                 opp@500000000 {
 615                         opp-hz = /bits/ 64 <500000000>;
 616                         opp-microvolt = <1100000>;
 617                 };
 618         };
 619
 620         vop: vop@ff370000 {
 621                 compatible = "rockchip,rk3328-vop";
 622                 reg = <0x0 0xff370000 0x0 0x3efc>;
 623                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 624                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 625                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 626                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 627                 reset-names = "axi", "ahb", "dclk";
 628                 iommus = <&vop_mmu>;
 629                 status = "disabled";
 630
 631                 vop_out: port {
 632                         #address-cells = <1>;
 633                         #size-cells = <0>;
 634                 };
 635         };
 636
 637         vop_mmu: iommu@ff373f00 {
 638                 compatible = "rockchip,iommu";
 639                 reg = <0x0 0xff373f00 0x0 0x100>;
 640                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 641                 interrupt-names = "vop_mmu";
 642                 #iommu-cells = <0>;
 643                 status = "disabled";
 644         };
 645
 646         display_subsystem: display-subsystem {
 647                 compatible = "rockchip,display-subsystem";
 648                 ports = <&vop_out>;
 649                 status = "disabled";
 650         };
 651
 652         cru: clock-controller@ff440000 {
 653                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 654                 reg = <0x0 0xff440000 0x0 0x1000>;
 655                 rockchip,grf = <&grf>;
 656                 #clock-cells = <1>;
 657                 #reset-cells = <1>;
 658                 assigned-clocks =
 659                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 660                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 661                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 662                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 663                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 664                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 665                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 666                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 667                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 668                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 669                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 670                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 671                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 672                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 673                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 674                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 675                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 676                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 677                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 678                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 679                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 680                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 681                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 682                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 683                 assigned-clock-parents =
 684                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 685                         <&cru PLL_GPLL>, <&xin24m>,
 686                         <&xin24m>, <&xin24m>;
 687                 assigned-clock-rates =
 688                         <0>, <61440000>,
 689                         <0>, <24000000>,
 690                         <24000000>, <24000000>,
 691                         <15000000>, <15000000>,
 692                         <100000000>, <100000000>,
 693                         <100000000>, <100000000>,
 694                         <50000000>, <100000000>,
 695                         <100000000>, <100000000>,
 696                         <50000000>, <50000000>,
 697                         <50000000>, <50000000>,
 698                         <24000000>, <600000000>,
 699                         <491520000>, <1200000000>,
 700                         <150000000>, <75000000>,
 701                         <75000000>, <150000000>,
 702                         <75000000>, <75000000>,
 703                         <300000000>, <100000000>,
 704                         <300000000>, <200000000>,
 705                         <400000000>, <500000000>,
 706                         <200000000>, <300000000>,
 707                         <300000000>, <250000000>,
 708                         <200000000>, <100000000>,
 709                         <24000000>, <100000000>,
 710                         <150000000>, <50000000>,
 711                         <32768>, <32768>;
 712         };
 713
 714         usb2phy_grf: syscon@ff450000 {
 715                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 716                              "simple-mfd";
 717                 reg = <0x0 0xff450000 0x0 0x10000>;
 718                 #address-cells = <1>;
 719                 #size-cells = <1>;
 720
 721                 u2phy: usb2-phy@100 {
 722                         compatible = "rockchip,rk3328-usb2phy";
 723                         reg = <0x100 0x10>;
 724                         clocks = <&xin24m>;
 725                         clock-names = "phyclk";
 726                         #clock-cells = <0>;
 727                         assigned-clocks = <&cru USB480M>;
 728                         assigned-clock-parents = <&u2phy>;
 729                         clock-output-names = "usb480m_phy";
 730                         status = "disabled";
 731
 732                         u2phy_host: host-port {
 733                                 #phy-cells = <0>;
 734                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 735                                 interrupt-names = "linestate";
 736                                 status = "disabled";
 737                         };
 738
 739                         u2phy_otg: otg-port {
 740                                 #phy-cells = <0>;
 741                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 742                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 743                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 744                                 interrupt-names = "otg-bvalid", "otg-id",
 745                                                   "linestate";
 746                                 status = "disabled";
 747                         };
 748                 };
 749         };
 750
 751         usb3phy_grf: syscon@ff460000 {
 752                 compatible = "rockchip,usb3phy-grf", "syscon";
 753                 reg = <0x0 0xff460000 0x0 0x1000>;
 754         };
 755
 756         u3phy: usb3-phy@ff470000 {
 757                 compatible = "rockchip,rk3328-u3phy";
 758                 reg = <0x0 0xff470000 0x0 0x0>;
 759                 rockchip,u3phygrf = <&usb3phy_grf>;
 760                 rockchip,grf = <&grf>;
 761                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 762                 interrupt-names = "linestate";
 763                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
 764                 clock-names = "u3phy-otg", "u3phy-pipe";
 765                 resets = <&cru SRST_USB3PHY_U2>,
 766                          <&cru SRST_USB3PHY_U3>,
 767                          <&cru SRST_USB3PHY_PIPE>,
 768                          <&cru SRST_USB3OTG_UTMI>,
 769                          <&cru SRST_USB3PHY_OTG_P>,
 770                          <&cru SRST_USB3PHY_PIPE_P>;
 771                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
 772                               "u3phy-pipe-mac", "u3phy-utmi-mac",
 773                               "u3phy-utmi-apb", "u3phy-pipe-apb";
 774                 #address-cells = <2>;
 775                 #size-cells = <2>;
 776                 ranges;
 777                 status = "disabled";
 778
 779                 u3phy_utmi: utmi@ff470000 {
 780                         reg = <0x0 0xff470000 0x0 0x8000>;
 781                         #phy-cells = <0>;
 782                         status = "disabled";
 783                 };
 784
 785                 u3phy_pipe: pipe@ff478000 {
 786                         reg = <0x0 0xff478000 0x0 0x8000>;
 787                         #phy-cells = <0>;
 788                         status = "disabled";
 789                 };
 790         };
 791
 792         sdmmc: rksdmmc@ff500000 {
 793                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 794                 reg = <0x0 0xff500000 0x0 0x4000>;
 795                 clock-freq-min-max = <400000 150000000>;
 796                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 797                 clock-names = "biu", "ciu";
 798                 fifo-depth = <0x100>;
 799                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 800                 status = "disabled";
 801         };
 802
 803         sdio: dwmmc@ff510000 {
 804                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 805                 reg = <0x0 0xff510000 0x0 0x4000>;
 806                 clock-freq-min-max = <400000 150000000>;
 807                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 808                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 809                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 810                 fifo-depth = <0x100>;
 811                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 812                 status = "disabled";
 813         };
 814
 815         emmc: rksdmmc@ff520000 {
 816                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 817                 reg = <0x0 0xff520000 0x0 0x4000>;
 818                 clock-freq-min-max = <400000 150000000>;
 819                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 820                 clock-names = "biu", "ciu";
 821                 fifo-depth = <0x100>;
 822                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 823                 status = "disabled";
 824         };
 825
 826         gmac2io: eth@ff540000 {
 827                 compatible = "rockchip,rk3328-gmac";
 828                 reg = <0x0 0xff540000 0x0 0x10000>;
 829                 rockchip,grf = <&grf>;
 830                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 831                 interrupt-names = "macirq";
 832                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 833                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 834                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 835                          <&cru PCLK_MAC2IO>;
 836                 clock-names = "stmmaceth", "mac_clk_rx",
 837                               "mac_clk_tx", "clk_mac_ref",
 838                               "clk_mac_refout", "aclk_mac",
 839                               "pclk_mac";
 840                 resets = <&cru SRST_GMAC2IO_A>;
 841                 reset-names = "stmmaceth";
 842                 status = "disabled";
 843         };
 844
 845         usb20_otg: usb@ff580000 {
 846                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 847                              "snps,dwc2";
 848                 reg = <0x0 0xff580000 0x0 0x40000>;
 849                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 850                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 851                 clock-names = "otg", "otg_pmu";
 852                 dr_mode = "otg";
 853                 g-np-tx-fifo-size = <16>;
 854                 g-rx-fifo-size = <275>;
 855                 g-tx-fifo-size = <256 128 128 64 64 32>;
 856                 g-use-dma;
 857                 phys = <&u2phy_otg>;
 858                 phy-names = "usb2-phy";
 859                 status = "disabled";
 860         };
 861
 862         usb_host0_ehci: usb@ff5c0000 {
 863                 compatible = "generic-ehci";
 864                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 865                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 866                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 867                          <&u2phy>;
 868                 clock-names = "usbhost", "arbiter", "utmi";
 869                 phys = <&u2phy_host>;
 870                 phy-names = "usb";
 871                 status = "disabled";
 872         };
 873
 874         usb_host0_ohci: usb@ff5d0000 {
 875                 compatible = "generic-ohci";
 876                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 877                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 878                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 879                          <&u2phy>;
 880                 clock-names = "usbhost", "arbiter", "utmi";
 881                 phys = <&u2phy_host>;
 882                 phy-names = "usb";
 883                 status = "disabled";
 884         };
 885
 886         sdmmc_ext: rksdmmc@ff5f0000 {
 887                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 888                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 889                 clock-freq-min-max = <400000 150000000>;
 890                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 891                 clock-names = "biu", "ciu";
 892                 fifo-depth = <0x100>;
 893                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 894                 status = "disabled";
 895         };
 896
 897         usbdrd3: usb@ff600000 {
 898                 compatible = "rockchip,rk3328-dwc3";
 899                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
 900                          <&cru ACLK_USB3OTG>;
 901                 clock-names = "ref_clk", "suspend_clk",
 902                               "bus_clk";
 903                 #address-cells = <2>;
 904                 #size-cells = <2>;
 905                 ranges;
 906                 status = "disabled";
 907
 908                 usbdrd_dwc3: dwc3@ff600000 {
 909                         compatible = "snps,dwc3";
 910                         reg = <0x0 0xff600000 0x0 0x100000>;
 911                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 912                         dr_mode = "host";
 913                         phys = <&u3phy_utmi>, <&u3phy_pipe>;
 914                         phy-names = "usb2-phy", "usb3-phy";
 915                         phy_type = "utmi_wide";
 916                         snps,dis_enblslpm_quirk;
 917                         snps,dis-u2-freeclk-exists-quirk;
 918                         snps,dis_u2_susphy_quirk;
 919                         snps,dis-u3-autosuspend-quirk;
 920                         snps,dis_u3_susphy_quirk;
 921                         snps,dis-del-phy-power-chg-quirk;
 922                         status = "disabled";
 923                 };
 924         };
 925
 926         gic: interrupt-controller@ff811000 {
 927                 compatible = "arm,gic-400";
 928                 #interrupt-cells = <3>;
 929                 #address-cells = <0>;
 930                 interrupt-controller;
 931                 reg = <0x0 0xff811000 0 0x1000>,
 932                       <0x0 0xff812000 0 0x2000>,
 933                       <0x0 0xff814000 0 0x2000>,
 934                       <0x0 0xff816000 0 0x2000>;
 935                 interrupts = <GIC_PPI 9
 936                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 937         };
 938
 939         pinctrl: pinctrl {
 940                 compatible = "rockchip,rk3328-pinctrl";
 941                 rockchip,grf = <&grf>;
 942                 #address-cells = <2>;
 943                 #size-cells = <2>;
 944                 ranges;
 945
 946                 gpio0: gpio0@ff210000 {
 947                         compatible = "rockchip,gpio-bank";
 948                         reg = <0x0 0xff210000 0x0 0x100>;
 949                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 950                         clocks = <&cru PCLK_GPIO0>;
 951
 952                         gpio-controller;
 953                         #gpio-cells = <2>;
 954
 955                         interrupt-controller;
 956                         #interrupt-cells = <2>;
 957                 };
 958
 959                 gpio1: gpio1@ff220000 {
 960                         compatible = "rockchip,gpio-bank";
 961                         reg = <0x0 0xff220000 0x0 0x100>;
 962                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 963                         clocks = <&cru PCLK_GPIO1>;
 964
 965                         gpio-controller;
 966                         #gpio-cells = <2>;
 967
 968                         interrupt-controller;
 969                         #interrupt-cells = <2>;
 970                 };
 971
 972                 gpio2: gpio2@ff230000 {
 973                         compatible = "rockchip,gpio-bank";
 974                         reg = <0x0 0xff230000 0x0 0x100>;
 975                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 976                         clocks = <&cru PCLK_GPIO2>;
 977
 978                         gpio-controller;
 979                         #gpio-cells = <2>;
 980
 981                         interrupt-controller;
 982                         #interrupt-cells = <2>;
 983                 };
 984
 985                 gpio3: gpio3@ff240000 {
 986                         compatible = "rockchip,gpio-bank";
 987                         reg = <0x0 0xff240000 0x0 0x100>;
 988                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 989                         clocks = <&cru PCLK_GPIO3>;
 990
 991                         gpio-controller;
 992                         #gpio-cells = <2>;
 993
 994                         interrupt-controller;
 995                         #interrupt-cells = <2>;
 996                 };
 997
 998                 pcfg_pull_up: pcfg-pull-up {
 999                         bias-pull-up;
1000                 };
1001
1002                 pcfg_pull_down: pcfg-pull-down {
1003                         bias-pull-down;
1004                 };
1005
1006                 pcfg_pull_none: pcfg-pull-none {
1007                         bias-disable;
1008                 };
1009
1010                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1011                         bias-disable;
1012                         drive-strength = <2>;
1013                 };
1014
1015                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1016                         bias-pull-up;
1017                         drive-strength = <2>;
1018                 };
1019
1020                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1021                         bias-pull-up;
1022                         drive-strength = <4>;
1023                 };
1024
1025                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1026                         bias-disable;
1027                         drive-strength = <4>;
1028                 };
1029
1030                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1031                         bias-pull-down;
1032                         drive-strength = <4>;
1033                 };
1034
1035                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1036                         bias-disable;
1037                         drive-strength = <8>;
1038                 };
1039
1040                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1041                         bias-pull-up;
1042                         drive-strength = <8>;
1043                 };
1044
1045                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1046                         bias-disable;
1047                         drive-strength = <12>;
1048                 };
1049
1050                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1051                         bias-pull-up;
1052                         drive-strength = <12>;
1053                 };
1054
1055                 pcfg_output_high: pcfg-output-high {
1056                         output-high;
1057                 };
1058
1059                 pcfg_output_low: pcfg-output-low {
1060                         output-low;
1061                 };
1062
1063                 pcfg_input_high: pcfg-input-high {
1064                         bias-pull-up;
1065                         input-enable;
1066                 };
1067
1068                 pcfg_input: pcfg-input {
1069                         input-enable;
1070                 };
1071
1072                 i2c0 {
1073                         i2c0_xfer: i2c0-xfer {
1074                                 rockchip,pins =
1075                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1076                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1077                         };
1078                 };
1079
1080                 i2c1 {
1081                         i2c1_xfer: i2c1-xfer {
1082                                 rockchip,pins =
1083                                         <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1084                                         <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>;
1085                         };
1086                 };
1087
1088                 i2c2 {
1089                         i2c2_xfer: i2c2-xfer {
1090                                 rockchip,pins =
1091                                         <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
1092                                         <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
1093                         };
1094                 };
1095
1096                 i2c3 {
1097                         i2c3_xfer: i2c3-xfer {
1098                                 rockchip,pins =
1099                                         <0 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1100                                         <0 RK_PA6 RK_FUNC_2 &pcfg_pull_none>;
1101                         };
1102                         i2c3_gpio: i2c3-gpio {
1103                                 rockchip,pins =
1104                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1105                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1106                         };
1107                 };
1108
1109                 hdmi_i2c {
1110                         hdmii2c_xfer: hdmii2c-xfer {
1111                                 rockchip,pins =
1112                                         <0 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
1113                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1114                         };
1115                 };
1116
1117                 tsadc {
1118                         otp_gpio: otp-gpio {
1119                                 rockchip,pins =
1120                                         <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1121                         };
1122
1123                         otp_out: otp-out {
1124                                 rockchip,pins =
1125                                         <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>;
1126                         };
1127                 };
1128
1129                 uart0 {
1130                         uart0_xfer: uart0-xfer {
1131                                 rockchip,pins =
1132                                         <1 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
1133                                         <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
1134                         };
1135
1136                         uart0_cts: uart0-cts {
1137                                 rockchip,pins =
1138                                         <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
1139                         };
1140
1141                         uart0_rts: uart0-rts {
1142                                 rockchip,pins =
1143                                         <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
1144                         };
1145
1146                         uart0_rts_gpio: uart0-rts-gpio {
1147                                 rockchip,pins =
1148                                         <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1149                         };
1150                 };
1151
1152                 uart1 {
1153                         uart1_xfer: uart1-xfer {
1154                                 rockchip,pins =
1155                                         <3 RK_PA4 RK_FUNC_4 &pcfg_pull_up>,
1156                                         <3 RK_PA6 RK_FUNC_4 &pcfg_pull_none>;
1157                         };
1158
1159                         uart1_cts: uart1-cts {
1160                                 rockchip,pins =
1161                                         <3 RK_PA7 RK_FUNC_4 &pcfg_pull_none>;
1162                         };
1163
1164                         uart1_rts: uart1-rts {
1165                                 rockchip,pins =
1166                                         <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>;
1167                         };
1168
1169                         uart1_rts_gpio: uart1-rts-gpio {
1170                                 rockchip,pins =
1171                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1172                         };
1173                 };
1174
1175                 uart2-0 {
1176                         uart2m0_xfer: uart2m0-xfer {
1177                                 rockchip,pins =
1178                                         <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up>,
1179                                         <1 RK_PA1 RK_FUNC_2 &pcfg_pull_none>;
1180                         };
1181                 };
1182
1183                 uart2-1 {
1184                         uart2m1_xfer: uart2m1-xfer {
1185                                 rockchip,pins =
1186                                         <2 RK_PA0 RK_FUNC_1 &pcfg_pull_up>,
1187                                         <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
1188                         };
1189                 };
1190
1191                 spi0-0 {
1192                         spi0m0_clk: spi0m0-clk {
1193                                 rockchip,pins =
1194                                         <2 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
1195                         };
1196
1197                         spi0m0_cs0: spi0m0-cs0 {
1198                                 rockchip,pins =
1199                                         <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
1200                         };
1201
1202                         spi0m0_tx: spi0m0-tx {
1203                                 rockchip,pins =
1204                                         <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>;
1205                         };
1206
1207                         spi0m0_rx: spi0m0-rx {
1208                                 rockchip,pins =
1209                                         <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>;
1210                         };
1211
1212                         spi0m0_cs1: spi0m0-cs1 {
1213                                 rockchip,pins =
1214                                         <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>;
1215                         };
1216                 };
1217
1218                 spi0-1 {
1219                         spi0m1_clk: spi0m1-clk {
1220                                 rockchip,pins =
1221                                         <3 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
1222                         };
1223
1224                         spi0m1_cs0: spi0m1-cs0 {
1225                                 rockchip,pins =
1226                                         <3 RK_PD2 RK_FUNC_2 &pcfg_pull_up>;
1227                         };
1228
1229                         spi0m1_tx: spi0m1-tx {
1230                                 rockchip,pins =
1231                                         <3 RK_PD1 RK_FUNC_2 &pcfg_pull_up>;
1232                         };
1233
1234                         spi0m1_rx: spi0m1-rx {
1235                                 rockchip,pins =
1236                                         <3 RK_PD0 RK_FUNC_2 &pcfg_pull_up>;
1237                         };
1238
1239                         spi0m1_cs1: spi0m1-cs1 {
1240                                 rockchip,pins =
1241                                         <3 RK_PD3 RK_FUNC_2 &pcfg_pull_up>;
1242                         };
1243                 };
1244
1245                 spi0-2 {
1246                         spi0m2_clk: spi0m2-clk {
1247                                 rockchip,pins =
1248                                         <3 RK_PA0 RK_FUNC_4 &pcfg_pull_up>;
1249                         };
1250
1251                         spi0m2_cs0: spi0m2-cs0 {
1252                                 rockchip,pins =
1253                                         <3 RK_PB0 RK_FUNC_3 &pcfg_pull_up>;
1254                         };
1255
1256                         spi0m2_tx: spi0m2-tx {
1257                                 rockchip,pins =
1258                                         <3 RK_PA1 RK_FUNC_4 &pcfg_pull_up>;
1259                         };
1260
1261                         spi0m2_rx: spi0m2-rx {
1262                                 rockchip,pins =
1263                                         <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>;
1264                         };
1265                 };
1266
1267                 pdm-0 {
1268                         pdmm0_clk: pdmm0-clk {
1269                                 rockchip,pins =
1270                                         <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
1271                         };
1272
1273                         pdmm0_fsync: pdmm0-fsync {
1274                                 rockchip,pins =
1275                                         <2 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
1276                         };
1277
1278                         pdmm0_sdi0: pdmm0-sdi0 {
1279                                 rockchip,pins =
1280                                         <2 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
1281                         };
1282
1283                         pdmm0_sdi1: pdmm0-sdi1 {
1284                                 rockchip,pins =
1285                                         <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
1286                         };
1287
1288                         pdmm0_sdi2: pdmm0-sdi2 {
1289                                 rockchip,pins =
1290                                         <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>;
1291                         };
1292
1293                         pdmm0_sdi3: pdmm0-sdi3 {
1294                                 rockchip,pins =
1295                                         <2 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
1296                         };
1297
1298                         pdmm0_sleep: pdmm0-sleep {
1299                                 rockchip,pins =
1300                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1301                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1302                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1303                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1304                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1305                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1306                         };
1307                 };
1308
1309                 i2s1 {
1310                         i2s1_mclk: i2s1-mclk {
1311                                 rockchip,pins =
1312                                         <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
1313                         };
1314
1315                         i2s1_sclk: i2s1-sclk {
1316                                 rockchip,pins =
1317                                         <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
1318                         };
1319
1320                         i2s1_lrckrx: i2s1-lrckrx {
1321                                 rockchip,pins =
1322                                         <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
1323                         };
1324
1325                         i2s1_lrcktx: i2s1-lrcktx {
1326                                 rockchip,pins =
1327                                         <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
1328                         };
1329
1330                         i2s1_sdi: i2s1-sdi {
1331                                 rockchip,pins =
1332                                         <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
1333                         };
1334
1335                         i2s1_sdo: i2s1-sdo {
1336                                 rockchip,pins =
1337                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1338                         };
1339
1340                         i2s1_sdio1: i2s1-sdio1 {
1341                                 rockchip,pins =
1342                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
1343                         };
1344
1345                         i2s1_sdio2: i2s1-sdio2 {
1346                                 rockchip,pins =
1347                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1348                         };
1349
1350                         i2s1_sdio3: i2s1-sdio3 {
1351                                 rockchip,pins =
1352                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1353                         };
1354
1355                         i2s1_sleep: i2s1-sleep {
1356                                 rockchip,pins =
1357                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1358                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1359                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1360                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1361                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1362                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1363                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1364                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1365                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1366                         };
1367                 };
1368
1369                 i2s2-0 {
1370                         i2s2m0_mclk: i2s2m0-mclk {
1371                                 rockchip,pins =
1372                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1373                         };
1374
1375                         i2s2m0_sclk: i2s2m0-sclk {
1376                                 rockchip,pins =
1377                                         <1 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1378                         };
1379
1380                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1381                                 rockchip,pins =
1382                                         <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
1383                         };
1384
1385                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1386                                 rockchip,pins =
1387                                         <1 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1388                         };
1389
1390                         i2s2m0_sdi: i2s2m0-sdi {
1391                                 rockchip,pins =
1392                                         <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
1393                         };
1394
1395                         i2s2m0_sdo: i2s2m0-sdo {
1396                                 rockchip,pins =
1397                                         <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1398                         };
1399
1400                         i2s2m0_sleep: i2s2m0-sleep {
1401                                 rockchip,pins =
1402                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1403                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1404                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1405                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1406                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1407                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1408                         };
1409                 };
1410
1411                 i2s2-1 {
1412                         i2s2m1_mclk: i2s2m1-mclk {
1413                                 rockchip,pins =
1414                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1415                         };
1416
1417                         i2s2m1_sclk: i2s2m1-sclk {
1418                                 rockchip,pins =
1419                                         <3 RK_PA0 RK_FUNC_6 &pcfg_pull_none>;
1420                         };
1421
1422                         i2s2m1_lrckrx: i2sm1-lrckrx {
1423                                 rockchip,pins =
1424                                         <3 RK_PB0 RK_FUNC_6 &pcfg_pull_none>;
1425                         };
1426
1427                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1428                                 rockchip,pins =
1429                                         <3 RK_PB0 RK_FUNC_4 &pcfg_pull_none>;
1430                         };
1431
1432                         i2s2m1_sdi: i2s2m1-sdi {
1433                                 rockchip,pins =
1434                                         <3 RK_PA2 RK_FUNC_6 &pcfg_pull_none>;
1435                         };
1436
1437                         i2s2m1_sdo: i2s2m1-sdo {
1438                                 rockchip,pins =
1439                                         <3 RK_PA1 RK_FUNC_6 &pcfg_pull_none>;
1440                         };
1441
1442                         i2s2m1_sleep: i2s2m1-sleep {
1443                                 rockchip,pins =
1444                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1445                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1446                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1447                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1448                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1449                         };
1450                 };
1451
1452                 spdif-0 {
1453                         spdifm0_tx: spdifm0-tx {
1454                                 rockchip,pins =
1455                                         <0 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
1456                         };
1457                 };
1458
1459                 spdif-1 {
1460                         spdifm1_tx: spdifm1-tx {
1461                                 rockchip,pins =
1462                                         <2 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
1463                         };
1464                 };
1465
1466                 spdif-2 {
1467                         spdifm2_tx: spdifm2-tx {
1468                                 rockchip,pins =
1469                                         <0 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1470                         };
1471                 };
1472
1473                 sdmmc0-0 {
1474                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1475                                 rockchip,pins =
1476                                         <2 RK_PA7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1477                         };
1478
1479                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1480                                 rockchip,pins =
1481                                         <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1482                         };
1483                 };
1484
1485                 sdmmc0-1 {
1486                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1487                                 rockchip,pins =
1488                                         <0 RK_PD6 RK_FUNC_3 &pcfg_pull_up_4ma>;
1489                         };
1490
1491                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1492                                 rockchip,pins =
1493                                         <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1494                         };
1495                 };
1496
1497                 sdmmc0 {
1498                         sdmmc0_clk: sdmmc0-clk {
1499                                 rockchip,pins =
1500                                         <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1501                         };
1502
1503                         sdmmc0_cmd: sdmmc0-cmd {
1504                                 rockchip,pins =
1505                                         <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1506                         };
1507
1508                         sdmmc0_dectn: sdmmc0-dectn {
1509                                 rockchip,pins =
1510                                         <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1511                         };
1512
1513                         sdmmc0_wrprt: sdmmc0-wrprt {
1514                                 rockchip,pins =
1515                                         <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1516                         };
1517
1518                         sdmmc0_bus1: sdmmc0-bus1 {
1519                                 rockchip,pins =
1520                                         <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1521                         };
1522
1523                         sdmmc0_bus4: sdmmc0-bus4 {
1524                                 rockchip,pins =
1525                                         <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1526                                         <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1527                                         <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1528                                         <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1529                         };
1530
1531                         sdmmc0_gpio: sdmmc0-gpio {
1532                                 rockchip,pins =
1533                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1534                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1535                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1536                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1537                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1538                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1539                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1540                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1541                         };
1542                 };
1543
1544                 sdmmc0ext {
1545                         sdmmc0ext_clk: sdmmc0ext-clk {
1546                                 rockchip,pins =
1547                                         <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1548                         };
1549
1550                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1551                                 rockchip,pins =
1552                                         <3 RK_PA0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1553                         };
1554
1555                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1556                                 rockchip,pins =
1557                                         <3 RK_PA3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1558                         };
1559
1560                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1561                                 rockchip,pins =
1562                                         <3 RK_PA1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1563                         };
1564
1565                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1566                                 rockchip,pins =
1567                                         <3 RK_PA4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1568                         };
1569
1570                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1571                                 rockchip,pins =
1572                                         <3 RK_PA4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1573                                         <3 RK_PA5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1574                                         <3 RK_PA6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1575                                         <3 RK_PA7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1576                         };
1577
1578                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1579                                 rockchip,pins =
1580                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1581                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1582                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1583                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1584                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1585                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1586                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1587                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1588                         };
1589                 };
1590
1591                 sdmmc1 {
1592                         sdmmc1_clk: sdmmc1-clk {
1593                                 rockchip,pins =
1594                                         <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none_8ma>;
1595                         };
1596
1597                         sdmmc1_cmd: sdmmc1-cmd {
1598                                 rockchip,pins =
1599                                         <1 RK_PB5 RK_FUNC_1 &pcfg_pull_up_8ma>;
1600                         };
1601
1602                         sdmmc1_pwren: sdmmc1-pwren {
1603                                 rockchip,pins =
1604                                         <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up_8ma>;
1605                         };
1606
1607                         sdmmc1_wrprt: sdmmc1-wrprt {
1608                                 rockchip,pins =
1609                                         <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up_8ma>;
1610                         };
1611
1612                         sdmmc1_dectn: sdmmc1-dectn {
1613                                 rockchip,pins =
1614                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_up_8ma>;
1615                         };
1616
1617                         sdmmc1_bus1: sdmmc1-bus1 {
1618                                 rockchip,pins =
1619                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_up_8ma>;
1620                         };
1621
1622                         sdmmc1_bus4: sdmmc1-bus4 {
1623                                 rockchip,pins =
1624                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_up_8ma>,
1625                                         <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up_8ma>,
1626                                         <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up_8ma>,
1627                                         <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up_8ma>;
1628                         };
1629
1630                         sdmmc1_gpio: sdmmc1-gpio {
1631                                 rockchip,pins =
1632                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1633                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1634                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1635                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1636                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1637                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1638                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1639                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1640                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1641                         };
1642                 };
1643
1644                 emmc {
1645                         emmc_clk: emmc-clk {
1646                                 rockchip,pins =
1647                                         <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none_12ma>;
1648                         };
1649
1650                         emmc_cmd: emmc-cmd {
1651                                 rockchip,pins =
1652                                         <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up_12ma>;
1653                         };
1654
1655                         emmc_pwren: emmc-pwren {
1656                                 rockchip,pins =
1657                                         <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
1658                         };
1659
1660                         emmc_rstnout: emmc-rstnout {
1661                                 rockchip,pins =
1662                                         <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
1663                         };
1664
1665                         emmc_bus1: emmc-bus1 {
1666                                 rockchip,pins =
1667                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1668                         };
1669
1670                         emmc_bus4: emmc-bus4 {
1671                                 rockchip,pins =
1672                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1673                                         <2 RK_PD4 RK_FUNC_2 &pcfg_pull_up_12ma>,
1674                                         <2 RK_PD5 RK_FUNC_2 &pcfg_pull_up_12ma>,
1675                                         <2 RK_PD6 RK_FUNC_2 &pcfg_pull_up_12ma>;
1676                         };
1677
1678                         emmc_bus8: emmc-bus8 {
1679                                 rockchip,pins =
1680                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1681                                         <2 RK_PD4 RK_FUNC_2 &pcfg_pull_up_12ma>,
1682                                         <2 RK_PD5 RK_FUNC_2 &pcfg_pull_up_12ma>,
1683                                         <2 RK_PD6 RK_FUNC_2 &pcfg_pull_up_12ma>,
1684                                         <2 RK_PD7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1685                                         <3 RK_PC0 RK_FUNC_2 &pcfg_pull_up_12ma>,
1686                                         <3 RK_PC1 RK_FUNC_2 &pcfg_pull_up_12ma>,
1687                                         <3 RK_PC2 RK_FUNC_2 &pcfg_pull_up_12ma>;
1688                         };
1689                 };
1690
1691                 pwm0 {
1692                         pwm0_pin: pwm0-pin {
1693                                 rockchip,pins =
1694                                         <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
1695                         };
1696                 };
1697
1698                 pwm1 {
1699                         pwm1_pin: pwm1-pin {
1700                                 rockchip,pins =
1701                                         <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
1702                         };
1703                 };
1704
1705                 pwm2 {
1706                         pwm2_pin: pwm2-pin {
1707                                 rockchip,pins =
1708                                         <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1709                         };
1710                 };
1711
1712                 pwmir {
1713                         pwmir_pin: pwmir-pin {
1714                                 rockchip,pins =
1715                                         <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>;
1716                         };
1717                 };
1718
1719                 gmac-1 {
1720                         rgmiim1_pins: rgmiim1-pins {
1721                                 rockchip,pins =
1722                                         /* mac_txclk */
1723                                         <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none_12ma>,
1724                                         /* mac_rxclk */
1725                                         <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1726                                         /* mac_mdio */
1727                                         <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1728                                         /* mac_txen */
1729                                         <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1730                                         /* mac_clk */
1731                                         <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1732                                         /* mac_rxdv */
1733                                         <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1734                                         /* mac_mdc */
1735                                         <1 RK_PC7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1736                                         /* mac_rxd1 */
1737                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_none_2ma>,
1738                                         /* mac_rxd0 */
1739                                         <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1740                                         /* mac_txd1 */
1741                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1742                                         /* mac_txd0 */
1743                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1744                                         /* mac_rxd3 */
1745                                         <1 RK_PB6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1746                                         /* mac_rxd2 */
1747                                         <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1748                                         /* mac_txd3 */
1749                                         <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1750                                         /* mac_txd2 */
1751                                         <1 RK_PC1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1752
1753                                         /* mac_txclk */
1754                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
1755                                         /* mac_txen */
1756                                         <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1757                                         /* mac_clk */
1758                                         <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1759                                         /* mac_txd1 */
1760                                         <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
1761                                         /* mac_txd0 */
1762                                         <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
1763                                         /* mac_txd3 */
1764                                         <0 RK_PC7 RK_FUNC_1 &pcfg_pull_none>,
1765                                         /* mac_txd2 */
1766                                         <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1767                         };
1768
1769                         rmiim1_pins: rmiim1-pins {
1770                                 rockchip,pins =
1771                                         /* mac_mdio */
1772                                         <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1773                                         /* mac_txen */
1774                                         <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1775                                         /* mac_clk */
1776                                         <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1777                                         /* mac_rxer */
1778                                         <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none_2ma>,
1779                                         /* mac_rxdv */
1780                                         <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1781                                         /* mac_mdc */
1782                                         <1 RK_PC7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1783                                         /* mac_rxd1 */
1784                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_none_2ma>,
1785                                         /* mac_rxd0 */
1786                                         <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1787                                         /* mac_txd1 */
1788                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1789                                         /* mac_txd0 */
1790                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1791
1792                                         /* mac_mdio */
1793                                         <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
1794                                         /* mac_txen */
1795                                         <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1796                                         /* mac_clk */
1797                                         <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1798                                         /* mac_mdc */
1799                                         <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
1800                                         /* mac_txd1 */
1801                                         <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
1802                                         /* mac_txd0 */
1803                                         <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
1804                         };
1805                 };
1806
1807                 gmac2phy {
1808                         fephyled_speed100: fephyled-speed100 {
1809                                 rockchip,pins =
1810                                         <0 RK_PD7 RK_FUNC_1 &pcfg_pull_none>;
1811                         };
1812
1813                         fephyled_speed10: fephyled-speed10 {
1814                                 rockchip,pins =
1815                                         <0 RK_PD6 RK_FUNC_1 &pcfg_pull_none>;
1816                         };
1817
1818                         fephyled_duplex: fephyled-duplex {
1819                                 rockchip,pins =
1820                                         <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
1821                         };
1822
1823                         fephyled_rxm0: fephyled-rxm0 {
1824                                 rockchip,pins =
1825                                         <0 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
1826                         };
1827
1828                         fephyled_txm0: fephyled-txm0 {
1829                                 rockchip,pins =
1830                                         <0 RK_PD5 RK_FUNC_2 &pcfg_pull_none>;
1831                         };
1832
1833                         fephyled_linkm0: fephyled-linkm0 {
1834                                 rockchip,pins =
1835                                         <0 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
1836                         };
1837
1838                         fephyled_rxm1: fephyled-rxm1 {
1839                                 rockchip,pins =
1840                                         <2 RK_PD1 RK_FUNC_2 &pcfg_pull_none>;
1841                         };
1842
1843                         fephyled_txm1: fephyled-txm1 {
1844                                 rockchip,pins =
1845                                         <2 RK_PD1 RK_FUNC_3 &pcfg_pull_none>;
1846                         };
1847
1848                         fephyled_linkm1: fephyled-linkm1 {
1849                                 rockchip,pins =
1850                                         <2 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
1851                         };
1852                 };
1853
1854                 tsadc_pin {
1855                         tsadc_int: tsadc-int {
1856                                 rockchip,pins =
1857                                         <2 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
1858                         };
1859                         tsadc_gpio: tsadc-gpio {
1860                                 rockchip,pins =
1861                                         <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1862                         };
1863                 };
1864
1865                 hdmi_pin {
1866                         hdmi_cec: hdmi-cec {
1867                                 rockchip,pins =
1868                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
1869                         };
1870
1871                         hdmi_hpd: hdmi-hpd {
1872                                 rockchip,pins =
1873                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_down>;
1874                         };
1875                 };
1876
1877                 cif-0 {
1878                         dvp_d2d9_m0:dvp-d2d9-m0 {
1879                                 rockchip,pins =
1880                                         /* cif_d0 */
1881                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1882                                         /* cif_d1 */
1883                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1884                                         /* cif_d2 */
1885                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_none>,
1886                                         /* cif_d3 */
1887                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>,
1888                                         /* cif_d4 */
1889                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1890                                         /* cif_d5m0 */
1891                                         <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>,
1892                                         /* cif_d6m0 */
1893                                         <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>,
1894                                         /* cif_d7m0 */
1895                                         <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
1896                                         /* cif_href */
1897                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>,
1898                                         /* cif_vsync */
1899                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_none>,
1900                                         /* cif_clkoutm0 */
1901                                         <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>,
1902                                         /* cif_clkin */
1903                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1904                         };
1905                 };
1906
1907                 cif-1 {
1908                         dvp_d2d9_m1:dvp-d2d9-m1 {
1909                                 rockchip,pins =
1910                                         /* cif_d0 */
1911                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1912                                         /* cif_d1 */
1913                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1914                                         /* cif_d2 */
1915                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_none>,
1916                                         /* cif_d3 */
1917                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>,
1918                                         /* cif_d4 */
1919                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1920                                         /* cif_d5m1 */
1921                                         <2 RK_PC0 RK_FUNC_4 &pcfg_pull_none>,
1922                                         /* cif_d6m1 */
1923                                         <2 RK_PC1 RK_FUNC_4 &pcfg_pull_none>,
1924                                         /* cif_d7m1 */
1925                                         <2 RK_PC2 RK_FUNC_4 &pcfg_pull_none>,
1926                                         /* cif_href */
1927                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>,
1928                                         /* cif_vsync */
1929                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_none>,
1930                                         /* cif_clkoutm1 */
1931                                         <2 RK_PB7 RK_FUNC_4 &pcfg_pull_none>,
1932                                         /* cif_clkin */
1933                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1934                         };
1935                 };
1936         };
1937 };