arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3328";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67         };
  68
  69         cpus {
  70                 #address-cells = <2>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53", "arm,armv8";
  76                         reg = <0x0 0x0>;
  77                         enable-method = "psci";
  78                         clocks = <&cru ARMCLK>;
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                 };
  81                 cpu1: cpu@1 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a53", "arm,armv8";
  84                         reg = <0x0 0x1>;
  85                         enable-method = "psci";
  86                         operating-points-v2 = <&cpu0_opp_table>;
  87                 };
  88                 cpu2: cpu@2 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a53", "arm,armv8";
  91                         reg = <0x0 0x2>;
  92                         enable-method = "psci";
  93                         operating-points-v2 = <&cpu0_opp_table>;
  94                 };
  95                 cpu3: cpu@3 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a53", "arm,armv8";
  98                         reg = <0x0 0x3>;
  99                         enable-method = "psci";
 100                         operating-points-v2 = <&cpu0_opp_table>;
 101                 };
 102         };
 103
 104         cpu0_opp_table: opp_table0 {
 105                 compatible = "operating-points-v2";
 106                 opp-shared;
 107
 108                 opp@408000000 {
 109                         opp-hz = /bits/ 64 <408000000>;
 110                         opp-microvolt = <950000>;
 111                         clock-latency-ns = <40000>;
 112                         opp-suspend;
 113                 };
 114                 opp@600000000 {
 115                         opp-hz = /bits/ 64 <600000000>;
 116                         opp-microvolt = <950000>;
 117                         clock-latency-ns = <40000>;
 118                 };
 119                 opp@816000000 {
 120                         opp-hz = /bits/ 64 <816000000>;
 121                         opp-microvolt = <1000000>;
 122                         clock-latency-ns = <40000>;
 123                 };
 124                 opp@1008000000 {
 125                         opp-hz = /bits/ 64 <1008000000>;
 126                         opp-microvolt = <1100000>;
 127                         clock-latency-ns = <40000>;
 128                 };
 129                 opp@1200000000 {
 130                         opp-hz = /bits/ 64 <1200000000>;
 131                         opp-microvolt = <1225000>;
 132                         clock-latency-ns = <40000>;
 133                 };
 134                 opp@1296000000 {
 135                         opp-hz = /bits/ 64 <1296000000>;
 136                         opp-microvolt = <1300000>;
 137                         clock-latency-ns = <40000>;
 138                 };
 139         };
 140
 141         arm-pmu {
 142                 compatible = "arm,cortex-a53-pmu";
 143                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 144                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 147                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 148         };
 149
 150         psci {
 151                 compatible = "arm,psci-1.0";
 152                 method = "smc";
 153         };
 154
 155         timer {
 156                 compatible = "arm,armv8-timer";
 157                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 158                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 159                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 160                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 161         };
 162
 163         xin24m: xin24m {
 164                 compatible = "fixed-clock";
 165                 #clock-cells = <0>;
 166                 clock-frequency = <24000000>;
 167                 clock-output-names = "xin24m";
 168         };
 169
 170         i2s0: i2s@ff000000 {
 171                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 172                 reg = <0x0 0xff000000 0x0 0x1000>;
 173                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 174                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 175                 clock-names = "i2s_clk", "i2s_hclk";
 176                 dmas = <&dmac 11>, <&dmac 12>;
 177                 #dma-cells = <2>;
 178                 dma-names = "tx", "rx";
 179                 status = "disabled";
 180         };
 181
 182         i2s1: i2s@ff010000 {
 183                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 184                 reg = <0x0 0xff010000 0x0 0x1000>;
 185                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 186                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 187                 clock-names = "i2s_clk", "i2s_hclk";
 188                 dmas = <&dmac 14>, <&dmac 15>;
 189                 #dma-cells = <2>;
 190                 dma-names = "tx", "rx";
 191                 status = "disabled";
 192         };
 193
 194         i2s2: i2s@ff020000 {
 195                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 196                 reg = <0x0 0xff020000 0x0 0x1000>;
 197                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 198                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 199                 clock-names = "i2s_clk", "i2s_hclk";
 200                 dmas = <&dmac 0>, <&dmac 1>;
 201                 #dma-cells = <2>;
 202                 dma-names = "tx", "rx";
 203                 pinctrl-names = "default", "sleep";
 204                 pinctrl-0 = <&i2s2m0_mclk
 205                              &i2s2m0_sclk
 206                              &i2s2m0_lrcktx
 207                              &i2s2m0_lrckrx
 208                              &i2s2m0_sdo
 209                              &i2s2m0_sdi>;
 210                 pinctrl-1 = <&i2s2m0_sleep>;
 211                 status = "disabled";
 212         };
 213
 214         spdif: spdif@ff030000 {
 215                 compatible = "rockchip,rk3328-spdif";
 216                 reg = <0x0 0xff030000 0x0 0x1000>;
 217                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 219                 clock-names = "mclk", "hclk";
 220                 dmas = <&dmac 10>;
 221                 #dma-cells = <1>;
 222                 dma-names = "tx";
 223                 pinctrl-names = "default";
 224                 pinctrl-0 = <&spdifm2_tx>;
 225                 status = "disabled";
 226         };
 227
 228         grf: syscon@ff100000 {
 229                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 230                 reg = <0x0 0xff100000 0x0 0x1000>;
 231                 #address-cells = <1>;
 232                 #size-cells = <1>;
 233
 234                 io_domains: io-domains {
 235                         compatible = "rockchip,rk3328-io-voltage-domain";
 236                         status = "disabled";
 237                 };
 238
 239                 power: power-controller {
 240                         compatible = "rockchip,rk3328-power-controller";
 241                         #power-domain-cells = <1>;
 242                         #address-cells = <1>;
 243                         #size-cells = <0>;
 244                         status = "disabled";
 245
 246                         pd_hevc@RK3328_PD_HEVC {
 247                                 reg = <RK3328_PD_HEVC>;
 248                         };
 249                         pd_video@RK3328_PD_VIDEO {
 250                                 reg = <RK3328_PD_VIDEO>;
 251                         };
 252                         pd_vpu@RK3328_PD_VPU {
 253                                 reg = <RK3328_PD_VPU>;
 254                         };
 255                 };
 256
 257                 reboot-mode {
 258                         compatible = "syscon-reboot-mode";
 259                         offset = <0x5c8>;
 260                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 261                         mode-charge = <BOOT_CHARGING>;
 262                         mode-fastboot = <BOOT_FASTBOOT>;
 263                         mode-loader = <BOOT_BL_DOWNLOAD>;
 264                         mode-normal = <BOOT_NORMAL>;
 265                         mode-recovery = <BOOT_RECOVERY>;
 266                         mode-ums = <BOOT_UMS>;
 267                 };
 268         };
 269
 270         thermal-zones {
 271                 soc_thermal: soc-thermal {
 272                         polling-delay-passive = <20>; /* milliseconds */
 273                         polling-delay = <1000>; /* milliseconds */
 274                         sustainable-power = <1000>; /* milliwatts */
 275
 276                         thermal-sensors = <&tsadc 0>;
 277
 278                         trips {
 279                                 threshold: trip-point@0 {
 280                                         temperature = <70000>; /* millicelsius */
 281                                         hysteresis = <2000>; /* millicelsius */
 282                                         type = "passive";
 283                                 };
 284                                 target: trip-point@1 {
 285                                         temperature = <85000>; /* millicelsius */
 286                                         hysteresis = <2000>; /* millicelsius */
 287                                         type = "passive";
 288                                 };
 289                                 soc_crit: soc-crit {
 290                                         temperature = <95000>; /* millicelsius */
 291                                         hysteresis = <2000>; /* millicelsius */
 292                                         type = "critical";
 293                                 };
 294                         };
 295
 296                 };
 297
 298         };
 299
 300         tsadc: tsadc@ff250000 {
 301                 compatible = "rockchip,rk3328-tsadc";
 302                 reg = <0x0 0xff250000 0x0 0x100>;
 303                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
 304                 rockchip,grf = <&grf>;
 305                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 306                 clock-names = "tsadc", "apb_pclk";
 307                 assigned-clocks = <&cru SCLK_TSADC>;
 308                 assigned-clock-rates = <50000>;
 309                 resets = <&cru SRST_TSADC>;
 310                 reset-names = "tsadc-apb";
 311                 pinctrl-names = "init", "default", "sleep";
 312                 pinctrl-0 = <&otp_gpio>;
 313                 pinctrl-1 = <&otp_out>;
 314                 pinctrl-2 = <&otp_gpio>;
 315                 #thermal-sensor-cells = <1>;
 316                 rockchip,hw-tshut-temp = <100000>;
 317                 status = "disabled";
 318         };
 319
 320         uart0: serial@ff110000 {
 321                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 322                 reg = <0x0 0xff110000 0x0 0x100>;
 323                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 324                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 325                 clock-names = "baudclk", "apb_pclk";
 326                 reg-shift = <2>;
 327                 reg-io-width = <4>;
 328                 dmas = <&dmac 2>, <&dmac 3>;
 329                 #dma-cells = <2>;
 330                 pinctrl-names = "default";
 331                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 332                 status = "disabled";
 333         };
 334
 335         uart1: serial@ff120000 {
 336                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 337                 reg = <0x0 0xff120000 0x0 0x100>;
 338                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 339                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 340                 clock-names = "sclk_uart", "pclk_uart";
 341                 reg-shift = <2>;
 342                 reg-io-width = <4>;
 343                 dmas = <&dmac 4>, <&dmac 5>;
 344                 #dma-cells = <2>;
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 347                 status = "disabled";
 348         };
 349
 350         uart2: serial@ff130000 {
 351                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 352                 reg = <0x0 0xff130000 0x0 0x100>;
 353                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 355                 clock-names = "baudclk", "apb_pclk";
 356                 reg-shift = <2>;
 357                 reg-io-width = <4>;
 358                 dmas = <&dmac 6>, <&dmac 7>;
 359                 #dma-cells = <2>;
 360                 pinctrl-names = "default";
 361                 pinctrl-0 = <&uart2m1_xfer>;
 362                 status = "disabled";
 363         };
 364
 365         pmu: power-management@ff140000 {
 366                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 367                 reg = <0x0 0xff140000 0x0 0x1000>;
 368         };
 369
 370         i2c0: i2c@ff150000 {
 371                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 372                 reg = <0x0 0xff150000 0x0 0x1000>;
 373                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 377                 clock-names = "i2c", "pclk";
 378                 pinctrl-names = "default";
 379                 pinctrl-0 = <&i2c0_xfer>;
 380                 status = "disabled";
 381         };
 382
 383         i2c1: i2c@ff160000 {
 384                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 385                 reg = <0x0 0xff160000 0x0 0x1000>;
 386                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 390                 clock-names = "i2c", "pclk";
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&i2c1_xfer>;
 393                 status = "disabled";
 394         };
 395
 396         i2c2: i2c@ff170000 {
 397                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 398                 reg = <0x0 0xff170000 0x0 0x1000>;
 399                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 403                 clock-names = "i2c", "pclk";
 404                 pinctrl-names = "default";
 405                 pinctrl-0 = <&i2c2_xfer>;
 406                 status = "disabled";
 407         };
 408
 409         i2c3: i2c@ff180000 {
 410                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 411                 reg = <0x0 0xff180000 0x0 0x1000>;
 412                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 413                 #address-cells = <1>;
 414                 #size-cells = <0>;
 415                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 416                 clock-names = "i2c", "pclk";
 417                 pinctrl-names = "default";
 418                 pinctrl-0 = <&i2c3_xfer>;
 419                 status = "disabled";
 420         };
 421
 422         spi0: spi@ff190000 {
 423                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 424                 reg = <0x0 0xff190000 0x0 0x1000>;
 425                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 426                 #address-cells = <1>;
 427                 #size-cells = <0>;
 428                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 429                 clock-names = "spiclk", "apb_pclk";
 430                 dmas = <&dmac 8>, <&dmac 9>;
 431                 #dma-cells = <2>;
 432                 dma-names = "tx", "rx";
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 435                 status = "disabled";
 436         };
 437
 438         wdt: watchdog@ff1a0000 {
 439                 compatible = "snps,dw-wdt";
 440                 reg = <0x0 0xff1a0000 0x0 0x100>;
 441                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 442                 status = "disabled";
 443         };
 444
 445         pwm0: pwm@ff1b0000 {
 446                 compatible = "rockchip,rk3328-pwm";
 447                 reg = <0x0 0xff1b0000 0x0 0x10>;
 448                 #pwm-cells = <3>;
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&pwm0_pin>;
 451                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 452                 clock-names = "pwm", "pclk";
 453                 status = "disabled";
 454         };
 455
 456         pwm1: pwm@ff1b0010 {
 457                 compatible = "rockchip,rk3328-pwm";
 458                 reg = <0x0 0xff1b0010 0x0 0x10>;
 459                 #pwm-cells = <3>;
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&pwm1_pin>;
 462                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 463                 clock-names = "pwm", "pclk";
 464                 status = "disabled";
 465         };
 466
 467         pwm2: pwm@ff1b0020 {
 468                 compatible = "rockchip,rk3328-pwm";
 469                 reg = <0x0 0xff1b0020 0x0 0x10>;
 470                 #pwm-cells = <3>;
 471                 pinctrl-names = "default";
 472                 pinctrl-0 = <&pwm2_pin>;
 473                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 474                 clock-names = "pwm", "pclk";
 475                 status = "disabled";
 476         };
 477
 478         pwm3: pwm@ff1b0030 {
 479                 compatible = "rockchip,rk3328-pwm";
 480                 reg = <0x0 0xff1b0030 0x0 0x10>;
 481                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 482                 #pwm-cells = <3>;
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&pwmir_pin>;
 485                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 486                 clock-names = "pwm", "pclk";
 487                 status = "disabled";
 488         };
 489
 490         amba {
 491                 compatible = "simple-bus";
 492                 #address-cells = <2>;
 493                 #size-cells = <2>;
 494                 ranges;
 495
 496                 dmac: dmac@ff1f0000 {
 497                         compatible = "arm,pl330", "arm,primecell";
 498                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 499                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 500                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 501                         clocks = <&cru ACLK_DMAC>;
 502                         clock-names = "apb_pclk";
 503                         #dma-cells = <1>;
 504                 };
 505         };
 506
 507         saradc: saradc@ff280000 {
 508                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 509                 reg = <0x0 0xff280000 0x0 0x100>;
 510                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 511                 #io-channel-cells = <1>;
 512                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 513                 clock-names = "saradc", "apb_pclk";
 514                 resets = <&cru SRST_SARADC_P>;
 515                 reset-names = "saradc-apb";
 516                 status = "disabled";
 517         };
 518
 519         cru: clock-controller@ff440000 {
 520                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 521                 reg = <0x0 0xff440000 0x0 0x1000>;
 522                 rockchip,grf = <&grf>;
 523                 #clock-cells = <1>;
 524                 #reset-cells = <1>;
 525                 assigned-clocks =
 526                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 527                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 528                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 529                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 530                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 531                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 532                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 533                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 534                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 535                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 536                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 537                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 538                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 539                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 540                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 541                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 542                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 543                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 544                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 545                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 546                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 547                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 548                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 549                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 550                 assigned-clock-parents =
 551                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 552                         <&cru PLL_GPLL>, <&xin24m>,
 553                         <&xin24m>, <&xin24m>;
 554                 assigned-clock-rates =
 555                         <0>, <61440000>,
 556                         <0>, <24000000>,
 557                         <24000000>, <24000000>,
 558                         <15000000>, <15000000>,
 559                         <100000000>, <100000000>,
 560                         <100000000>, <100000000>,
 561                         <50000000>, <100000000>,
 562                         <100000000>, <100000000>,
 563                         <50000000>, <50000000>,
 564                         <50000000>, <50000000>,
 565                         <24000000>, <600000000>,
 566                         <491520000>, <1200000000>,
 567                         <150000000>, <75000000>,
 568                         <75000000>, <150000000>,
 569                         <75000000>, <75000000>,
 570                         <300000000>, <100000000>,
 571                         <300000000>, <200000000>,
 572                         <400000000>, <500000000>,
 573                         <200000000>, <300000000>,
 574                         <300000000>, <250000000>,
 575                         <200000000>, <100000000>,
 576                         <24000000>, <100000000>,
 577                         <150000000>, <50000000>,
 578                         <32768>, <32768>;
 579         };
 580
 581         usb2phy_grf: syscon@ff450000 {
 582                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 583                              "simple-mfd";
 584                 reg = <0x0 0xff450000 0x0 0x10000>;
 585                 #address-cells = <1>;
 586                 #size-cells = <1>;
 587
 588                 u2phy: usb2-phy@100 {
 589                         compatible = "rockchip,rk3328-usb2phy";
 590                         reg = <0x100 0x10>;
 591                         clocks = <&xin24m>;
 592                         clock-names = "phyclk";
 593                         #clock-cells = <0>;
 594                         assigned-clocks = <&cru USB480M>;
 595                         assigned-clock-parents = <&u2phy>;
 596                         clock-output-names = "usb480m_phy";
 597                         status = "disabled";
 598
 599                         u2phy_host: host-port {
 600                                 #phy-cells = <0>;
 601                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 602                                 interrupt-names = "linestate";
 603                                 status = "disabled";
 604                         };
 605
 606                         u2phy_otg: otg-port {
 607                                 #phy-cells = <0>;
 608                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 609                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 610                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 611                                 interrupt-names = "otg-bvalid", "otg-id",
 612                                                   "linestate";
 613                                 status = "disabled";
 614                         };
 615                 };
 616         };
 617
 618         usb3phy_grf: syscon@ff460000 {
 619                 compatible = "rockchip,usb3phy-grf", "syscon";
 620                 reg = <0x0 0xff460000 0x0 0x1000>;
 621         };
 622
 623         u3phy: usb3-phy@ff470000 {
 624                 compatible = "rockchip,rk3328-u3phy";
 625                 reg = <0x0 0xff470000 0x0 0x0>;
 626                 rockchip,u3phygrf = <&usb3phy_grf>;
 627                 rockchip,grf = <&grf>;
 628                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 629                 interrupt-names = "linestate";
 630                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
 631                 clock-names = "u3phy-otg", "u3phy-pipe";
 632                 resets = <&cru SRST_USB3PHY_U2>,
 633                          <&cru SRST_USB3PHY_U3>,
 634                          <&cru SRST_USB3PHY_PIPE>,
 635                          <&cru SRST_USB3OTG_UTMI>,
 636                          <&cru SRST_USB3PHY_OTG_P>,
 637                          <&cru SRST_USB3PHY_PIPE_P>;
 638                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
 639                               "u3phy-pipe-mac", "u3phy-utmi-mac",
 640                               "u3phy-utmi-apb", "u3phy-pipe-apb";
 641                 #address-cells = <2>;
 642                 #size-cells = <2>;
 643                 ranges;
 644                 status = "disabled";
 645
 646                 u3phy_utmi: utmi@ff470000 {
 647                         reg = <0x0 0xff470000 0x0 0x8000>;
 648                         #phy-cells = <0>;
 649                         status = "disabled";
 650                 };
 651
 652                 u3phy_pipe: pipe@ff478000 {
 653                         reg = <0x0 0xff478000 0x0 0x8000>;
 654                         #phy-cells = <0>;
 655                         status = "disabled";
 656                 };
 657         };
 658
 659         sdmmc: rksdmmc@ff500000 {
 660                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 661                 reg = <0x0 0xff500000 0x0 0x4000>;
 662                 clock-freq-min-max = <400000 150000000>;
 663                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 664                 clock-names = "biu", "ciu";
 665                 fifo-depth = <0x100>;
 666                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 667                 status = "disabled";
 668         };
 669
 670         sdio: dwmmc@ff510000 {
 671                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 672                 reg = <0x0 0xff510000 0x0 0x4000>;
 673                 clock-freq-min-max = <400000 150000000>;
 674                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 675                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 676                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 677                 fifo-depth = <0x100>;
 678                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 679                 status = "disabled";
 680         };
 681
 682         emmc: rksdmmc@ff520000 {
 683                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 684                 reg = <0x0 0xff520000 0x0 0x4000>;
 685                 clock-freq-min-max = <400000 150000000>;
 686                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 687                 clock-names = "biu", "ciu";
 688                 fifo-depth = <0x100>;
 689                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 690                 status = "disabled";
 691         };
 692
 693         gmac2io: eth@ff540000 {
 694                 compatible = "rockchip,rk3328-gmac";
 695                 reg = <0x0 0xff540000 0x0 0x10000>;
 696                 rockchip,grf = <&grf>;
 697                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 698                 interrupt-names = "macirq";
 699                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 700                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 701                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 702                          <&cru PCLK_MAC2IO>;
 703                 clock-names = "stmmaceth", "mac_clk_rx",
 704                               "mac_clk_tx", "clk_mac_ref",
 705                               "clk_mac_refout", "aclk_mac",
 706                               "pclk_mac";
 707                 resets = <&cru SRST_GMAC2IO_A>;
 708                 reset-names = "stmmaceth";
 709                 status = "disabled";
 710         };
 711
 712         usb20_otg: usb@ff580000 {
 713                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 714                              "snps,dwc2";
 715                 reg = <0x0 0xff580000 0x0 0x40000>;
 716                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 717                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 718                 clock-names = "otg", "otg_pmu";
 719                 dr_mode = "otg";
 720                 g-np-tx-fifo-size = <16>;
 721                 g-rx-fifo-size = <275>;
 722                 g-tx-fifo-size = <256 128 128 64 64 32>;
 723                 g-use-dma;
 724                 phys = <&u2phy_otg>;
 725                 phy-names = "usb2-phy";
 726                 status = "disabled";
 727         };
 728
 729         usb_host0_ehci: usb@ff5c0000 {
 730                 compatible = "generic-ehci";
 731                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 732                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 733                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 734                          <&u2phy>;
 735                 clock-names = "usbhost", "arbiter", "utmi";
 736                 phys = <&u2phy_host>;
 737                 phy-names = "usb";
 738                 status = "disabled";
 739         };
 740
 741         usb_host0_ohci: usb@ff5d0000 {
 742                 compatible = "generic-ohci";
 743                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 744                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 745                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 746                          <&u2phy>;
 747                 clock-names = "usbhost", "arbiter", "utmi";
 748                 phys = <&u2phy_host>;
 749                 phy-names = "usb";
 750                 status = "disabled";
 751         };
 752
 753         sdmmc_ext: rksdmmc@ff5f0000 {
 754                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 755                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 756                 clock-freq-min-max = <400000 150000000>;
 757                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 758                 clock-names = "biu", "ciu";
 759                 fifo-depth = <0x100>;
 760                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 761                 status = "disabled";
 762         };
 763
 764         usbdrd3: usb@ff600000 {
 765                 compatible = "rockchip,rk3328-dwc3";
 766                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
 767                          <&cru ACLK_USB3OTG>;
 768                 clock-names = "ref_clk", "suspend_clk",
 769                               "bus_clk";
 770                 #address-cells = <2>;
 771                 #size-cells = <2>;
 772                 ranges;
 773                 status = "disabled";
 774
 775                 usbdrd_dwc3: dwc3@ff600000 {
 776                         compatible = "snps,dwc3";
 777                         reg = <0x0 0xff600000 0x0 0x100000>;
 778                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 779                         dr_mode = "host";
 780                         phys = <&u3phy_utmi>, <&u3phy_pipe>;
 781                         phy-names = "usb2-phy", "usb3-phy";
 782                         phy_type = "utmi_wide";
 783                         snps,dis_enblslpm_quirk;
 784                         snps,dis-u2-freeclk-exists-quirk;
 785                         snps,dis_u2_susphy_quirk;
 786                         snps,dis-u3-autosuspend-quirk;
 787                         snps,dis_u3_susphy_quirk;
 788                         snps,dis-del-phy-power-chg-quirk;
 789                         status = "disabled";
 790                 };
 791         };
 792
 793         gic: interrupt-controller@ff811000 {
 794                 compatible = "arm,gic-400";
 795                 #interrupt-cells = <3>;
 796                 #address-cells = <0>;
 797                 interrupt-controller;
 798                 reg = <0x0 0xff811000 0 0x1000>,
 799                       <0x0 0xff812000 0 0x2000>,
 800                       <0x0 0xff814000 0 0x2000>,
 801                       <0x0 0xff816000 0 0x2000>;
 802                 interrupts = <GIC_PPI 9
 803                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 804         };
 805
 806         pinctrl: pinctrl {
 807                 compatible = "rockchip,rk3328-pinctrl";
 808                 rockchip,grf = <&grf>;
 809                 #address-cells = <2>;
 810                 #size-cells = <2>;
 811                 ranges;
 812
 813                 gpio0: gpio0@ff210000 {
 814                         compatible = "rockchip,gpio-bank";
 815                         reg = <0x0 0xff210000 0x0 0x100>;
 816                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 817                         clocks = <&cru PCLK_GPIO0>;
 818
 819                         gpio-controller;
 820                         #gpio-cells = <2>;
 821
 822                         interrupt-controller;
 823                         #interrupt-cells = <2>;
 824                 };
 825
 826                 gpio1: gpio1@ff220000 {
 827                         compatible = "rockchip,gpio-bank";
 828                         reg = <0x0 0xff220000 0x0 0x100>;
 829                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 830                         clocks = <&cru PCLK_GPIO1>;
 831
 832                         gpio-controller;
 833                         #gpio-cells = <2>;
 834
 835                         interrupt-controller;
 836                         #interrupt-cells = <2>;
 837                 };
 838
 839                 gpio2: gpio2@ff230000 {
 840                         compatible = "rockchip,gpio-bank";
 841                         reg = <0x0 0xff230000 0x0 0x100>;
 842                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 843                         clocks = <&cru PCLK_GPIO2>;
 844
 845                         gpio-controller;
 846                         #gpio-cells = <2>;
 847
 848                         interrupt-controller;
 849                         #interrupt-cells = <2>;
 850                 };
 851
 852                 gpio3: gpio3@ff240000 {
 853                         compatible = "rockchip,gpio-bank";
 854                         reg = <0x0 0xff240000 0x0 0x100>;
 855                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 856                         clocks = <&cru PCLK_GPIO3>;
 857
 858                         gpio-controller;
 859                         #gpio-cells = <2>;
 860
 861                         interrupt-controller;
 862                         #interrupt-cells = <2>;
 863                 };
 864
 865                 pcfg_pull_up: pcfg-pull-up {
 866                         bias-pull-up;
 867                 };
 868
 869                 pcfg_pull_down: pcfg-pull-down {
 870                         bias-pull-down;
 871                 };
 872
 873                 pcfg_pull_none: pcfg-pull-none {
 874                         bias-disable;
 875                 };
 876
 877                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 878                         bias-disable;
 879                         drive-strength = <2>;
 880                 };
 881
 882                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 883                         bias-pull-up;
 884                         drive-strength = <2>;
 885                 };
 886
 887                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 888                         bias-pull-up;
 889                         drive-strength = <4>;
 890                 };
 891
 892                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 893                         bias-disable;
 894                         drive-strength = <4>;
 895                 };
 896
 897                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 898                         bias-pull-down;
 899                         drive-strength = <4>;
 900                 };
 901
 902                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 903                         bias-disable;
 904                         drive-strength = <8>;
 905                 };
 906
 907                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 908                         bias-pull-up;
 909                         drive-strength = <8>;
 910                 };
 911
 912                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 913                         bias-disable;
 914                         drive-strength = <12>;
 915                 };
 916
 917                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 918                         bias-pull-up;
 919                         drive-strength = <12>;
 920                 };
 921
 922                 pcfg_output_high: pcfg-output-high {
 923                         output-high;
 924                 };
 925
 926                 pcfg_output_low: pcfg-output-low {
 927                         output-low;
 928                 };
 929
 930                 pcfg_input_high: pcfg-input-high {
 931                         bias-pull-up;
 932                         input-enable;
 933                 };
 934
 935                 pcfg_input: pcfg-input {
 936                         input-enable;
 937                 };
 938
 939                 i2c0 {
 940                         i2c0_xfer: i2c0-xfer {
 941                                 rockchip,pins =
 942                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 943                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 944                         };
 945                 };
 946
 947                 i2c1 {
 948                         i2c1_xfer: i2c1-xfer {
 949                                 rockchip,pins =
 950                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 951                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 952                         };
 953                 };
 954
 955                 i2c2 {
 956                         i2c2_xfer: i2c2-xfer {
 957                                 rockchip,pins =
 958                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 959                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 960                         };
 961                 };
 962
 963                 i2c3 {
 964                         i2c3_xfer: i2c3-xfer {
 965                                 rockchip,pins =
 966                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 967                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 968                         };
 969                         i2c3_gpio: i2c3-gpio {
 970                                 rockchip,pins =
 971                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 972                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 973                         };
 974                 };
 975
 976                 hdmi_i2c {
 977                         hdmii2c_xfer: hdmii2c-xfer {
 978                                 rockchip,pins =
 979                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 980                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 981                         };
 982                 };
 983
 984                 tsadc {
 985                         otp_gpio: otp-gpio {
 986                                 rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
 987                         };
 988
 989                         otp_out: otp-out {
 990                                 rockchip,pins = <2 13 RK_FUNC_1 &pcfg_pull_none>;
 991                         };
 992                 };
 993
 994                 uart0 {
 995                         uart0_xfer: uart0-xfer {
 996                                 rockchip,pins =
 997                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 998                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 999                         };
1000
1001                         uart0_cts: uart0-cts {
1002                                 rockchip,pins =
1003                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1004                         };
1005
1006                         uart0_rts: uart0-rts {
1007                                 rockchip,pins =
1008                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
1009                         };
1010
1011                         uart0_rts_gpio: uart0-rts-gpio {
1012                                 rockchip,pins =
1013                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
1014                         };
1015                 };
1016
1017                 uart1 {
1018                         uart1_xfer: uart1-xfer {
1019                                 rockchip,pins =
1020                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
1021                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
1022                         };
1023
1024                         uart1_cts: uart1-cts {
1025                                 rockchip,pins =
1026                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
1027                         };
1028
1029                         uart1_rts: uart1-rts {
1030                                 rockchip,pins =
1031                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
1032                         };
1033
1034                         uart1_rts_gpio: uart1-rts-gpio {
1035                                 rockchip,pins =
1036                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
1037                         };
1038                 };
1039
1040                 uart2-0 {
1041                         uart2m0_xfer: uart2m0-xfer {
1042                                 rockchip,pins =
1043                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
1044                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
1045                         };
1046                 };
1047
1048                 uart2-1 {
1049                         uart2m1_xfer: uart2m1-xfer {
1050                                 rockchip,pins =
1051                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
1052                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
1053                         };
1054                 };
1055
1056                 spi0-0 {
1057                         spi0m0_clk: spi0m0-clk {
1058                                 rockchip,pins =
1059                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
1060                         };
1061
1062                         spi0m0_cs0: spi0m0-cs0 {
1063                                 rockchip,pins =
1064                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1065                         };
1066
1067                         spi0m0_tx: spi0m0-tx {
1068                                 rockchip,pins =
1069                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1070                         };
1071
1072                         spi0m0_rx: spi0m0-rx {
1073                                 rockchip,pins =
1074                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1075                         };
1076
1077                         spi0m0_cs1: spi0m0-cs1 {
1078                                 rockchip,pins =
1079                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1080                         };
1081                 };
1082
1083                 spi0-1 {
1084                         spi0m1_clk: spi0m1-clk {
1085                                 rockchip,pins =
1086                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
1087                         };
1088
1089                         spi0m1_cs0: spi0m1-cs0 {
1090                                 rockchip,pins =
1091                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
1092                         };
1093
1094                         spi0m1_tx: spi0m1-tx {
1095                                 rockchip,pins =
1096                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
1097                         };
1098
1099                         spi0m1_rx: spi0m1-rx {
1100                                 rockchip,pins =
1101                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
1102                         };
1103
1104                         spi0m1_cs1: spi0m1-cs1 {
1105                                 rockchip,pins =
1106                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
1107                         };
1108                 };
1109
1110                 spi0-2 {
1111                         spi0m2_clk: spi0m2-clk {
1112                                 rockchip,pins =
1113                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
1114                         };
1115
1116                         spi0m2_cs0: spi0m2-cs0 {
1117                                 rockchip,pins =
1118                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
1119                         };
1120
1121                         spi0m2_tx: spi0m2-tx {
1122                                 rockchip,pins =
1123                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
1124                         };
1125
1126                         spi0m2_rx: spi0m2-rx {
1127                                 rockchip,pins =
1128                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
1129                         };
1130                 };
1131
1132                 i2s1 {
1133                         i2s1_mclk: i2s1-mclk {
1134                                 rockchip,pins =
1135                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
1136                         };
1137
1138                         i2s1_sclk: i2s1-sclk {
1139                                 rockchip,pins =
1140                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1141                         };
1142
1143                         i2s1_lrckrx: i2s1-lrckrx {
1144                                 rockchip,pins =
1145                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
1146                         };
1147
1148                         i2s1_lrcktx: i2s1-lrcktx {
1149                                 rockchip,pins =
1150                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1151                         };
1152
1153                         i2s1_sdi: i2s1-sdi {
1154                                 rockchip,pins =
1155                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1156                         };
1157
1158                         i2s1_sdo: i2s1-sdo {
1159                                 rockchip,pins =
1160                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
1161                         };
1162
1163                         i2s1_sdio1: i2s1-sdio1 {
1164                                 rockchip,pins =
1165                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
1166                         };
1167
1168                         i2s1_sdio2: i2s1-sdio2 {
1169                                 rockchip,pins =
1170                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
1171                         };
1172
1173                         i2s1_sdio3: i2s1-sdio3 {
1174                                 rockchip,pins =
1175                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
1176                         };
1177
1178                         i2s1_sleep: i2s1-sleep {
1179                                 rockchip,pins =
1180                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
1181                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
1182                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
1183                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
1184                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
1185                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
1186                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
1187                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
1188                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
1189                         };
1190                 };
1191
1192                 i2s2-0 {
1193                         i2s2m0_mclk: i2s2m0-mclk {
1194                                 rockchip,pins =
1195                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1196                         };
1197
1198                         i2s2m0_sclk: i2s2m0-sclk {
1199                                 rockchip,pins =
1200                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
1201                         };
1202
1203                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1204                                 rockchip,pins =
1205                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
1206                         };
1207
1208                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1209                                 rockchip,pins =
1210                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
1211                         };
1212
1213                         i2s2m0_sdi: i2s2m0-sdi {
1214                                 rockchip,pins =
1215                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
1216                         };
1217
1218                         i2s2m0_sdo: i2s2m0-sdo {
1219                                 rockchip,pins =
1220                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
1221                         };
1222
1223                         i2s2m0_sleep: i2s2m0-sleep {
1224                                 rockchip,pins =
1225                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1226                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
1227                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
1228                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
1229                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
1230                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
1231                         };
1232                 };
1233
1234                 i2s2-1 {
1235                         i2s2m1_mclk: i2s2m1-mclk {
1236                                 rockchip,pins =
1237                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1238                         };
1239
1240                         i2s2m1_sclk: i2s2m1-sclk {
1241                                 rockchip,pins =
1242                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
1243                         };
1244
1245                         i2s2m1_lrckrx: i2sm1-lrckrx {
1246                                 rockchip,pins =
1247                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
1248                         };
1249
1250                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1251                                 rockchip,pins =
1252                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
1253                         };
1254
1255                         i2s2m1_sdi: i2s2m1-sdi {
1256                                 rockchip,pins =
1257                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
1258                         };
1259
1260                         i2s2m1_sdo: i2s2m1-sdo {
1261                                 rockchip,pins =
1262                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
1263                         };
1264
1265                         i2s2m1_sleep: i2s2m1-sleep {
1266                                 rockchip,pins =
1267                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1268                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
1269                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
1270                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
1271                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
1272                         };
1273                 };
1274
1275                 spdif-0 {
1276                         spdifm0_tx: spdifm0-tx {
1277                                 rockchip,pins =
1278                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
1279                         };
1280                 };
1281
1282                 spdif-1 {
1283                         spdifm1_tx: spdifm1-tx {
1284                                 rockchip,pins =
1285                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1286                         };
1287                 };
1288
1289                 spdif-2 {
1290                         spdifm2_tx: spdifm2-tx {
1291                                 rockchip,pins =
1292                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
1293                         };
1294                 };
1295
1296                 sdmmc0-0 {
1297                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1298                                 rockchip,pins =
1299                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1300                         };
1301
1302                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1303                                 rockchip,pins =
1304                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1305                         };
1306                 };
1307
1308                 sdmmc0-1 {
1309                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1310                                 rockchip,pins =
1311                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1312                         };
1313
1314                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1315                                 rockchip,pins =
1316                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1317                         };
1318                 };
1319
1320                 sdmmc0 {
1321                         sdmmc0_clk: sdmmc0-clk {
1322                                 rockchip,pins =
1323                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1324                         };
1325
1326                         sdmmc0_cmd: sdmmc0-cmd {
1327                                 rockchip,pins =
1328                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1329                         };
1330
1331                         sdmmc0_dectn: sdmmc0-dectn {
1332                                 rockchip,pins =
1333                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1334                         };
1335
1336                         sdmmc0_wrprt: sdmmc0-wrprt {
1337                                 rockchip,pins =
1338                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1339                         };
1340
1341                         sdmmc0_bus1: sdmmc0-bus1 {
1342                                 rockchip,pins =
1343                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1344                         };
1345
1346                         sdmmc0_bus4: sdmmc0-bus4 {
1347                                 rockchip,pins =
1348                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1349                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1350                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1351                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1352                         };
1353
1354                         sdmmc0_gpio: sdmmc0-gpio {
1355                                 rockchip,pins =
1356                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1357                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1358                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1359                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1360                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1361                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1362                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1363                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1364                         };
1365                 };
1366
1367                 sdmmc0ext {
1368                         sdmmc0ext_clk: sdmmc0ext-clk {
1369                                 rockchip,pins =
1370                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1371                         };
1372
1373                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1374                                 rockchip,pins =
1375                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1376                         };
1377
1378                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1379                                 rockchip,pins =
1380                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1381                         };
1382
1383                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1384                                 rockchip,pins =
1385                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1386                         };
1387
1388                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1389                                 rockchip,pins =
1390                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1391                         };
1392
1393                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1394                                 rockchip,pins =
1395                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1396                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1397                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1398                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1399                         };
1400
1401                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1402                                 rockchip,pins =
1403                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1404                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1405                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1406                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1407                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1408                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1409                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1410                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1411                         };
1412                 };
1413
1414                 sdmmc1 {
1415                         sdmmc1_clk: sdmmc1-clk {
1416                                 rockchip,pins =
1417                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1418                         };
1419
1420                         sdmmc1_cmd: sdmmc1-cmd {
1421                                 rockchip,pins =
1422                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1423                         };
1424
1425                         sdmmc1_pwren: sdmmc1-pwren {
1426                                 rockchip,pins =
1427                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1428                         };
1429
1430                         sdmmc1_wrprt: sdmmc1-wrprt {
1431                                 rockchip,pins =
1432                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1433                         };
1434
1435                         sdmmc1_dectn: sdmmc1-dectn {
1436                                 rockchip,pins =
1437                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1438                         };
1439
1440                         sdmmc1_bus1: sdmmc1-bus1 {
1441                                 rockchip,pins =
1442                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1443                         };
1444
1445                         sdmmc1_bus4: sdmmc1-bus4 {
1446                                 rockchip,pins =
1447                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1448                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1449                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1450                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1451                         };
1452
1453                         sdmmc1_gpio: sdmmc1-gpio {
1454                                 rockchip,pins =
1455                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1456                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1457                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1458                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1459                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1460                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1461                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1462                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1463                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1464                         };
1465                 };
1466
1467                 emmc {
1468                         emmc_clk: emmc-clk {
1469                                 rockchip,pins =
1470                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1471                         };
1472
1473                         emmc_cmd: emmc-cmd {
1474                                 rockchip,pins =
1475                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1476                         };
1477
1478                         emmc_pwren: emmc-pwren {
1479                                 rockchip,pins =
1480                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1481                         };
1482
1483                         emmc_rstnout: emmc-rstnout {
1484                                 rockchip,pins =
1485                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1486                         };
1487
1488                         emmc_bus1: emmc-bus1 {
1489                                 rockchip,pins =
1490                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1491                         };
1492
1493                         emmc_bus4: emmc-bus4 {
1494                                 rockchip,pins =
1495                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1496                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1497                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1498                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1499                         };
1500
1501                         emmc_bus8: emmc-bus8 {
1502                                 rockchip,pins =
1503                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1504                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1505                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1506                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1507                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1508                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1509                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1510                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1511                         };
1512                 };
1513
1514                 pwm0 {
1515                         pwm0_pin: pwm0-pin {
1516                                 rockchip,pins =
1517                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1518                         };
1519                 };
1520
1521                 pwm1 {
1522                         pwm1_pin: pwm1-pin {
1523                                 rockchip,pins =
1524                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1525                         };
1526                 };
1527
1528                 pwm2 {
1529                         pwm2_pin: pwm2-pin {
1530                                 rockchip,pins =
1531                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1532                         };
1533                 };
1534
1535                 pwmir {
1536                         pwmir_pin: pwmir-pin {
1537                                 rockchip,pins =
1538                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1539                         };
1540                 };
1541
1542                 gmac-0 {
1543                         rgmiim0_pins: rgmiim0-pins {
1544                                 rockchip,pins =
1545                                         /* mac_txclk */
1546                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1547                                         /* mac_rxclk */
1548                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1549                                         /* mac_mdio */
1550                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1551                                         /* mac_txen */
1552                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1553                                         /* mac_clk */
1554                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1555                                         /* mac_rxdv */
1556                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1557                                         /* mac_mdc */
1558                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1559                                         /* mac_rxd1 */
1560                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1561                                         /* mac_rxd0 */
1562                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1563                                         /* mac_txd1 */
1564                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1565                                         /* mac_txd0 */
1566                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1567                                         /* mac_rxd3 */
1568                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1569                                         /* mac_rxd2 */
1570                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1571                                         /* mac_txd3 */
1572                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1573                                         /* mac_txd2 */
1574                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1575                         };
1576
1577                         rmiim0_pins: rmiim0-pins {
1578                                 rockchip,pins =
1579                                         /* mac_mdio */
1580                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1581                                         /* mac_txen */
1582                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1583                                         /* mac_clk */
1584                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1585                                         /* mac_rxer */
1586                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1587                                         /* mac_rxdv */
1588                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1589                                         /* mac_mdc */
1590                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1591                                         /* mac_rxd1 */
1592                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1593                                         /* mac_rxd0 */
1594                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1595                                         /* mac_txd1 */
1596                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1597                                         /* mac_txd0 */
1598                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1599                         };
1600                 };
1601
1602                 gmac-1 {
1603                         rgmiim1_pins: rgmiim1-pins {
1604                                 rockchip,pins =
1605                                         /* mac_txclk */
1606                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1607                                         /* mac_rxclk */
1608                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1609                                         /* mac_mdio */
1610                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1611                                         /* mac_txen */
1612                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1613                                         /* mac_clk */
1614                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1615                                         /* mac_rxdv */
1616                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1617                                         /* mac_mdc */
1618                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1619                                         /* mac_rxd1 */
1620                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1621                                         /* mac_rxd0 */
1622                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1623                                         /* mac_txd1 */
1624                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1625                                         /* mac_txd0 */
1626                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1627                                         /* mac_rxd3 */
1628                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1629                                         /* mac_rxd2 */
1630                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1631                                         /* mac_txd3 */
1632                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1633                                         /* mac_txd2 */
1634                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1635
1636                                         /* mac_txclk */
1637                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1638                                         /* mac_txen */
1639                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1640                                         /* mac_clk */
1641                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1642                                         /* mac_txd1 */
1643                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1644                                         /* mac_txd0 */
1645                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1646                                         /* mac_txd3 */
1647                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1648                                         /* mac_txd2 */
1649                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1650                         };
1651
1652                         rmiim1_pins: rmiim1-pins {
1653                                 rockchip,pins =
1654                                         /* mac_mdio */
1655                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1656                                         /* mac_txen */
1657                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1658                                         /* mac_clk */
1659                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1660                                         /* mac_rxer */
1661                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1662                                         /* mac_rxdv */
1663                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1664                                         /* mac_mdc */
1665                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1666                                         /* mac_rxd1 */
1667                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1668                                         /* mac_rxd0 */
1669                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1670                                         /* mac_txd1 */
1671                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1672                                         /* mac_txd0 */
1673                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1674
1675                                         /* mac_mdio */
1676                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1677                                         /* mac_txen */
1678                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1679                                         /* mac_clk */
1680                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1681                                         /* mac_mdc */
1682                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1683                                         /* mac_txd1 */
1684                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1685                                         /* mac_txd0 */
1686                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1687                         };
1688                 };
1689
1690                 gmac2phy {
1691                         fephyled_speed100: fephyled-speed100 {
1692                                 rockchip,pins =
1693                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1694                         };
1695
1696                         fephyled_speed10: fephyled-speed10 {
1697                                 rockchip,pins =
1698                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1699                         };
1700
1701                         fephyled_duplex: fephyled-duplex {
1702                                 rockchip,pins =
1703                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1704                         };
1705
1706                         fephyled_rxm0: fephyled-rxm0 {
1707                                 rockchip,pins =
1708                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1709                         };
1710
1711                         fephyled_txm0: fephyled-txm0 {
1712                                 rockchip,pins =
1713                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1714                         };
1715
1716                         fephyled_linkm0: fephyled-linkm0 {
1717                                 rockchip,pins =
1718                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1719                         };
1720
1721                         fephyled_rxm1: fephyled-rxm1 {
1722                                 rockchip,pins =
1723                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1724                         };
1725
1726                         fephyled_txm1: fephyled-txm1 {
1727                                 rockchip,pins =
1728                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1729                         };
1730
1731                         fephyled_linkm1: fephyled-linkm1 {
1732                                 rockchip,pins =
1733                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1734                         };
1735                 };
1736
1737                 tsadc_pin {
1738                         tsadc_int: tsadc-int {
1739                                 rockchip,pins =
1740                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1741                         };
1742                         tsadc_gpio: tsadc-gpio {
1743                                 rockchip,pins =
1744                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1745                         };
1746                 };
1747
1748                 hdmi_pin {
1749                         hdmi_cec: hdmi-cec {
1750                                 rockchip,pins =
1751                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1752                         };
1753
1754                         hdmi_hpd: hdmi-hpd {
1755                                 rockchip,pins =
1756                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1757                         };
1758                 };
1759
1760                 cif-0 {
1761                         dvp_d2d9_m0:dvp-d2d9-m0 {
1762                                 rockchip,pins =
1763                                         /* cif_d0 */
1764                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1765                                         /* cif_d1 */
1766                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1767                                         /* cif_d2 */
1768                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1769                                         /* cif_d3 */
1770                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1771                                         /* cif_d4 */
1772                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1773                                         /* cif_d5m0 */
1774                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1775                                         /* cif_d6m0 */
1776                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1777                                         /* cif_d7m0 */
1778                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1779                                         /* cif_href */
1780                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1781                                         /* cif_vsync */
1782                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1783                                         /* cif_clkoutm0 */
1784                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1785                                         /* cif_clkin */
1786                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1787                         };
1788                 };
1789
1790                 cif-1 {
1791                         dvp_d2d9_m1:dvp-d2d9-m1 {
1792                                 rockchip,pins =
1793                                         /* cif_d0 */
1794                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1795                                         /* cif_d1 */
1796                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1797                                         /* cif_d2 */
1798                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1799                                         /* cif_d3 */
1800                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1801                                         /* cif_d4 */
1802                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1803                                         /* cif_d5m1 */
1804                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1805                                         /* cif_d6m1 */
1806                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1807                                         /* cif_d7m1 */
1808                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1809                                         /* cif_href */
1810                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1811                                         /* cif_vsync */
1812                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1813                                         /* cif_clkoutm1 */
1814                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1815                                         /* cif_clkin */
1816                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1817                         };
1818                 };
1819         };
1820 };