arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 big0: cpu@100 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53", "arm,armv8";
  43                         reg = <0x0 0x100>;
  44                         enable-method = "psci";
  45                 };
  46                 big1: cpu@101 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         reg = <0x0 0x101>;
  50                         enable-method = "psci";
  51                 };
  52                 big2: cpu@102 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53", "arm,armv8";
  55                         reg = <0x0 0x102>;
  56                         enable-method = "psci";
  57                 };
  58                 big3: cpu@103 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x103>;
  62                         enable-method = "psci";
  63                 };
  64                 little0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53", "arm,armv8";
  67                         reg = <0x0 0x0>;
  68                         enable-method = "psci";
  69                 };
  70                 little1: cpu@1 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53", "arm,armv8";
  73                         reg = <0x0 0x1>;
  74                         enable-method = "psci";
  75                 };
  76                 little2: cpu@2 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53", "arm,armv8";
  79                         reg = <0x0 0x2>;
  80                         enable-method = "psci";
  81                 };
  82                 little3: cpu@3 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53", "arm,armv8";
  85                         reg = <0x0 0x3>;
  86                         enable-method = "psci";
  87                 };
  88
  89                 cpu-map {
  90                         cluster0 {
  91                                 core0 {
  92                                         cpu = <&big0>;
  93                                 };
  94                                 core1 {
  95                                         cpu = <&big1>;
  96                                 };
  97                                 core2 {
  98                                         cpu = <&big2>;
  99                                 };
 100                                 core3 {
 101                                         cpu = <&big3>;
 102                                 };
 103                         };
 104                         cluster1 {
 105                                 core0 {
 106                                         cpu = <&little0>;
 107                                 };
 108                                 core1 {
 109                                         cpu = <&little1>;
 110                                 };
 111                                 core2 {
 112                                         cpu = <&little2>;
 113                                 };
 114                                 core3 {
 115                                         cpu = <&little3>;
 116                                 };
 117                         };
 118                 };
 119         };
 120
 121         psci {
 122                 compatible = "arm,psci";
 123                 method = "smc";
 124                 cpu_on = <0xC4000003>;
 125         };
 126
 127         gic: interrupt-controller@ffb70000 {
 128                 compatible = "arm,cortex-a15-gic";
 129                 #interrupt-cells = <3>;
 130                 #address-cells = <0>;
 131                 interrupt-controller;
 132                 reg = <0x0 0xffb71000 0 0x1000>,
 133                       <0x0 0xffb72000 0 0x1000>;
 134         };
 135
 136         pmu: syscon@ff730000 {
 137                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 138                 reg = <0x0 0xff730000 0x0 0x1000>;
 139         };
 140
 141         pmugrf: syscon@ff738000 {
 142                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 143                 reg = <0x0 0xff738000 0x0 0x1000>;
 144         };
 145
 146         sgrf: syscon@ff740000 {
 147                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 148                 reg = <0x0 0xff740000 0x0 0x1000>;
 149
 150         };
 151
 152         cru: syscon@ff760000 {
 153                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 154                 reg = <0x0 0xff760000 0x0 0x1000>;
 155         };
 156
 157         grf: syscon@ff770000 {
 158                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 159                 reg = <0x0 0xff770000 0x0 0x1000>;
 160         };
 161
 162         arm-pmu {
 163                 compatible = "arm,armv8-pmuv3";
 164                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 172         };
 173
 174         cpu_axi_bus: cpu_axi_bus {
 175                 compatible = "rockchip,cpu_axi_bus";
 176                 #address-cells = <2>;
 177                 #size-cells = <2>;
 178                 ranges;
 179
 180                 qos {
 181                         #address-cells = <2>;
 182                         #size-cells = <2>;
 183                         ranges;
 184
 185                         dmac {
 186                                 reg = <0x0 0xffa80000 0x0 0x20>;
 187                         };
 188                         crypto {
 189                                 reg = <0x0 0xffa80080 0x0 0x20>;
 190                         };
 191                         bus_cpup {
 192                                 reg = <0x0 0xffa90000 0x0 0x20>;
 193                         };
 194                         cci_r {
 195                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 196                         };
 197                         cci_w {
 198                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 199                         };
 200                         peri {
 201                                 reg = <0x0 0xffab0000 0x0 0x20>;
 202                         };
 203                         iep {
 204                                 reg = <0x0 0xffad0000 0x0 0x20>;
 205                         };
 206                         isp_r0 {
 207                                 reg = <0x0 0xffad0080 0x0 0x20>;
 208                         };
 209                         isp_r1 {
 210                                 reg = <0x0 0xffad0100 0x0 0x20>;
 211                         };
 212                         isp_w0 {
 213                                 reg = <0x0 0xffad0180 0x0 0x20>;
 214                                 rockchip,priority = <2 2>;
 215                         };
 216                         isp_w1 {
 217                                 reg = <0x0 0xffad0200 0x0 0x20>;
 218                                 rockchip,priority = <2 2>;
 219                         };
 220                         vip {
 221                                 reg = <0x0 0xffad0280 0x0 0x20>;
 222                         };
 223                         vop {
 224                                 reg = <0x0 0xffad0300 0x0 0x20>;
 225                                 rockchip,priority = <2 2>;
 226                         };
 227                         rga_r {
 228                                 reg = <0x0 0xffad0380 0x0 0x20>;
 229                         };
 230                         rga_w {
 231                                 reg = <0x0 0xffad0400 0x0 0x20>;
 232                         };
 233                         hevc_r {
 234                                 reg = <0x0 0xffae0000 0x0 0x20>;
 235                         };
 236                         vpu_r {
 237                                 reg = <0x0 0xffae0080 0x0 0x20>;
 238                         };
 239                         vpu_w {
 240                                 reg = <0x0 0xffae0100 0x0 0x20>;
 241                         };
 242                 };
 243
 244                 msch {
 245                         #address-cells = <2>;
 246                         #size-cells = <2>;
 247                         ranges;
 248
 249                         msch {
 250                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 251                                 rockchip,read-latency = <0x34>;
 252                         };
 253                 };
 254         };
 255
 256         timer {
 257                 compatible = "arm,armv8-timer";
 258                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 259                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 260                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 261                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 262                 clock-frequency = <24000000>;
 263         };
 264
 265         timer@ff810000 {
 266                 compatible = "rockchip,timer";
 267                 reg = <0x0 0xff810000 0x0 0x20>;
 268                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 269                 rockchip,broadcast = <1>;
 270         };
 271
 272         sram: sram@ff8c0000 {
 273                 compatible = "mmio-sram";
 274                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 275                 map-exec;
 276         };
 277
 278         watchdog: wdt@ff800000 {
 279                 compatible = "rockchip,watch dog";
 280                 reg = <0x0 0xff800000 0x0 0x100>;
 281                 clocks = <&pclk_alive_pre>;
 282                 clock-names = "pclk_wdt";
 283                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 284                 rockchip,irq = <1>;
 285                 rockchip,timeout = <60>;
 286                 rockchip,atboot = <1>;
 287                 rockchip,debug = <0>;
 288                 status = "disabled";
 289         };
 290
 291         amba {
 292                 #address-cells = <2>;
 293                 #size-cells = <2>;
 294                 compatible = "arm,amba-bus";
 295                 interrupt-parent = <&gic>;
 296                 ranges;
 297
 298                 pdma0: pdma@ff600000 {
 299                         compatible = "arm,pl330", "arm,primecell";
 300                         reg = <0x0 0xff600000 0x0 0x4000>;
 301                         clocks = <&clk_gates12 11>;
 302                         clock-names = "apb_pclk";
 303                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 305                         #dma-cells = <1>;
 306
 307                 };
 308
 309                 pdma1: pdma@ff250000 {
 310                         compatible = "arm,pl330", "arm,primecell";
 311                         reg = <0x0 0xff250000 0x0 0x4000>;
 312                         clocks = <&clk_gates19 3>;
 313                         clock-names = "apb_pclk";
 314                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 315                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 316                         #dma-cells = <1>;
 317                 };
 318         };
 319
 320         reset: reset@ff760300{
 321                 compatible = "rockchip,reset";
 322                 reg = <0x0 0xff760300 0x0 0x38>;
 323                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 324                 #reset-cells = <1>;
 325         };
 326
 327         nandc0: nandc@ff400000 {
 328                 compatible = "rockchip,rk-nandc";
 329                 reg = <0x0 0xff400000 0x0 0x4000>;
 330                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 331                 nandc_id = <0>;
 332                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 333                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 334         };
 335
 336         nandc0reg: nandc0@ff400000 {
 337                 compatible = "rockchip,rk-nandc";
 338                 reg = <0x0 0xff400000 0x0 0x4000>;
 339         };
 340
 341         emmc: rksdmmc@ff0f0000 {
 342                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 343                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 344                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 345                 #address-cells = <1>;
 346                 #size-cells = <0>;
 347                 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
 348                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 349                 rockchip,grf = <&grf>;
 350                 num-slots = <1>;
 351                 fifo-depth = <0x100>;
 352                 bus-width = <8>;
 353         };
 354
 355         sdmmc: rksdmmc@ff0c0000 {
 356                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 357                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 358                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 pinctrl-names = "default", "idle";
 362                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 363                 pinctrl-1 = <&sdmmc_gpio>;
 364                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 365                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
 366                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 367                 rockchip,grf = <&grf>;
 368                 num-slots = <1>;
 369                 fifo-depth = <0x100>;
 370                 bus-width = <4>;
 371         };
 372
 373         sdio: rksdmmc@ff0d0000 {
 374                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 375                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 376                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379                 pinctrl-names = "default","idle";
 380                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 381                 pinctrl-1 = <&sdio0_gpio>;
 382                 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
 383                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 384                 rockchip,grf = <&grf>;
 385                 num-slots = <1>;
 386                 fifo-depth = <0x100>;
 387                 bus-width = <4>;
 388         };
 389
 390         spi0: spi@ff110000 {
 391                 compatible = "rockchip,rockchip-spi";
 392                 reg = <0x0 0xff110000 0x0 0x1000>;
 393                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 398                 rockchip,spi-src-clk = <0>;
 399                 num-cs = <2>;
 400                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 401                 clock-names = "spi", "pclk_spi0";
 402                 //dmas = <&pdma1 11>, <&pdma1 12>;
 403                 //#dma-cells = <2>;
 404                 //dma-names = "tx", "rx";
 405                 status = "disabled";
 406         };
 407
 408         spi1: spi@ff120000 {
 409                 compatible = "rockchip,rockchip-spi";
 410                 reg = <0x0 0xff120000 0x0 0x1000>;
 411                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 412                 #address-cells = <1>;
 413                 #size-cells = <0>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 416                 rockchip,spi-src-clk = <1>;
 417                 num-cs = <1>;
 418                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 419                 clock-names = "spi", "pclk_spi1";
 420                 //dmas = <&pdma1 13>, <&pdma1 14>;
 421                 //#dma-cells = <2>;
 422                 //dma-names = "tx", "rx";
 423                 status = "disabled";
 424         };
 425
 426         spi2: spi@ff130000 {
 427                 compatible = "rockchip,rockchip-spi";
 428                 reg = <0x0 0xff130000 0x0 0x1000>;
 429                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 434                 rockchip,spi-src-clk = <2>;
 435                 num-cs = <1>;
 436                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 437                 clock-names = "spi", "pclk_spi2";
 438                 //dmas = <&pdma1 15>, <&pdma1 16>;
 439                 //#dma-cells = <2>;
 440                 //dma-names = "tx", "rx";
 441                 status = "disabled";
 442         };
 443
 444         uart_bt: serial@ff180000 {
 445                 compatible = "rockchip,serial";
 446                 reg = <0x0 0xff180000 0x0 0x100>;
 447                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 448                 clock-frequency = <24000000>;
 449                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 450                 clock-names = "sclk_uart", "pclk_uart";
 451                 reg-shift = <2>;
 452                 reg-io-width = <4>;
 453                 //dmas = <&pdma1 1>, <&pdma1 2>;
 454                 //#dma-cells = <2>;
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 457                 status = "disabled";
 458         };
 459
 460         uart_bb: serial@ff190000 {
 461                 compatible = "rockchip,serial";
 462                 reg = <0x0 0xff190000 0x0 0x100>;
 463                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 464                 clock-frequency = <24000000>;
 465                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 466                 clock-names = "sclk_uart", "pclk_uart";
 467                 reg-shift = <2>;
 468                 reg-io-width = <4>;
 469                 //dmas = <&pdma1 3>, <&pdma1 4>;
 470                 //#dma-cells = <2>;
 471                 pinctrl-names = "default";
 472                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 473                 status = "disabled";
 474         };
 475
 476         uart_dbg: serial@ff690000 {
 477                 compatible = "rockchip,serial";
 478                 reg = <0x0 0xff690000 0x0 0x100>;
 479                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 480                 clock-frequency = <24000000>;
 481                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 482                 clock-names = "sclk_uart", "pclk_uart";
 483                 reg-shift = <2>;
 484                 reg-io-width = <4>;
 485                 //dmas = <&pdma0 4>, <&pdma0 5>;
 486                 //#dma-cells = <2>;
 487                 //pinctrl-names = "default";
 488                 //pinctrl-0 = <&uart2_xfer>;
 489                 status = "disabled";
 490         };
 491
 492         uart_gps: serial@ff1b0000 {
 493                 compatible = "rockchip,serial";
 494                 reg = <0x0 0xff1b0000 0x0 0x100>;
 495                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 496                 clock-frequency = <24000000>;
 497                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 498                 clock-names = "sclk_uart", "pclk_uart";
 499                 current-speed = <115200>;
 500                 reg-shift = <2>;
 501                 reg-io-width = <4>;
 502                 //dmas = <&pdma1 7>, <&pdma1 8>;
 503                 //#dma-cells = <2>;
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 506                 status = "disabled";
 507         };
 508
 509         uart_exp: serial@ff1c0000 {
 510                 compatible = "rockchip,serial";
 511                 reg = <0x0 0xff1c0000 0x0 0x100>;
 512                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 513                 clock-frequency = <24000000>;
 514                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 515                 clock-names = "sclk_uart", "pclk_uart";
 516                 reg-shift = <2>;
 517                 reg-io-width = <4>;
 518                 //dmas = <&pdma1 9>, <&pdma1 10>;
 519                 //#dma-cells = <2>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 522                 status = "disabled";
 523         };
 524
 525         rockchip_clocks_init: clocks-init{
 526                 compatible = "rockchip,clocks-init";
 527                 rockchip,clocks-init-parent =
 528                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 529                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 530                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 531                         <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
 532                 rockchip,clocks-init-rate =
 533                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 534                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 535                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 536                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 537                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 538                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 539                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 540                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 541                         <&aclk_cci 600000000>,          <&clk_mac 125000000>,
 542                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 543                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 544                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 545                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 546                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 547                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 548                         <&clk_hevc_cabac 300000000>;
 549 /*
 550                 rockchip,clocks-uboot-has-init =
 551                         <&aclk_vio0>;
 552 */
 553         };
 554
 555         rockchip_clocks_enable: clocks-enable {
 556                 compatible = "rockchip,clocks-enable";
 557                 clocks =
 558                 <&pd_vio>,
 559                <&pd_video>,
 560                <&pd_gpu_0>,
 561                <&pd_gpu_1>,
 562
 563                         /*PLL*/
 564                         <&clk_apllb>,
 565                         <&clk_aplll>,
 566                         <&clk_dpll>,
 567                         <&clk_gpll>,
 568                         <&clk_cpll>,
 569
 570                         /*PD_CORE*/
 571                         <&clk_cs>,
 572                         <&clkin_trace>,
 573                         <&aclk_cci>,
 574
 575                         /*PD_BUS*/
 576                         <&aclk_bus>,
 577                         <&hclk_bus>,
 578                         <&pclk_bus>,
 579                         <&clk_gates12 12>,/*aclk_strc_sys*/
 580                         <&clk_gates12 6>,/*aclk_intmem1*/
 581                         <&clk_gates12 5>,/*aclk_intmem0*/
 582                         <&clk_gates12 4>,/*aclk_intmem*/
 583                         <&clk_gates13 9>,/*aclk_gic400*/
 584
 585                         /*PD_ALIVE*/
 586                         <&clk_gates22 13>,/*pclk_timer1*/
 587                         <&clk_gates22 12>,/*pclk_timer0*/
 588                         <&clk_gates22 9>,/*pclk_alive_niu*/
 589                         <&clk_gates22 8>,/*pclk_grf*/
 590
 591                         /*PD_PMU*/
 592                         <&clk_gates23 5>,/*pclk_pmugrf*/
 593                         <&clk_gates23 3>,/*pclk_sgrf*/
 594                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 595                         <&clk_gates23 1>,/*pclk_intmem1*/
 596                         <&clk_gates23 0>,/*pclk_pmu*/
 597
 598                         /*PD_PERI*/
 599                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 600                         <&clk_gates20 8>,/*aclk_peri_niu*/
 601                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 602                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 603                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 604                         <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
 605         };
 606
 607         /* I2C_PMU */
 608         i2c0: i2c@ff650000 {
 609                 compatible = "rockchip,rk30-i2c";
 610                 reg = <0x0 0xff650000 0x0 0x1000>;
 611                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 612                 #address-cells = <1>;
 613                 #size-cells = <0>;
 614                 pinctrl-names = "default", "gpio";
 615                 pinctrl-0 = <&i2c0_xfer>;
 616                 pinctrl-1 = <&i2c0_gpio>;
 617                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 618                 clocks = <&clk_gates12 2>;
 619                 rockchip,check-idle = <1>;
 620                 status = "disabled";
 621         };
 622
 623         /* I2C_AUDIO */
 624         i2c1: i2c@ff660000 {
 625                 compatible = "rockchip,rk30-i2c";
 626                 reg = <0x0 0xff660000 0x0 0x1000>;
 627                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 628                 #address-cells = <1>;
 629                 #size-cells = <0>;
 630                 pinctrl-names = "default", "gpio";
 631                 pinctrl-0 = <&i2c1_xfer>;
 632                 pinctrl-1 = <&i2c1_gpio>;
 633                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 634                 clocks = <&clk_gates12 3>;
 635                 rockchip,check-idle = <1>;
 636                 status = "disabled";
 637         };
 638
 639         /* I2C_SENSOR */
 640         i2c2: i2c@ff140000 {
 641                 compatible = "rockchip,rk30-i2c";
 642                 reg = <0x0 0xff140000 0x0 0x1000>;
 643                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 644                 #address-cells = <1>;
 645                 #size-cells = <0>;
 646                 pinctrl-names = "default", "gpio";
 647                 pinctrl-0 = <&i2c2_xfer>;
 648                 pinctrl-1 = <&i2c2_gpio>;
 649                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 650                 clocks = <&clk_gates19 11>;
 651                 rockchip,check-idle = <1>;
 652                 status = "disabled";
 653         };
 654
 655         /* I2C_CAM */
 656         i2c3: i2c@ff150000 {
 657                 compatible = "rockchip,rk30-i2c";
 658                 reg = <0x0 0xff150000 0x0 0x1000>;
 659                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 660                 #address-cells = <1>;
 661                 #size-cells = <0>;
 662                 pinctrl-names = "default", "gpio";
 663                 pinctrl-0 = <&i2c3_xfer>;
 664                 pinctrl-1 = <&i2c3_gpio>;
 665                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 666                 clocks = <&clk_gates19 12>;
 667                 rockchip,check-idle = <1>;
 668                 status = "disabled";
 669         };
 670
 671         /* I2C_TP */
 672         i2c4: i2c@ff160000 {
 673                 compatible = "rockchip,rk30-i2c";
 674                 reg = <0x0 0xff160000 0x0 0x1000>;
 675                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 676                 #address-cells = <1>;
 677                 #size-cells = <0>;
 678                 pinctrl-names = "default", "gpio";
 679                 pinctrl-0 = <&i2c4_xfer>;
 680                 pinctrl-1 = <&i2c4_gpio>;
 681                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 682                 clocks = <&clk_gates19 13>;
 683                 rockchip,check-idle = <1>;
 684                 status = "disabled";
 685         };
 686
 687         /* I2C_HDMI */
 688         i2c5: i2c@ff170000 {
 689                 compatible = "rockchip,rk30-i2c";
 690                 reg = <0x0 0xff170000 0x0 0x1000>;
 691                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 692                 #address-cells = <1>;
 693                 #size-cells = <0>;
 694                 pinctrl-names = "default", "gpio";
 695                 pinctrl-0 = <&i2c5_xfer>;
 696                 pinctrl-1 = <&i2c5_gpio>;
 697                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 698                 clocks = <&clk_gates19 14>;
 699                 rockchip,check-idle = <1>;
 700                 status = "disabled";
 701         };
 702
 703         fb: fb {
 704                 compatible = "rockchip,rk-fb";
 705                 rockchip,disp-mode = <NO_DUAL>;
 706         };
 707
 708
 709         rk_screen: rk_screen {
 710                 compatible = "rockchip,screen";
 711         };
 712
 713         dsihost0: mipi@ff960000{
 714                 compatible = "rockchip,rk3368-dsi";
 715                 rockchip,prop = <0>;
 716                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 717                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 718                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 719                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>;
 720                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 721                 status = "okay";
 722         };
 723
 724         lvds: lvds@ff968000 {
 725                 compatible = "rockchip,rk3368-lvds";
 726                 rockchip,grf = <&grf>;
 727                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 728                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 729                 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
 730                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 731                 status = "disabled";
 732         };
 733
 734         edp: edp@ff970000 {
 735                 compatible = "rockchip,rk32-edp";
 736                 reg = <0x0 0xff970000 0x0 0x4000>;
 737                 rockchip,grf = <&grf>;
 738                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 739                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 740                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 741                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 742                 reset-names = "edp_24m", "edp_apb";
 743         };
 744
 745         hdmi: hdmi@ff980000 {
 746                 compatible = "rockchip,rk3368-hdmi";
 747                 reg = <0x0 0xff980000 0x0 0x20000>;
 748                 rockchip,grf = <&grf>;
 749                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 750                 pinctrl-names = "default", "gpio";
 751                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 752                 pinctrl-1 = <&i2c5_gpio>;
 753                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 754                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 755                 status = "disabled";
 756         };
 757
 758         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 759                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 760                 reg = <0x0 0xff978000 0x0 0x2000>;
 761                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 762                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 763                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 764                 status = "disabled";
 765         };
 766
 767         lcdc: lcdc@ff930000 {
 768                  compatible = "rockchip,rk3368-lcdc";
 769                  rockchip,grf = <&grf>;
 770                  rockchip,pmugrf = <&pmugrf>;
 771                  rockchip,prop = <PRMRY>;
 772                  rockchip,pwr18 = <0>;
 773                  rockchip,iommu-enabled = <0>;
 774                  reg = <0x0 0xff930000 0x0 0x10000>;
 775                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 776                 /*pinctrl-names = "default", "gpio";
 777                  *pinctrl-0 = <&lcdc_lcdc>;
 778                  *pinctrl-1 = <&lcdc_gpio>;
 779                  */
 780                  status = "disabled";
 781                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
 782                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
 783         };
 784
 785         adc: adc@ff100000 {
 786                 compatible = "rockchip,saradc";
 787                 reg = <0x0 0xff100000 0x0 0x100>;
 788                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 789                 #io-channel-cells = <1>;
 790                 io-channel-ranges;
 791                 rockchip,adc-vref = <1800>;
 792                 clock-frequency = <1000000>;
 793                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 794                 clock-names = "saradc", "pclk_saradc";
 795                 status = "disabled";
 796         };
 797
 798         rga@ff920000 {
 799                 compatible = "rockchip,rk3368-rga2";
 800                 reg = <0x0 0xff920000 0x0 0x1000>;
 801                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 802                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 803                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 804         };
 805
 806         i2s0: i2s0@ff898000 {
 807                 compatible = "rockchip-i2s";
 808                 reg = <0x0 0xff898000 0x0 0x1000>;
 809                 i2s-id = <0>;
 810                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 811                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 812                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 813                 dmas = <&pdma0 0>, <&pdma0 1>;
 814                 #dma-cells = <2>;
 815                 dma-names = "tx", "rx";
 816                 pinctrl-names = "default", "sleep";
 817                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 818                 pinctrl-1 = <&i2s_gpio>;
 819         };
 820
 821         i2s1: i2s1@ff890000 {
 822                 compatible = "rockchip-i2s";
 823                 reg = <0x0 0xff890000 0x0 0x1000>;
 824                 i2s-id = <1>;
 825                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 826                 clock-names = "i2s_clk", "i2s_hclk";
 827                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 828                 dmas = <&pdma0 6>, <&pdma0 7>;
 829                 #dma-cells = <2>;
 830                 dma-names = "tx", "rx";
 831         };
 832
 833         spdif: spdif@ff880000 {
 834                 compatible = "rockchip-spdif";
 835                 reg = <0x0 0xff880000 0x0 0x1000>;
 836                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 837                 clock-names = "spdif_mclk", "spdif_hclk";
 838                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 839                 dmas = <&pdma0 3>;
 840                 #dma-cells = <1>;
 841                 dma-names = "tx";
 842                 pinctrl-names = "default";
 843                 pinctrl-0 = <&spdif_tx>;
 844         };
 845
 846         pwm0: pwm@ff680000 {
 847                 compatible = "rockchip,rk-pwm";
 848                 reg = <0x0 0xff680000 0x0 0x10>;
 849                 #pwm-cells = <2>;
 850                 pinctrl-names = "default";
 851                 pinctrl-0 = <&pwm0_pin>;
 852                 clocks = <&clk_gates13 6>;
 853                 clock-names = "pclk_pwm";
 854                 status = "disabled";
 855         };
 856
 857         pwm1: pwm@ff680010 {
 858                 compatible = "rockchip,rk-pwm";
 859                 reg = <0x0 0xff680010 0x0 0x10>;
 860                 #pwm-cells = <2>;
 861                 pinctrl-names = "default";
 862                 pinctrl-0 = <&pwm1_pin>;
 863                 clocks = <&clk_gates13 6>;
 864                 clock-names = "pclk_pwm";
 865                 status = "disabled";
 866         };
 867
 868         pwm2: pwm@ff680020 {
 869                 compatible = "rockchip,rk-pwm";
 870                 reg = <0x0 0xff680020 0x0 0x10>;
 871                 #pwm-cells = <2>;
 872                 //pinctrl-names = "default";
 873                 //pinctrl-0 = <&pwm1_pin>;
 874                 clocks = <&clk_gates13 6>;
 875                 clock-names = "pclk_pwm";
 876                 status = "disabled";
 877         };
 878
 879         pwm3: pwm@ff680030 {
 880                 compatible = "rockchip,rk-pwm";
 881                 reg = <0x0 0xff680030 0x0 0x10>;
 882                 #pwm-cells = <2>;
 883                 pinctrl-names = "default";
 884                 pinctrl-0 = <&pwm3_pin>;
 885                 clocks = <&clk_gates13 6>;
 886                 clock-names = "pclk_pwm";
 887                 status = "disabled";
 888         };
 889
 890         remotectl: pwm@ff680030 {
 891                 compatible = "rockchip,remotectl-pwm";
 892                 reg = <0x0 0xff680030 0x0 0x50>;
 893                 #pwm-cells = <2>;
 894                 pinctrl-names = "default";
 895                 pinctrl-0 = <&pwm3_pin>;
 896                 clocks = <&clk_gates13 6>;
 897                 clock-names = "pclk_pwm";
 898                 dmas = <&pdma0 2>;
 899                 #dma-cells = <2>;
 900                 dma-names = "rx";
 901                 remote_pwm_id = <3>;
 902                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 903                 status = "disabled";
 904         };
 905
 906         voppwm: pwm@ff9301a0 {
 907                 compatible = "rockchip,vop-pwm";
 908                 reg = <0x0 0xff9301a0 0x0 0x10>;
 909                 #pwm-cells = <2>;
 910                 pinctrl-names = "default";
 911                 pinctrl-0 = <&vop_pwm_pin>;
 912                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 913                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 914                 status = "disabled";
 915         };
 916
 917         pvtm {
 918                 compatible = "rockchip,rk3368-pvtm";
 919                 rockchip,grf = <&grf>;
 920                 rockchip,pmugrf = <&pmugrf>;
 921                 rockchip,pvtm-clk-out = <1>;
 922         };
 923
 924         cpufreq {
 925                 compatible = "rockchip,rk3368-cpufreq";
 926                 rockchip,grf = <&grf>;
 927         };
 928
 929         dvfs {
 930
 931                 vd_arm: vd_arm {
 932                         regulator_name = "vdd_arm";
 933                         suspend_volt = <1000>; //mV
 934                         pd_core {
 935                                 clk_core_b_dvfs_table: clk_core_b {
 936                                         operating-points = <
 937                                                 /* KHz    uV */
 938                                                 312000 1200000
 939                                                 504000 1200000
 940                                                 816000 1200000
 941                                                 1008000 1200000
 942                                                 >;
 943                                         status = "okay";
 944                                 };
 945                                 clk_core_l_dvfs_table: clk_core_l {
 946                                         operating-points = <
 947                                                 /* KHz    uV */
 948                                                 312000 1200000
 949                                                 504000 1200000
 950                                                 816000 1200000
 951                                                 1008000 1200000
 952                                                 >;
 953                                         status = "okay";
 954                                 };
 955                         };
 956                 };
 957
 958                 vd_logic: vd_logic {
 959                         regulator_name = "vdd_logic";
 960                         suspend_volt = <1000>; //mV
 961                         pd_ddr {
 962                                 clk_ddr_dvfs_table: clk_ddr {
 963                                         operating-points = <
 964                                                 /* KHz    uV */
 965                                                 200000 1200000
 966                                                 300000 1200000
 967                                                 400000 1200000
 968                                                 >;
 969                                         channel = <2>;
 970                                         status = "disabled";
 971                                 };
 972                         };
 973
 974                         pd_gpu {
 975                                 clk_gpu_dvfs_table: clk_gpu {
 976                                         operating-points = <
 977                                                 /* KHz    uV */
 978                                                 200000 1200000
 979                                                 300000 1200000
 980                                                 400000 1200000
 981                                                 >;
 982                                         channel = <1>;
 983                                         status = "okay";
 984                                         regu-mode-table = <
 985                                                 /*freq     mode*/
 986                                                 200000     4
 987                                                 0          3
 988                                         >;
 989                                         regu-mode-en = <0>;
 990                                 };
 991                         };
 992                 };
 993         };
 994
 995         ion {
 996                 compatible = "rockchip,ion";
 997                 #address-cells = <1>;
 998                 #size-cells = <0>;
 999
1000                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1001                         compatible = "rockchip,ion-heap";
1002                         rockchip,ion_heap = <4>;
1003                         reg = <0x00000000 0x08000000>; /* 512MB */
1004                 };
1005                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1006                         compatible = "rockchip,ion-heap";
1007                         rockchip,ion_heap = <0>;
1008                 };
1009         };
1010
1011         vpu: vpu_service {
1012                 compatible = "rockchip,vpu_sub";
1013                 iommu_enabled = <0>;
1014                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1015                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1016                 interrupt-names = "irq_enc", "irq_dec";
1017                 dev_mode = <0>;
1018                 name = "vpu_service";
1019         };
1020
1021         hevc: hevc_service {
1022                 compatible = "rockchip,hevc_sub";
1023                 iommu_enabled = <0>;
1024                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1025                 interrupt-names = "irq_dec";
1026                 dev_mode = <1>;
1027                 name = "hevc_service";
1028         };
1029
1030         vpu_combo: vpu_combo@ff9a0000 {
1031                 compatible = "rockchip,vpu_combo";
1032                 reg = <0x0 0xff9a0000 0x0 0x800>;
1033                 rockchip,grf = <&grf>;
1034                 subcnt = <2>;
1035                 rockchip,sub = <&vpu>, <&hevc>;
1036                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1037                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1038                 mode_bit = <12>;
1039                 mode_ctrl = <0x418>;
1040                 name = "vpu_combo";
1041                 status = "okay";
1042         };
1043
1044         iep: iep@ff900000 {
1045                 compatible = "rockchip,iep";
1046                 iommu_enabled = <0>;
1047                 reg = <0x0 0xff900000 0x0 0x800>;
1048                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1049                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1050                 clock-names = "aclk_iep", "hclk_iep";
1051                 status = "okay";
1052         };
1053
1054         gmac: eth@ff290000 {
1055                 compatible = "rockchip,rk3368-gmac";
1056                 reg = <0x0 0xff290000 0x0 0x10000>;
1057                 rockchip,grf = <&grf>;
1058                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1059                 interrupt-names = "macirq";
1060
1061                 clocks = <&clk_mac>, <&clk_gates7 4>,
1062                          <&clk_gates7 5>, <&clk_gates7 6>,
1063                          <&clk_gates7 7>, <&clk_gates20 13>,
1064                          <&clk_gates20 14>;
1065                 clock-names = "clk_mac", "mac_clk_rx",
1066                               "mac_clk_tx", "clk_mac_ref",
1067                               "clk_mac_refout", "aclk_mac",
1068                               "pclk_mac";
1069
1070                 phy-mode = "rgmii";
1071                 pinctrl-names = "default";
1072                 pinctrl-0 = <&rgmii_pins>;
1073         };
1074
1075         gpu {
1076                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1077                 reg = <0x0 0xffa30000 0x0 0x10000>;
1078                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1079                 interrupt-names = "GPU";
1080         };
1081
1082         iep_mmu {
1083                 dbgname = "iep";
1084                 compatible = "rockchip,iep_mmu";
1085                 reg = <0x0 0xff900800 0x0 0x100>;
1086                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1087                 interrupt-names = "iep_mmu";
1088         };
1089
1090         vip_mmu {
1091                 dbgname = "vip";
1092                 compatible = "rockchip,vip_mmu";
1093                 reg = <0x0 0xff950800 0x0 0x100>;
1094                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1095                 interrupt-names = "vip_mmu";
1096         };
1097
1098         vop_mmu {
1099                 dbgname = "vop";
1100                 compatible = "rockchip,vopb_mmu";
1101                 reg = <0x0 0xff930300 0x0 0x100>;
1102                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1103                 interrupt-names = "vop_mmu";
1104         };
1105
1106         isp_mmu {
1107                 dbgname = "isp_mmu";
1108                 compatible = "rockchip,isp_mmu";
1109                 reg = <0x0 0xff914000 0x0 0x100>,
1110                 <0x0 0xff915000 0x0 0x100>;
1111                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1112                 interrupt-names = "isp_mmu";
1113         };
1114
1115         hdcp_mmu {
1116                 dbgname = "hdcp_mmu";
1117                 compatible = "rockchip,hdcp_mmu";
1118                 reg = <0x0 0xff940000 0x0 0x100>;
1119                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1120                 interrupt-names = "hdcp_mmu";
1121         };
1122
1123         hevc_mmu {
1124                 dbgname = "hevc";
1125                 compatible = "rockchip,hevc_mmu";
1126                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
1127                           <0x0 0xff9c0480 0x0 0x40>;
1128                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1129                 interrupt-names = "hevc_mmu";
1130         };
1131
1132         vpu_mmu {
1133                 dbgname = "vpu";
1134                 compatible = "rockchip,vpu_mmu";
1135                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1136                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1137                 interrupt-names = "vpu_mmu";
1138         };
1139
1140         rockchip_suspend {
1141                 rockchip,ctrbits = <
1142                         (0
1143                          |RKPM_CTR_PWR_DMNS
1144                          |RKPM_CTR_GTCLKS
1145                          |RKPM_CTR_PLLS
1146                          |RKPM_CTR_GPIOS
1147                         /*
1148                          |RKPM_CTR_SYSCLK_DIV
1149                          |RKPM_CTR_IDLEAUTO_MD
1150                          |RKPM_CTR_ARMOFF_LPMD
1151                         */
1152                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1153                         )
1154                         >;
1155                 rockchip,pmic-suspend_gpios = <
1156                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1157                         >;
1158                 rockchip,pmic-resume_gpios = <
1159                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1160                         >;
1161         };
1162
1163         isp: isp@ff910000{
1164                 compatible = "rockchip,isp";
1165                 reg = <0x0 0xff910000 0x0 0x10000>;
1166                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1167                 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1168                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1169                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1170                 pinctrl-0 = <&cif_clkout>;
1171                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1172                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1173                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1174                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1175                 pinctrl-5 = <&cif_clkout>;
1176                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1177                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1178                 pinctrl-8 = <&isp_flash_trigger>;
1179                 rockchip,isp,mipiphy = <2>;
1180                 rockchip,isp,cifphy = <1>;
1181                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1182                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1183                 rockchip,grf = <&grf>;
1184                 rockchip,cru = <&cru>;
1185                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1186                 rockchip,isp,iommu_enable = <0>;
1187                 status = "okay";
1188         };
1189
1190         cif: cif@ff950000 {
1191                 compatible = "rockchip,cif";
1192                 reg = <0x0 0xff950000 0x0 0x10000>;
1193                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1194                 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1195                 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1196                 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1197                 pinctrl-names = "cif_pin_all";
1198                 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1199                 rockchip,grf = <&grf>;
1200                 rockchip,cru = <&cru>;
1201                 status = "okay";
1202         };
1203
1204 /*
1205         thermal-zones {
1206                 #include "rk3368-thermal.dtsi"
1207         };
1208 */
1209
1210         tsadc: tsadc@ff280000 {
1211                 compatible = "rockchip,rk3368-tsadc";
1212                 reg = <0x0 0xff280000 0x0 0x100>;
1213                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1214                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1215                 rockchip,grf = <&grf>;
1216                 rockchip,cru = <&cru>;
1217                 rockchip,pmu = <&pmu>;
1218                 clock-names = "tsadc", "apb_pclk";
1219                 clock-frequency = <32000>;
1220                 resets = <&reset RK3368_SRST_TSADC_P>;
1221                 reset-names = "tsadc-apb";
1222                 //pinctrl-names = "default";
1223                 //pinctrl-0 = <&tsadc_int>;
1224                 #thermal-sensor-cells = <1>;
1225                 hw-shut-temp = <120000>;
1226                 status = "disabled";
1227         };
1228
1229         tsp: tsp@FF8B0000 {
1230                 compatible = "rockchip,rk3368-tsp";
1231                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1232                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1233                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1234                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1235                 interrupt-names = "irq_tsp";
1236                 // pinctrl-names = "default";
1237                 // pinctrl-0 = <&isp_hsadc>;
1238                 status = "okay";
1239         };
1240
1241         crypto: crypto@FF8A0000{
1242                 compatible = "rockchip,rk3368-crypto";
1243                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1244                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1245                 interrupt-names = "irq_crypto";
1246                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1247                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1248                 status = "okay";
1249         };
1250
1251         dwc_control_usb: dwc-control-usb {
1252                 compatible = "rockchip,rk3368-dwc-control-usb";
1253                 rockchip,grf = <&grf>;
1254                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1255                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1256                 interrupt-names = "otg_id", "otg_bvalid",
1257                                   "otg_linestate", "host0_linestate";
1258                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1259                 clock-names = "hclk_usb_peri", "usbphy_480m";
1260                 //resets = <&reset RK3128_RST_USBPOR>;
1261                 //reset-names = "usbphy_por";
1262                 usb_bc{
1263                         compatible = "inno,phy";
1264                         regbase = &dwc_control_usb;
1265                         rk_usb,bvalid     = <0x4bc 23 1>;
1266                         rk_usb,iddig      = <0x4bc 26 1>;
1267                         rk_usb,vdmsrcen   = <0x718 12 1>;
1268                         rk_usb,vdpsrcen   = <0x718 11 1>;
1269                         rk_usb,rdmpden    = <0x718 10 1>;
1270                         rk_usb,idpsrcen   = <0x718  9 1>;
1271                         rk_usb,idmsinken  = <0x718  8 1>;
1272                         rk_usb,idpsinken  = <0x718  7 1>;
1273                         rk_usb,dpattach   = <0x4b8 31 1>;
1274                         rk_usb,cpdet      = <0x4b8 30 1>;
1275                         rk_usb,dcpattach  = <0x4b8 29 1>;
1276                 };
1277         };
1278
1279         usb0: usb@ff580000 {
1280                 compatible = "rockchip,rk3368_usb20_otg";
1281                 reg = <0x0 0xff580000 0x0 0x40000>;
1282                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1283                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1284                 clock-names = "clk_usbphy0", "hclk_otg";
1285                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1286                                 <&reset RK3368_SRST_USBOTGC0>;
1287                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1288                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1289                 rockchip,usb-mode = <0>;
1290         };
1291
1292         usb_ehci: usb@ff500000 {
1293                 compatible = "generic-ehci";
1294                 reg = <0x0 0xff500000 0x0 0x20000>;
1295                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1296                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1297                 clock-names = "clk_usbphy0", "hclk_ehci";
1298                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1299                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1300                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1301         };
1302
1303         usb_ohci: usb@ff520000 {
1304                 compatible = "generic-ohci";
1305                 reg = <0x0 0xff520000 0x0 0x20000>;
1306                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1307                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1308                 clock-names =  "clk_usbphy0", "hclk_ohci";
1309         };
1310
1311         usb_hsic: usb@ff5c0000 {
1312                 compatible = "rockchip,rk3288_rk_hsic_host";
1313                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1314                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1315 /*
1316                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1317                          <&hsicphy_12m>, <&usbphy_480m>,
1318                          <&otgphy1_480m>, <&otgphy2_480m>;
1319                 clock-names = "hsicphy_480m", "hclk_hsic",
1320                               "hsicphy_12m", "usbphy_480m",
1321                               "hsic_usbphy1", "hsic_usbphy2";
1322                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1323                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1324                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1325 */
1326                 status = "disabled";
1327         };
1328
1329         pinctrl: pinctrl {
1330                 compatible = "rockchip,rk3368-pinctrl";
1331                 rockchip,grf = <&grf>;
1332                 rockchip,pmugrf = <&pmugrf>;
1333                 #address-cells = <2>;
1334                 #size-cells = <2>;
1335                 ranges;
1336
1337                 gpio0: gpio0@ff750000 {
1338                         compatible = "rockchip,gpio-bank";
1339                         reg =   <0x0 0xff750000 0x0 0x100>;
1340                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1341                         clocks = <&clk_gates23 4>;
1342
1343                         gpio-controller;
1344                         #gpio-cells = <2>;
1345
1346                         interrupt-controller;
1347                         #interrupt-cells = <2>;
1348                 };
1349
1350                 gpio1: gpio1@ff780000 {
1351                         compatible = "rockchip,gpio-bank";
1352                         reg = <0x0 0xff780000 0x0 0x100>;
1353                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1354                         clocks = <&clk_gates22 1>;
1355
1356                         gpio-controller;
1357                         #gpio-cells = <2>;
1358
1359                         interrupt-controller;
1360                         #interrupt-cells = <2>;
1361                 };
1362
1363                 gpio2: gpio2@ff790000 {
1364                         compatible = "rockchip,gpio-bank";
1365                         reg = <0x0 0xff790000 0x0 0x100>;
1366                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1367                         clocks = <&clk_gates22 2>;
1368
1369                         gpio-controller;
1370                         #gpio-cells = <2>;
1371
1372                         interrupt-controller;
1373                         #interrupt-cells = <2>;
1374                 };
1375
1376                 gpio3: gpio3@ff7a0000 {
1377                         compatible = "rockchip,gpio-bank";
1378                         reg = <0x0 0xff7a0000 0x0 0x100>;
1379                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1380                         clocks = <&clk_gates22 3>;
1381
1382                         gpio-controller;
1383                         #gpio-cells = <2>;
1384
1385                         interrupt-controller;
1386                         #interrupt-cells = <2>;
1387                 };
1388
1389                 pcfg_pull_up: pcfg-pull-up {
1390                         bias-pull-up;
1391                 };
1392
1393                 pcfg_pull_down: pcfg-pull-down {
1394                         bias-pull-down;
1395                 };
1396
1397                 pcfg_pull_none: pcfg-pull-none {
1398                         bias-disable;
1399                 };
1400
1401                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1402                         drive-strength = <8>;
1403                 };
1404
1405                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1406                         drive-strength = <12>;
1407                 };
1408
1409                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1410                         bias-pull-up;
1411                         drive-strength = <8>;
1412                 };
1413
1414                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1415                         drive-strength = <4>;
1416                 };
1417
1418                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1419                         bias-pull-up;
1420                         drive-strength = <4>;
1421                 };
1422
1423                 pcfg_output_high: pcfg-output-high {
1424                         output-high;
1425                 };
1426
1427                 pcfg_output_low: pcfg-output-low {
1428                         output-low;
1429                 };
1430
1431                 i2c0 {
1432                         i2c0_xfer: i2c0-xfer {
1433                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1434                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1435                         };
1436                         i2c0_gpio: i2c0-gpio {
1437                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1438                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1439                         };
1440                 };
1441
1442                 i2c1 {
1443                         i2c1_xfer: i2c1-xfer {
1444                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1445                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1446                         };
1447                         i2c1_gpio: i2c1-gpio {
1448                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1449                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1450                         };
1451                 };
1452
1453                 i2c2 {
1454                         i2c2_xfer: i2c2-xfer {
1455                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1456                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1457                         };
1458                         i2c2_gpio: i2c2-gpio {
1459                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1460                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1461             };
1462                 };
1463
1464                 i2c3 {
1465                         i2c3_xfer: i2c3-xfer {
1466                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1467                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1468                         };
1469                         i2c3_gpio: i2c3-gpio {
1470                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1471                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1472                         };
1473                 };
1474
1475                 i2c4 {
1476                         i2c4_xfer: i2c4-xfer {
1477                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1478                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1479                         };
1480                         i2c4_gpio: i2c4-gpio {
1481                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1482                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1483                         };
1484                 };
1485
1486                 i2c5 {
1487                         i2c5_xfer: i2c5-xfer {
1488                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1489                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1490                         };
1491                         i2c5_gpio: i2c5-gpio {
1492                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1493                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1494                         };
1495                 };
1496
1497                 uart0 {
1498                         uart0_xfer: uart0-xfer {
1499                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1500                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1501                         };
1502
1503                         uart0_cts: uart0-cts {
1504                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1505                         };
1506
1507                         uart0_rts: uart0-rts {
1508                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1509                         };
1510
1511                         uart0_rts_gpio: uart0-rts-gpio {
1512                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1513                         };
1514                 };
1515
1516                 uart1 {
1517                         uart1_xfer: uart1-xfer {
1518                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1519                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1520                         };
1521
1522                         uart1_cts: uart1-cts {
1523                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1524                         };
1525
1526                         uart1_rts: uart1-rts {
1527                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1528                         };
1529                 };
1530
1531                 uart2 {
1532                         uart2_xfer: uart2-xfer {
1533                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1534                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1535                         };
1536                 };
1537
1538                 uart3 {
1539                         uart3_xfer: uart3-xfer {
1540                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1541                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1542                         };
1543
1544                         uart3_cts: uart3-cts {
1545                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1546                         };
1547
1548                         uart3_rts: uart3-rts {
1549                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1550                         };
1551                 };
1552
1553                 uart4 {
1554                         uart4_xfer: uart4-xfer {
1555                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1556                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1557                         };
1558
1559                         uart4_cts: uart4-cts {
1560                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1561                         };
1562
1563                         uart4_rts: uart4-rts {
1564                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1565                         };
1566                 };
1567
1568                 spi0 {
1569                         spi0_clk: spi0-clk {
1570                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1571                         };
1572                         spi0_cs0: spi0-cs0 {
1573                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1574                         };
1575                         spi0_tx: spi0-tx {
1576                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1577                         };
1578                         spi0_rx: spi0-rx {
1579                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1580                         };
1581                         spi0_cs1: spi0-cs1 {
1582                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1583                         };
1584                 };
1585
1586                 spi1 {
1587                         spi1_clk: spi1-clk {
1588                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1589                         };
1590                         spi1_cs0: spi1-cs0 {
1591                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1592                         };
1593                         spi1_rx: spi1-rx {
1594                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1595                         };
1596                         spi1_tx: spi1-tx {
1597                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1598                         };
1599                 };
1600
1601                 spi2 {
1602                         spi2_clk: spi2-clk {
1603                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1604                         };
1605                         spi2_cs0: spi2-cs0 {
1606                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1607                         };
1608                         spi2_rx: spi2-rx {
1609                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1610                         };
1611                         spi2_tx: spi2-tx {
1612                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1613                         };
1614                 };
1615
1616                 i2s {
1617                         i2s_mclk: i2s-mclk {
1618                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1619                         };
1620
1621                         i2s_sclk:i2s-sclk {
1622                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1623                         };
1624
1625                         i2s_lrckrx:i2s-lrckrx {
1626                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1627                         };
1628
1629                         i2s_lrcktx:i2s-lrcktx {
1630                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1631                         };
1632
1633                         i2s_sdi:i2s-sdi {
1634                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1635                         };
1636
1637                         i2s_sdo0:i2s-sdo0 {
1638                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1639                         };
1640
1641                         i2s_sdo1:i2s-sdo1 {
1642                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1643                         };
1644
1645                         i2s_sdo2:i2s-sdo2 {
1646                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1647                         };
1648
1649                         i2s_sdo3:i2s-sdo3 {
1650                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1651                         };
1652
1653                         i2s_gpio: i2s-gpio {
1654                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1655                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1656                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1657                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1658                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1659                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1660                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1661                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1662                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1663                         };
1664                 };
1665
1666                 spdif {
1667                         spdif_tx: spdif-tx {
1668                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1669                         };
1670                 };
1671
1672                 sdmmc {
1673                         sdmmc_clk: sdmmc-clk {
1674                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1675                         };
1676
1677                         sdmmc_cmd: sdmmc-cmd {
1678                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1679                         };
1680
1681                         sdmmc_dectn: sdmmc-dectn {
1682                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1683                         };
1684
1685                         sdmmc_bus1: sdmmc-bus1 {
1686                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1687                         };
1688
1689                         sdmmc_bus4: sdmmc-bus4 {
1690                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1691                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1692                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1693                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1694                         };
1695
1696                         sdmmc_gpio: sdmmc-gpio {
1697                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1698                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1699                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1700                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1701                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1702                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1703                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1704                         };
1705                 };
1706
1707                 sdio0 {
1708                         sdio0_bus1: sdio0-bus1 {
1709                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1710                         };
1711
1712                         sdio0_bus4: sdio0-bus4 {
1713                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1714                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1715                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1716                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1717                         };
1718
1719                         sdio0_cmd: sdio0-cmd {
1720                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1721                         };
1722
1723                         sdio0_clk: sdio0-clk {
1724                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1725                         };
1726
1727                         sdio0_dectn: sdio0-dectn {
1728                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1729                         };
1730
1731                         sdio0_wrprt: sdio0-wrprt {
1732                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1733                         };
1734
1735                         sdio0_pwren: sdio0-pwren {
1736                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1737                         };
1738
1739                         sdio0_bkpwr: sdio0-bkpwr {
1740                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1741                         };
1742
1743                         sdio0_int: sdio0-int {
1744                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1745                         };
1746
1747                         sdio0_gpio: sdio0-gpio {
1748                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1749                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1750                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1751                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1752                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1753                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1754                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1755                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1756                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1757                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1758                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1759                         };
1760                 };
1761
1762                 emmc {
1763                         emmc_clk: emmc-clk {
1764                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1765                         };
1766
1767                         emmc_cmd: emmc-cmd {
1768                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1769                         };
1770
1771                         emmc_pwren: emmc-pwren {
1772                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1773                         };
1774
1775                         emmc_rstnout: emmc_rstnout {
1776                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1777                         };
1778
1779                         emmc_bus1: emmc-bus1 {
1780                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1781                         };
1782
1783                         emmc_bus4: emmc-bus4 {
1784                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1785                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1786                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1787                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1788                         };
1789                 };
1790
1791                 pwm0 {
1792                         pwm0_pin: pwm0-pin {
1793                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1794                         };
1795
1796                         vop_pwm_pin:vop-pwm {
1797                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1798                         };
1799                 };
1800
1801                 pwm1 {
1802                         pwm1_pin: pwm1-pin {
1803                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1804                         };
1805                 };
1806
1807                 pwm3 {
1808                         pwm3_pin: pwm3-pin {
1809                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1810                         };
1811                 };
1812
1813                 lcdc {
1814                         lcdc_lcdc: lcdc-lcdc {
1815                                 rockchip,pins =
1816                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1817                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1818                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1819                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1820                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1821                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1822                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1823                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1824                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1825                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1826                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1827                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1828                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1829                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1830                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1831                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1832                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1833                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1834                         };
1835
1836                         lcdc_gpio: lcdc-gpio {
1837                                 rockchip,pins =
1838                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1839                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1840                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1841                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1842                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1843                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1844                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1845                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1846                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1847                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1848                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1849                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1850                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1851                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1852                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1853                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1854                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1855                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1856                         };
1857                 };
1858
1859                 isp {
1860                         cif_clkout: cif-clkout {
1861                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1862                         };
1863
1864                         isp_dvp_d2d9: isp-dvp-d2d9 {
1865                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1866                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1867                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1868                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1869                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1870                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1871                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1872                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1873                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1874                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1875                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1876                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1877                         };
1878
1879                         isp_dvp_d0d1: isp-dvp-d0d1 {
1880                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1881                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1882                         };
1883
1884                         isp_dvp_d10d11:isp_d10d11       {
1885                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1886                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1887                         };
1888
1889                         isp_dvp_d0d7: isp-dvp-d0d7 {
1890                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1891                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1892                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1893                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1894                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1895                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1896                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1897                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1898                         };
1899
1900                         isp_shutter: isp-shutter {
1901                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1902                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1903                         };
1904
1905                         isp_flash_trigger: isp-flash-trigger {
1906                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1907                         };
1908
1909                         isp_prelight: isp-prelight {
1910                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1911                         };
1912
1913                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1914                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1915                         };
1916                 };
1917
1918                 gps {
1919                         gps_mag: gps-mag {
1920                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1921                         };
1922
1923                         gps_sig: gps-sig {
1924                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1925
1926                         };
1927
1928                         gps_rfclk: gps-rfclk {
1929                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1930                         };
1931                 };
1932
1933                 gmac {
1934                         rgmii_pins: rgmii-pins {
1935                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1936                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1937                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1938                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1939                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1940                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
1941                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
1942                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
1943                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1944                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1945                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1946                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1947                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1948                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1949                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
1950                         };
1951
1952                         rmii_pins: rmii-pins {
1953                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1954                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1955                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1956                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1957                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1958                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1959                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1960                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1961                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1962                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
1963                         };
1964                 };
1965
1966                 tsadc_pin {
1967                         tsadc_int: tsadc-int {
1968                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1969                         };
1970                         tsadc_gpio: tsadc-gpio {
1971                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1972                         };
1973                 };
1974
1975                 hdmi_pin {
1976                         hdmi_cec: hdmi-cec {
1977                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1978                         };
1979                 };
1980
1981                 hdmi_i2c {
1982                         hdmii2c_xfer: hdmii2c-xfer {
1983                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1984                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1985                         };
1986                 };
1987         };
1988
1989         reboot {
1990                 compatible = "rockchip,rk3368-reboot";
1991                 rockchip,cru = <&cru>;
1992                 rockchip,pmugrf = <&pmugrf>;
1993         };
1994 };