arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 big0: cpu@100 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53", "arm,armv8";
  43                         reg = <0x0 0x100>;
  44                         enable-method = "psci";
  45                 };
  46                 big1: cpu@101 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         reg = <0x0 0x101>;
  50                         enable-method = "psci";
  51                 };
  52                 big2: cpu@102 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53", "arm,armv8";
  55                         reg = <0x0 0x102>;
  56                         enable-method = "psci";
  57                 };
  58                 big3: cpu@103 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x103>;
  62                         enable-method = "psci";
  63                 };
  64 /*
  65                 little0: cpu@0 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         reg = <0x0 0x0>;
  69                         enable-method = "psci";
  70                 };
  71                 little1: cpu@1 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53", "arm,armv8";
  74                         reg = <0x0 0x1>;
  75                         enable-method = "psci";
  76                 };
  77                 little2: cpu@2 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a53", "arm,armv8";
  80                         reg = <0x0 0x2>;
  81                         enable-method = "psci";
  82                 };
  83                 little3: cpu@3 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53", "arm,armv8";
  86                         reg = <0x0 0x3>;
  87                         enable-method = "psci";
  88                 };
  89 */
  90
  91                 cpu-map {
  92                         cluster0 {
  93                                 core0 {
  94                                         cpu = <&big0>;
  95                                 };
  96                                 core1 {
  97                                         cpu = <&big1>;
  98                                 };
  99                                 core2 {
 100                                         cpu = <&big2>;
 101                                 };
 102                                 core3 {
 103                                         cpu = <&big3>;
 104                                 };
 105                         };
 106 /*
 107                         cluster1 {
 108                                 core0 {
 109                                         cpu = <&little0>;
 110                                 };
 111                                 core1 {
 112                                         cpu = <&little1>;
 113                                 };
 114                                 core2 {
 115                                         cpu = <&little2>;
 116                                 };
 117                                 core3 {
 118                                         cpu = <&little3>;
 119                                 };
 120                         };
 121 */
 122                 };
 123         };
 124
 125         psci {
 126                 compatible = "arm,psci";
 127                 method = "smc";
 128                 cpu_on = <0xC4000003>;
 129         };
 130
 131         gic: interrupt-controller@ffb70000 {
 132                 compatible = "arm,cortex-a15-gic";
 133                 #interrupt-cells = <3>;
 134                 #address-cells = <0>;
 135                 interrupt-controller;
 136                 reg = <0x0 0xffb71000 0 0x1000>,
 137                       <0x0 0xffb72000 0 0x1000>;
 138         };
 139
 140         pmu_grf: syscon@ff738000 {
 141                 compatible = "rockchip,rk3388-pmu-grf", "syscon";
 142                 reg = <0x0 0xff738000 0x0 0x100>;
 143         };
 144
 145         sgrf: syscon@ff740000 {
 146                 compatible = "rockchip,rk3388-sgrf", "syscon";
 147                 reg = <0x0 0xff740000 0x0 0x1000>;
 148
 149         };
 150
 151         grf: syscon@ff770000 {
 152                 compatible = "rockchip,rk3388-grf", "syscon";
 153                 reg = <0x0 0xff770000 0x0 0x1000>;
 154         };
 155
 156         arm-pmu {
 157                 compatible = "arm,armv8-pmuv3";
 158                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 159                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 161                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 162                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 163                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 164                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 166         };
 167
 168         cpu_axi_bus: cpu_axi_bus {
 169                 compatible = "rockchip,cpu_axi_bus";
 170                 #address-cells = <2>;
 171                 #size-cells = <2>;
 172                 ranges;
 173
 174                 qos {
 175                         #address-cells = <2>;
 176                         #size-cells = <2>;
 177                         ranges;
 178
 179                         dmac {
 180                                 reg = <0x0 0xffa80000 0x0 0x20>;
 181                         };
 182                         crypto {
 183                                 reg = <0x0 0xffa80080 0x0 0x20>;
 184                         };
 185                         bus_cpup {
 186                                 reg = <0x0 0xffa90000 0x0 0x20>;
 187                         };
 188                         cci_r {
 189                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 190                         };
 191                         cci_w {
 192                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 193                         };
 194                         peri {
 195                                 reg = <0x0 0xffab0000 0x0 0x20>;
 196                         };
 197                         iep {
 198                                 reg = <0x0 0xffad0000 0x0 0x20>;
 199                         };
 200                         isp_r0 {
 201                                 reg = <0x0 0xffad0080 0x0 0x20>;
 202                         };
 203                         isp_r1 {
 204                                 reg = <0x0 0xffad0100 0x0 0x20>;
 205                         };
 206                         isp_w0 {
 207                                 reg = <0x0 0xffad0180 0x0 0x20>;
 208                                 rockchip,priority = <2 2>;
 209                         };
 210                         isp_w1 {
 211                                 reg = <0x0 0xffad0200 0x0 0x20>;
 212                                 rockchip,priority = <2 2>;
 213                         };
 214                         vip {
 215                                 reg = <0x0 0xffad0280 0x0 0x20>;
 216                         };
 217                         vop {
 218                                 reg = <0x0 0xffad0300 0x0 0x20>;
 219                                 rockchip,priority = <2 2>;
 220                         };
 221                         rga_r {
 222                                 reg = <0x0 0xffad0380 0x0 0x20>;
 223                         };
 224                         rga_w {
 225                                 reg = <0x0 0xffad0400 0x0 0x20>;
 226                         };
 227                         hevc_r {
 228                                 reg = <0x0 0xffae0000 0x0 0x20>;
 229                         };
 230                         vpu_r {
 231                                 reg = <0x0 0xffae0080 0x0 0x20>;
 232                         };
 233                         vpu_w {
 234                                 reg = <0x0 0xffae0100 0x0 0x20>;
 235                         };
 236                 };
 237
 238                 msch {
 239                         #address-cells = <2>;
 240                         #size-cells = <2>;
 241                         ranges;
 242
 243                         msch {
 244                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 245                                 rockchip,read-latency = <0x34>;
 246                         };
 247                 };
 248         };
 249
 250         timer {
 251                 compatible = "arm,armv8-timer";
 252                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 253                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 254                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 255                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 256                 clock-frequency = <24000000>;
 257         };
 258
 259         timer@ff810000 {
 260                 compatible = "rockchip,timer";
 261                 reg = <0x0 0xff810000 0x0 0x20>;
 262                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 263                 rockchip,broadcast = <1>;
 264         };
 265
 266         sram: sram@ff8c0000 {
 267                 compatible = "mmio-sram";
 268                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 269                 map-exec;
 270         };
 271
 272         watchdog: wdt@ff800000 {
 273                 compatible = "rockchip,watch dog";
 274                 reg = <0x0 0xff800000 0x0 0x100>;
 275                 clocks = <&pclk_alive_pre>;
 276                 clock-names = "pclk_wdt";
 277                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 278                 rockchip,irq = <1>;
 279                 rockchip,timeout = <60>;
 280                 rockchip,atboot = <1>;
 281                 rockchip,debug = <0>;
 282                 status = "disabled";
 283         };
 284
 285         amba {
 286                 #address-cells = <2>;
 287                 #size-cells = <2>;
 288                 compatible = "arm,amba-bus";
 289                 interrupt-parent = <&gic>;
 290                 ranges;
 291
 292                 pdma0: pdma@ff600000 {
 293                         compatible = "arm,pl330", "arm,primecell";
 294                         reg = <0x0 0xff600000 0x0 0x4000>;
 295                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 297                         #dma-cells = <1>;
 298                 };
 299
 300                 pdma1: pdma@ff250000 {
 301                         compatible = "arm,pl330", "arm,primecell";
 302                         reg = <0x0 0xff250000 0x0 0x4000>;
 303                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 305                         #dma-cells = <1>;
 306                 };
 307         };
 308
 309         reset: reset@ff760300{
 310                 compatible = "rockchip,reset";
 311                 reg = <0x0 0xff760300 0x0 0x38>;
 312                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 313                 #reset-cells = <1>;
 314         };
 315
 316         nandc0: nandc@ff400000 {
 317                 compatible = "rockchip,rk-nandc";
 318                 reg = <0x0 0xff400000 0x0 0x4000>;
 319                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 320                 nandc_id = <0>;
 321                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 322                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 323         };
 324
 325         nandc0reg: nandc0@ff400000 {
 326                 compatible = "rockchip,rk-nandc";
 327                 reg = <0x0 0xff400000 0x0 0x4000>;
 328         };
 329
 330         emmc: rksdmmc@ff0f0000 {
 331                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 332                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 333                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 clocks = <&clk_emmc>, <&clk_gates21 2>;
 337                 clock-names = "clk_mmc", "hclk_mmc";
 338                 num-slots = <1>;
 339                 fifo-depth = <0x100>;
 340                 bus-width = <8>;
 341         };
 342
 343         sdmmc: rksdmmc@ff0c0000 {
 344                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 345                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 346                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 pinctrl-names = "default", "idle";
 350                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 351                 pinctrl-1 = <&sdmmc_gpio>;
 352                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 353                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>;
 354                 clock-names = "clk_mmc", "hclk_mmc";
 355                 num-slots = <1>;
 356                 fifo-depth = <0x100>;
 357                 bus-width = <4>;
 358         };
 359
 360         sdio: rksdmmc@ff0d0000 {
 361                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 362                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 363                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 pinctrl-names = "default","idle";
 367                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 368                 pinctrl-1 = <&sdio0_gpio>;
 369                 clocks = <&clk_sdio0>, <&clk_gates21 1>;
 370                 clock-names = "clk_mmc", "hclk_mmc";
 371                 num-slots = <1>;
 372                 fifo-depth = <0x100>;
 373                 bus-width = <4>;
 374         };
 375
 376         spi0: spi@ff110000 {
 377                 compatible = "rockchip,rockchip-spi";
 378                 reg = <0x0 0xff110000 0x0 0x1000>;
 379                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 380                 #address-cells = <1>;
 381                 #size-cells = <0>;
 382                 pinctrl-names = "default";
 383                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 384                 rockchip,spi-src-clk = <0>;
 385                 num-cs = <2>;
 386                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 387                 clock-names = "spi", "pclk_spi0";
 388                 //dmas = <&pdma1 11>, <&pdma1 12>;
 389                 //#dma-cells = <2>;
 390                 //dma-names = "tx", "rx";
 391                 status = "disabled";
 392         };
 393
 394         spi1: spi@ff120000 {
 395                 compatible = "rockchip,rockchip-spi";
 396                 reg = <0x0 0xff120000 0x0 0x1000>;
 397                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 402                 rockchip,spi-src-clk = <1>;
 403                 num-cs = <1>;
 404                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 405                 clock-names = "spi", "pclk_spi1";
 406                 //dmas = <&pdma1 13>, <&pdma1 14>;
 407                 //#dma-cells = <2>;
 408                 //dma-names = "tx", "rx";
 409                 status = "disabled";
 410         };
 411
 412         spi2: spi@ff130000 {
 413                 compatible = "rockchip,rockchip-spi";
 414                 reg = <0x0 0xff130000 0x0 0x1000>;
 415                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 pinctrl-names = "default";
 419                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 420                 rockchip,spi-src-clk = <2>;
 421                 num-cs = <1>;
 422                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 423                 clock-names = "spi", "pclk_spi2";
 424                 //dmas = <&pdma1 15>, <&pdma1 16>;
 425                 //#dma-cells = <2>;
 426                 //dma-names = "tx", "rx";
 427                 status = "disabled";
 428         };
 429
 430         uart_bt: serial@ff180000 {
 431                 compatible = "rockchip,serial";
 432                 reg = <0x0 0xff180000 0x0 0x100>;
 433                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 434                 clock-frequency = <24000000>;
 435                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 436                 clock-names = "sclk_uart", "pclk_uart";
 437                 reg-shift = <2>;
 438                 reg-io-width = <4>;
 439                 //dmas = <&pdma1 1>, <&pdma1 2>;
 440                 //#dma-cells = <2>;
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 443                 status = "disabled";
 444         };
 445
 446         uart_bb: serial@ff190000 {
 447                 compatible = "rockchip,serial";
 448                 reg = <0x0 0xff190000 0x0 0x100>;
 449                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 450                 clock-frequency = <24000000>;
 451                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 452                 clock-names = "sclk_uart", "pclk_uart";
 453                 reg-shift = <2>;
 454                 reg-io-width = <4>;
 455                 //dmas = <&pdma1 3>, <&pdma1 4>;
 456                 //#dma-cells = <2>;
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 459                 status = "disabled";
 460         };
 461
 462         uart_dbg: serial@ff690000 {
 463                 compatible = "rockchip,serial";
 464                 reg = <0x0 0xff690000 0x0 0x100>;
 465                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 466                 clock-frequency = <24000000>;
 467                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 468                 clock-names = "sclk_uart", "pclk_uart";
 469                 reg-shift = <2>;
 470                 reg-io-width = <4>;
 471                 //dmas = <&pdma0 4>, <&pdma0 5>;
 472                 //#dma-cells = <2>;
 473                 //pinctrl-names = "default";
 474                 //pinctrl-0 = <&uart2_xfer>;
 475                 status = "disabled";
 476         };
 477
 478         uart_gps: serial@ff1b0000 {
 479                 compatible = "rockchip,serial";
 480                 reg = <0x0 0xff1b0000 0x0 0x100>;
 481                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 482                 clock-frequency = <24000000>;
 483                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 484                 clock-names = "sclk_uart", "pclk_uart";
 485                 current-speed = <115200>;
 486                 reg-shift = <2>;
 487                 reg-io-width = <4>;
 488                 //dmas = <&pdma1 7>, <&pdma1 8>;
 489                 //#dma-cells = <2>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 492                 status = "disabled";
 493         };
 494
 495         uart_exp: serial@ff1c0000 {
 496                 compatible = "rockchip,serial";
 497                 reg = <0x0 0xff1c0000 0x0 0x100>;
 498                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 499                 clock-frequency = <24000000>;
 500                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 501                 clock-names = "sclk_uart", "pclk_uart";
 502                 reg-shift = <2>;
 503                 reg-io-width = <4>;
 504                 //dmas = <&pdma1 9>, <&pdma1 10>;
 505                 //#dma-cells = <2>;
 506                 pinctrl-names = "default";
 507                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 508                 status = "disabled";
 509         };
 510
 511         rockchip_clocks_init: clocks-init{
 512                 compatible = "rockchip,clocks-init";
 513                 rockchip,clocks-init-parent =
 514                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 515                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 516                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 517                         <&clk_cs &clk_gpll>;
 518                 rockchip,clocks-init-rate =
 519                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 520                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 521                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 522                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 523                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 524                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 525                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 526                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 527                         <&aclk_cci 600000000>,          <&clk_mac 50000000>,
 528                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 529                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 530                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 531                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 532                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 533                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 534                         <&clk_hevc_cabac 300000000>;
 535 /*
 536                 rockchip,clocks-uboot-has-init =
 537                         <&aclk_vio0>;
 538 */
 539         };
 540
 541         rockchip_clocks_enable: clocks-enable {
 542                 compatible = "rockchip,clocks-enable";
 543                 clocks =
 544                         /*PLL*/
 545                         <&clk_apllb>,
 546                         <&clk_aplll>,
 547                         <&clk_dpll>,
 548                         <&clk_gpll>,
 549                         <&clk_cpll>,
 550
 551                         /*PD_CORE*/
 552                         <&clk_cs>,
 553                         <&clkin_trace>,
 554
 555                         /*PD_BUS*/
 556                         <&aclk_bus>,
 557                         <&hclk_bus>,
 558                         <&pclk_bus>,
 559                         <&clk_gates12 12>,/*aclk_strc_sys*/
 560                         <&clk_gates12 6>,/*aclk_intmem1*/
 561                         <&clk_gates12 5>,/*aclk_intmem0*/
 562                         <&clk_gates12 4>,/*aclk_intmem*/
 563                         <&clk_gates13 9>,/*aclk_gic400*/
 564
 565                         /*PD_ALIVE*/
 566                         <&clk_gates22 13>,/*pclk_timer1*/
 567                         <&clk_gates22 12>,/*pclk_timer0*/
 568                         <&clk_gates22 9>,/*pclk_alive_niu*/
 569                         <&clk_gates22 8>,/*pclk_grf*/
 570
 571                         /*PD_PMU*/
 572                         <&clk_gates23 5>,/*pclk_pmugrf*/
 573                         <&clk_gates23 3>,/*pclk_sgrf*/
 574                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 575                         <&clk_gates23 1>,/*pclk_intmem1*/
 576                         <&clk_gates23 0>,/*pclk_pmu*/
 577
 578                         /*PD_PERI*/
 579                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 580                         <&clk_gates20 8>,/*aclk_peri_niu*/
 581                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 582                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 583                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 584                         <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
 585         };
 586
 587         /* I2C_PMU */
 588         i2c0: i2c@ff650000 {
 589                 compatible = "rockchip,rk30-i2c";
 590                 reg = <0x0 0xff650000 0x0 0x1000>;
 591                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 592                 #address-cells = <1>;
 593                 #size-cells = <0>;
 594                 pinctrl-names = "default", "gpio";
 595                 pinctrl-0 = <&i2c0_xfer>;
 596                 pinctrl-1 = <&i2c0_gpio>;
 597                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 598                 clocks = <&clk_gates12 2>;
 599                 rockchip,check-idle = <1>;
 600                 status = "disabled";
 601         };
 602
 603         /* I2C_AUDIO */
 604         i2c1: i2c@ff660000 {
 605                 compatible = "rockchip,rk30-i2c";
 606                 reg = <0x0 0xff660000 0x0 0x1000>;
 607                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 608                 #address-cells = <1>;
 609                 #size-cells = <0>;
 610                 pinctrl-names = "default", "gpio";
 611                 pinctrl-0 = <&i2c1_xfer>;
 612                 pinctrl-1 = <&i2c1_gpio>;
 613                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 614                 clocks = <&clk_gates12 3>;
 615                 rockchip,check-idle = <1>;
 616                 status = "disabled";
 617         };
 618
 619         /* I2C_SENSOR */
 620         i2c2: i2c@ff140000 {
 621                 compatible = "rockchip,rk30-i2c";
 622                 reg = <0x0 0xff140000 0x0 0x1000>;
 623                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 624                 #address-cells = <1>;
 625                 #size-cells = <0>;
 626                 pinctrl-names = "default", "gpio";
 627                 pinctrl-0 = <&i2c2_xfer>;
 628                 pinctrl-1 = <&i2c2_gpio>;
 629                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 630                 clocks = <&clk_gates19 11>;
 631                 rockchip,check-idle = <1>;
 632                 status = "disabled";
 633         };
 634
 635         /* I2C_CAM */
 636         i2c3: i2c@ff150000 {
 637                 compatible = "rockchip,rk30-i2c";
 638                 reg = <0x0 0xff150000 0x0 0x1000>;
 639                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 640                 #address-cells = <1>;
 641                 #size-cells = <0>;
 642                 pinctrl-names = "default", "gpio";
 643                 pinctrl-0 = <&i2c3_xfer>;
 644                 pinctrl-1 = <&i2c3_gpio>;
 645                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 646                 clocks = <&clk_gates19 12>;
 647                 rockchip,check-idle = <1>;
 648                 status = "disabled";
 649         };
 650
 651         /* I2C_TP */
 652         i2c4: i2c@ff160000 {
 653                 compatible = "rockchip,rk30-i2c";
 654                 reg = <0x0 0xff160000 0x0 0x1000>;
 655                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 656                 #address-cells = <1>;
 657                 #size-cells = <0>;
 658                 pinctrl-names = "default", "gpio";
 659                 pinctrl-0 = <&i2c4_xfer>;
 660                 pinctrl-1 = <&i2c4_gpio>;
 661                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 662                 clocks = <&clk_gates19 13>;
 663                 rockchip,check-idle = <1>;
 664                 status = "disabled";
 665         };
 666
 667         /* I2C_HDMI */
 668         i2c5: i2c@ff170000 {
 669                 compatible = "rockchip,rk30-i2c";
 670                 reg = <0x0 0xff170000 0x0 0x1000>;
 671                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 672                 #address-cells = <1>;
 673                 #size-cells = <0>;
 674                 pinctrl-names = "default", "gpio";
 675                 pinctrl-0 = <&i2c5_xfer>;
 676                 pinctrl-1 = <&i2c5_gpio>;
 677                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 678                 clocks = <&clk_gates19 14>;
 679                 rockchip,check-idle = <1>;
 680                 status = "disabled";
 681         };
 682
 683         fb: fb {
 684                 compatible = "rockchip,rk-fb";
 685                 rockchip,disp-mode = <NO_DUAL>;
 686         };
 687
 688
 689         rk_screen: rk_screen {
 690                 compatible = "rockchip,screen";
 691         };
 692
 693         dsihost0: mipi@ff960000{
 694                 compatible = "rockchip,rk33x-dsi";
 695                 rockchip,prop = <0>;
 696                 reg = <0xff960000 0x4000>, <0xff968000 0x4000>;
 697                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 698                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 699                 clocks = <&clk_gates4 14>, <&clk_gates17 3>, <&clk_gates22 10>;
 700                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi_host", "pclk_mipi_dsi_phy";
 701                 status = "okay";
 702         };
 703
 704         lvds: lvds@ff968000 {
 705                 compatible = "rockchip,rk3368-lvds";
 706                 rockchip,grf = <&grf>;
 707                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
 708                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 709                 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
 710                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 711                 status = "disabled";
 712         };
 713
 714         edp: edp@ff970000 {
 715                 compatible = "rockchip,rk32-edp";
 716                 reg = <0x0 0xff970000 0x0 0x4000>;
 717                 rockchip,grf = <&grf>;
 718                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 719                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 720                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 721                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 722                 reset-names = "edp_24m", "edp_apb";
 723         };
 724
 725         hdmi: hdmi@ff980000 {
 726                 compatible = "rockchip,rk3368-hdmi";
 727                 reg = <0x0 0xff980000 0x0 0x20000>;
 728                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 729                 pinctrl-names = "default", "gpio";
 730                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 731                 pinctrl-1 = <&i2c5_gpio>;
 732                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 733                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 734                 status = "disabled";
 735         };
 736
 737         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 738                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 739                 reg = <0x0 0xff978000 0x0 0x2000>;
 740                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 741                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 742                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 743                 status = "disabled";
 744         };
 745
 746         lcdc: lcdc@ff930000 {
 747                  compatible = "rockchip,rk3368-lcdc";
 748                  rockchip,grf = <&grf>;
 749                  rockchip,pmu = <&pmu_grf>;
 750                  rockchip,prop = <PRMRY>;
 751                  rockchip,pwr18 = <0>;
 752                  rockchip,iommu-enabled = <0>;
 753                  reg = <0x0 0xff930000 0x0 0x10000>;
 754                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 755                 /*pinctrl-names = "default", "gpio";
 756                  *pinctrl-0 = <&lcdc_lcdc>;
 757                  *pinctrl-1 = <&lcdc_gpio>;
 758                  */
 759                  status = "disabled";
 760                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
 761                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
 762         };
 763
 764         adc: adc@ff100000 {
 765                 compatible = "rockchip,saradc";
 766                 reg = <0x0 0xff100000 0x0 0x100>;
 767                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 768                 #io-channel-cells = <1>;
 769                 io-channel-ranges;
 770                 rockchip,adc-vref = <1800>;
 771                 clock-frequency = <1000000>;
 772                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 773                 clock-names = "saradc", "pclk_saradc";
 774                 status = "disabled";
 775         };
 776
 777         rga@ff920000 {
 778                 compatible = "rockchip,rk3368-rga2";
 779                 reg = <0x0 0xff920000 0x0 0x1000>;
 780                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 781                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 782                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 783         };
 784
 785         i2s0: i2s0@ff898000 {
 786                 compatible = "rockchip-i2s";
 787                 reg = <0x0 0xff898000 0x0 0x1000>;
 788                 i2s-id = <0>;
 789                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 790                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 791                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 792                 dmas = <&pdma0 0>, <&pdma0 1>;
 793                 #dma-cells = <2>;
 794                 dma-names = "tx", "rx";
 795                 pinctrl-names = "default", "sleep";
 796                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 797                 pinctrl-1 = <&i2s_gpio>;
 798         };
 799
 800         i2s1: i2s1@ff890000 {
 801                 compatible = "rockchip-i2s";
 802                 reg = <0x0 0xff890000 0x0 0x1000>;
 803                 i2s-id = <1>;
 804                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 805                 clock-names = "i2s_clk", "i2s_hclk";
 806                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 807                 dmas = <&pdma0 6>, <&pdma0 7>;
 808                 #dma-cells = <2>;
 809                 dma-names = "tx", "rx";
 810         };
 811
 812         spdif: spdif@ff880000 {
 813                 compatible = "rockchip-spdif";
 814                 reg = <0x0 0xff880000 0x0 0x1000>;
 815                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 816                 clock-names = "spdif_mclk", "spdif_hclk";
 817                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 818                 dmas = <&pdma0 3>;
 819                 #dma-cells = <1>;
 820                 dma-names = "tx";
 821                 pinctrl-names = "default";
 822                 pinctrl-0 = <&spdif_tx>;
 823         };
 824
 825         pwm0: pwm@ff680000 {
 826                 compatible = "rockchip,rk-pwm";
 827                 reg = <0x0 0xff680000 0x0 0x10>;
 828                 #pwm-cells = <2>;
 829                 pinctrl-names = "default";
 830                 pinctrl-0 = <&pwm0_pin>;
 831                 clocks = <&clk_gates13 6>;
 832                 clock-names = "pclk_pwm";
 833                 status = "disabled";
 834         };
 835
 836         pwm1: pwm@ff680010 {
 837                 compatible = "rockchip,rk-pwm";
 838                 reg = <0x0 0xff680010 0x0 0x10>;
 839                 #pwm-cells = <2>;
 840                 pinctrl-names = "default";
 841                 pinctrl-0 = <&pwm1_pin>;
 842                 clocks = <&clk_gates13 6>;
 843                 clock-names = "pclk_pwm";
 844                 status = "disabled";
 845         };
 846
 847         pwm2: pwm@ff680020 {
 848                 compatible = "rockchip,rk-pwm";
 849                 reg = <0x0 0xff680020 0x0 0x10>;
 850                 #pwm-cells = <2>;
 851                 //pinctrl-names = "default";
 852                 //pinctrl-0 = <&pwm1_pin>;
 853                 clocks = <&clk_gates13 6>;
 854                 clock-names = "pclk_pwm";
 855                 status = "disabled";
 856         };
 857
 858         pwm3: pwm@ff680030 {
 859                 compatible = "rockchip,rk-pwm";
 860                 reg = <0x0 0xff680030 0x0 0x10>;
 861                 #pwm-cells = <2>;
 862                 pinctrl-names = "default";
 863                 pinctrl-0 = <&pwm3_pin>;
 864                 clocks = <&clk_gates13 6>;
 865                 clock-names = "pclk_pwm";
 866                 status = "disabled";
 867         };
 868
 869         voppwm: pwm@ff9301a0 {
 870                 compatible = "rockchip,vop-pwm";
 871                 reg = <0x0 0xff9301a0 0x0 0x10>;
 872                 #pwm-cells = <2>;
 873                 pinctrl-names = "default";
 874                 pinctrl-0 = <&vop_pwm_pin>;
 875                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 876                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 877                 status = "disabled";
 878         };
 879
 880         dvfs {
 881
 882                 vd_arm: vd_arm {
 883                         regulator_name = "vdd_arm";
 884                         suspend_volt = <1000>; //mV
 885                         pd_core {
 886                                 clk_core_dvfs_table: clk_core {
 887                                         operating-points = <
 888                                                 /* KHz    uV */
 889                                                 312000 1100000
 890                                                 504000 1100000
 891                                                 816000 1100000
 892                                                 1008000 1100000
 893                                                 >;
 894                                         channel = <0>;
 895                                         temp-limit-enable = <0>;
 896                                         target-temp = <80>;
 897                                         normal-temp-limit = <
 898                                         /*delta-temp    delta-freq*/
 899                                                 3       96000
 900                                                 6       144000
 901                                                 9       192000
 902                                                 15      384000
 903                                                 >;
 904                                         performance-temp-limit = <
 905                                                 /*temp    freq*/
 906                                                 100     816000
 907                                                 >;
 908                                         status = "okay";
 909                                         regu-mode-table = <
 910                                                 /*freq     mode*/
 911                                                 1008000    4
 912                                                 0          3
 913                                         >;
 914                                         regu-mode-en = <0>;
 915                                 };
 916                         };
 917                 };
 918
 919                 vd_logic: vd_logic {
 920                         regulator_name = "vdd_logic";
 921                         suspend_volt = <1000>; //mV
 922                         pd_ddr {
 923                                 clk_ddr_dvfs_table: clk_ddr {
 924                                         operating-points = <
 925                                                 /* KHz    uV */
 926                                                 200000 1200000
 927                                                 300000 1200000
 928                                                 400000 1200000
 929                                                 >;
 930                                         channel = <2>;
 931                                         status = "disabled";
 932                                 };
 933                         };
 934
 935                         pd_vio {
 936                                 aclk_vio1_dvfs_table: aclk_vio1 {
 937                                         operating-points = <
 938                                                 /* KHz    uV */
 939                                                 100000 1100000
 940                                                 500000 1100000
 941                                                 >;
 942                                         status = "okay";
 943                                 };
 944                         };
 945                 };
 946
 947                 vd_gpu: vd_gpu {
 948                         regulator_name = "vdd_gpu";
 949                         suspend_volt = <1000>; //mV
 950                         pd_gpu {
 951                                 clk_gpu_dvfs_table: clk_gpu {
 952                                         operating-points = <
 953                                                 /* KHz    uV */
 954                                                 200000 1200000
 955                                                 300000 1200000
 956                                                 400000 1200000
 957                                                 >;
 958                                         channel = <1>;
 959                                         status = "okay";
 960                                         regu-mode-table = <
 961                                                 /*freq     mode*/
 962                                                 200000     4
 963                                                 0          3
 964                                         >;
 965                                         regu-mode-en = <0>;
 966                                 };
 967                         };
 968                 };
 969         };
 970
 971         ion {
 972                 compatible = "rockchip,ion";
 973                 #address-cells = <1>;
 974                 #size-cells = <0>;
 975
 976                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 977                         compatible = "rockchip,ion-heap";
 978                         rockchip,ion_heap = <1>;
 979                         reg = <0x0 0x00000000 0x0 0x08000000>; /* 512MB */
 980                 };
 981                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 982                         compatible = "rockchip,ion-heap";
 983                         rockchip,ion_heap = <3>;
 984                 };
 985         };
 986
 987         vpu: vpu_service@ff9a0000 {
 988                 compatible = "vpu_service";
 989                 iommu_enabled = <0>;
 990                 reg = <0x0 0xff9a0000 0x0 0x800>;
 991                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 992                 interrupt-names = "irq_enc", "irq_dec";
 993                 /*
 994                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 995                 clock-names = "aclk_vcodec", "hclk_vcodec";
 996                 */
 997                 name = "vpu_service";
 998                 /* status = "disabled"; */
 999         };
1000
1001         iep: iep@ff900000 {
1002                 compatible = "rockchip,iep";
1003                 iommu_enabled = <0>;
1004                 reg = <0x0 0xff900000 0x0 0x800>;
1005                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1006                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1007                 clock-names = "aclk_iep", "hclk_iep";
1008                 status = "okay";
1009         };
1010
1011         gmac: eth@ff290000 {
1012                 compatible = "rockchip,rk3368-gmac";
1013                 reg = <0x0 0xff290000 0x0 0x10000>;
1014                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1015                 interrupt-names = "macirq";
1016
1017                 clocks = <&clk_mac>, <&clk_gates5 0>,
1018                          <&clk_gates5 1>, <&clk_gates5 2>,
1019                          <&clk_gates5 3>, <&clk_gates8 0>,
1020                          <&clk_gates8 1>;
1021                 clock-names = "clk_mac", "mac_clk_rx",
1022                               "mac_clk_tx", "clk_mac_ref",
1023                               "clk_mac_refout", "aclk_mac",
1024                               "pclk_mac";
1025
1026                 phy-mode = "rgmii";
1027                 pinctrl-names = "default";
1028                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1029         };
1030
1031         gpu {
1032                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1033                 reg = <0x0 0xffa30000 0x0 0x10000>;
1034                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1035                 interrupt-names = "GPU";
1036         };
1037
1038         iep_mmu {
1039                 dbgname = "iep";
1040                 compatible = "rockchip,iep_mmu";
1041                 reg = <0x0 0xff900800 0x0 0x100>;
1042                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1043                 interrupt-names = "iep_mmu";
1044         };
1045
1046         vip_mmu {
1047                 dbgname = "vip";
1048                 compatible = "rockchip,vip_mmu";
1049                 reg = <0x0 0xff950800 0x0 0x100>;
1050                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1051                 interrupt-names = "vip_mmu";
1052         };
1053
1054         vop_mmu {
1055                 dbgname = "vop";
1056                 compatible = "rockchip,vop_mmu";
1057                 reg = <0x0 0xff930300 0x0 0x100>;
1058                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1059                 interrupt-names = "vop_mmu";
1060         };
1061
1062         isp_mmu {
1063                 dbgname = "isp_mmu";
1064                 compatible = "rockchip,isp_mmu";
1065                 reg = <0x0 0xff914000 0x0 0x100>,
1066                 <0x0 0xff915000 0x0 0x100>;
1067                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1068                 interrupt-names = "isp_mmu";
1069         };
1070
1071         hdcp_mmu {
1072                 dbgname = "hdcp_mmu";
1073                 compatible = "rockchip,hdcp_mmu";
1074                 reg = <0x0 0xff940000 0x0 0x100>;
1075                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1076                 interrupt-names = "hdcp_mmu";
1077         };
1078
1079         hevc_mmu {
1080                 dbgname = "hevc";
1081                 compatible = "rockchip,hevc_mmu";
1082                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
1083                           <0x0 0xff9c0480 0x0 0x40>;
1084                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1085                 interrupt-names = "hevc_mmu";
1086         };
1087
1088         vpu_mmu {
1089                 dbgname = "vpu";
1090                 compatible = "rockchip,vpu_mmu";
1091                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1092                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1093                 interrupt-names = "vpu_mmu";
1094         };
1095
1096         rockchip_suspend {
1097                 rockchip,ctrbits = <
1098                         (0
1099                          |RKPM_CTR_PWR_DMNS
1100                          |RKPM_CTR_GTCLKS
1101                          |RKPM_CTR_PLLS
1102                          |RKPM_CTR_GPIOS
1103                         /*
1104                          |RKPM_CTR_SYSCLK_DIV
1105                          |RKPM_CTR_IDLEAUTO_MD
1106                          |RKPM_CTR_ARMOFF_LPMD
1107                         */
1108                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1109                         )
1110                         >;
1111                 rockchip,pmic-suspend_gpios = <
1112                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1113                         >;
1114                 rockchip,pmic-resume_gpios = <
1115                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1116                         >;
1117         };
1118
1119         isp: isp@ff910000{
1120                 compatible = "rockchip,isp";
1121                 reg = <0x0 0xff910000 0x0 0x10000>;
1122                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1123                 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1124                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1125                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1126                 pinctrl-0 = <&cif_clkout>;
1127                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1128                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1129                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1130                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1131                 pinctrl-5 = <&cif_clkout>;
1132                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1133                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1134                 pinctrl-8 = <&isp_flash_trigger>;
1135                 rockchip,isp,mipiphy = <2>;
1136                 rockchip,isp,cifphy = <1>;
1137                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1138                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1139                 rockchip,isp,iommu_enable = <1>;
1140                 status = "okay";
1141         };
1142
1143         tsadc: tsadc@ff280000 {
1144                 compatible = "rockchip,tsadc";
1145                 reg = <0x0 0xff280000 0x0 0x100>;
1146                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1147                 #io-channel-cells = <1>;
1148                 io-channel-ranges;
1149                 clock-frequency = <10000>;
1150                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1151                 clock-names = "tsadc", "pclk_tsadc";
1152                 pinctrl-names = "default", "tsadc_int";
1153                 pinctrl-0 = <&tsadc_gpio>;
1154                 pinctrl-1 = <&tsadc_int>;
1155                 tsadc-ht-temp = <120>;
1156                 tsadc-ht-reset-cru = <1>;
1157                 tsadc-ht-pull-gpio = <0>;
1158                 status = "disabled";
1159         };
1160
1161         tsp: tsp@FF8B0000 {
1162                 compatible = "rockchip,rk3368-tsp";
1163                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1164                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1165                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1166                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1167                 interrupt-names = "irq_tsp";
1168                 // pinctrl-names = "default";
1169                 // pinctrl-0 = <&isp_hsadc>;
1170                 status = "okay";
1171         };
1172
1173         crypto: crypto@FF8A0000{
1174                 compatible = "rockchip,rk3368-crypto";
1175                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1176                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1177                 interrupt-names = "irq_crypto";
1178                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1179                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1180                 status = "okay";
1181         };
1182
1183         pinctrl: pinctrl {
1184                 compatible = "rockchip,rk3368-pinctrl";
1185                 rockchip,grf = <&grf>;
1186                 rockchip,pmu = <&pmu_grf>;
1187                 #address-cells = <2>;
1188                 #size-cells = <2>;
1189                 ranges;
1190
1191                 gpio0: gpio0@ff750000 {
1192                         compatible = "rockchip,gpio-bank";
1193                         reg =   <0x0 0xff750000 0x0 0x100>;
1194                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1195                         clocks = <&clk_gates23 4>;
1196
1197                         gpio-controller;
1198                         #gpio-cells = <2>;
1199
1200                         interrupt-controller;
1201                         #interrupt-cells = <2>;
1202                 };
1203
1204                 gpio1: gpio1@ff780000 {
1205                         compatible = "rockchip,gpio-bank";
1206                         reg = <0x0 0xff780000 0x0 0x100>;
1207                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1208                         clocks = <&clk_gates22 1>;
1209
1210                         gpio-controller;
1211                         #gpio-cells = <2>;
1212
1213                         interrupt-controller;
1214                         #interrupt-cells = <2>;
1215                 };
1216
1217                 gpio2: gpio2@ff790000 {
1218                         compatible = "rockchip,gpio-bank";
1219                         reg = <0x0 0xff790000 0x0 0x100>;
1220                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1221                         clocks = <&clk_gates22 2>;
1222
1223                         gpio-controller;
1224                         #gpio-cells = <2>;
1225
1226                         interrupt-controller;
1227                         #interrupt-cells = <2>;
1228                 };
1229
1230                 gpio3: gpio3@ff7a0000 {
1231                         compatible = "rockchip,gpio-bank";
1232                         reg = <0x0 0xff7a0000 0x0 0x100>;
1233                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1234                         clocks = <&clk_gates22 3>;
1235
1236                         gpio-controller;
1237                         #gpio-cells = <2>;
1238
1239                         interrupt-controller;
1240                         #interrupt-cells = <2>;
1241                 };
1242
1243                 pcfg_pull_up: pcfg-pull-up {
1244                         bias-pull-up;
1245                 };
1246
1247                 pcfg_pull_down: pcfg-pull-down {
1248                         bias-pull-down;
1249                 };
1250
1251                 pcfg_pull_none: pcfg-pull-none {
1252                         bias-disable;
1253                 };
1254
1255                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1256                         drive-strength = <8>;
1257                 };
1258
1259                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1260                         bias-pull-up;
1261                         drive-strength = <8>;
1262                 };
1263
1264                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1265                         drive-strength = <4>;
1266                 };
1267
1268                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1269                         bias-pull-up;
1270                         drive-strength = <4>;
1271                 };
1272
1273                 pcfg_output_high: pcfg-output-high {
1274                         output-high;
1275                 };
1276
1277                 pcfg_output_low: pcfg-output-low {
1278                         output-low;
1279                 };
1280
1281                 i2c0 {
1282                         i2c0_xfer: i2c0-xfer {
1283                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1284                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1285                         };
1286                         i2c0_gpio: i2c0-gpio {
1287                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1288                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1289                         };
1290                 };
1291
1292                 i2c1 {
1293                         i2c1_xfer: i2c1-xfer {
1294                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1295                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1296                         };
1297                         i2c1_gpio: i2c1-gpio {
1298                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1299                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1300                         };
1301                 };
1302
1303                 i2c2 {
1304                         i2c2_xfer: i2c2-xfer {
1305                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1306                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1307                         };
1308                         i2c2_gpio: i2c2-gpio {
1309                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1310                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1311             };
1312                 };
1313
1314                 i2c3 {
1315                         i2c3_xfer: i2c3-xfer {
1316                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1317                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1318                         };
1319                         i2c3_gpio: i2c3-gpio {
1320                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1321                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1322                         };
1323                 };
1324
1325                 i2c4 {
1326                         i2c4_xfer: i2c4-xfer {
1327                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1328                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1329                         };
1330                         i2c4_gpio: i2c4-gpio {
1331                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1332                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1333                         };
1334                 };
1335
1336                 i2c5 {
1337                         i2c5_xfer: i2c5-xfer {
1338                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1339                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1340                         };
1341                         i2c5_gpio: i2c5-gpio {
1342                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1343                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1344                         };
1345                 };
1346
1347                 uart0 {
1348                         uart0_xfer: uart0-xfer {
1349                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1350                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1351                         };
1352
1353                         uart0_cts: uart0-cts {
1354                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1355                         };
1356
1357                         uart0_rts: uart0-rts {
1358                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1359                         };
1360
1361                         uart0_rts_gpio: uart0-rts-gpio {
1362                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1363                         };
1364                 };
1365
1366                 uart1 {
1367                         uart1_xfer: uart1-xfer {
1368                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1369                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1370                         };
1371
1372                         uart1_cts: uart1-cts {
1373                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1374                         };
1375
1376                         uart1_rts: uart1-rts {
1377                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1378                         };
1379                 };
1380
1381                 uart2 {
1382                         uart2_xfer: uart2-xfer {
1383                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1384                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1385                         };
1386                 };
1387
1388                 uart3 {
1389                         uart3_xfer: uart3-xfer {
1390                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1391                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1392                         };
1393
1394                         uart3_cts: uart3-cts {
1395                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1396                         };
1397
1398                         uart3_rts: uart3-rts {
1399                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1400                         };
1401                 };
1402
1403                 uart4 {
1404                         uart4_xfer: uart4-xfer {
1405                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1406                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1407                         };
1408
1409                         uart4_cts: uart4-cts {
1410                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1411                         };
1412
1413                         uart4_rts: uart4-rts {
1414                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1415                         };
1416                 };
1417
1418                 spi0 {
1419                         spi0_clk: spi0-clk {
1420                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1421                         };
1422                         spi0_cs0: spi0-cs0 {
1423                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1424                         };
1425                         spi0_tx: spi0-tx {
1426                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1427                         };
1428                         spi0_rx: spi0-rx {
1429                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1430                         };
1431                         spi0_cs1: spi0-cs1 {
1432                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1433                         };
1434                 };
1435
1436                 spi1 {
1437                         spi1_clk: spi1-clk {
1438                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1439                         };
1440                         spi1_cs0: spi1-cs0 {
1441                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1442                         };
1443                         spi1_rx: spi1-rx {
1444                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1445                         };
1446                         spi1_tx: spi1-tx {
1447                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1448                         };
1449                 };
1450
1451                 spi2 {
1452                         spi2_clk: spi2-clk {
1453                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1454                         };
1455                         spi2_cs0: spi2-cs0 {
1456                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1457                         };
1458                         spi2_rx: spi2-rx {
1459                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1460                         };
1461                         spi2_tx: spi2-tx {
1462                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1463                         };
1464                 };
1465
1466                 i2s {
1467                         i2s_mclk: i2s-mclk {
1468                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1469                         };
1470
1471                         i2s_sclk:i2s-sclk {
1472                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1473                         };
1474
1475                         i2s_lrckrx:i2s-lrckrx {
1476                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1477                         };
1478
1479                         i2s_lrcktx:i2s-lrcktx {
1480                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1481                         };
1482
1483                         i2s_sdi:i2s-sdi {
1484                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1485                         };
1486
1487                         i2s_sdo0:i2s-sdo0 {
1488                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1489                         };
1490
1491                         i2s_sdo1:i2s-sdo1 {
1492                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1493                         };
1494
1495                         i2s_sdo2:i2s-sdo2 {
1496                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1497                         };
1498
1499                         i2s_sdo3:i2s-sdo3 {
1500                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1501                         };
1502
1503                         i2s_gpio: i2s-gpio {
1504                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1505                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1506                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1507                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1508                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1509                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1510                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1511                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1512                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1513                         };
1514                 };
1515
1516                 spdif {
1517                         spdif_tx: spdif-tx {
1518                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1519                         };
1520                 };
1521
1522                 sdmmc {
1523                         sdmmc_clk: sdmmc-clk {
1524                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1525                         };
1526
1527                         sdmmc_cmd: sdmmc-cmd {
1528                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1529                         };
1530
1531                         sdmmc_dectn: sdmmc-dectn {
1532                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1533                         };
1534
1535                         sdmmc_bus1: sdmmc-bus1 {
1536                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1537                         };
1538
1539                         sdmmc_bus4: sdmmc-bus4 {
1540                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1541                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1542                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1543                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1544                         };
1545
1546                         sdmmc_gpio: sdmmc-gpio {
1547                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1548                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1549                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1550                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1551                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1552                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1553                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1554                         };
1555                 };
1556
1557                 sdio0 {
1558                         sdio0_bus1: sdio0-bus1 {
1559                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1560                         };
1561
1562                         sdio0_bus4: sdio0-bus4 {
1563                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1564                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1565                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1566                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1567                         };
1568
1569                         sdio0_cmd: sdio0-cmd {
1570                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1571                         };
1572
1573                         sdio0_clk: sdio0-clk {
1574                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1575                         };
1576
1577                         sdio0_dectn: sdio0-dectn {
1578                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1579                         };
1580
1581                         sdio0_wrprt: sdio0-wrprt {
1582                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1583                         };
1584
1585                         sdio0_pwren: sdio0-pwren {
1586                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1587                         };
1588
1589                         sdio0_bkpwr: sdio0-bkpwr {
1590                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1591                         };
1592
1593                         sdio0_int: sdio0-int {
1594                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1595                         };
1596
1597                         sdio0_gpio: sdio0-gpio {
1598                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1599                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1600                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1601                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1602                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1603                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1604                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1605                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1606                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1607                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1608                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1609                         };
1610                 };
1611
1612                 emmc {
1613                         emmc_clk: emmc-clk {
1614                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1615                         };
1616
1617                         emmc_cmd: emmc-cmd {
1618                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1619                         };
1620
1621                         emmc_pwren: emmc-pwren {
1622                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1623                         };
1624
1625                         emmc_rstnout: emmc_rstnout {
1626                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1627                         };
1628
1629                         emmc_bus1: emmc-bus1 {
1630                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1631                         };
1632
1633                         emmc_bus4: emmc-bus4 {
1634                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1635                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1636                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1637                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1638                         };
1639                 };
1640
1641                 pwm0 {
1642                         pwm0_pin: pwm0-pin {
1643                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1644                         };
1645
1646                         vop_pwm_pin:vop-pwm {
1647                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1648                         };
1649                 };
1650
1651                 pwm1 {
1652                         pwm1_pin: pwm1-pin {
1653                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1654                         };
1655                 };
1656
1657                 pwm3 {
1658                         pwm3_pin: pwm3-pin {
1659                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1660                         };
1661                 };
1662
1663                 lcdc {
1664                         lcdc_lcdc: lcdc-lcdc {
1665                                 rockchip,pins =
1666                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1667                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1668                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1669                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1670                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1671                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1672                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1673                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1674                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1675                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1676                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1677                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1678                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1679                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1680                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1681                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1682                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1683                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1684                         };
1685
1686                         lcdc_gpio: lcdc-gpio {
1687                                 rockchip,pins =
1688                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1689                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1690                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1691                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1692                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1693                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1694                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1695                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1696                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1697                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1698                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1699                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1700                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1701                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1702                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1703                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1704                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1705                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1706                         };
1707                 };
1708
1709                 isp {
1710                         cif_clkout: cif-clkout {
1711                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1712                         };
1713
1714                         isp_dvp_d2d9: isp-dvp-d2d9 {
1715                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1716                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1717                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1718                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1719                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1720                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1721                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1722                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1723                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1724                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1725                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1726                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1727                         };
1728
1729                         isp_dvp_d0d1: isp-dvp-d0d1 {
1730                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1731                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1732                         };
1733
1734                         isp_dvp_d10d11:isp_d10d11       {
1735                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1736                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1737                         };
1738
1739                         isp_dvp_d0d7: isp-dvp-d0d7 {
1740                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1741                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1742                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1743                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1744                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1745                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1746                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1747                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1748                         };
1749
1750                         isp_shutter: isp-shutter {
1751                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1752                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1753                         };
1754
1755                         isp_flash_trigger: isp-flash-trigger {
1756                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1757                         };
1758
1759                         isp_prelight: isp-prelight {
1760                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1761                         };
1762
1763                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1764                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1765                         };
1766                 };
1767
1768                 gps {
1769                         gps_mag: gps-mag {
1770                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1771                         };
1772
1773                         gps_sig: gps-sig {
1774                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1775
1776                         };
1777
1778                         gps_rfclk: gps-rfclk {
1779                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1780                         };
1781                 };
1782
1783                 gmac {
1784                         mac_clk: mac-clk {
1785                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1786                         };
1787
1788                         mac_txpins: mac-txpins {
1789                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//TXD0
1790                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//TXD1
1791                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//TXD2
1792                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//TXD3
1793                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//TXEN
1794                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;//TXCLK
1795                         };
1796
1797                         mac_rxpins: mac-rxpins {
1798                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1799                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1800                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1801                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1802                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1803                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//RXER
1804                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1805                                                 <3 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;//COL
1806                         };
1807
1808                         mac_crs: mac-crs {
1809                                 rockchip,pins = <3 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; //CRS
1810                         };
1811
1812                         mac_mdpins: mac-mdpins {
1813                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1814                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;//MDC
1815                         };
1816                 };
1817
1818                 tsadc_pin {
1819                         tsadc_int: tsadc-int {
1820                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1821                         };
1822                         tsadc_gpio: tsadc-gpio {
1823                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1824                         };
1825                 };
1826
1827                 hdmi_pin {
1828                         hdmi_cec: hdmi-cec {
1829                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1830                         };
1831                 };
1832
1833                 hdmi_i2c {
1834                         hdmii2c_xfer: hdmii2c-xfer {
1835                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1836                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1837                         };
1838                 };
1839         };
1840 };