2 * Copyright (C) 2014-2015 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <dt-bindings/clock/rockchip,rk3368.h>
18 compatible = "rockchip,rk-clocks";
19 rockchip,grf = <&grf>;
25 compatible = "rockchip,rk-fixed-rate-cons";
28 compatible = "rockchip,rk-fixed-clock";
29 clock-output-names = "xin24m";
30 clock-frequency = <24000000>;
35 compatible = "rockchip,rk-fixed-clock";
37 clock-output-names = "xin12m";
38 clock-frequency = <12000000>;
43 compatible = "rockchip,rk-fixed-clock";
44 clock-output-names = "xin32k";
45 clock-frequency = <32000>;
50 compatible = "rockchip,rk-fixed-clock";
51 clock-output-names = "dummy";
52 clock-frequency = <0>;
56 jtag_clkin: jtag_clkin {
57 compatible = "rockchip,rk-fixed-clock";
58 clock-output-names = "jtag_clkin";
59 clock-frequency = <0>;
63 gmac_clkin: gmac_clkin {
64 compatible = "rockchip,rk-fixed-clock";
65 clock-output-names = "gmac_clkin";
66 clock-frequency = <0>;
70 pclkin_isp: pclkin_isp {
71 compatible = "rockchip,rk-fixed-clock";
72 clock-output-names = "pclkin_isp";
73 clock-frequency = <0>;
77 pclkin_vip: pclkin_vip {
78 compatible = "rockchip,rk-fixed-clock";
79 clock-output-names = "pclkin_vip";
80 clock-frequency = <0>;
84 clkin_hsadc_tsp: clkin_hsadc_tsp {
85 compatible = "rockchip,rk-fixed-clock";
86 clock-output-names = "clkin_hsadc_tsp";
87 clock-frequency = <0>;
91 i2s_clkin: i2s_clkin {
92 compatible = "rockchip,rk-fixed-clock";
93 clock-output-names = "i2s_clkin";
94 clock-frequency = <0>;
100 compatible = "rockchip,rk-fixed-factor-cons";
102 hclk_vepu: hclk_vepu {
103 compatible = "rockchip,rk-fixed-factor-clock";
104 clocks = <&aclk_vepu>;
105 clock-output-names = "hclk_vepu";
111 hclk_vdpu: hclk_vdpu {
112 compatible = "rockchip,rk-fixed-factor-clock";
113 clocks = <&aclk_vdpu>;
114 clock-output-names = "hclk_vdpu";
120 usbotg_480m_out: usbotg_480m_out {
121 compatible = "rockchip,rk-fixed-factor-clock";
122 clocks = <&clk_gates8 1>;
123 clock-output-names = "usbotg_480m_out";
129 pclkin_isp_inv: pclkin_isp_inv {
130 compatible = "rockchip,rk-fixed-factor-clock";
131 clocks = <&clk_gates17 2>;
132 clock-output-names = "pclkin_isp_inv";
138 pclkin_vip_inv: pclkin_vip_inv {
139 compatible = "rockchip,rk-fixed-factor-clock";
140 clocks = <&clk_gates16 13>;
141 clock-output-names = "pclkin_vip_inv";
148 compatible = "rockchip,rk-fixed-factor-clock";
149 clocks = <&clk_gates16 8>;
150 clock-output-names = "pclk_vio";
158 compatible = "rockchip,rk-clock-regs";
159 #address-cells = <1>;
161 ranges = <0x0 0x0 0xff760000 0x1000>;
162 reg = <0x0 0xff760000 0x0 0x1000>;
164 /* PLL control regs */
166 compatible = "rockchip,rk-pll-cons";
167 #address-cells = <1>;
171 clk_apllb: pll-clk@0000 {
172 compatible = "rockchip,rk3188-pll-clk";
174 mode-reg = <0x000c 8>;
175 status-reg = <0x0480 1>;
177 clock-output-names = "clk_apllb";
178 rockchip,pll-type = <CLK_PLL_3368_APLLB>;
183 clk_aplll: pll-clk@0010 {
184 compatible = "rockchip,rk3188-pll-clk";
186 mode-reg = <0x001c 8>;
187 status-reg = <0x0480 0>;
189 clock-output-names = "clk_aplll";
190 rockchip,pll-type = <CLK_PLL_3368_APLLL>;
194 clk_dpll: pll-clk@0020 {
195 compatible = "rockchip,rk3188-pll-clk";
197 mode-reg = <0x002c 8>;
198 status-reg = <0x0480 2>;
200 clock-output-names = "clk_dpll";
201 rockchip,pll-type = <CLK_PLL_3188PLUS>;
206 clk_cpll: pll-clk@0030 {
207 compatible = "rockchip,rk3188-pll-clk";
209 mode-reg = <0x003c 8>;
210 status-reg = <0x0480 3>;
212 clock-output-names = "clk_cpll";
213 rockchip,pll-type = <CLK_PLL_3188PLUS>;
215 #clock-init-cells = <1>;
218 clk_gpll: pll-clk@0040 {
219 compatible = "rockchip,rk3188-pll-clk";
221 mode-reg = <0x004c 8>;
222 status-reg = <0x0480 4>;
224 clock-output-names = "clk_gpll";
225 rockchip,pll-type = <CLK_PLL_3188PLUS>;
227 #clock-init-cells = <1>;
230 clk_npll: pll-clk@0050 {
231 compatible = "rockchip,rk3188-pll-clk";
233 mode-reg = <0x005c 8>;
234 status-reg = <0x0480 5>;
236 clock-output-names = "clk_npll";
237 rockchip,pll-type = <CLK_PLL_3188PLUS_AUTO>;
239 #clock-init-cells = <1>;
243 /* Select control regs */
245 compatible = "rockchip,rk-sel-cons";
246 #address-cells = <1>;
250 clk_sel_con0: sel-con@0100 {
251 compatible = "rockchip,rk3188-selcon";
253 #address-cells = <1>;
256 clk_core_b_div: clk_core_b_div {
257 compatible = "rockchip,rk3188-div-con";
258 rockchip,bits = <0 5>;
259 clocks = <&clk_core_b>;
260 clock-output-names = "clk_core_b";
261 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
263 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
264 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
265 CLK_SET_RATE_NO_REPARENT)>;
270 clk_core_b: clk_core_b_mux {
271 compatible = "rockchip,rk3188-mux-con";
272 rockchip,bits = <7 1>;
273 clocks = <&clk_apllb>, <&clk_gpll>;
274 clock-output-names = "clk_core_b";
276 #clock-init-cells = <1>;
279 aclkm_core_b: aclkm_core_b_div {
280 compatible = "rockchip,rk3188-div-con";
281 rockchip,bits = <8 5>;
282 clocks = <&clk_core_b>;
283 clock-output-names = "aclkm_core_b";
284 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
286 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
292 clk_sel_con1: sel-con@0104 {
293 compatible = "rockchip,rk3188-selcon";
295 #address-cells = <1>;
298 atclk_core_b: atclk_core_b_div {
299 compatible = "rockchip,rk3188-div-con";
300 rockchip,bits = <0 5>;
301 clocks = <&clk_core_b>;
302 clock-output-names = "atclk_core_b";
303 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
305 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
310 pclk_dbg_b: pclk_dbg_b_div {
311 compatible = "rockchip,rk3188-div-con";
312 rockchip,bits = <8 5>;
313 clocks = <&clk_core_b>;
314 clock-output-names = "pclk_dbg_b";
315 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
317 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
321 clk_sel_con2: sel-con@0108 {
322 compatible = "rockchip,rk3188-selcon";
324 #address-cells = <1>;
327 clk_core_l_div: clk_core_l_div {
328 compatible = "rockchip,rk3188-div-con";
329 rockchip,bits = <0 5>;
330 clocks = <&clk_core_l>;
331 clock-output-names = "clk_core_l";
332 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
334 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
335 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
336 CLK_SET_RATE_NO_REPARENT)>;
341 clk_core_l: clk_core_l_mux {
342 compatible = "rockchip,rk3188-mux-con";
343 rockchip,bits = <7 1>;
344 clocks = <&clk_aplll>, <&clk_gpll>;
345 clock-output-names = "clk_core_l";
347 #clock-init-cells = <1>;
350 aclkm_core_l: aclkm_core_l_div {
351 compatible = "rockchip,rk3188-div-con";
352 rockchip,bits = <8 5>;
353 clocks = <&clk_core_l>;
354 clock-output-names = "aclkm_core_l";
355 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
357 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
363 clk_sel_con3: sel-con@010c {
364 compatible = "rockchip,rk3188-selcon";
366 #address-cells = <1>;
369 atclk_core_l: atclk_core_l_div {
370 compatible = "rockchip,rk3188-div-con";
371 rockchip,bits = <0 5>;
372 clocks = <&clk_core_l>;
373 clock-output-names = "atclk_core_l";
374 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
376 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
381 pclk_dbg_l: pclk_dbg_l_div {
382 compatible = "rockchip,rk3188-div-con";
383 rockchip,bits = <8 5>;
384 clocks = <&clk_core_l>;
385 clock-output-names = "pclk_dbg_l";
386 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
388 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
392 clk_sel_con4: sel-con@0110 {
393 compatible = "rockchip,rk3188-selcon";
395 #address-cells = <1>;
398 clk_cs_div: clk_cs_div {
399 compatible = "rockchip,rk3188-div-con";
400 rockchip,bits = <0 5>;
402 clock-output-names = "clk_cs";
403 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
405 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
406 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
412 compatible = "rockchip,rk3188-mux-con";
413 rockchip,bits = <6 2>;
414 clocks = <&clk_gates0 9>, <&clk_gates0 10>, <&clk_gates0 8>, <&dummy>;
415 clock-output-names = "clk_cs";
417 #clock-init-cells = <1>;
420 clkin_trace: clkin_trace_div {
421 compatible = "rockchip,rk3188-div-con";
422 rockchip,bits = <8 5>;
424 clock-output-names = "clkin_trace";
425 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
427 #clock-init-cells = <1>;
432 clk_sel_con5: sel-con@0114 {
433 compatible = "rockchip,rk3188-selcon";
435 #address-cells = <1>;
438 aclk_cci_div: aclk_cci_div {
439 compatible = "rockchip,rk3188-div-con";
440 rockchip,bits = <0 5>;
441 clocks = <&aclk_cci>;
442 clock-output-names = "aclk_cci";
443 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
445 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
450 aclk_cci: aclk_cci_mux {
451 compatible = "rockchip,rk3188-mux-con";
452 rockchip,bits = <6 2>;
453 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
454 clock-output-names = "aclk_cci";
456 #clock-init-cells = <1>;
460 /* sel[7:6] reserved */
462 clk_sel_con8: sel-con@0120 {
463 compatible = "rockchip,rk3188-selcon";
465 #address-cells = <1>;
468 aclk_bus_div: aclk_bus_div {
469 compatible = "rockchip,rk3188-div-con";
470 rockchip,bits = <0 5>;
471 clocks = <&aclk_bus>;
472 clock-output-names = "aclk_bus";
473 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
475 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
480 aclk_bus: aclk_bus_mux {
481 compatible = "rockchip,rk3188-mux-con";
482 rockchip,bits = <7 1>;
483 clocks = <&clk_gates1 11>, <&clk_gates1 10>;
484 clock-output-names = "aclk_bus";
486 #clock-init-cells = <1>;
489 hclk_bus: hclk_bus_div {
490 compatible = "rockchip,rk3188-div-con";
491 rockchip,bits = <8 2>;
492 clocks = <&aclk_bus>;
493 clock-output-names = "hclk_bus";
494 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
496 #clock-init-cells = <1>;
501 pclk_bus: pclk_bus_div {
502 compatible = "rockchip,rk3188-div-con";
503 rockchip,bits = <12 3>;
504 clocks = <&aclk_bus>;
505 clock-output-names = "pclk_bus";
506 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
508 #clock-init-cells = <1>;
512 clk_sel_con9: sel-con@0124 {
513 compatible = "rockchip,rk3188-selcon";
515 #address-cells = <1>;
518 aclk_peri_div: aclk_peri_div {
519 compatible = "rockchip,rk3188-div-con";
520 rockchip,bits = <0 5>;
521 clocks = <&aclk_peri>;
522 clock-output-names = "aclk_peri";
523 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
525 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
530 aclk_peri: aclk_peri_mux {
531 compatible = "rockchip,rk3188-mux-con";
532 rockchip,bits = <7 1>;
533 clocks = <&clk_cpll>, <&clk_gpll>;
534 clock-output-names = "aclk_peri";
536 #clock-init-cells = <1>;
539 hclk_peri: hclk_peri_div {
540 compatible = "rockchip,rk3188-div-con";
541 rockchip,bits = <8 2>;
542 clocks = <&aclk_peri>;
543 clock-output-names = "hclk_peri";
544 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
545 rockchip,div-relations =
550 #clock-init-cells = <1>;
555 pclk_peri: pclk_peri_div {
556 compatible = "rockchip,rk3188-div-con";
557 rockchip,bits = <12 2>;
558 clocks = <&aclk_peri>;
559 clock-output-names = "pclk_peri";
560 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
561 rockchip,div-relations =
567 #clock-init-cells = <1>;
571 clk_sel_con10: sel-con@0128 {
572 compatible = "rockchip,rk3188-selcon";
574 #address-cells = <1>;
577 pclk_pmu_pre: pclk_pmu_pre_div {
578 compatible = "rockchip,rk3188-div-con";
579 rockchip,bits = <0 5>;
580 clocks = <&clk_gpll>;
581 clock-output-names = "pclk_pmu_pre";
582 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
584 #clock-init-cells = <1>;
589 pclk_alive_pre: pclk_alive_pre_div {
590 compatible = "rockchip,rk3188-div-con";
591 rockchip,bits = <8 5>;
592 clocks = <&clk_gpll>;
593 clock-output-names = "pclk_alive_pre";
594 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
596 #clock-init-cells = <1>;
601 clk_crypto: clk_crypto_div {
602 compatible = "rockchip,rk3188-div-con";
603 rockchip,bits = <14 2>;
604 clocks = <&aclk_bus>;
605 clock-output-names = "clk_crypto";
606 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
608 #clock-init-cells = <1>;
612 /* sel[11]: reserved */
614 clk_sel_con12: sel-con@0130 {
615 compatible = "rockchip,rk3188-selcon";
617 #address-cells = <1>;
620 fclk_mcu_div: fclk_mcu_div {
621 compatible = "rockchip,rk3188-div-con";
622 rockchip,bits = <0 5>;
623 clocks = <&fclk_mcu>;
624 clock-output-names = "fclk_mcu";
625 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
627 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
632 fclk_mcu: fclk_mcu_mux {
633 compatible = "rockchip,rk3188-mux-con";
634 rockchip,bits = <7 1>;
635 clocks = <&clk_cpll>, <&clk_gpll>;
636 clock-output-names = "fclk_mcu";
638 #clock-init-cells = <1>;
641 stclk_mcu: stclk_mcu_div {
642 compatible = "rockchip,rk3188-div-con";
643 rockchip,bits = <8 3>;
644 clocks = <&fclk_mcu>;
645 clock-output-names = "stclk_mcu";
646 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
651 clk_sel_con13: sel-con@0134 {
652 compatible = "rockchip,rk3188-selcon";
654 #address-cells = <1>;
657 clk_ddr_div: clk_ddr_div {
658 compatible = "rockchip,rk3188-div-con";
659 rockchip,bits = <0 2>;
661 clock-output-names = "clk_ddr";
662 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
664 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
665 CLK_SET_RATE_NO_REPARENT)>;
666 rockchip,clkops-idx =
667 <CLKOPS_RATE_DDR_DIV4>;
672 clk_ddr: clk_ddr_mux {
673 compatible = "rockchip,rk3188-mux-con";
674 rockchip,bits = <4 1>;
675 clocks = <&clk_dpll>, <&clk_gpll>;
676 clock-output-names = "clk_ddr";
682 usbphy_480m: usbphy_480m_mux {
683 compatible = "rockchip,rk3188-mux-con";
684 rockchip,bits = <8 1>;
685 clocks = <&xin24m>, <&usbotg_480m_out>;
686 clock-output-names = "usbphy_480m";
688 rockchip,clkops-idx =
689 <CLKOPS_RATE_RK3288_USB480M>;
690 #clock-init-cells = <1>;
693 clk4x_ddr: clk4x_ddr_mux {
694 compatible = "rockchip,rk3188-mux-con";
695 rockchip,bits = <4 1>;
696 clocks = <&clk_dpll>, <&clk_gpll>;
697 clock-output-names = "clk4x_ddr";
702 clk_sel_con14: sel-con@0138 {
703 compatible = "rockchip,rk3188-selcon";
705 #address-cells = <1>;
708 clk_gpu_core_div: clk_gpu_core_div {
709 compatible = "rockchip,rk3188-div-con";
710 rockchip,bits = <0 5>;
711 clocks = <&clk_gpu_core>;
712 clock-output-names = "clk_gpu_core";
713 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
715 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
716 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
721 clk_gpu_core: clk_gpu_core_mux {
722 compatible = "rockchip,rk3188-mux-con";
723 rockchip,bits = <6 2>;
724 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
725 clock-output-names = "clk_gpu_core";
727 #clock-init-cells = <1>;
730 aclk_gpu_mem: aclk_gpu_mem_div {
731 compatible = "rockchip,rk3188-div-con";
732 rockchip,bits = <8 5>;
733 clocks = <&aclk_gpu>;
734 clock-output-names = "aclk_gpu_mem";
735 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
737 #clock-init-cells = <1>;
742 aclk_gpu: aclk_gpu_mux {
743 compatible = "rockchip,rk3188-mux-con";
744 rockchip,bits = <14 1>;
745 clocks = <&clk_cpll>, <&clk_gpll>;
746 clock-output-names = "aclk_gpu";
748 #clock-init-cells = <1>;
752 clk_sel_con15: sel-con@013c {
753 compatible = "rockchip,rk3188-selcon";
755 #address-cells = <1>;
758 aclk_vepu_div: aclk_vepu_div {
759 compatible = "rockchip,rk3188-div-con";
760 rockchip,bits = <0 5>;
761 clocks = <&aclk_vepu>;
762 clock-output-names = "aclk_vepu";
763 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
765 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
770 aclk_vepu: aclk_vepu_mux {
771 compatible = "rockchip,rk3188-mux-con";
772 rockchip,bits = <6 2>;
773 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
774 clock-output-names = "aclk_vepu";
776 #clock-init-cells = <1>;
779 aclk_vdpu_div: aclk_vdpu_div {
780 compatible = "rockchip,rk3188-div-con";
781 rockchip,bits = <8 5>;
782 clocks = <&aclk_vdpu>;
783 clock-output-names = "aclk_vdpu";
784 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
786 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
791 aclk_vdpu: aclk_vdpu_mux {
792 compatible = "rockchip,rk3188-mux-con";
793 rockchip,bits = <14 2>;
794 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
795 clock-output-names = "aclk_vdpu";
797 #clock-init-cells = <1>;
801 clk_sel_con16: sel-con@0140 {
802 compatible = "rockchip,rk3188-selcon";
804 #address-cells = <1>;
807 aclk_gpu_cfg: aclk_gpu_cfg_div {
808 compatible = "rockchip,rk3188-div-con";
809 rockchip,bits = <8 5>;
810 clocks = <&aclk_gpu>;
811 clock-output-names = "aclk_gpu_cfg";
812 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
814 #clock-init-cells = <1>;
818 clk_sel_con17: sel-con@0144 {
819 compatible = "rockchip,rk3188-selcon";
821 #address-cells = <1>;
824 clk_hevc_cabac_div: clk_hevc_cabac_div {
825 compatible = "rockchip,rk3188-div-con";
826 rockchip,bits = <0 5>;
827 clocks = <&clk_hevc_cabac>;
828 clock-output-names = "clk_hevc_cabac";
829 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
831 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
836 clk_hevc_cabac: clk_hevc_cabac_mux {
837 compatible = "rockchip,rk3188-mux-con";
838 rockchip,bits = <6 2>;
839 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
840 clock-output-names = "clk_hevc_cabac";
842 #clock-init-cells = <1>;
845 clk_hevc_core_div: clk_hevc_core_div {
846 compatible = "rockchip,rk3188-div-con";
847 rockchip,bits = <8 5>;
848 clocks = <&clk_hevc_core>;
849 clock-output-names = "clk_hevc_core";
850 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
852 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
857 clk_hevc_core: clk_hevc_core_mux {
858 compatible = "rockchip,rk3188-mux-con";
859 rockchip,bits = <14 2>;
860 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
861 clock-output-names = "clk_hevc_core";
863 #clock-init-cells = <1>;
867 clk_sel_con18: sel-con@0148 {
868 compatible = "rockchip,rk3188-selcon";
870 #address-cells = <1>;
873 clk_rga_div: clk_rga_div {
874 compatible = "rockchip,rk3188-div-con";
875 rockchip,bits = <0 5>;
877 clock-output-names = "clk_rga";
878 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
880 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
885 clk_rga: clk_rga_mux {
886 compatible = "rockchip,rk3188-mux-con";
887 rockchip,bits = <6 2>;
888 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
889 clock-output-names = "clk_rga";
891 #clock-init-cells = <1>;
894 aclk_rga_div: aclk_rga_div {
895 compatible = "rockchip,rk3188-div-con";
896 rockchip,bits = <8 5>;
897 clocks = <&aclk_rga_pre>;
898 clock-output-names = "aclk_rga_pre";
899 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
901 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
906 aclk_rga_pre: aclk_rga_mux {
907 compatible = "rockchip,rk3188-mux-con";
908 rockchip,bits = <14 2>;
909 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
910 clock-output-names = "aclk_rga_pre";
912 #clock-init-cells = <1>;
916 clk_sel_con19: sel-con@014c {
917 compatible = "rockchip,rk3188-selcon";
919 #address-cells = <1>;
922 aclk_vio0_div: aclk_vio0_div {
923 compatible = "rockchip,rk3188-div-con";
924 rockchip,bits = <0 5>;
925 clocks = <&aclk_vio0>;
926 clock-output-names = "aclk_vio0";
927 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
929 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
934 aclk_vio0: aclk_vio0_mux {
935 compatible = "rockchip,rk3188-mux-con";
936 rockchip,bits = <6 2>;
937 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
938 clock-output-names = "aclk_vio0";
940 #clock-init-cells = <1>;
944 clk_sel_con20: sel-con@0150 {
945 compatible = "rockchip,rk3188-selcon";
947 #address-cells = <1>;
950 dclk_vop0_div: dclk_vop0_div {
951 compatible = "rockchip,rk3188-div-con";
952 rockchip,bits = <0 8>;
953 clocks = <&dclk_vop0>;
954 clock-output-names = "dclk_vop0";
955 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
957 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
958 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
961 dclk_vop0: dclk_vop0_mux {
962 compatible = "rockchip,rk3188-mux-con";
963 rockchip,bits = <8 2>;
964 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&dummy>;
965 clock-output-names = "dclk_vop0";
967 #clock-init-cells = <1>;
973 clk_sel_con21: sel-con@0154 {
974 compatible = "rockchip,rk3188-selcon";
976 #address-cells = <1>;
979 hclk_vio: hclk_vio_div {
980 compatible = "rockchip,rk3188-div-con";
981 rockchip,bits = <0 5>;
982 clocks = <&aclk_vio0>;
983 clock-output-names = "hclk_vio";
984 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
986 #clock-init-cells = <1>;
991 pclk_isp: pclk_isp_mux {
992 compatible = "rockchip,rk3188-mux-con";
993 rockchip,bits = <6 1>;
994 clocks = <&clk_gates17 2>, <&pclkin_isp_inv>;
995 clock-output-names = "pclk_isp";
1001 clk_vip_div: clk_vip_div {
1002 compatible = "rockchip,rk3188-div-con";
1003 rockchip,bits = <8 5>;
1004 clocks = <&clk_vip>;
1005 clock-output-names = "clk_vip";
1006 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1008 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1011 pclk_vip: pclk_vip_mux {
1012 compatible = "rockchip,rk3188-mux-con";
1013 rockchip,bits = <13 1>;
1014 clocks = <&clk_gates16 13>, <&pclkin_vip_inv>;
1015 clock-output-names = "pclk_vip";
1019 clk_vip: clk_vip_mux {
1020 compatible = "rockchip,rk3188-mux-con";
1021 rockchip,bits = <14 2>;
1022 clocks = <&clk_cpll>, <&xin24m>, <&clk_gpll>, <&xin24m>;
1023 clock-output-names = "clk_vip";
1025 #clock-init-cells = <1>;
1029 clk_sel_con22: sel-con@0158 {
1030 compatible = "rockchip,rk3188-selcon";
1032 #address-cells = <1>;
1035 clk_isp_div: clk_isp_div {
1036 compatible = "rockchip,rk3188-div-con";
1037 rockchip,bits = <0 6>;
1038 clocks = <&clk_isp>;
1039 clock-output-names = "clk_isp";
1040 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1042 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1045 clk_isp: clk_isp_mux {
1046 compatible = "rockchip,rk3188-mux-con";
1047 rockchip,bits = <6 2>;
1048 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1049 clock-output-names = "clk_isp";
1051 #clock-init-cells = <1>;
1055 clk_sel_con23: sel-con@015c {
1056 compatible = "rockchip,rk3188-selcon";
1058 #address-cells = <1>;
1061 clk_edp_div: clk_edp_div {
1062 compatible = "rockchip,rk3188-div-con";
1063 rockchip,bits = <0 6>;
1064 clocks = <&clk_edp>;
1065 clock-output-names = "clk_edp";
1066 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1068 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1071 clk_edp: clk_edp_mux {
1072 compatible = "rockchip,rk3188-mux-con";
1073 rockchip,bits = <6 2>;
1074 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1075 clock-output-names = "clk_edp";
1077 #clock-init-cells = <1>;
1080 clk_edp_24m: clk_edp_24m_mux {
1081 compatible = "rockchip,rk3188-mux-con";
1082 rockchip,bits = <8 1>;
1083 clocks = <&xin24m>, <&dummy>;
1084 clock-output-names = "clk_edp_24m";
1089 /* sel[24]: reserved */
1091 clk_sel_con25: sel-con@0164 {
1092 compatible = "rockchip,rk3188-selcon";
1094 #address-cells = <1>;
1097 clk_tsadc: clk_tsadc_div {
1098 compatible = "rockchip,rk3188-div-con";
1099 rockchip,bits = <0 6>;
1100 clocks = <&clk_32k_mux>;
1101 clock-output-names = "clk_tsadc";
1102 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1106 clk_saradc: clk_saradc_div {
1107 compatible = "rockchip,rk3188-div-con";
1108 rockchip,bits = <8 8>;
1110 clock-output-names = "clk_saradc";
1111 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1116 clk_sel_con26: sel-con@0168 {
1117 compatible = "rockchip,rk3188-selcon";
1119 #address-cells = <1>;
1124 hsic_usb_480m: hsic_usb_480m_mux {
1125 compatible = "rockchip,rk3188-mux-con";
1126 rockchip,bits = <8 1>;
1127 clocks = <&usbotg_480m_out>, <&dummy>;
1128 clock-output-names = "hsic_usb_480m";
1134 hsicphy_480m: hsicphy_480m_mux {
1135 compatible = "rockchip,rk3188-mux-con";
1136 rockchip,bits = <12 2>;
1137 clocks = <&clk_cpll>, <&clk_gpll>, <&hsic_usb_480m>, <&hsic_usb_480m>;
1138 clock-output-names = "hsicphy_480m";
1143 clk_sel_con27: sel-con@016c {
1144 compatible = "rockchip,rk3188-selcon";
1146 #address-cells = <1>;
1149 i2s_pll_div: i2s_pll_div {
1150 compatible = "rockchip,rk3188-div-con";
1151 rockchip,bits = <0 7>;
1152 clocks = <&i2s_pll>;
1153 clock-output-names = "i2s_pll";
1154 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1156 rockchip,clkops-idx =
1157 <CLKOPS_RATE_MUX_DIV>;
1158 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1163 clk_i2s: clk_i2s_mux {
1164 compatible = "rockchip,rk3188-mux-con";
1165 rockchip,bits = <8 2>;
1166 clocks = <&i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
1167 clock-output-names = "clk_i2s";
1169 rockchip,clkops-idx =
1170 <CLKOPS_RATE_RK3288_I2S>;
1171 rockchip,flags = <CLK_SET_RATE_PARENT>;
1174 /* 11:10 reserved */
1176 i2s_pll: i2s_pll_mux {
1177 compatible = "rockchip,rk3188-mux-con";
1178 rockchip,bits = <12 1>;
1179 clocks = <&clk_cpll>, <&clk_gpll>;
1180 clock-output-names = "i2s_pll";
1182 #clock-init-cells = <1>;
1185 /* 14:13 reserved */
1187 i2s_out: i2s_out_mux {
1188 compatible = "rockchip,rk3188-mux-con";
1189 rockchip,bits = <15 1>;
1190 clocks = <&clk_i2s>, <&xin12m>;
1191 clock-output-names = "i2s_out";
1196 clk_sel_con28: sel-con@0170 {
1197 compatible = "rockchip,rk3188-selcon";
1199 #address-cells = <1>;
1202 i2s_frac: i2s_frac {
1203 compatible = "rockchip,rk3188-frac-con";
1204 clocks = <&i2s_pll>;
1205 clock-output-names = "i2s_frac";
1206 /* numerator denominator */
1207 rockchip,bits = <0 32>;
1208 rockchip,clkops-idx =
1214 /* sel[30:29] reserved */
1216 clk_sel_con31: sel-con@017c {
1217 compatible = "rockchip,rk3188-selcon";
1219 #address-cells = <1>;
1223 spdif_8ch_pll_div: spdif_8ch_pll_div {
1224 compatible = "rockchip,rk3188-div-con";
1225 rockchip,bits = <0 7>;
1226 clocks = <&spdif_8ch_pll>;
1227 clock-output-names = "spdif_8ch_pll";
1228 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1230 rockchip,clkops-idx =
1231 <CLKOPS_RATE_MUX_DIV>;
1232 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1237 clk_spidf_8ch: clk_spidf_8ch_mux {
1238 compatible = "rockchip,rk3188-mux-con";
1239 rockchip,bits = <8 2>;
1240 clocks = <&spdif_8ch_pll>, <&spdif_8ch_frac>, <&i2s_clkin>, <&xin12m>;
1241 clock-output-names = "clk_spidf_8ch";
1243 rockchip,clkops-idx =
1244 <CLKOPS_RATE_RK3288_I2S>;
1245 rockchip,flags = <CLK_SET_RATE_PARENT>;
1248 /* 11:10 reserved */
1250 spdif_8ch_pll: spdif_8ch_pll_mux {
1251 compatible = "rockchip,rk3188-mux-con";
1252 rockchip,bits = <12 1>;
1253 clocks = <&clk_cpll>, <&clk_gpll>;
1254 clock-output-names = "spdif_8ch_pll";
1256 #clock-init-cells = <1>;
1259 /* 15:13 reserved */
1262 clk_sel_con32: sel-con@0180 {
1263 compatible = "rockchip,rk3188-selcon";
1265 #address-cells = <1>;
1268 spdif_8ch_frac: spdif_8ch_frac {
1269 compatible = "rockchip,rk3188-frac-con";
1270 clocks = <&spdif_8ch_pll>;
1271 clock-output-names = "spdif_8ch_frac";
1272 /* numerator denominator */
1273 rockchip,bits = <0 32>;
1274 rockchip,clkops-idx =
1280 clk_sel_con33: sel-con@0184 {
1281 compatible = "rockchip,rk3188-selcon";
1283 #address-cells = <1>;
1286 clk_uart0_pll_div: clk_uart0_pll_div {
1287 compatible = "rockchip,rk3188-div-con";
1288 rockchip,bits = <0 7>;
1289 clocks = <&clk_uart0_pll>;
1290 clock-output-names = "clk_uart0_pll";
1291 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1293 rockchip,clkops-idx =
1294 <CLKOPS_RATE_MUX_DIV>;
1299 clk_uart0: clk_uart0_mux {
1300 compatible = "rockchip,rk3188-mux-con";
1301 rockchip,bits = <8 2>;
1302 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&xin24m>;
1303 clock-output-names = "clk_uart0";
1305 rockchip,clkops-idx =
1306 <CLKOPS_RATE_RK3288_I2S>;
1307 rockchip,flags = <CLK_SET_RATE_PARENT>;
1310 /* 11:10 reserved */
1312 clk_uart0_pll: clk_uart0_pll_mux {
1313 compatible = "rockchip,rk3188-mux-con";
1314 rockchip,bits = <12 2>;
1315 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1316 clock-output-names = "clk_uart0_pll";
1321 clk_sel_con34: sel-con@0188 {
1322 compatible = "rockchip,rk3188-selcon";
1324 #address-cells = <1>;
1327 uart0_frac: uart0_frac {
1328 compatible = "rockchip,rk3188-frac-con";
1329 clocks = <&clk_uart0_pll>;
1330 clock-output-names = "uart0_frac";
1331 /* numerator denominator */
1332 rockchip,bits = <0 32>;
1333 rockchip,clkops-idx =
1339 clk_sel_con35: sel-con@018c {
1340 compatible = "rockchip,rk3188-selcon";
1342 #address-cells = <1>;
1345 uart1_div: uart1_div {
1346 compatible = "rockchip,rk3188-div-con";
1347 rockchip,bits = <0 7>;
1348 clocks = <&clk_uart_pll>;
1349 clock-output-names = "uart1_div";
1350 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1356 clk_uart1: clk_uart1_mux {
1357 compatible = "rockchip,rk3188-mux-con";
1358 rockchip,bits = <8 2>;
1359 clocks = <&uart1_div>, <&uart1_frac>, <&xin24m>, <&xin24m>;
1360 clock-output-names = "clk_uart1";
1362 rockchip,clkops-idx =
1363 <CLKOPS_RATE_RK3288_I2S>;
1364 rockchip,flags = <CLK_SET_RATE_PARENT>;
1367 /* 11:10 reserved */
1369 clk_uart_pll: clk_uart_pll_mux {
1370 compatible = "rockchip,rk3188-mux-con";
1371 rockchip,bits = <12 1>;
1372 clocks = <&clk_cpll>, <&clk_gpll>;
1373 clock-output-names = "clk_uart_pll";
1375 #clock-init-cells = <1>;
1378 /* 14:13 reserved */
1381 clk_sel_con36: sel-con@0190 {
1382 compatible = "rockchip,rk3188-selcon";
1384 #address-cells = <1>;
1387 uart1_frac: uart1_frac {
1388 compatible = "rockchip,rk3188-frac-con";
1389 clocks = <&uart1_div>;
1390 clock-output-names = "uart1_frac";
1391 /* numerator denominator */
1392 rockchip,bits = <0 32>;
1393 rockchip,clkops-idx =
1399 clk_sel_con37: sel-con@0194 {
1400 compatible = "rockchip,rk3188-selcon";
1402 #address-cells = <1>;
1405 uart2_div: uart2_div {
1406 compatible = "rockchip,rk3188-div-con";
1407 rockchip,bits = <0 7>;
1408 clocks = <&clk_uart_pll>;
1409 clock-output-names = "uart2_div";
1410 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1416 clk_uart2: clk_uart2_mux {
1417 compatible = "rockchip,rk3188-mux-con";
1418 rockchip,bits = <8 1>;
1419 clocks = <&uart2_div>, <&xin24m>;
1420 clock-output-names = "clk_uart2";
1422 rockchip,flags = <CLK_SET_RATE_PARENT>;
1426 /* sel[38] reserved */
1428 clk_sel_con39: sel-con@019c {
1429 compatible = "rockchip,rk3188-selcon";
1431 #address-cells = <1>;
1434 uart3_div: uart3_div {
1435 compatible = "rockchip,rk3188-div-con";
1436 rockchip,bits = <0 7>;
1437 clocks = <&clk_uart_pll>;
1438 clock-output-names = "uart3_div";
1439 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1445 clk_uart3: clk_uart3_mux {
1446 compatible = "rockchip,rk3188-mux-con";
1447 rockchip,bits = <8 2>;
1448 clocks = <&uart3_div>, <&uart3_frac>, <&xin24m>, <&xin24m>;
1449 clock-output-names = "clk_uart3";
1451 rockchip,clkops-idx =
1452 <CLKOPS_RATE_RK3288_I2S>;
1453 rockchip,flags = <CLK_SET_RATE_PARENT>;
1457 clk_sel_con40: sel-con@01a0 {
1458 compatible = "rockchip,rk3188-selcon";
1460 #address-cells = <1>;
1463 uart3_frac: uart3_frac {
1464 compatible = "rockchip,rk3188-frac-con";
1465 clocks = <&uart3_div>;
1466 clock-output-names = "uart3_frac";
1467 /* numerator denominator */
1468 rockchip,bits = <0 32>;
1469 rockchip,clkops-idx =
1475 clk_sel_con41: sel-con@01a4 {
1476 compatible = "rockchip,rk3188-selcon";
1478 #address-cells = <1>;
1481 uart4_div: uart4_div {
1482 compatible = "rockchip,rk3188-div-con";
1483 rockchip,bits = <0 7>;
1484 clocks = <&clk_uart_pll>;
1485 clock-output-names = "uart4_div";
1486 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1492 clk_uart4: clk_uart4_mux {
1493 compatible = "rockchip,rk3188-mux-con";
1494 rockchip,bits = <8 2>;
1495 clocks = <&uart4_div>, <&uart4_frac>, <&xin24m>, <&xin24m>;
1496 clock-output-names = "clk_uart4";
1498 rockchip,clkops-idx =
1499 <CLKOPS_RATE_RK3288_I2S>;
1500 rockchip,flags = <CLK_SET_RATE_PARENT>;
1504 clk_sel_con42: sel-con@01a8 {
1505 compatible = "rockchip,rk3188-selcon";
1507 #address-cells = <1>;
1510 uart4_frac: uart4_frac {
1511 compatible = "rockchip,rk3188-frac-con";
1512 clocks = <&uart4_div>;
1513 clock-output-names = "uart4_frac";
1514 /* numerator denominator */
1515 rockchip,bits = <0 32>;
1516 rockchip,clkops-idx =
1522 clk_sel_con43: sel-con@01ac {
1523 compatible = "rockchip,rk3188-selcon";
1525 #address-cells = <1>;
1528 clk_mac_pll_div: clk_mac_pll_div {
1529 compatible = "rockchip,rk3188-div-con";
1530 rockchip,bits = <0 5>;
1531 clocks = <&clk_mac_pll>;
1532 clock-output-names = "clk_mac_pll";
1533 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1535 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1540 clk_mac_pll: clk_mac_pll_mux {
1541 compatible = "rockchip,rk3188-mux-con";
1542 rockchip,bits = <6 2>;
1543 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>, <&clk_gpll>;
1544 clock-output-names = "clk_mac_pll";
1548 clk_mac: clk_mac_mux {
1549 compatible = "rockchip,rk3188-mux-con";
1550 rockchip,bits = <8 1>;
1551 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1552 clock-output-names = "clk_mac";
1554 rockchip,flags = <CLK_SET_RATE_PARENT>;
1555 #clock-init-cells = <1>;
1560 /* 12: test_clk: wifi_pll_sel */
1562 /* 15:13 reserved */
1565 clk_sel_con44: sel-con@01b0 {
1566 compatible = "rockchip,rk3188-selcon";
1568 #address-cells = <1>;
1571 /* test_clk: wifi_frac */
1574 clk_sel_con45: sel-con@01b4 {
1575 compatible = "rockchip,rk3188-selcon";
1577 #address-cells = <1>;
1580 clk_spi0_div: clk_spi0_div {
1581 compatible = "rockchip,rk3188-div-con";
1582 rockchip,bits = <0 7>;
1583 clocks = <&clk_spi0>;
1584 clock-output-names = "clk_spi0";
1585 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1587 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1590 clk_spi0: clk_spi0_mux {
1591 compatible = "rockchip,rk3188-mux-con";
1592 rockchip,bits = <7 1>;
1593 clocks = <&clk_cpll>, <&clk_gpll>;
1594 clock-output-names = "clk_spi0";
1598 clk_spi1_div: clk_spi1_div {
1599 compatible = "rockchip,rk3188-div-con";
1600 rockchip,bits = <8 7>;
1601 clocks = <&clk_spi1>;
1602 clock-output-names = "clk_spi1";
1603 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1605 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1608 clk_spi1: clk_spi1_mux {
1609 compatible = "rockchip,rk3188-mux-con";
1610 rockchip,bits = <15 1>;
1611 clocks = <&clk_cpll>, <&clk_gpll>;
1612 clock-output-names = "clk_spi1";
1617 clk_sel_con46: sel-con@01b8 {
1618 compatible = "rockchip,rk3188-selcon";
1620 #address-cells = <1>;
1623 clk_tsp_div: clk_tsp_div {
1624 compatible = "rockchip,rk3188-div-con";
1625 rockchip,bits = <0 5>;
1626 clocks = <&clk_tsp>;
1627 clock-output-names = "clk_tsp";
1628 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1630 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1635 clk_tsp: clk_tsp_mux {
1636 compatible = "rockchip,rk3188-mux-con";
1637 rockchip,bits = <6 2>;
1638 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1639 clock-output-names = "clk_tsp";
1643 clk_spi2_div: clk_spi2_div {
1644 compatible = "rockchip,rk3188-div-con";
1645 rockchip,bits = <8 7>;
1646 clocks = <&clk_spi2>;
1647 clock-output-names = "clk_spi2";
1648 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1650 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1653 clk_spi2: clk_spi2_mux {
1654 compatible = "rockchip,rk3188-mux-con";
1655 rockchip,bits = <15 1>;
1656 clocks = <&clk_cpll>, <&clk_gpll>;
1657 clock-output-names = "clk_spi2";
1662 clk_sel_con47: sel-con@01bc {
1663 compatible = "rockchip,rk3188-selcon";
1665 #address-cells = <1>;
1668 clk_nandc0_div: clk_nandc0_div {
1669 compatible = "rockchip,rk3188-div-con";
1670 rockchip,bits = <0 5>;
1671 clocks = <&clk_nandc0>;
1672 clock-output-names = "clk_nandc0";
1673 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1675 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1680 clk_nandc0: clk_nandc0_mux {
1681 compatible = "rockchip,rk3188-mux-con";
1682 rockchip,bits = <7 1>;
1683 clocks = <&clk_cpll>, <&clk_gpll>;
1684 clock-output-names = "clk_nandc0";
1690 /* 15:13 reserved */
1693 clk_sel_con48: sel-con@01c0 {
1694 compatible = "rockchip,rk3188-selcon";
1696 #address-cells = <1>;
1699 clk_sdio0_div: clk_sdio0_div {
1700 compatible = "rockchip,rk3188-div-con";
1701 rockchip,bits = <0 7>;
1702 clocks = <&clk_sdio0>;
1703 clock-output-names = "clk_sdio0";
1704 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1706 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1711 clk_sdio0: clk_sdio0_mux {
1712 compatible = "rockchip,rk3188-mux-con";
1713 rockchip,bits = <8 2>;
1714 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1715 clock-output-names = "clk_sdio0";
1719 /* 15:10 reserved */
1722 /* sel[49] reserved */
1724 clk_sel_con50: sel-con@01c8 {
1725 compatible = "rockchip,rk3188-selcon";
1727 #address-cells = <1>;
1730 clk_sdmmc0_div: clk_sdmmc0_div {
1731 compatible = "rockchip,rk3188-div-con";
1732 rockchip,bits = <0 7>;
1733 clocks = <&clk_sdmmc0>;
1734 clock-output-names = "clk_sdmmc0";
1735 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1737 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1742 clk_sdmmc0: clk_sdmmc0_mux {
1743 compatible = "rockchip,rk3188-mux-con";
1744 rockchip,bits = <8 2>;
1745 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1746 clock-output-names = "clk_sdmmc0";
1750 /* 15:10 reserved */
1753 clk_sel_con51: sel-con@01cc {
1754 compatible = "rockchip,rk3188-selcon";
1756 #address-cells = <1>;
1759 clk_emmc_div: clk_emmc_div {
1760 compatible = "rockchip,rk3188-div-con";
1761 rockchip,bits = <0 7>;
1762 clocks = <&clk_emmc>;
1763 clock-output-names = "clk_emmc";
1764 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1766 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1771 clk_emmc: clk_emmc_mux {
1772 compatible = "rockchip,rk3188-mux-con";
1773 rockchip,bits = <8 2>;
1774 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1775 clock-output-names = "clk_emmc";
1779 /* 15:10 reserved */
1782 clk_sel_con52: sel-con@01d0 {
1783 compatible = "rockchip,rk3188-selcon";
1785 #address-cells = <1>;
1788 clk_sfc_div: clk_sfc_div {
1789 compatible = "rockchip,rk3188-div-con";
1790 rockchip,bits = <0 5>;
1791 clocks = <&clk_sfc>;
1792 clock-output-names = "clk_sfc";
1793 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1795 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1800 clk_sfc: clk_sfc_mux {
1801 compatible = "rockchip,rk3188-mux-con";
1802 rockchip,bits = <7 1>;
1803 clocks = <&clk_cpll>, <&clk_gpll>;
1804 clock-output-names = "clk_sfc";
1811 clk_sel_con53: sel-con@01d4 {
1812 compatible = "rockchip,rk3188-selcon";
1814 #address-cells = <1>;
1817 i2s_2ch_pll_div: i2s_2ch_pll_div {
1818 compatible = "rockchip,rk3188-div-con";
1819 rockchip,bits = <0 7>;
1820 clocks = <&i2s_2ch_pll>;
1821 clock-output-names = "i2s_2ch_pll";
1822 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1824 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1825 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1830 clk_i2s_2ch: clk_i2s_2ch_mux {
1831 compatible = "rockchip,rk3188-mux-con";
1832 rockchip,bits = <8 2>;
1833 clocks = <&i2s_2ch_pll>, <&i2s_2ch_frac>, <&dummy>, <&xin12m>;
1834 clock-output-names = "clk_i2s_2ch";
1836 rockchip,clkops-idx =
1837 <CLKOPS_RATE_RK3288_I2S>;
1838 rockchip,flags = <CLK_SET_RATE_PARENT>;
1841 /* 11:10 reserved */
1843 i2s_2ch_pll: i2s_2ch_pll_mux {
1844 compatible = "rockchip,rk3188-mux-con";
1845 rockchip,bits = <12 1>;
1846 clocks = <&clk_cpll>, <&clk_gpll>;
1847 clock-output-names = "i2s_2ch_pll";
1849 #clock-init-cells = <1>;
1854 clk_sel_con54: sel-con@01d8 {
1855 compatible = "rockchip,rk3188-selcon";
1857 #address-cells = <1>;
1860 i2s_2ch_frac: i2s_2ch_frac {
1861 compatible = "rockchip,rk3188-frac-con";
1862 clocks = <&i2s_2ch_pll>;
1863 clock-output-names = "i2s_2ch_frac";
1864 /* numerator denominator */
1865 rockchip,bits = <0 32>;
1866 rockchip,clkops-idx =
1872 clk_sel_con55: sel-con@01dc {
1873 compatible = "rockchip,rk3188-selcon";
1875 #address-cells = <1>;
1878 clk_hdcp_div: clk_hdcp_div {
1879 compatible = "rockchip,rk3188-div-con";
1880 rockchip,bits = <0 6>;
1881 clocks = <&clk_hdcp>;
1882 clock-output-names = "clk_hdcp";
1883 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1885 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1888 clk_hdcp: clk_hdcp_mux {
1889 compatible = "rockchip,rk3188-mux-con";
1890 rockchip,bits = <6 2>;
1891 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1892 clock-output-names = "clk_hdcp";
1898 /* Gate control regs */
1900 compatible = "rockchip,rk-gate-cons";
1901 #address-cells = <1>;
1905 clk_gates0: gate-clk@0200 {
1906 compatible = "rockchip,rk3188-gate-clk";
1915 <&clk_gpll>, <&clk_apllb>,
1916 <&clk_aplll>, <&dummy>,
1918 <&aclk_cci>, <&clkin_trace>,
1921 clock-output-names =
1922 "reserved", "reserved",/* core_b_apll core_b_gpll */
1923 "reserved", "reserved",
1925 "reserved", "reserved",/* core_l_apll core_l_gpll */
1926 "reserved", "reserved",
1928 "g_clk_cs_gpll", "g_clk_cs_apllb",
1929 "g_clk_cs_aplll", "reserved",
1931 "aclk_cci", "clkin_trace",
1932 "reserved", "reserved";
1937 clk_gates1: gate-clk@0204 {
1938 compatible = "rockchip,rk3188-gate-clk";
1941 <&aclk_bus>, <&hclk_bus>,
1942 <&pclk_bus>, <&fclk_mcu>,
1948 <&clk_gpll>, <&clk_cpll>,
1953 clock-output-names =
1954 "aclk_bus", "hclk_bus",
1955 "pclk_bus", "fclk_mcu",
1957 "reserved", "reserved",
1958 "reserved", "reserved",
1960 "reserved", "reserved",/* ddr_dpll ddr_gpll */
1961 "aclk_bus_gpll", "aclk_bus_cpll",
1963 "reserved", "reserved",
1964 "reserved", "reserved";
1969 clk_gates2: gate-clk@0208 {
1970 compatible = "rockchip,rk3188-gate-clk";
1973 <&clk_uart0_pll>, <&uart0_frac>,
1974 <&uart1_div>, <&uart1_frac>,
1976 <&uart2_div>, <&dummy>,
1977 <&uart3_div>, <&uart3_frac>,
1979 <&uart4_div>, <&uart4_frac>,
1985 clock-output-names =
1986 "clk_uart0_pll", "uart0_frac",
1987 "uart1_div", "uart1_frac",
1989 "uart2_div", "reserved",
1990 "uart3_div", "uart3_frac",
1992 "uart4_div", "uart4_frac",
1993 "reserved", "reserved",
1995 "reserved", "reserved",
1996 "reserved", "reserved";
2001 clk_gates3: gate-clk@020c {
2002 compatible = "rockchip,rk3188-gate-clk";
2005 <&aclk_peri>, <&dummy>,
2006 <&hclk_peri>, <&pclk_peri>,
2008 <&clk_mac_pll>, <&clk_tsadc>,
2009 <&clk_saradc>, <&clk_spi0>,
2011 <&clk_spi1>, <&clk_spi2>,
2017 clock-output-names =
2018 "aclk_peri", "reserved", /* bit1: aclk_peri */
2019 "hclk_peri", "pclk_peri",
2021 "clk_mac_pll", "clk_tsadc",
2022 "clk_saradc", "clk_spi0",
2024 "clk_spi1", "clk_spi2",
2025 "reserved", "reserved",
2027 "reserved", "reserved",
2028 "reserved", "reserved";
2033 clk_gates4: gate-clk@0210 {
2034 compatible = "rockchip,rk3188-gate-clk";
2037 <&aclk_vio0>, <&dclk_vop0>,
2038 <&xin24m>, <&aclk_rga_pre>,
2040 <&clk_rga>, <&clk_vip>,
2041 <&aclk_vepu>, <&aclk_vdpu>,
2043 <&dummy>, <&clk_isp>,
2044 <&dummy>, <&clk_gpu_core>,
2046 <&xin32k>, <&xin24m>,
2047 <&xin24m>, <&dummy>;
2049 clock-output-names =
2050 "aclk_vio0", "dclk_vop0",
2051 "clk_vop0_pwm", "aclk_rga_pre",
2053 "clk_rga", "clk_vip",
2054 "aclk_vepu", "aclk_vdpu",
2056 "reserved", "clk_isp", /* bit8: hclk_vpu */
2057 "reserved", "clk_gpu_core",
2059 "clk_hdmi_cec", "clk_hdmi_hdcp",
2060 "clk_dsiphy_24m", "reserved";
2065 clk_gates5: gate-clk@0214 {
2066 compatible = "rockchip,rk3188-gate-clk";
2069 <&dummy>, <&clk_hevc_cabac>,
2070 <&clk_hevc_core>, <&clk_edp>,
2072 <&clk_edp_24m>, <&clk_hdcp>,
2075 <&aclk_gpu_mem>, <&aclk_gpu_cfg>,
2078 <&dummy>, <&i2s_2ch_pll>,
2079 <&i2s_2ch_frac>, <&clk_i2s_2ch>;
2081 clock-output-names =
2082 "reserved", "clk_hevc_cabac",
2083 "clk_hevc_core", "clk_edp",
2085 "clk_edp_24m", "clk_hdcp",
2086 "reserved", "reserved",
2088 "aclk_gpu_mem", "aclk_gpu_cfg",
2089 "reserved", "reserved",
2091 "reserved", "i2s_2ch_pll",
2092 "i2s_2ch_frac", "clk_i2s_2ch";
2097 clk_gates6: gate-clk@0218 {
2098 compatible = "rockchip,rk3188-gate-clk";
2101 <&i2s_out>, <&i2s_pll>,
2102 <&i2s_frac>, <&clk_i2s>,
2104 <&spdif_8ch_pll>, <&spdif_8ch_frac>,
2105 <&clk_spidf_8ch>, <&clk_sfc>,
2110 <&clk_tsp>, <&dummy>,
2113 clock-output-names =
2114 "i2s_out", "i2s_pll",
2115 "i2s_frac", "clk_i2s",
2117 "spdif_8ch_pll", "spdif_8ch_frac",
2118 "clk_spidf_8ch", "clk_sfc",
2120 "reserved", "reserved",
2121 "reserved", "reserved",
2123 "clk_tsp", "reserved",
2124 "reserved", "reserved";/* clk_ddrphy_gate clk4x_ddrphy_gate */
2129 clk_gates7: gate-clk@021c {
2130 compatible = "rockchip,rk3188-gate-clk";
2133 <&jtag_clkin>, <&dummy>,
2134 <&clk_crypto>, <&xin24m>,
2137 <&clk_mac>, <&clk_mac>,
2139 <&clk_nandc0>, <&pclk_pmu_pre>,
2140 <&xin24m>, <&xin24m>,
2145 clock-output-names =
2146 "clk_jtag", "reserved",/* bit1: test_clk */
2147 "clk_crypto", "clk_pvtm_pmu",
2149 "reserved", "reserved",/* clk_mac_rx clk_mac_tx */
2150 "clk_mac_ref", "clk_mac_refout",
2152 "clk_nandc0", "pclk_pmu_pre",
2153 "clk_pvtm_core", "clk_pvtm_gpu",
2155 "clk_sdmmc0", "clk_sdio0",
2156 "reserved", "clk_emmc";
2161 clk_gates8: gate-clk@0220 {
2162 compatible = "rockchip,rk3188-gate-clk";
2165 <&hsic_usb_480m>, <&xin24m>,
2168 <&clk_32k_mux>, <&dummy>,
2169 <&xin12m>, <&hsicphy_480m>,
2177 clock-output-names =
2178 "hsic_usb_480m", "clk_otgphy0",
2179 "reserved", "reserved",
2181 "g_clk_otg_adp", "reserved",/* bit4: clk_otg_adp */
2182 "hsicphy_12m", "hsicphy_480m",
2184 "reserved", "reserved",
2185 "reserved", "reserved",
2187 "reserved", "reserved",
2188 "reserved", "reserved";
2193 clk_gates9: gate-clk@0224 {
2194 compatible = "rockchip,rk3188-gate-clk";
2209 clock-output-names =
2210 "reserved", "reserved",
2211 "reserved", "reserved",
2213 "reserved", "reserved",
2214 "reserved", "reserved",
2216 "reserved", "reserved",
2217 "reserved", "reserved",
2219 "reserved", "reserved",
2220 "reserved", "reserved";
2225 clk_gates10: gate-clk@0228 {
2226 compatible = "rockchip,rk3188-gate-clk";
2241 clock-output-names =
2242 "reserved", "reserved",
2243 "reserved", "reserved",
2245 "reserved", "reserved",
2246 "reserved", "reserved",
2248 "reserved", "reserved",
2249 "reserved", "reserved",
2251 "reserved", "reserved",
2252 "reserved", "reserved";
2257 clk_gates11: gate-clk@022c {
2258 compatible = "rockchip,rk3188-gate-clk";
2273 clock-output-names =
2274 "reserved", "reserved",
2275 "reserved", "reserved",
2277 "reserved", "reserved",
2278 "reserved", "reserved",
2280 "reserved", "reserved",
2281 "reserved", "reserved",
2283 "reserved", "reserved",
2284 "reserved", "reserved";
2289 clk_gates12: gate-clk@0230 {
2290 compatible = "rockchip,rk3188-gate-clk";
2293 <&pclk_bus>, <&pclk_bus>,
2294 <&pclk_bus>, <&pclk_bus>,
2296 <&aclk_bus>, <&aclk_bus>,
2297 <&aclk_bus>, <&hclk_bus>,
2299 <&hclk_bus>, <&hclk_bus>,
2300 <&hclk_bus>, <&aclk_bus>,
2302 <&aclk_bus>, <&dummy>,
2305 clock-output-names =
2306 "g_pclk_pwm0", "g_p_mailbox",
2307 "g_p_i2cpmu", "g_p_i2caudio",
2309 "g_aclk_intmem", "g_clk_intmem0",
2310 "g_clk_intmem1", "g_h_i2s_8ch",
2312 "g_h_i2s_2ch", "g_hclk_rom",
2313 "g_hclk_spdif", "g_aclk_dmac",
2315 "g_a_strc_sys", "reserved",/* bit13: pclk_ddrupctl */
2316 "reserved", "reserved";/* bit14: pclk_ddrphy */
2321 clk_gates13: gate-clk@0234 {
2322 compatible = "rockchip,rk3188-gate-clk";
2325 <&pclk_bus>, <&pclk_bus>,
2326 <&dummy>, <&hclk_bus>,
2328 <&hclk_bus>, <&pclk_bus>,
2329 <&pclk_bus>, <&clkin_hsadc_tsp>,
2331 <&pclk_bus>, <&aclk_bus>,
2332 <&hclk_bus>, <&dummy>,
2337 clock-output-names =
2338 "g_p_efuse_1024", "g_p_efuse_256",
2339 "reserved", "g_mclk_crypto",/* bit2: nclk_ddrupctl */
2341 "g_sclk_crypto", "g_p_uartdbg",
2342 "g_pclk_pwm1", "clk_hsadc_tsp",
2344 "g_pclk_sim", "g_aclk_gic400",
2345 "g_hclk_tsp", "reserved",
2347 "reserved", "reserved",
2348 "reserved", "reserved";
2353 clk_gates14: gate-clk@0238 {
2354 compatible = "rockchip,rk3188-gate-clk";
2369 clock-output-names =
2370 "reserved", "reserved",
2371 "reserved", "reserved",
2373 "reserved", "reserved",
2374 "reserved", "reserved",
2376 "reserved", "reserved",
2377 "reserved", "reserved",
2379 "reserved", "reserved",
2380 "reserved", "reserved";
2385 clk_gates15: gate-clk@023c {
2386 compatible = "rockchip,rk3188-gate-clk";
2401 clock-output-names =
2402 "reserved", "reserved",/* aclk_video hclk_video */
2403 "reserved", "reserved",
2405 "reserved", "reserved",
2406 "reserved", "reserved",
2408 "reserved", "reserved",
2409 "reserved", "reserved",
2411 "reserved", "reserved",
2412 "reserved", "reserved";
2417 clk_gates16: gate-clk@0240 {
2418 compatible = "rockchip,rk3188-gate-clk";
2421 <&clk_gates16 10>, <&clk_gates16 8>,
2422 <&clk_gates16 9>, <&clk_gates16 8>,
2424 <&clk_gates16 9>, <&clk_gates16 9>,
2425 <&clk_gates16 8>, <&clk_gates16 8>,
2427 <&hclk_vio>, <&aclk_vio0>,
2428 <&aclk_rga_pre>, <&clk_gates16 9>,
2430 <&clk_gates16 8>, <&pclkin_vip>,
2431 <&clk_isp>, <&dummy>;
2433 clock-output-names =
2434 "g_aclk_rga", "g_hclk_rga",
2435 "g_aclk_iep", "g_hclk_iep",
2437 "g_aclk_vop_iep", "g_aclk_vop",
2438 "g_hclk_vop", "h_vio_ahb_arbi",
2440 "g_hclk_vio_noc", "g_aclk_vio0_noc",
2441 "g_aclk_vio1_noc", "g_aclk_vip",
2443 "g_hclk_vip", "g_pclkin_vip",
2444 "g_hclk_isp", "reserved";
2449 clk_gates17: gate-clk@0244 {
2450 compatible = "rockchip,rk3188-gate-clk";
2453 <&clk_isp>, <&dummy>,
2454 <&pclkin_isp>, <&pclk_vio>,
2456 <&pclk_vio>, <&dummy>,
2457 <&pclk_vio>, <&clk_gates16 8>,
2459 <&pclk_vio>, <&pclk_vio>,
2460 <&clk_gates16 10>, <&pclk_vio>,
2462 <&clk_gates16 8>, <&dummy>,
2465 clock-output-names =
2466 "g_aclk_isp", "reserved",
2467 "g_pclkin_isp", "g_p_mipi_dsi0",
2469 "g_p_mipi_csi", "reserved",
2470 "g_p_hdmi_ctrl", "g_hclk_vio_h2p",
2472 "g_pclk_vio_h2p", "g_p_edp_ctrl",
2473 "g_aclk_hdcp", "g_pclk_hdcp",
2475 "g_h_hdcpmmu", "reserved",
2476 "reserved", "reserved";
2481 clk_gates18: gate-clk@0248 {
2482 compatible = "rockchip,rk3188-gate-clk";
2497 clock-output-names =
2498 "reserved", "reserved",/* bit0-1: aclk_gpu_cfg aclk_gpu_mem */
2499 "reserved", "reserved",/* bit2: clk_gpu_core */
2501 "reserved", "reserved",
2502 "reserved", "reserved",
2504 "reserved", "reserved",
2505 "reserved", "reserved",
2507 "reserved", "reserved",
2508 "reserved", "reserved";
2513 clk_gates19: gate-clk@024c {
2514 compatible = "rockchip,rk3188-gate-clk";
2517 <&hclk_peri>, <&pclk_peri>,
2518 <&aclk_peri>, <&aclk_peri>,
2520 <&pclk_peri>, <&pclk_peri>,
2521 <&pclk_peri>, <&pclk_peri>,
2523 <&pclk_peri>, <&pclk_peri>,
2524 <&pclk_peri>, <&pclk_peri>,
2526 <&pclk_peri>, <&pclk_peri>,
2527 <&pclk_peri>, <&pclk_peri>;
2529 clock-output-names =
2530 "g_hp_axi_matrix", "g_pp_axi_matrix",
2531 "g_ap_axi_matrix", "g_a_dmac_peri",
2533 "g_pclk_spi0", "g_pclk_spi1",
2534 "g_pclk_spi2", "g_pclk_uart0",
2536 "g_pclk_uart1", "g_pclk_uart3",
2537 "g_pclk_uart4", "g_pclk_i2c2",
2539 "g_pclk_i2c3", "g_pclk_i2c4",
2540 "g_pclk_i2c5", "g_pclk_saradc";
2545 clk_gates20: gate-clk@0250 {
2546 compatible = "rockchip,rk3188-gate-clk";
2549 <&pclk_peri>, <&hclk_peri>,
2550 <&hclk_peri>, <&hclk_peri>,
2552 <&dummy>, <&hclk_peri>,
2553 <&hclk_peri>, <&hclk_peri>,
2555 <&aclk_peri>, <&hclk_peri>,
2556 <&hclk_peri>, <&hclk_peri>,
2558 <&dummy>, <&aclk_peri>,
2559 <&pclk_peri>, <&aclk_peri>;
2561 clock-output-names =
2562 "g_pclk_tsadc", "g_hclk_otg0",
2563 "g_h_pmu_otg0", "g_hclk_host0",
2565 "reserved", "g_hclk_hsic",
2566 "g_h_usb_peri", "g_h_p_ahb_arbi",
2568 "g_a_peri_niu", "g_h_emem_peri",
2569 "g_h_mmc_peri", "g_hclk_nand0",
2571 "reserved", "g_aclk_gmac",
2572 "g_pclk_gmac", "g_hclk_sfc";
2577 clk_gates21: gate-clk@0254 {
2578 compatible = "rockchip,rk3188-gate-clk";
2581 <&hclk_peri>, <&hclk_peri>,
2582 <&hclk_peri>, <&hclk_peri>,
2584 <&aclk_peri>, <&dummy>,
2593 clock-output-names =
2594 "g_hclk_sdmmc", "g_hclk_sdio0",
2595 "g_hclk_emmc", "g_hclk_hsadc",
2597 "g_aclk_peri_mmu", "reserved",
2598 "reserved", "reserved",
2600 "reserved", "reserved",
2601 "reserved", "reserved",
2603 "reserved", "reserved",
2604 "reserved", "reserved";
2609 clk_gates22: gate-clk@0258 {
2610 compatible = "rockchip,rk3188-gate-clk";
2613 <&dummy>, <&pclk_alive_pre>,
2614 <&pclk_alive_pre>, <&pclk_alive_pre>,
2619 <&pclk_alive_pre>, <&pclk_alive_pre>,
2620 <&pclk_vio>, <&pclk_vio>,
2622 <&pclk_alive_pre>, <&pclk_alive_pre>,
2625 clock-output-names =
2626 "reserved", "g_pclk_gpio1",
2627 "g_pclk_gpio2", "g_pclk_gpio3",
2629 "reserved", "reserved",
2630 "reserved", "reserved",
2632 "g_pclk_grf", "g_p_alive_niu",
2633 "g_pclk_dphytx0", "g_pclk_dphyrx",
2635 "g_pclk_timer0", "g_pclk_timer1",
2636 "reserved", "reserved";
2641 clk_gates23: gate-clk@025c {
2642 compatible = "rockchip,rk3188-gate-clk";
2645 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
2646 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
2648 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
2657 clock-output-names =
2658 "g_pclk_pmu", "g_pclk_intmem1",
2659 "g_pclk_pmu_noc", "g_pclk_sgrf",
2661 "g_pclk_gpio0", "g_pclk_pmugrf",
2662 "reserved", "reserved",
2664 "reserved", "reserved",
2665 "reserved", "reserved",
2667 "reserved", "reserved",
2668 "reserved", "reserved";
2673 clk_gates24: gate-clk@0260 {
2674 compatible = "rockchip,rk3188-gate-clk";
2677 <&xin24m>, <&xin24m>,
2678 <&xin24m>, <&xin24m>,
2680 <&xin24m>, <&xin24m>,
2681 <&xin24m>, <&xin24m>,
2683 <&xin24m>, <&xin24m>,
2684 <&xin24m>, <&xin24m>,
2689 clock-output-names =
2690 "g_clk_timer0", "g_clk_timer1",
2691 "g_clk_timer2", "g_clk_timer3",
2693 "g_clk_timer4", "g_clk_timer5",
2694 "g_clk_timer10", "g_clk_timer11",
2696 "g_clk_timer12", "g_clk_timer13",
2697 "g_clk_timer14", "g_clk_timer15",
2699 "reserved", "reserved",
2700 "reserved", "reserved";
2708 compatible = "rockchip,rk-clock-special-regs";
2709 #address-cells = <2>;
2713 clk_32k_mux: clk_32k_mux {
2714 compatible = "rockchip,rk3188-mux-con";
2715 reg = <0x0 0xff738100 0x0 0x4>;
2716 rockchip,bits = <6 1>;
2717 clocks = <&xin32k>, <&clk_gates7 3>;
2718 clock-output-names = "clk_32k_mux";
2720 #clock-init-cells = <1>;