arch/arm64/boot/dts/rk3368-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014-2015 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3368.h>
  15
  16 /{
  17         clocks {
  18                 compatible = "rockchip,rk-clocks";
  19                 rockchip,grf = <&grf>;
  20                 #address-cells = <2>;
  21                 #size-cells = <2>;
  22                 ranges;
  23
  24                 fixed_rate_cons {
  25                         compatible = "rockchip,rk-fixed-rate-cons";
  26
  27                         xin24m: xin24m {
  28                                 compatible = "rockchip,rk-fixed-clock";
  29                                 clock-output-names = "xin24m";
  30                                 clock-frequency = <24000000>;
  31                                 #clock-cells = <0>;
  32                         };
  33
  34                         xin12m: xin12m {
  35                                 compatible = "rockchip,rk-fixed-clock";
  36                                 clocks = <&xin24m>;
  37                                 clock-output-names = "xin12m";
  38                                 clock-frequency = <12000000>;
  39                                 #clock-cells = <0>;
  40                         };
  41
  42                         xin32k: xin32k {
  43                                 compatible = "rockchip,rk-fixed-clock";
  44                                 clock-output-names = "xin32k";
  45                                 clock-frequency = <32000>;
  46                                 #clock-cells = <0>;
  47                         };
  48
  49                         dummy: dummy {
  50                                 compatible = "rockchip,rk-fixed-clock";
  51                                 clock-output-names = "dummy";
  52                                 clock-frequency = <0>;
  53                                 #clock-cells = <0>;
  54                         };
  55
  56                         jtag_clkin: jtag_clkin {
  57                                 compatible = "rockchip,rk-fixed-clock";
  58                                 clock-output-names = "jtag_clkin";
  59                                 clock-frequency = <0>;
  60                                 #clock-cells = <0>;
  61                         };
  62
  63                         gmac_clkin: gmac_clkin {
  64                                 compatible = "rockchip,rk-fixed-clock";
  65                                 clock-output-names = "gmac_clkin";
  66                                 clock-frequency = <0>;
  67                                 #clock-cells = <0>;
  68                         };
  69
  70                         pclkin_isp: pclkin_isp {
  71                                 compatible = "rockchip,rk-fixed-clock";
  72                                 clock-output-names = "pclkin_isp";
  73                                 clock-frequency = <0>;
  74                                 #clock-cells = <0>;
  75                         };
  76
  77                         pclkin_vip: pclkin_vip {
  78                                 compatible = "rockchip,rk-fixed-clock";
  79                                 clock-output-names = "pclkin_vip";
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                         };
  83
  84                         clkin_hsadc_tsp: clkin_hsadc_tsp {
  85                                 compatible = "rockchip,rk-fixed-clock";
  86                                 clock-output-names = "clkin_hsadc_tsp";
  87                                 clock-frequency = <0>;
  88                                 #clock-cells = <0>;
  89                         };
  90
  91                         i2s_clkin: i2s_clkin {
  92                                 compatible = "rockchip,rk-fixed-clock";
  93                                 clock-output-names = "i2s_clkin";
  94                                 clock-frequency = <0>;
  95                                 #clock-cells = <0>;
  96                         };
  97                 };
  98
  99                 fixed_factor_cons {
 100                         compatible = "rockchip,rk-fixed-factor-cons";
 101
 102                         hclk_vepu: hclk_vepu {
 103                                 compatible = "rockchip,rk-fixed-factor-clock";
 104                                 clocks = <&aclk_vepu>;
 105                                 clock-output-names = "hclk_vepu";
 106                                 clock-div = <4>;
 107                                 clock-mult = <1>;
 108                                 #clock-cells = <0>;
 109                         };
 110
 111                         hclk_vdpu: hclk_vdpu {
 112                                 compatible = "rockchip,rk-fixed-factor-clock";
 113                                 clocks = <&aclk_vdpu>;
 114                                 clock-output-names = "hclk_vdpu";
 115                                 clock-div = <4>;
 116                                 clock-mult = <1>;
 117                                 #clock-cells = <0>;
 118                         };
 119
 120                         usbotg_480m_out: usbotg_480m_out {
 121                                 compatible = "rockchip,rk-fixed-factor-clock";
 122                                 clocks = <&clk_gates8 1>;
 123                                 clock-output-names = "usbotg_480m_out";
 124                                 clock-div = <1>;
 125                                 clock-mult = <20>;
 126                                 #clock-cells = <0>;
 127                         };
 128
 129                         pclkin_isp_inv: pclkin_isp_inv {
 130                                 compatible = "rockchip,rk-fixed-factor-clock";
 131                                 clocks = <&clk_gates17 2>;
 132                                 clock-output-names = "pclkin_isp_inv";
 133                                 clock-div = <1>;
 134                                 clock-mult = <1>;
 135                                 #clock-cells = <0>;
 136                         };
 137
 138                         pclkin_vip_inv: pclkin_vip_inv {
 139                                 compatible = "rockchip,rk-fixed-factor-clock";
 140                                 clocks = <&clk_gates16 13>;
 141                                 clock-output-names = "pclkin_vip_inv";
 142                                 clock-div = <1>;
 143                                 clock-mult = <1>;
 144                                 #clock-cells = <0>;
 145                         };
 146
 147                         pclk_vio: pclk_vio {
 148                                 compatible = "rockchip,rk-fixed-factor-clock";
 149                                 clocks = <&clk_gates16 8>;
 150                                 clock-output-names = "pclk_vio";
 151                                 clock-div = <1>;
 152                                 clock-mult = <1>;
 153                                 #clock-cells = <0>;
 154                         };
 155                 };
 156
 157                 clock_regs {
 158                         compatible = "rockchip,rk-clock-regs";
 159                         #address-cells = <1>;
 160                         #size-cells = <1>;
 161                         ranges = <0x0 0x0 0xff760000 0x1000>;
 162                         reg = <0x0 0xff760000 0x0 0x1000>;
 163
 164                         /* PLL control regs */
 165                         pll_cons {
 166                                 compatible = "rockchip,rk-pll-cons";
 167                                 #address-cells = <1>;
 168                                 #size-cells = <1>;
 169                                 ranges;
 170
 171                                 clk_apllb: pll-clk@0000 {
 172                                         compatible = "rockchip,rk3188-pll-clk";
 173                                         reg = <0x0000 0x10>;
 174                                         mode-reg = <0x000c 8>;
 175                                         status-reg = <0x0480 1>;
 176                                         clocks = <&xin24m>;
 177                                         clock-output-names = "clk_apllb";
 178                                         rockchip,pll-type = <CLK_PLL_3368_APLLB>;
 179                                         #clock-cells = <0>;
 180                                 };
 181
 182
 183                                 clk_aplll: pll-clk@0010 {
 184                                         compatible = "rockchip,rk3188-pll-clk";
 185                                         reg = <0x0010 0x10>;
 186                                         mode-reg = <0x001c 8>;
 187                                         status-reg = <0x0480 0>;
 188                                         clocks = <&xin24m>;
 189                                         clock-output-names = "clk_aplll";
 190                                         rockchip,pll-type = <CLK_PLL_3368_APLLL>;
 191                                         #clock-cells = <0>;
 192                                 };
 193
 194                                 clk_dpll: pll-clk@0020 {
 195                                         compatible = "rockchip,rk3188-pll-clk";
 196                                         reg = <0x0020 0x10>;
 197                                         mode-reg = <0x002c 8>;
 198                                         status-reg = <0x0480 2>;
 199                                         clocks = <&xin24m>;
 200                                         clock-output-names = "clk_dpll";
 201                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 202                                         #clock-cells = <0>;
 203                                 };
 204
 205
 206                                 clk_cpll: pll-clk@0030 {
 207                                         compatible = "rockchip,rk3188-pll-clk";
 208                                         reg = <0x0030 0x10>;
 209                                         mode-reg = <0x003c 8>;
 210                                         status-reg = <0x0480 3>;
 211                                         clocks = <&xin24m>;
 212                                         clock-output-names = "clk_cpll";
 213                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 214                                         #clock-cells = <0>;
 215                                         #clock-init-cells = <1>;
 216                                 };
 217
 218                                 clk_gpll: pll-clk@0040 {
 219                                         compatible = "rockchip,rk3188-pll-clk";
 220                                         reg = <0x0040 0x10>;
 221                                         mode-reg = <0x004c 8>;
 222                                         status-reg = <0x0480 4>;
 223                                         clocks = <&xin24m>;
 224                                         clock-output-names = "clk_gpll";
 225                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 226                                         #clock-cells = <0>;
 227                                         #clock-init-cells = <1>;
 228                                 };
 229
 230                                 clk_npll: pll-clk@0050 {
 231                                         compatible = "rockchip,rk3188-pll-clk";
 232                                         reg = <0x0050 0x10>;
 233                                         mode-reg = <0x005c 8>;
 234                                         status-reg = <0x0480 5>;
 235                                         clocks = <&xin24m>;
 236                                         clock-output-names = "clk_npll";
 237                                         rockchip,pll-type = <CLK_PLL_3368_LOW_JITTER>;
 238                                         #clock-cells = <0>;
 239                                         #clock-init-cells = <1>;
 240                                 };
 241                         };
 242
 243                         /* Select control regs */
 244                         clk_sel_cons {
 245                                 compatible = "rockchip,rk-sel-cons";
 246                                 #address-cells = <1>;
 247                                 #size-cells = <1>;
 248                                 ranges;
 249
 250                                 clk_sel_con0: sel-con@0100 {
 251                                         compatible = "rockchip,rk3188-selcon";
 252                                         reg = <0x0100 0x4>;
 253                                         #address-cells = <1>;
 254                                         #size-cells = <1>;
 255
 256                                         clk_core_b_div: clk_core_b_div {
 257                                                 compatible = "rockchip,rk3188-div-con";
 258                                                 rockchip,bits = <0 5>;
 259                                                 clocks = <&clk_core_b>;
 260                                                 clock-output-names = "clk_core_b";
 261                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 262                                                 #clock-cells = <0>;
 263                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 264                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 265                                                                         CLK_SET_RATE_NO_REPARENT)>;
 266                                         };
 267
 268                                         /* 6:5 reserved */
 269
 270                                         clk_core_b: clk_core_b_mux {
 271                                                 compatible = "rockchip,rk3188-mux-con";
 272                                                 rockchip,bits = <7 1>;
 273                                                 clocks = <&clk_apllb>, <&clk_gpll>;
 274                                                 clock-output-names = "clk_core_b";
 275                                                 #clock-cells = <0>;
 276                                                 #clock-init-cells = <1>;
 277                                         };
 278
 279                                         aclkm_core_b: aclkm_core_b_div {
 280                                                 compatible = "rockchip,rk3188-div-con";
 281                                                 rockchip,bits = <8 5>;
 282                                                 clocks = <&clk_core_b>;
 283                                                 clock-output-names = "aclkm_core_b";
 284                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 285                                                 #clock-cells = <0>;
 286                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 287                                         };
 288
 289                                         /* 15:13 reserved */
 290                                 };
 291
 292                                 clk_sel_con1: sel-con@0104 {
 293                                         compatible = "rockchip,rk3188-selcon";
 294                                         reg = <0x0104 0x4>;
 295                                         #address-cells = <1>;
 296                                         #size-cells = <1>;
 297
 298                                         atclk_core_b: atclk_core_b_div {
 299                                                 compatible = "rockchip,rk3188-div-con";
 300                                                 rockchip,bits = <0 5>;
 301                                                 clocks = <&clk_core_b>;
 302                                                 clock-output-names = "atclk_core_b";
 303                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 304                                                 #clock-cells = <0>;
 305                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 306                                         };
 307
 308                                         /* 7:5 reserved */
 309
 310                                         pclk_dbg_b: pclk_dbg_b_div {
 311                                                 compatible = "rockchip,rk3188-div-con";
 312                                                 rockchip,bits = <8 5>;
 313                                                 clocks = <&clk_core_b>;
 314                                                 clock-output-names = "pclk_dbg_b";
 315                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 316                                                 #clock-cells = <0>;
 317                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 318                                         };
 319                                 };
 320
 321                                 clk_sel_con2: sel-con@0108 {
 322                                         compatible = "rockchip,rk3188-selcon";
 323                                         reg = <0x0108 0x4>;
 324                                         #address-cells = <1>;
 325                                         #size-cells = <1>;
 326
 327                                         clk_core_l_div: clk_core_l_div {
 328                                                 compatible = "rockchip,rk3188-div-con";
 329                                                 rockchip,bits = <0 5>;
 330                                                 clocks = <&clk_core_l>;
 331                                                 clock-output-names = "clk_core_l";
 332                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 333                                                 #clock-cells = <0>;
 334                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 335                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 336                                                                         CLK_SET_RATE_NO_REPARENT)>;
 337                                         };
 338
 339                                         /* 6:5 reserved */
 340
 341                                         clk_core_l: clk_core_l_mux {
 342                                                 compatible = "rockchip,rk3188-mux-con";
 343                                                 rockchip,bits = <7 1>;
 344                                                 clocks = <&clk_aplll>, <&clk_gpll>;
 345                                                 clock-output-names = "clk_core_l";
 346                                                 #clock-cells = <0>;
 347                                                 #clock-init-cells = <1>;
 348                                         };
 349
 350                                         aclkm_core_l: aclkm_core_l_div {
 351                                                 compatible = "rockchip,rk3188-div-con";
 352                                                 rockchip,bits = <8 5>;
 353                                                 clocks = <&clk_core_l>;
 354                                                 clock-output-names = "aclkm_core_l";
 355                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 356                                                 #clock-cells = <0>;
 357                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 358                                         };
 359
 360                                         /* 15:13 reserved */
 361                                 };
 362
 363                                 clk_sel_con3: sel-con@010c {
 364                                         compatible = "rockchip,rk3188-selcon";
 365                                         reg = <0x010c 0x4>;
 366                                         #address-cells = <1>;
 367                                         #size-cells = <1>;
 368
 369                                         atclk_core_l: atclk_core_l_div {
 370                                                 compatible = "rockchip,rk3188-div-con";
 371                                                 rockchip,bits = <0 5>;
 372                                                 clocks = <&clk_core_l>;
 373                                                 clock-output-names = "atclk_core_l";
 374                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 375                                                 #clock-cells = <0>;
 376                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 377                                         };
 378
 379                                         /* 7:5 reserved */
 380
 381                                         pclk_dbg_l: pclk_dbg_l_div {
 382                                                 compatible = "rockchip,rk3188-div-con";
 383                                                 rockchip,bits = <8 5>;
 384                                                 clocks = <&clk_core_l>;
 385                                                 clock-output-names = "pclk_dbg_l";
 386                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 387                                                 #clock-cells = <0>;
 388                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 389                                         };
 390                                 };
 391
 392                                 clk_sel_con4: sel-con@0110 {
 393                                         compatible = "rockchip,rk3188-selcon";
 394                                         reg = <0x0110 0x4>;
 395                                         #address-cells = <1>;
 396                                         #size-cells = <1>;
 397
 398                                         clk_cs_div: clk_cs_div {
 399                                                 compatible = "rockchip,rk3188-div-con";
 400                                                 rockchip,bits = <0 5>;
 401                                                 clocks = <&clk_cs>;
 402                                                 clock-output-names = "clk_cs";
 403                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 404                                                 #clock-cells = <0>;
 405                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 406                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 407                                         };
 408
 409                                         /* 5 reserved */
 410
 411                                         clk_cs: clk_cs_mux {
 412                                                 compatible = "rockchip,rk3188-mux-con";
 413                                                 rockchip,bits = <6 2>;
 414                                                 clocks = <&clk_gates0 9>, <&clk_gates0 10>, <&clk_gates0 8>, <&dummy>;
 415                                                 clock-output-names = "clk_cs";
 416                                                 #clock-cells = <0>;
 417                                                 #clock-init-cells = <1>;
 418                                         };
 419
 420                                         clkin_trace: clkin_trace_div {
 421                                                 compatible = "rockchip,rk3188-div-con";
 422                                                 rockchip,bits = <8 5>;
 423                                                 clocks = <&clk_cs>;
 424                                                 clock-output-names = "clkin_trace";
 425                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 426                                                 #clock-cells = <0>;
 427                                                 #clock-init-cells = <1>;
 428                                         };
 429
 430                                 };
 431
 432                                 clk_sel_con5: sel-con@0114 {
 433                                         compatible = "rockchip,rk3188-selcon";
 434                                         reg = <0x0114 0x4>;
 435                                         #address-cells = <1>;
 436                                         #size-cells = <1>;
 437
 438                                         aclk_cci_div: aclk_cci_div {
 439                                                 compatible = "rockchip,rk3188-div-con";
 440                                                 rockchip,bits = <0 5>;
 441                                                 clocks = <&aclk_cci>;
 442                                                 clock-output-names = "aclk_cci";
 443                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 444                                                 #clock-cells = <0>;
 445                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 446                                         };
 447
 448                                         /* 5 reserved */
 449
 450                                         aclk_cci: aclk_cci_mux {
 451                                                 compatible = "rockchip,rk3188-mux-con";
 452                                                 rockchip,bits = <6 2>;
 453                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 454                                                 clock-output-names = "aclk_cci";
 455                                                 #clock-cells = <0>;
 456                                                 #clock-init-cells = <1>;
 457                                         };
 458                                 };
 459
 460                                 /* sel[7:6] reserved */
 461
 462                                 clk_sel_con8: sel-con@0120 {
 463                                         compatible = "rockchip,rk3188-selcon";
 464                                         reg = <0x0120 0x4>;
 465                                         #address-cells = <1>;
 466                                         #size-cells = <1>;
 467
 468                                         aclk_bus_div: aclk_bus_div {
 469                                                 compatible = "rockchip,rk3188-div-con";
 470                                                 rockchip,bits = <0 5>;
 471                                                 clocks = <&aclk_bus>;
 472                                                 clock-output-names = "aclk_bus";
 473                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 474                                                 #clock-cells = <0>;
 475                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 476                                         };
 477
 478                                         /* 6:5 reserved */
 479
 480                                         aclk_bus: aclk_bus_mux {
 481                                                 compatible = "rockchip,rk3188-mux-con";
 482                                                 rockchip,bits = <7 1>;
 483                                                 clocks = <&clk_gates1 11>, <&clk_gates1 10>;
 484                                                 clock-output-names = "aclk_bus";
 485                                                 #clock-cells = <0>;
 486                                                 #clock-init-cells = <1>;
 487                                         };
 488
 489                                         hclk_bus: hclk_bus_div {
 490                                                 compatible = "rockchip,rk3188-div-con";
 491                                                 rockchip,bits = <8 2>;
 492                                                 clocks = <&aclk_bus>;
 493                                                 clock-output-names = "hclk_bus";
 494                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 495                                                 #clock-cells = <0>;
 496                                                 #clock-init-cells = <1>;
 497                                         };
 498
 499                                         /* 11:10 reserved */
 500
 501                                         pclk_bus: pclk_bus_div {
 502                                                 compatible = "rockchip,rk3188-div-con";
 503                                                 rockchip,bits = <12 3>;
 504                                                 clocks = <&aclk_bus>;
 505                                                 clock-output-names = "pclk_bus";
 506                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 507                                                 #clock-cells = <0>;
 508                                                 #clock-init-cells = <1>;
 509                                         };
 510                                 };
 511
 512                                 clk_sel_con9: sel-con@0124 {
 513                                         compatible = "rockchip,rk3188-selcon";
 514                                         reg = <0x0124 0x4>;
 515                                         #address-cells = <1>;
 516                                         #size-cells = <1>;
 517
 518                                         aclk_peri_div: aclk_peri_div {
 519                                                 compatible = "rockchip,rk3188-div-con";
 520                                                 rockchip,bits = <0 5>;
 521                                                 clocks = <&aclk_peri>;
 522                                                 clock-output-names = "aclk_peri";
 523                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 524                                                 #clock-cells = <0>;
 525                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 526                                         };
 527
 528                                         /* 6:5 reserved */
 529
 530                                         aclk_peri: aclk_peri_mux {
 531                                                 compatible = "rockchip,rk3188-mux-con";
 532                                                 rockchip,bits = <7 1>;
 533                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 534                                                 clock-output-names = "aclk_peri";
 535                                                 #clock-cells = <0>;
 536                                                 #clock-init-cells = <1>;
 537                                         };
 538
 539                                         hclk_peri: hclk_peri_div {
 540                                                 compatible = "rockchip,rk3188-div-con";
 541                                                 rockchip,bits = <8 2>;
 542                                                 clocks = <&aclk_peri>;
 543                                                 clock-output-names = "hclk_peri";
 544                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 545                                                 rockchip,div-relations =
 546                                                                 <0x0 1
 547                                                                  0x1 2
 548                                                                  0x2 4>;
 549                                                 #clock-cells = <0>;
 550                                                 #clock-init-cells = <1>;
 551                                         };
 552
 553                                         /* 11:10 reserved */
 554
 555                                         pclk_peri: pclk_peri_div {
 556                                                 compatible = "rockchip,rk3188-div-con";
 557                                                 rockchip,bits = <12 2>;
 558                                                 clocks = <&aclk_peri>;
 559                                                 clock-output-names = "pclk_peri";
 560                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 561                                                 rockchip,div-relations =
 562                                                                 <0x0 1
 563                                                                  0x1 2
 564                                                                  0x2 4
 565                                                                  0x3 8>;
 566                                                 #clock-cells = <0>;
 567                                                 #clock-init-cells = <1>;
 568                                         };
 569                                 };
 570
 571                                 clk_sel_con10: sel-con@0128 {
 572                                         compatible = "rockchip,rk3188-selcon";
 573                                         reg = <0x0128 0x4>;
 574                                         #address-cells = <1>;
 575                                         #size-cells = <1>;
 576
 577                                         pclk_pmu_pre: pclk_pmu_pre_div {
 578                                                 compatible = "rockchip,rk3188-div-con";
 579                                                 rockchip,bits = <0 5>;
 580                                                 clocks = <&clk_gpll>;
 581                                                 clock-output-names = "pclk_pmu_pre";
 582                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 583                                                 #clock-cells = <0>;
 584                                                 #clock-init-cells = <1>;
 585                                         };
 586
 587                                         /* 7:5 reserved */
 588
 589                                         pclk_alive_pre: pclk_alive_pre_div {
 590                                                 compatible = "rockchip,rk3188-div-con";
 591                                                 rockchip,bits = <8 5>;
 592                                                 clocks = <&clk_gpll>;
 593                                                 clock-output-names = "pclk_alive_pre";
 594                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 595                                                 #clock-cells = <0>;
 596                                                 #clock-init-cells = <1>;
 597                                         };
 598
 599                                         /* 13 reserved */
 600
 601                                         clk_crypto: clk_crypto_div {
 602                                                 compatible = "rockchip,rk3188-div-con";
 603                                                 rockchip,bits = <14 2>;
 604                                                 clocks = <&aclk_bus>;
 605                                                 clock-output-names = "clk_crypto";
 606                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 607                                                 #clock-cells = <0>;
 608                                                 #clock-init-cells = <1>;
 609                                         };
 610                                 };
 611
 612                                 /* sel[11]: reserved */
 613
 614                                 clk_sel_con12: sel-con@0130 {
 615                                         compatible = "rockchip,rk3188-selcon";
 616                                         reg = <0x0130 0x4>;
 617                                         #address-cells = <1>;
 618                                         #size-cells = <1>;
 619
 620                                         fclk_mcu_div: fclk_mcu_div {
 621                                                 compatible = "rockchip,rk3188-div-con";
 622                                                 rockchip,bits = <0 5>;
 623                                                 clocks = <&fclk_mcu>;
 624                                                 clock-output-names = "fclk_mcu";
 625                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 626                                                 #clock-cells = <0>;
 627                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 628                                         };
 629
 630                                         /* 6:5 reserved */
 631
 632                                         fclk_mcu: fclk_mcu_mux {
 633                                                 compatible = "rockchip,rk3188-mux-con";
 634                                                 rockchip,bits = <7 1>;
 635                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 636                                                 clock-output-names = "fclk_mcu";
 637                                                 #clock-cells = <0>;
 638                                                 #clock-init-cells = <1>;
 639                                         };
 640
 641                                         stclk_mcu: stclk_mcu_div {
 642                                                 compatible = "rockchip,rk3188-div-con";
 643                                                 rockchip,bits = <8 3>;
 644                                                 clocks = <&fclk_mcu>;
 645                                                 clock-output-names = "stclk_mcu";
 646                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 647                                                 #clock-cells = <0>;
 648                                         };
 649                                 };
 650
 651                                 clk_sel_con13: sel-con@0134 {
 652                                         compatible = "rockchip,rk3188-selcon";
 653                                         reg = <0x0134 0x4>;
 654                                         #address-cells = <1>;
 655                                         #size-cells = <1>;
 656
 657                                         clk_ddr_div: clk_ddr_div {
 658                                                 compatible = "rockchip,rk3188-div-con";
 659                                                 rockchip,bits = <0 2>;
 660                                                 clocks = <&clk_ddr>;
 661                                                 clock-output-names = "clk_ddr";
 662                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 663                                                 #clock-cells = <0>;
 664                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 665                                                                         CLK_SET_RATE_NO_REPARENT)>;
 666                                                 rockchip,clkops-idx =
 667                                                         <CLKOPS_RATE_DDR_DIV4>;
 668                                         };
 669
 670                                         /* 3:2 reserved */
 671
 672                                         clk_ddr: clk_ddr_mux {
 673                                                 compatible = "rockchip,rk3188-mux-con";
 674                                                 rockchip,bits = <4 1>;
 675                                                 clocks = <&clk_dpll>, <&clk_gpll>;
 676                                                 clock-output-names = "clk_ddr";
 677                                                 #clock-cells = <0>;
 678                                         };
 679
 680                                         /* 7:5 reserved */
 681
 682                                         usbphy_480m: usbphy_480m_mux {
 683                                                 compatible = "rockchip,rk3188-mux-con";
 684                                                 rockchip,bits = <8 1>;
 685                                                 clocks = <&xin24m>, <&usbotg_480m_out>;
 686                                                 clock-output-names = "usbphy_480m";
 687                                                 #clock-cells = <0>;
 688                                                 rockchip,clkops-idx =
 689                                                         <CLKOPS_RATE_RK3288_USB480M>;
 690                                                 #clock-init-cells = <1>;
 691                                         };
 692                                 };
 693
 694                                 clk_sel_con14: sel-con@0138 {
 695                                         compatible = "rockchip,rk3188-selcon";
 696                                         reg = <0x0138 0x4>;
 697                                         #address-cells = <1>;
 698                                         #size-cells = <1>;
 699
 700                                         clk_gpu_core_div: clk_gpu_core_div {
 701                                                 compatible = "rockchip,rk3188-div-con";
 702                                                 rockchip,bits = <0 5>;
 703                                                 clocks = <&clk_gpu_core>;
 704                                                 clock-output-names = "clk_gpu";
 705                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 706                                                 #clock-cells = <0>;
 707                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 708                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
 709                                         };
 710
 711                                         /* 5 reserved */
 712
 713                                         clk_gpu_core: clk_gpu_core_mux {
 714                                                 compatible = "rockchip,rk3188-mux-con";
 715                                                 rockchip,bits = <6 2>;
 716                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 717                                                 clock-output-names = "clk_gpu";
 718                                                 #clock-cells = <0>;
 719                                                 #clock-init-cells = <1>;
 720                                         };
 721
 722                                         aclk_gpu_mem: aclk_gpu_mem_div {
 723                                                 compatible = "rockchip,rk3188-div-con";
 724                                                 rockchip,bits = <8 5>;
 725                                                 clocks = <&aclk_gpu>;
 726                                                 clock-output-names = "aclk_gpu_mem";
 727                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 728                                                 #clock-cells = <0>;
 729                                                 #clock-init-cells = <1>;
 730                                         };
 731
 732                                         /* 13 reserved */
 733
 734                                         aclk_gpu: aclk_gpu_mux {
 735                                                 compatible = "rockchip,rk3188-mux-con";
 736                                                 rockchip,bits = <14 1>;
 737                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 738                                                 clock-output-names = "aclk_gpu";
 739                                                 #clock-cells = <0>;
 740                                                 #clock-init-cells = <1>;
 741                                         };
 742                                 };
 743
 744                                 clk_sel_con15: sel-con@013c {
 745                                         compatible = "rockchip,rk3188-selcon";
 746                                         reg = <0x013c 0x4>;
 747                                         #address-cells = <1>;
 748                                         #size-cells = <1>;
 749
 750                                         aclk_vepu_div: aclk_vepu_div {
 751                                                 compatible = "rockchip,rk3188-div-con";
 752                                                 rockchip,bits = <0 5>;
 753                                                 clocks = <&aclk_vepu>;
 754                                                 clock-output-names = "aclk_vepu";
 755                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 756                                                 #clock-cells = <0>;
 757                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 758                                         };
 759
 760                                         /* 5 reserved */
 761
 762                                         aclk_vepu: aclk_vepu_mux {
 763                                                 compatible = "rockchip,rk3188-mux-con";
 764                                                 rockchip,bits = <6 2>;
 765                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 766                                                 clock-output-names = "aclk_vepu";
 767                                                 #clock-cells = <0>;
 768                                                 #clock-init-cells = <1>;
 769                                         };
 770
 771                                         aclk_vdpu_div: aclk_vdpu_div {
 772                                                 compatible = "rockchip,rk3188-div-con";
 773                                                 rockchip,bits = <8 5>;
 774                                                 clocks = <&aclk_vdpu>;
 775                                                 clock-output-names = "aclk_vdpu";
 776                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 777                                                 #clock-cells = <0>;
 778                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 779                                         };
 780
 781                                         /* 13 reserved */
 782
 783                                         aclk_vdpu: aclk_vdpu_mux {
 784                                                 compatible = "rockchip,rk3188-mux-con";
 785                                                 rockchip,bits = <14 2>;
 786                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 787                                                 clock-output-names = "aclk_vdpu";
 788                                                 #clock-cells = <0>;
 789                                                 #clock-init-cells = <1>;
 790                                         };
 791                                 };
 792
 793                                 clk_sel_con16: sel-con@0140 {
 794                                         compatible = "rockchip,rk3188-selcon";
 795                                         reg = <0x0140 0x4>;
 796                                         #address-cells = <1>;
 797                                         #size-cells = <1>;
 798
 799                                         aclk_gpu_cfg: aclk_gpu_cfg_div {
 800                                                 compatible = "rockchip,rk3188-div-con";
 801                                                 rockchip,bits = <8 5>;
 802                                                 clocks = <&aclk_gpu>;
 803                                                 clock-output-names = "aclk_gpu_cfg";
 804                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 805                                                 #clock-cells = <0>;
 806                                                 #clock-init-cells = <1>;
 807                                         };
 808                                 };
 809
 810                                 clk_sel_con17: sel-con@0144 {
 811                                         compatible = "rockchip,rk3188-selcon";
 812                                         reg = <0x0144 0x4>;
 813                                         #address-cells = <1>;
 814                                         #size-cells = <1>;
 815
 816                                         clk_hevc_cabac_div: clk_hevc_cabac_div {
 817                                                 compatible = "rockchip,rk3188-div-con";
 818                                                 rockchip,bits = <0 5>;
 819                                                 clocks = <&clk_hevc_cabac>;
 820                                                 clock-output-names = "clk_hevc_cabac";
 821                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 822                                                 #clock-cells = <0>;
 823                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 824                                         };
 825
 826                                         /* 5 reserved */
 827
 828                                         clk_hevc_cabac: clk_hevc_cabac_mux {
 829                                                 compatible = "rockchip,rk3188-mux-con";
 830                                                 rockchip,bits = <6 2>;
 831                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 832                                                 clock-output-names = "clk_hevc_cabac";
 833                                                 #clock-cells = <0>;
 834                                                 #clock-init-cells = <1>;
 835                                         };
 836
 837                                         clk_hevc_core_div: clk_hevc_core_div {
 838                                                 compatible = "rockchip,rk3188-div-con";
 839                                                 rockchip,bits = <8 5>;
 840                                                 clocks = <&clk_hevc_core>;
 841                                                 clock-output-names = "clk_hevc_core";
 842                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 843                                                 #clock-cells = <0>;
 844                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 845                                         };
 846
 847                                         /* 13 reserved */
 848
 849                                         clk_hevc_core: clk_hevc_core_mux {
 850                                                 compatible = "rockchip,rk3188-mux-con";
 851                                                 rockchip,bits = <14 2>;
 852                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 853                                                 clock-output-names = "clk_hevc_core";
 854                                                 #clock-cells = <0>;
 855                                                 #clock-init-cells = <1>;
 856                                         };
 857                                 };
 858
 859                                 clk_sel_con18: sel-con@0148 {
 860                                         compatible = "rockchip,rk3188-selcon";
 861                                         reg = <0x0148 0x4>;
 862                                         #address-cells = <1>;
 863                                         #size-cells = <1>;
 864
 865                                         clk_rga_div: clk_rga_div {
 866                                                 compatible = "rockchip,rk3188-div-con";
 867                                                 rockchip,bits = <0 5>;
 868                                                 clocks = <&clk_rga>;
 869                                                 clock-output-names = "clk_rga";
 870                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 871                                                 #clock-cells = <0>;
 872                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 873                                         };
 874
 875                                         /* 5 reserved */
 876
 877                                         clk_rga: clk_rga_mux {
 878                                                 compatible = "rockchip,rk3188-mux-con";
 879                                                 rockchip,bits = <6 2>;
 880                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 881                                                 clock-output-names = "clk_rga";
 882                                                 #clock-cells = <0>;
 883                                                 #clock-init-cells = <1>;
 884                                         };
 885
 886                                         aclk_rga_div: aclk_rga_div {
 887                                                 compatible = "rockchip,rk3188-div-con";
 888                                                 rockchip,bits = <8 5>;
 889                                                 clocks = <&aclk_rga_pre>;
 890                                                 clock-output-names = "aclk_rga_pre";
 891                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 892                                                 #clock-cells = <0>;
 893                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 894                                         };
 895
 896                                         /* 13 reserved */
 897
 898                                         aclk_rga_pre: aclk_rga_mux {
 899                                                 compatible = "rockchip,rk3188-mux-con";
 900                                                 rockchip,bits = <14 2>;
 901                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 902                                                 clock-output-names = "aclk_rga_pre";
 903                                                 #clock-cells = <0>;
 904                                                 #clock-init-cells = <1>;
 905                                         };
 906                                 };
 907
 908                                 clk_sel_con19: sel-con@014c {
 909                                         compatible = "rockchip,rk3188-selcon";
 910                                         reg = <0x014c 0x4>;
 911                                         #address-cells = <1>;
 912                                         #size-cells = <1>;
 913
 914                                         aclk_vio0_div: aclk_vio0_div {
 915                                                 compatible = "rockchip,rk3188-div-con";
 916                                                 rockchip,bits = <0 5>;
 917                                                 clocks = <&aclk_vio0>;
 918                                                 clock-output-names = "aclk_vio0";
 919                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 920                                                 #clock-cells = <0>;
 921                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 922                                         };
 923
 924                                         /* 5 reserved */
 925
 926                                         aclk_vio0: aclk_vio0_mux {
 927                                                 compatible = "rockchip,rk3188-mux-con";
 928                                                 rockchip,bits = <6 2>;
 929                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
 930                                                 clock-output-names = "aclk_vio0";
 931                                                 #clock-cells = <0>;
 932                                                 #clock-init-cells = <1>;
 933                                         };
 934                                 };
 935
 936                                 clk_sel_con20: sel-con@0150 {
 937                                         compatible = "rockchip,rk3188-selcon";
 938                                         reg = <0x0150 0x4>;
 939                                         #address-cells = <1>;
 940                                         #size-cells = <1>;
 941
 942                                         dclk_vop0_div: dclk_vop0_div {
 943                                                 compatible = "rockchip,rk3188-div-con";
 944                                                 rockchip,bits = <0 8>;
 945                                                 clocks = <&dclk_vop0>;
 946                                                 clock-output-names = "dclk_vop0";
 947                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 948                                                 #clock-cells = <0>;
 949                                                 rockchip,clkops-idx =
 950                                                         <CLKOPS_RATE_RK3368_DCLK_LCDC>;
 951                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 952
 953                                         };
 954
 955                                         dclk_vop0: dclk_vop0_mux {
 956                                                 compatible = "rockchip,rk3188-mux-con";
 957                                                 rockchip,bits = <8 2>;
 958                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&dummy>;
 959                                                 clock-output-names = "dclk_vop0";
 960                                                 #clock-cells = <0>;
 961                                                 #clock-init-cells = <1>;
 962                                         };
 963
 964                                         /* 15:10 reserved */
 965                                 };
 966
 967                                 clk_sel_con21: sel-con@0154 {
 968                                         compatible = "rockchip,rk3188-selcon";
 969                                         reg = <0x0154 0x4>;
 970                                         #address-cells = <1>;
 971                                         #size-cells = <1>;
 972
 973                                         hclk_vio: hclk_vio_div {
 974                                                 compatible = "rockchip,rk3188-div-con";
 975                                                 rockchip,bits = <0 5>;
 976                                                 clocks = <&aclk_vio0>;
 977                                                 clock-output-names = "hclk_vio";
 978                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 979                                                 #clock-cells = <0>;
 980                                                 #clock-init-cells = <1>;
 981                                         };
 982
 983                                         /* 5 reserved */
 984
 985                                         pclk_isp: pclk_isp_mux {
 986                                                 compatible = "rockchip,rk3188-mux-con";
 987                                                 rockchip,bits = <6 1>;
 988                                                 clocks = <&clk_gates17 2>, <&pclkin_isp_inv>;
 989                                                 clock-output-names = "pclk_isp";
 990                                                 #clock-cells = <0>;
 991                                         };
 992
 993                                         /* 7 reserved */
 994
 995                                         clk_vip_div: clk_vip_div {
 996                                                 compatible = "rockchip,rk3188-div-con";
 997                                                 rockchip,bits = <8 5>;
 998                                                 clocks = <&clk_vip>;
 999                                                 clock-output-names = "clk_vip";
1000                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1001                                                 #clock-cells = <0>;
1002                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1003                                         };
1004
1005                                         pclk_vip: pclk_vip_mux {
1006                                                 compatible = "rockchip,rk3188-mux-con";
1007                                                 rockchip,bits = <13 1>;
1008                                                 clocks = <&clk_gates16 13>, <&pclkin_vip_inv>;
1009                                                 clock-output-names = "pclk_vip";
1010                                                 #clock-cells = <0>;
1011                                         };
1012
1013                                         clk_vip: clk_vip_mux {
1014                                                 compatible = "rockchip,rk3188-mux-con";
1015                                                 rockchip,bits = <14 1>;
1016                                                 clocks = <&clk_vip_pll>, <&xin24m>;
1017                                                 clock-output-names = "clk_vip";
1018                                                 #clock-cells = <0>;
1019                                                 #clock-init-cells = <1>;
1020                                         };
1021
1022                                         clk_vip_pll: clk_vip_pll_mux {
1023                                                 compatible = "rockchip,rk3188-mux-con";
1024                                                 rockchip,bits = <15 1>;
1025                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1026                                                 clock-output-names = "clk_vip_pll";
1027                                                 #clock-cells = <0>;
1028                                                 #clock-init-cells = <1>;
1029                                         };
1030                                 };
1031
1032                                 clk_sel_con22: sel-con@0158 {
1033                                         compatible = "rockchip,rk3188-selcon";
1034                                         reg = <0x0158 0x4>;
1035                                         #address-cells = <1>;
1036                                         #size-cells = <1>;
1037
1038                                         clk_isp_div: clk_isp_div {
1039                                                 compatible = "rockchip,rk3188-div-con";
1040                                                 rockchip,bits = <0 6>;
1041                                                 clocks = <&clk_isp>;
1042                                                 clock-output-names = "clk_isp";
1043                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1044                                                 #clock-cells = <0>;
1045                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1046                                         };
1047
1048                                         clk_isp: clk_isp_mux {
1049                                                 compatible = "rockchip,rk3188-mux-con";
1050                                                 rockchip,bits = <6 2>;
1051                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1052                                                 clock-output-names = "clk_isp";
1053                                                 #clock-cells = <0>;
1054                                                 #clock-init-cells = <1>;
1055                                         };
1056                                 };
1057
1058                                 clk_sel_con23: sel-con@015c {
1059                                         compatible = "rockchip,rk3188-selcon";
1060                                         reg = <0x015c 0x4>;
1061                                         #address-cells = <1>;
1062                                         #size-cells = <1>;
1063
1064                                         clk_edp_div: clk_edp_div {
1065                                                 compatible = "rockchip,rk3188-div-con";
1066                                                 rockchip,bits = <0 6>;
1067                                                 clocks = <&clk_edp>;
1068                                                 clock-output-names = "clk_edp";
1069                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1070                                                 #clock-cells = <0>;
1071                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1072                                         };
1073
1074                                         clk_edp: clk_edp_mux {
1075                                                 compatible = "rockchip,rk3188-mux-con";
1076                                                 rockchip,bits = <6 2>;
1077                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1078                                                 clock-output-names = "clk_edp";
1079                                                 #clock-cells = <0>;
1080                                                 #clock-init-cells = <1>;
1081                                         };
1082
1083                                         clk_edp_24m: clk_edp_24m_mux {
1084                                                 compatible = "rockchip,rk3188-mux-con";
1085                                                 rockchip,bits = <8 1>;
1086                                                 clocks = <&xin24m>, <&dummy>;
1087                                                 clock-output-names = "clk_edp_24m";
1088                                                 #clock-cells = <0>;
1089                                         };
1090                                 };
1091
1092                                 /* sel[24]: reserved */
1093
1094                                 clk_sel_con25: sel-con@0164 {
1095                                         compatible = "rockchip,rk3188-selcon";
1096                                         reg = <0x0164 0x4>;
1097                                         #address-cells = <1>;
1098                                         #size-cells = <1>;
1099
1100                                         clk_tsadc: clk_tsadc_div {
1101                                                 compatible = "rockchip,rk3188-div-con";
1102                                                 rockchip,bits = <0 6>;
1103                                                 clocks = <&clk_32k_mux>;
1104                                                 clock-output-names = "clk_tsadc";
1105                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1106                                                 #clock-cells = <0>;
1107                                         };
1108
1109                                         /* 7:6 reserved */
1110
1111                                         clk_saradc: clk_saradc_div {
1112                                                 compatible = "rockchip,rk3188-div-con";
1113                                                 rockchip,bits = <8 8>;
1114                                                 clocks = <&xin24m>;
1115                                                 clock-output-names = "clk_saradc";
1116                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1117                                                 #clock-cells = <0>;
1118                                         };
1119                                 };
1120
1121                                 clk_sel_con26: sel-con@0168 {
1122                                         compatible = "rockchip,rk3188-selcon";
1123                                         reg = <0x0168 0x4>;
1124                                         #address-cells = <1>;
1125                                         #size-cells = <1>;
1126
1127                                         /* 7:0 reserved */
1128
1129                                         hsic_usb_480m: hsic_usb_480m_mux {
1130                                                 compatible = "rockchip,rk3188-mux-con";
1131                                                 rockchip,bits = <8 1>;
1132                                                 clocks = <&usbotg_480m_out>, <&dummy>;
1133                                                 clock-output-names = "hsic_usb_480m";
1134                                                 #clock-cells = <0>;
1135                                         };
1136
1137                                         /* 11:9 reserved */
1138
1139                                         hsicphy_480m: hsicphy_480m_mux {
1140                                                 compatible = "rockchip,rk3188-mux-con";
1141                                                 rockchip,bits = <12 2>;
1142                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hsic_usb_480m>, <&hsic_usb_480m>;
1143                                                 clock-output-names = "hsicphy_480m";
1144                                                 #clock-cells = <0>;
1145                                         };
1146                                 };
1147
1148                                 clk_sel_con27: sel-con@016c {
1149                                         compatible = "rockchip,rk3188-selcon";
1150                                         reg = <0x016c 0x4>;
1151                                         #address-cells = <1>;
1152                                         #size-cells = <1>;
1153
1154                                         i2s_pll_div: i2s_pll_div {
1155                                                 compatible = "rockchip,rk3188-div-con";
1156                                                 rockchip,bits = <0 7>;
1157                                                 clocks = <&i2s_pll>;
1158                                                 clock-output-names = "i2s_pll";
1159                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1160                                                 #clock-cells = <0>;
1161                                                 rockchip,clkops-idx =
1162                                                         <CLKOPS_RATE_MUX_DIV>;
1163                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1164                                         };
1165
1166                                         /* 7 reserved */
1167
1168                                         clk_i2s: clk_i2s_mux {
1169                                                 compatible = "rockchip,rk3188-mux-con";
1170                                                 rockchip,bits = <8 2>;
1171                                                 clocks = <&i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
1172                                                 clock-output-names = "clk_i2s";
1173                                                 #clock-cells = <0>;
1174                                                 rockchip,clkops-idx =
1175                                                         <CLKOPS_RATE_RK3288_I2S>;
1176                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1177                                         };
1178
1179                                         /* 11:10 reserved */
1180
1181                                         i2s_pll: i2s_pll_mux {
1182                                                 compatible = "rockchip,rk3188-mux-con";
1183                                                 rockchip,bits = <12 1>;
1184                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1185                                                 clock-output-names = "i2s_pll";
1186                                                 #clock-cells = <0>;
1187                                                 #clock-init-cells = <1>;
1188                                         };
1189
1190                                         /* 14:13 reserved */
1191
1192                                         i2s_out: i2s_out_mux {
1193                                                 compatible = "rockchip,rk3188-mux-con";
1194                                                 rockchip,bits = <15 1>;
1195                                                 clocks = <&clk_i2s>, <&xin12m>;
1196                                                 clock-output-names = "i2s_out";
1197                                                 #clock-cells = <0>;
1198                                         };
1199                                 };
1200
1201                                 clk_sel_con28: sel-con@0170 {
1202                                         compatible = "rockchip,rk3188-selcon";
1203                                         reg = <0x0170 0x4>;
1204                                         #address-cells = <1>;
1205                                         #size-cells = <1>;
1206
1207                                         i2s_frac: i2s_frac {
1208                                                 compatible = "rockchip,rk3188-frac-con";
1209                                                 clocks = <&i2s_pll>;
1210                                                 clock-output-names = "i2s_frac";
1211                                                 /* numerator    denominator */
1212                                                 rockchip,bits = <0 32>;
1213                                                 rockchip,clkops-idx =
1214                                                         <CLKOPS_RATE_FRAC>;
1215                                                 #clock-cells = <0>;
1216                                         };
1217                                 };
1218
1219                                 /* sel[30:29] reserved */
1220
1221                                 clk_sel_con31: sel-con@017c {
1222                                         compatible = "rockchip,rk3188-selcon";
1223                                         reg = <0x017c 0x4>;
1224                                         #address-cells = <1>;
1225                                         #size-cells = <1>;
1226
1227
1228                                         spdif_8ch_pll_div: spdif_8ch_pll_div {
1229                                                 compatible = "rockchip,rk3188-div-con";
1230                                                 rockchip,bits = <0 7>;
1231                                                 clocks = <&spdif_8ch_pll>;
1232                                                 clock-output-names = "spdif_8ch_pll";
1233                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1234                                                 #clock-cells = <0>;
1235                                                 rockchip,clkops-idx =
1236                                                         <CLKOPS_RATE_MUX_DIV>;
1237                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1238                                         };
1239
1240                                         /* 7 reserved */
1241
1242                                         clk_spidf_8ch: clk_spidf_8ch_mux {
1243                                                 compatible = "rockchip,rk3188-mux-con";
1244                                                 rockchip,bits = <8 2>;
1245                                                 clocks = <&spdif_8ch_pll>, <&spdif_8ch_frac>, <&i2s_clkin>, <&xin12m>;
1246                                                 clock-output-names = "clk_spidf_8ch";
1247                                                 #clock-cells = <0>;
1248                                                 rockchip,clkops-idx =
1249                                                         <CLKOPS_RATE_RK3288_I2S>;
1250                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1251                                         };
1252
1253                                         /* 11:10 reserved */
1254
1255                                         spdif_8ch_pll: spdif_8ch_pll_mux {
1256                                                 compatible = "rockchip,rk3188-mux-con";
1257                                                 rockchip,bits = <12 1>;
1258                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1259                                                 clock-output-names = "spdif_8ch_pll";
1260                                                 #clock-cells = <0>;
1261                                                 #clock-init-cells = <1>;
1262                                         };
1263
1264                                         /* 15:13 reserved */
1265                                 };
1266
1267                                 clk_sel_con32: sel-con@0180 {
1268                                         compatible = "rockchip,rk3188-selcon";
1269                                         reg = <0x0180 0x4>;
1270                                         #address-cells = <1>;
1271                                         #size-cells = <1>;
1272
1273                                         spdif_8ch_frac: spdif_8ch_frac {
1274                                                 compatible = "rockchip,rk3188-frac-con";
1275                                                 clocks = <&spdif_8ch_pll>;
1276                                                 clock-output-names = "spdif_8ch_frac";
1277                                                 /* numerator    denominator */
1278                                                 rockchip,bits = <0 32>;
1279                                                 rockchip,clkops-idx =
1280                                                         <CLKOPS_RATE_FRAC>;
1281                                                 #clock-cells = <0>;
1282                                         };
1283                                 };
1284
1285                                 clk_sel_con33: sel-con@0184 {
1286                                         compatible = "rockchip,rk3188-selcon";
1287                                         reg = <0x0184 0x4>;
1288                                         #address-cells = <1>;
1289                                         #size-cells = <1>;
1290
1291                                         clk_uart0_pll_div: clk_uart0_pll_div {
1292                                                 compatible = "rockchip,rk3188-div-con";
1293                                                 rockchip,bits = <0 7>;
1294                                                 clocks = <&clk_uart0_pll>;
1295                                                 clock-output-names = "clk_uart0_pll";
1296                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1297                                                 #clock-cells = <0>;
1298                                                 rockchip,clkops-idx =
1299                                                         <CLKOPS_RATE_MUX_DIV>;
1300                                         };
1301
1302                                         /* 7: reserved */
1303
1304                                         clk_uart0: clk_uart0_mux {
1305                                                 compatible = "rockchip,rk3188-mux-con";
1306                                                 rockchip,bits = <8 2>;
1307                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&xin24m>;
1308                                                 clock-output-names = "clk_uart0";
1309                                                 #clock-cells = <0>;
1310                                                 rockchip,clkops-idx =
1311                                                         <CLKOPS_RATE_RK3288_I2S>;
1312                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1313                                         };
1314
1315                                         /* 11:10 reserved */
1316
1317                                         clk_uart0_pll: clk_uart0_pll_mux {
1318                                                 compatible = "rockchip,rk3188-mux-con";
1319                                                 rockchip,bits = <12 2>;
1320                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1321                                                 clock-output-names = "clk_uart0_pll";
1322                                                 #clock-cells = <0>;
1323                                         };
1324                                 };
1325
1326                                 clk_sel_con34: sel-con@0188 {
1327                                         compatible = "rockchip,rk3188-selcon";
1328                                         reg = <0x0188 0x4>;
1329                                         #address-cells = <1>;
1330                                         #size-cells = <1>;
1331
1332                                         uart0_frac: uart0_frac {
1333                                                 compatible = "rockchip,rk3188-frac-con";
1334                                                 clocks = <&clk_uart0_pll>;
1335                                                 clock-output-names = "uart0_frac";
1336                                                 /* numerator    denominator */
1337                                                 rockchip,bits = <0 32>;
1338                                                 rockchip,clkops-idx =
1339                                                         <CLKOPS_RATE_FRAC>;
1340                                                 #clock-cells = <0>;
1341                                         };
1342                                 };
1343
1344                                 clk_sel_con35: sel-con@018c {
1345                                         compatible = "rockchip,rk3188-selcon";
1346                                         reg = <0x018c 0x4>;
1347                                         #address-cells = <1>;
1348                                         #size-cells = <1>;
1349
1350                                         uart1_div: uart1_div {
1351                                                 compatible = "rockchip,rk3188-div-con";
1352                                                 rockchip,bits = <0 7>;
1353                                                 clocks = <&clk_uart_pll>;
1354                                                 clock-output-names = "uart1_div";
1355                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1356                                                 #clock-cells = <0>;
1357                                         };
1358
1359                                         /* 7 reserved */
1360
1361                                         clk_uart1: clk_uart1_mux {
1362                                                 compatible = "rockchip,rk3188-mux-con";
1363                                                 rockchip,bits = <8 2>;
1364                                                 clocks = <&uart1_div>, <&uart1_frac>, <&xin24m>, <&xin24m>;
1365                                                 clock-output-names = "clk_uart1";
1366                                                 #clock-cells = <0>;
1367                                                 rockchip,clkops-idx =
1368                                                         <CLKOPS_RATE_RK3288_I2S>;
1369                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1370                                         };
1371
1372                                         /* 11:10 reserved */
1373
1374                                         clk_uart_pll: clk_uart_pll_mux {
1375                                                 compatible = "rockchip,rk3188-mux-con";
1376                                                 rockchip,bits = <12 1>;
1377                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1378                                                 clock-output-names = "clk_uart_pll";
1379                                                 #clock-cells = <0>;
1380                                                 #clock-init-cells = <1>;
1381                                         };
1382                                 };
1383
1384                                 clk_sel_con36: sel-con@0190 {
1385                                         compatible = "rockchip,rk3188-selcon";
1386                                         reg = <0x0190 0x4>;
1387                                         #address-cells = <1>;
1388                                         #size-cells = <1>;
1389
1390                                         uart1_frac: uart1_frac {
1391                                                 compatible = "rockchip,rk3188-frac-con";
1392                                                 clocks = <&uart1_div>;
1393                                                 clock-output-names = "uart1_frac";
1394                                                 /* numerator    denominator */
1395                                                 rockchip,bits = <0 32>;
1396                                                 rockchip,clkops-idx =
1397                                                         <CLKOPS_RATE_FRAC>;
1398                                                 #clock-cells = <0>;
1399                                         };
1400                                 };
1401
1402                                 clk_sel_con37: sel-con@0194 {
1403                                         compatible = "rockchip,rk3188-selcon";
1404                                         reg = <0x0194 0x4>;
1405                                         #address-cells = <1>;
1406                                         #size-cells = <1>;
1407
1408                                         uart2_div: uart2_div {
1409                                                 compatible = "rockchip,rk3188-div-con";
1410                                                 rockchip,bits = <0 7>;
1411                                                 clocks = <&clk_uart_pll>;
1412                                                 clock-output-names = "uart2_div";
1413                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1414                                                 #clock-cells = <0>;
1415                                         };
1416
1417                                         /* 7 reserved */
1418
1419                                         clk_uart2: clk_uart2_mux {
1420                                                 compatible = "rockchip,rk3188-mux-con";
1421                                                 rockchip,bits = <8 1>;
1422                                                 clocks = <&uart2_div>, <&xin24m>;
1423                                                 clock-output-names = "clk_uart2";
1424                                                 #clock-cells = <0>;
1425                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1426                                         };
1427                                 };
1428
1429                                 /* sel[38] reserved */
1430
1431                                 clk_sel_con39: sel-con@019c {
1432                                         compatible = "rockchip,rk3188-selcon";
1433                                         reg = <0x019c 0x4>;
1434                                         #address-cells = <1>;
1435                                         #size-cells = <1>;
1436
1437                                         uart3_div: uart3_div {
1438                                                 compatible = "rockchip,rk3188-div-con";
1439                                                 rockchip,bits = <0 7>;
1440                                                 clocks = <&clk_uart_pll>;
1441                                                 clock-output-names = "uart3_div";
1442                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1443                                                 #clock-cells = <0>;
1444                                         };
1445
1446                                         /* 7 reserved */
1447
1448                                         clk_uart3: clk_uart3_mux {
1449                                                 compatible = "rockchip,rk3188-mux-con";
1450                                                 rockchip,bits = <8 2>;
1451                                                 clocks = <&uart3_div>, <&uart3_frac>, <&xin24m>, <&xin24m>;
1452                                                 clock-output-names = "clk_uart3";
1453                                                 #clock-cells = <0>;
1454                                                 rockchip,clkops-idx =
1455                                                         <CLKOPS_RATE_RK3288_I2S>;
1456                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1457                                         };
1458                                 };
1459
1460                                 clk_sel_con40: sel-con@01a0 {
1461                                         compatible = "rockchip,rk3188-selcon";
1462                                         reg = <0x01a0 0x4>;
1463                                         #address-cells = <1>;
1464                                         #size-cells = <1>;
1465
1466                                         uart3_frac: uart3_frac {
1467                                                 compatible = "rockchip,rk3188-frac-con";
1468                                                 clocks = <&uart3_div>;
1469                                                 clock-output-names = "uart3_frac";
1470                                                 /* numerator    denominator */
1471                                                 rockchip,bits = <0 32>;
1472                                                 rockchip,clkops-idx =
1473                                                         <CLKOPS_RATE_FRAC>;
1474                                                 #clock-cells = <0>;
1475                                         };
1476                                 };
1477
1478                                 clk_sel_con41: sel-con@01a4 {
1479                                         compatible = "rockchip,rk3188-selcon";
1480                                         reg = <0x01a4 0x4>;
1481                                         #address-cells = <1>;
1482                                         #size-cells = <1>;
1483
1484                                         uart4_div: uart4_div {
1485                                                 compatible = "rockchip,rk3188-div-con";
1486                                                 rockchip,bits = <0 7>;
1487                                                 clocks = <&clk_uart_pll>;
1488                                                 clock-output-names = "uart4_div";
1489                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1490                                                 #clock-cells = <0>;
1491                                         };
1492
1493                                         /* 7 reserved */
1494
1495                                         clk_uart4: clk_uart4_mux {
1496                                                 compatible = "rockchip,rk3188-mux-con";
1497                                                 rockchip,bits = <8 2>;
1498                                                 clocks = <&uart4_div>, <&uart4_frac>, <&xin24m>, <&xin24m>;
1499                                                 clock-output-names = "clk_uart4";
1500                                                 #clock-cells = <0>;
1501                                                 rockchip,clkops-idx =
1502                                                         <CLKOPS_RATE_RK3288_I2S>;
1503                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1504                                         };
1505                                 };
1506
1507                                 clk_sel_con42: sel-con@01a8 {
1508                                         compatible = "rockchip,rk3188-selcon";
1509                                         reg = <0x01a8 0x4>;
1510                                         #address-cells = <1>;
1511                                         #size-cells = <1>;
1512
1513                                         uart4_frac: uart4_frac {
1514                                                 compatible = "rockchip,rk3188-frac-con";
1515                                                 clocks = <&uart4_div>;
1516                                                 clock-output-names = "uart4_frac";
1517                                                 /* numerator    denominator */
1518                                                 rockchip,bits = <0 32>;
1519                                                 rockchip,clkops-idx =
1520                                                         <CLKOPS_RATE_FRAC>;
1521                                                 #clock-cells = <0>;
1522                                         };
1523                                 };
1524
1525                                 clk_sel_con43: sel-con@01ac {
1526                                         compatible = "rockchip,rk3188-selcon";
1527                                         reg = <0x01ac 0x4>;
1528                                         #address-cells = <1>;
1529                                         #size-cells = <1>;
1530
1531                                         clk_mac_pll_div: clk_mac_pll_div {
1532                                                 compatible = "rockchip,rk3188-div-con";
1533                                                 rockchip,bits = <0 5>;
1534                                                 clocks = <&clk_mac_pll>;
1535                                                 clock-output-names = "clk_mac_pll";
1536                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1537                                                 #clock-cells = <0>;
1538                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1539                                         };
1540
1541                                         /* 5 reserved */
1542
1543                                         clk_mac_pll: clk_mac_pll_mux {
1544                                                 compatible = "rockchip,rk3188-mux-con";
1545                                                 rockchip,bits = <6 2>;
1546                                                 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>, <&clk_gpll>;
1547                                                 clock-output-names = "clk_mac_pll";
1548                                                 #clock-cells = <0>;
1549                                         };
1550
1551                                         clk_mac: clk_mac_mux {
1552                                                 compatible = "rockchip,rk3188-mux-con";
1553                                                 rockchip,bits = <8 1>;
1554                                                 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1555                                                 clock-output-names = "clk_mac";
1556                                                 #clock-cells = <0>;
1557                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1558                                                 #clock-init-cells = <1>;
1559                                         };
1560
1561                                         /* 11:9 reserved */
1562
1563                                         /* 12: test_clk: wifi_pll_sel */
1564
1565                                         /* 15:13 reserved */
1566                                 };
1567
1568                                 clk_sel_con44: sel-con@01b0 {
1569                                         compatible = "rockchip,rk3188-selcon";
1570                                         reg = <0x01b0 0x4>;
1571                                         #address-cells = <1>;
1572                                         #size-cells = <1>;
1573
1574                                         /* test_clk: wifi_frac */
1575                                 };
1576
1577                                 clk_sel_con45: sel-con@01b4 {
1578                                         compatible = "rockchip,rk3188-selcon";
1579                                         reg = <0x01b4 0x4>;
1580                                         #address-cells = <1>;
1581                                         #size-cells = <1>;
1582
1583                                         clk_spi0_div: clk_spi0_div {
1584                                                 compatible = "rockchip,rk3188-div-con";
1585                                                 rockchip,bits = <0 7>;
1586                                                 clocks = <&clk_spi0>;
1587                                                 clock-output-names = "clk_spi0";
1588                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1589                                                 #clock-cells = <0>;
1590                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1591                                         };
1592
1593                                         clk_spi0: clk_spi0_mux {
1594                                                 compatible = "rockchip,rk3188-mux-con";
1595                                                 rockchip,bits = <7 1>;
1596                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1597                                                 clock-output-names = "clk_spi0";
1598                                                 #clock-cells = <0>;
1599                                         };
1600
1601                                         clk_spi1_div: clk_spi1_div {
1602                                                 compatible = "rockchip,rk3188-div-con";
1603                                                 rockchip,bits = <8 7>;
1604                                                 clocks = <&clk_spi1>;
1605                                                 clock-output-names = "clk_spi1";
1606                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1607                                                 #clock-cells = <0>;
1608                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1609                                         };
1610
1611                                         clk_spi1: clk_spi1_mux {
1612                                                 compatible = "rockchip,rk3188-mux-con";
1613                                                 rockchip,bits = <15 1>;
1614                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1615                                                 clock-output-names = "clk_spi1";
1616                                                 #clock-cells = <0>;
1617                                         };
1618                                 };
1619
1620                                 clk_sel_con46: sel-con@01b8 {
1621                                         compatible = "rockchip,rk3188-selcon";
1622                                         reg = <0x01b8 0x4>;
1623                                         #address-cells = <1>;
1624                                         #size-cells = <1>;
1625
1626                                         clk_tsp_div: clk_tsp_div {
1627                                                 compatible = "rockchip,rk3188-div-con";
1628                                                 rockchip,bits = <0 5>;
1629                                                 clocks = <&clk_tsp>;
1630                                                 clock-output-names = "clk_tsp";
1631                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1632                                                 #clock-cells = <0>;
1633                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1634                                         };
1635
1636                                         /* 5 reserved */
1637
1638                                         clk_tsp: clk_tsp_mux {
1639                                                 compatible = "rockchip,rk3188-mux-con";
1640                                                 rockchip,bits = <6 2>;
1641                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1642                                                 clock-output-names = "clk_tsp";
1643                                                 #clock-cells = <0>;
1644                                         };
1645
1646                                         clk_spi2_div: clk_spi2_div {
1647                                                 compatible = "rockchip,rk3188-div-con";
1648                                                 rockchip,bits = <8 7>;
1649                                                 clocks = <&clk_spi2>;
1650                                                 clock-output-names = "clk_spi2";
1651                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1652                                                 #clock-cells = <0>;
1653                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1654                                         };
1655
1656                                         clk_spi2: clk_spi2_mux {
1657                                                 compatible = "rockchip,rk3188-mux-con";
1658                                                 rockchip,bits = <15 1>;
1659                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1660                                                 clock-output-names = "clk_spi2";
1661                                                 #clock-cells = <0>;
1662                                         };
1663                                 };
1664
1665                                 clk_sel_con47: sel-con@01bc {
1666                                         compatible = "rockchip,rk3188-selcon";
1667                                         reg = <0x01bc 0x4>;
1668                                         #address-cells = <1>;
1669                                         #size-cells = <1>;
1670
1671                                         clk_nandc0_div: clk_nandc0_div {
1672                                                 compatible = "rockchip,rk3188-div-con";
1673                                                 rockchip,bits = <0 5>;
1674                                                 clocks = <&clk_nandc0>;
1675                                                 clock-output-names = "clk_nandc0";
1676                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1677                                                 #clock-cells = <0>;
1678                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1679                                         };
1680
1681                                         /* 6:5 reserved */
1682
1683                                         clk_nandc0: clk_nandc0_mux {
1684                                                 compatible = "rockchip,rk3188-mux-con";
1685                                                 rockchip,bits = <7 1>;
1686                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1687                                                 clock-output-names = "clk_nandc0";
1688                                                 #clock-cells = <0>;
1689                                         };
1690
1691                                         /* 12:8 test_div */
1692
1693                                         /* 15:13 reserved */
1694                                 };
1695
1696                                 clk_sel_con48: sel-con@01c0 {
1697                                         compatible = "rockchip,rk3188-selcon";
1698                                         reg = <0x01c0 0x4>;
1699                                         #address-cells = <1>;
1700                                         #size-cells = <1>;
1701
1702                                         clk_sdio0_div: clk_sdio0_div {
1703                                                 compatible = "rockchip,rk3188-div-con";
1704                                                 rockchip,bits = <0 7>;
1705                                                 clocks = <&clk_sdio0>;
1706                                                 clock-output-names = "clk_sdio0";
1707                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1708                                                 #clock-cells = <0>;
1709                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1710                                         };
1711
1712                                         /* 7 reserved */
1713
1714                                         clk_sdio0: clk_sdio0_mux {
1715                                                 compatible = "rockchip,rk3188-mux-con";
1716                                                 rockchip,bits = <8 2>;
1717                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1718                                                 clock-output-names = "clk_sdio0";
1719                                                 #clock-cells = <0>;
1720                                         };
1721
1722                                         /* 15:10 reserved */
1723                                 };
1724
1725                                 /* sel[49] reserved */
1726
1727                                 clk_sel_con50: sel-con@01c8 {
1728                                         compatible = "rockchip,rk3188-selcon";
1729                                         reg = <0x01c8 0x4>;
1730                                         #address-cells = <1>;
1731                                         #size-cells = <1>;
1732
1733                                         clk_sdmmc0_div: clk_sdmmc0_div {
1734                                                 compatible = "rockchip,rk3188-div-con";
1735                                                 rockchip,bits = <0 7>;
1736                                                 clocks = <&clk_sdmmc0>;
1737                                                 clock-output-names = "clk_sdmmc0";
1738                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1739                                                 #clock-cells = <0>;
1740                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1741                                         };
1742
1743                                         /* 7 reserved */
1744
1745                                         clk_sdmmc0: clk_sdmmc0_mux {
1746                                                 compatible = "rockchip,rk3188-mux-con";
1747                                                 rockchip,bits = <8 2>;
1748                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1749                                                 clock-output-names = "clk_sdmmc0";
1750                                                 #clock-cells = <0>;
1751                                         };
1752
1753                                         /* 15:10 reserved */
1754                                 };
1755
1756                                 clk_sel_con51: sel-con@01cc {
1757                                         compatible = "rockchip,rk3188-selcon";
1758                                         reg = <0x01cc 0x4>;
1759                                         #address-cells = <1>;
1760                                         #size-cells = <1>;
1761
1762                                         clk_emmc_div: clk_emmc_div {
1763                                                 compatible = "rockchip,rk3188-div-con";
1764                                                 rockchip,bits = <0 7>;
1765                                                 clocks = <&clk_emmc>;
1766                                                 clock-output-names = "clk_emmc";
1767                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1768                                                 #clock-cells = <0>;
1769                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1770                                         };
1771
1772                                         /* 7 reserved */
1773
1774                                         clk_emmc: clk_emmc_mux {
1775                                                 compatible = "rockchip,rk3188-mux-con";
1776                                                 rockchip,bits = <8 2>;
1777                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1778                                                 clock-output-names = "clk_emmc";
1779                                                 #clock-cells = <0>;
1780                                         };
1781
1782                                         /* 15:10 reserved */
1783                                 };
1784
1785                                 clk_sel_con52: sel-con@01d0 {
1786                                         compatible = "rockchip,rk3188-selcon";
1787                                         reg = <0x01d0 0x4>;
1788                                         #address-cells = <1>;
1789                                         #size-cells = <1>;
1790
1791                                         clk_sfc_div: clk_sfc_div {
1792                                                 compatible = "rockchip,rk3188-div-con";
1793                                                 rockchip,bits = <0 5>;
1794                                                 clocks = <&clk_sfc>;
1795                                                 clock-output-names = "clk_sfc";
1796                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1797                                                 #clock-cells = <0>;
1798                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1799                                         };
1800
1801                                         /* 6:5 reserved */
1802
1803                                         clk_sfc: clk_sfc_mux {
1804                                                 compatible = "rockchip,rk3188-mux-con";
1805                                                 rockchip,bits = <7 1>;
1806                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1807                                                 clock-output-names = "clk_sfc";
1808                                                 #clock-cells = <0>;
1809                                         };
1810
1811                                         /* 15:8 reserved */
1812                                 };
1813
1814                                 clk_sel_con53: sel-con@01d4 {
1815                                         compatible = "rockchip,rk3188-selcon";
1816                                         reg = <0x01d4 0x4>;
1817                                         #address-cells = <1>;
1818                                         #size-cells = <1>;
1819
1820                                         i2s_2ch_pll_div: i2s_2ch_pll_div {
1821                                                 compatible = "rockchip,rk3188-div-con";
1822                                                 rockchip,bits = <0 7>;
1823                                                 clocks = <&i2s_2ch_pll>;
1824                                                 clock-output-names = "i2s_2ch_pll";
1825                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1826                                                 #clock-cells = <0>;
1827                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1828                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1829                                         };
1830
1831                                         /* 7 reserved */
1832
1833                                         clk_i2s_2ch: clk_i2s_2ch_mux {
1834                                                 compatible = "rockchip,rk3188-mux-con";
1835                                                 rockchip,bits = <8 2>;
1836                                                 clocks = <&i2s_2ch_pll>, <&i2s_2ch_frac>, <&dummy>, <&xin12m>;
1837                                                 clock-output-names = "clk_i2s_2ch";
1838                                                 #clock-cells = <0>;
1839                                                 rockchip,clkops-idx =
1840                                                         <CLKOPS_RATE_RK3288_I2S>;
1841                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1842                                         };
1843
1844                                         /* 11:10 reserved */
1845
1846                                         i2s_2ch_pll: i2s_2ch_pll_mux {
1847                                                 compatible = "rockchip,rk3188-mux-con";
1848                                                 rockchip,bits = <12 1>;
1849                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1850                                                 clock-output-names = "i2s_2ch_pll";
1851                                                 #clock-cells = <0>;
1852                                                 #clock-init-cells = <1>;
1853                                         };
1854
1855                                 };
1856
1857                                 clk_sel_con54: sel-con@01d8 {
1858                                         compatible = "rockchip,rk3188-selcon";
1859                                         reg = <0x01d8 0x4>;
1860                                         #address-cells = <1>;
1861                                         #size-cells = <1>;
1862
1863                                         i2s_2ch_frac: i2s_2ch_frac {
1864                                                 compatible = "rockchip,rk3188-frac-con";
1865                                                 clocks = <&i2s_2ch_pll>;
1866                                                 clock-output-names = "i2s_2ch_frac";
1867                                                 /* numerator    denominator */
1868                                                 rockchip,bits = <0 32>;
1869                                                 rockchip,clkops-idx =
1870                                                         <CLKOPS_RATE_FRAC>;
1871                                                 #clock-cells = <0>;
1872                                         };
1873                                 };
1874
1875                                 clk_sel_con55: sel-con@01dc {
1876                                         compatible = "rockchip,rk3188-selcon";
1877                                         reg = <0x01dc 0x4>;
1878                                         #address-cells = <1>;
1879                                         #size-cells = <1>;
1880
1881                                         clk_hdcp_div: clk_hdcp_div {
1882                                                 compatible = "rockchip,rk3188-div-con";
1883                                                 rockchip,bits = <0 6>;
1884                                                 clocks = <&clk_hdcp>;
1885                                                 clock-output-names = "clk_hdcp";
1886                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1887                                                 #clock-cells = <0>;
1888                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1889                                         };
1890
1891                                         clk_hdcp: clk_hdcp_mux {
1892                                                 compatible = "rockchip,rk3188-mux-con";
1893                                                 rockchip,bits = <6 2>;
1894                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1895                                                 clock-output-names = "clk_hdcp";
1896                                                 #clock-cells = <0>;
1897                                         };
1898                                 };
1899                         };
1900
1901                         /* Gate control regs */
1902                         clk_gate_cons {
1903                                 compatible = "rockchip,rk-gate-cons";
1904                                 #address-cells = <1>;
1905                                 #size-cells = <1>;
1906                                 ranges;
1907
1908                                 clk_gates0: gate-clk@0200 {
1909                                         compatible = "rockchip,rk3188-gate-clk";
1910                                         reg = <0x0200 0x4>;
1911                                         clocks =
1912                                                 <&dummy>,       <&dummy>,
1913                                                 <&dummy>,       <&dummy>,
1914
1915                                                 <&dummy>,       <&dummy>,
1916                                                 <&dummy>,       <&dummy>,
1917
1918                                                 <&clk_gpll>,    <&clk_apllb>,
1919                                                 <&clk_aplll>,   <&dummy>,
1920
1921                                                 <&aclk_cci>,    <&clkin_trace>,
1922                                                 <&dummy>,       <&dummy>;
1923
1924                                         clock-output-names =
1925                                                 "reserved",     "reserved",/* core_b_apll core_b_gpll */
1926                                                 "reserved",     "reserved",
1927
1928                                                 "reserved",     "reserved",/* core_l_apll core_l_gpll */
1929                                                 "reserved",     "reserved",
1930
1931                                                 "g_clk_cs_gpll",        "g_clk_cs_apllb",
1932                                                 "g_clk_cs_aplll",       "reserved",
1933
1934                                                 "aclk_cci",     "clkin_trace",
1935                                                 "reserved",     "reserved";
1936
1937                                         #clock-cells = <1>;
1938                                 };
1939
1940                                 clk_gates1: gate-clk@0204 {
1941                                         compatible = "rockchip,rk3188-gate-clk";
1942                                         reg = <0x0204 0x4>;
1943                                         clocks =
1944                                                 <&aclk_bus>,    <&hclk_bus>,
1945                                                 <&pclk_bus>,    <&fclk_mcu>,
1946
1947                                                 <&dummy>,       <&dummy>,
1948                                                 <&dummy>,       <&dummy>,
1949
1950                                                 <&dummy>,       <&dummy>,
1951                                                 <&clk_gpll>,    <&clk_cpll>,
1952
1953                                                 <&dummy>,       <&dummy>,
1954                                                 <&dummy>,       <&dummy>;
1955
1956                                         clock-output-names =
1957                                                 "aclk_bus",     "hclk_bus",
1958                                                 "pclk_bus",     "fclk_mcu",
1959
1960                                                 "reserved",     "reserved",
1961                                                 "reserved",     "reserved",
1962
1963                                                 "reserved",     "reserved",/* ddr_dpll  ddr_gpll */
1964                                                 "aclk_bus_gpll",        "aclk_bus_cpll",
1965
1966                                                 "reserved",     "reserved",
1967                                                 "reserved",     "reserved";
1968
1969                                         #clock-cells = <1>;
1970                                 };
1971
1972                                 clk_gates2: gate-clk@0208 {
1973                                         compatible = "rockchip,rk3188-gate-clk";
1974                                         reg = <0x0208 0x4>;
1975                                         clocks =
1976                                                 <&clk_uart0_pll>,       <&uart0_frac>,
1977                                                 <&uart1_div>,   <&uart1_frac>,
1978
1979                                                 <&uart2_div>,   <&dummy>,
1980                                                 <&uart3_div>,   <&uart3_frac>,
1981
1982                                                 <&uart4_div>,   <&uart4_frac>,
1983                                                 <&dummy>,       <&dummy>,
1984
1985                                                 <&dummy>,       <&dummy>,
1986                                                 <&dummy>,       <&dummy>;
1987
1988                                         clock-output-names =
1989                                                 "clk_uart0_pll",        "uart0_frac",
1990                                                 "uart1_div",    "uart1_frac",
1991
1992                                                 "uart2_div",    "reserved",
1993                                                 "uart3_div",    "uart3_frac",
1994
1995                                                 "uart4_div",    "uart4_frac",
1996                                                 "reserved",     "reserved",
1997
1998                                                 "reserved",     "reserved",
1999                                                 "reserved",     "reserved";
2000
2001                                         #clock-cells = <1>;
2002                                 };
2003
2004                                 clk_gates3: gate-clk@020c {
2005                                         compatible = "rockchip,rk3188-gate-clk";
2006                                         reg = <0x020c 0x4>;
2007                                         clocks =
2008                                                 <&aclk_peri>,   <&dummy>,
2009                                                 <&hclk_peri>,   <&pclk_peri>,
2010
2011                                                 <&clk_mac_pll>, <&clk_tsadc>,
2012                                                 <&clk_saradc>,  <&clk_spi0>,
2013
2014                                                 <&clk_spi1>,    <&clk_spi2>,
2015                                                 <&dummy>,       <&dummy>,
2016
2017                                                 <&dummy>,       <&dummy>,
2018                                                 <&dummy>,       <&dummy>;
2019
2020                                         clock-output-names =
2021                                                 "aclk_peri",    "reserved", /* bit1: aclk_peri */
2022                                                 "hclk_peri",    "pclk_peri",
2023
2024                                                 "clk_mac_pll",  "clk_tsadc",
2025                                                 "clk_saradc",   "clk_spi0",
2026
2027                                                 "clk_spi1",     "clk_spi2",
2028                                                 "reserved",     "reserved",
2029
2030                                                 "reserved",     "reserved",
2031                                                 "reserved",     "reserved";
2032
2033                                         #clock-cells = <1>;
2034                                 };
2035
2036                                 clk_gates4: gate-clk@0210 {
2037                                         compatible = "rockchip,rk3188-gate-clk";
2038                                         reg = <0x0210 0x4>;
2039                                         clocks =
2040                                                 <&aclk_vio0>,   <&dclk_vop0>,
2041                                                 <&xin24m>,      <&aclk_rga_pre>,
2042
2043                                                 <&clk_rga>,     <&clk_vip_pll>,
2044                                                 <&aclk_vepu>,   <&aclk_vdpu>,
2045
2046                                                 <&dummy>,       <&clk_isp>,
2047                                                 <&dummy>,       <&clk_gpu_core>,
2048
2049                                                 <&xin32k>,      <&xin24m>,
2050                                                 <&xin24m>,      <&dummy>;
2051
2052                                         clock-output-names =
2053                                                 "aclk_vio0",    "dclk_vop0",
2054                                                 "clk_vop0_pwm", "aclk_rga_pre",
2055
2056                                                 "clk_rga",      "clk_vip_pll",
2057                                                 "aclk_vepu",    "aclk_vdpu",
2058
2059                                                 "reserved",     "clk_isp", /* bit8: hclk_vpu */
2060                                                 "reserved",     "clk_gpu",
2061
2062                                                 "clk_hdmi_cec", "clk_hdmi_hdcp",
2063                                                 "clk_dsiphy_24m",       "reserved";
2064
2065                                         #clock-cells = <1>;
2066                                 };
2067
2068                                 clk_gates5: gate-clk@0214 {
2069                                         compatible = "rockchip,rk3188-gate-clk";
2070                                         reg = <0x0214 0x4>;
2071                                         clocks =
2072                                                 <&dummy>,       <&clk_hevc_cabac>,
2073                                                 <&clk_hevc_core>,       <&clk_edp>,
2074
2075                                                 <&clk_edp_24m>, <&clk_hdcp>,
2076                                                 <&dummy>,       <&dummy>,
2077
2078                                                 <&aclk_gpu_mem>,        <&aclk_gpu_cfg>,
2079                                                 <&dummy>,       <&dummy>,
2080
2081                                                 <&dummy>,       <&i2s_2ch_pll>,
2082                                                 <&i2s_2ch_frac>,        <&clk_i2s_2ch>;
2083
2084                                         clock-output-names =
2085                                                 "reserved",     "clk_hevc_cabac",
2086                                                 "clk_hevc_core",        "clk_edp",
2087
2088                                                 "clk_edp_24m",  "clk_hdcp",
2089                                                 "reserved",     "reserved",
2090
2091                                                 "aclk_gpu_mem", "aclk_gpu_cfg",
2092                                                 "reserved",     "reserved",
2093
2094                                                 "reserved",     "i2s_2ch_pll",
2095                                                 "i2s_2ch_frac", "clk_i2s_2ch";
2096
2097                                         #clock-cells = <1>;
2098                                 };
2099
2100                                 clk_gates6: gate-clk@0218 {
2101                                         compatible = "rockchip,rk3188-gate-clk";
2102                                         reg = <0x0218 0x4>;
2103                                         clocks =
2104                                                 <&i2s_out>,     <&i2s_pll>,
2105                                                 <&i2s_frac>,    <&clk_i2s>,
2106
2107                                                 <&spdif_8ch_pll>,       <&spdif_8ch_frac>,
2108                                                 <&clk_spidf_8ch>,       <&clk_sfc>,
2109
2110                                                 <&dummy>,       <&dummy>,
2111                                                 <&dummy>,       <&dummy>,
2112
2113                                                 <&clk_tsp>,     <&dummy>,
2114                                                 <&dummy>,       <&dummy>;
2115
2116                                         clock-output-names =
2117                                                 "i2s_out",      "i2s_pll",
2118                                                 "i2s_frac",     "clk_i2s",
2119
2120                                                 "spdif_8ch_pll",        "spdif_8ch_frac",
2121                                                 "clk_spidf_8ch",        "clk_sfc",
2122
2123                                                 "reserved",     "reserved",
2124                                                 "reserved",     "reserved",
2125
2126                                                 "clk_tsp",      "reserved",
2127                                                 "reserved",     "reserved";/* clk_ddrphy_gate   clk4x_ddrphy_gate */
2128
2129                                         #clock-cells = <1>;
2130                                 };
2131
2132                                 clk_gates7: gate-clk@021c {
2133                                         compatible = "rockchip,rk3188-gate-clk";
2134                                         reg = <0x021c 0x4>;
2135                                         clocks =
2136                                                 <&jtag_clkin>,  <&dummy>,
2137                                                 <&clk_crypto>,  <&xin24m>,
2138
2139                                                 <&dummy>,       <&dummy>,
2140                                                 <&clk_mac>,     <&clk_mac>,
2141
2142                                                 <&clk_nandc0>,  <&pclk_pmu_pre>,
2143                                                 <&xin24m>,      <&xin24m>,
2144
2145                                                 <&dummy>,       <&dummy>,
2146                                                 <&dummy>,       <&dummy>;
2147
2148                                         clock-output-names =
2149                                                 "clk_jtag",     "reserved",/* bit1: test_clk */
2150                                                 "clk_crypto",   "clk_pvtm_pmu",
2151
2152                                                 "reserved",     "reserved",/* clk_mac_rx  clk_mac_tx */
2153                                                 "clk_mac_ref",  "clk_mac_refout",
2154
2155                                                 "clk_nandc0",   "pclk_pmu_pre",
2156                                                 "clk_pvtm_core",        "clk_pvtm_gpu",
2157
2158                                                 "clk_sdmmc0",   "clk_sdio0",
2159                                                 "reserved",     "clk_emmc";
2160
2161                                         #clock-cells = <1>;
2162                                 };
2163
2164                                 clk_gates8: gate-clk@0220 {
2165                                         compatible = "rockchip,rk3188-gate-clk";
2166                                         reg = <0x0220 0x4>;
2167                                         clocks =
2168                                                 <&hsic_usb_480m>,       <&xin24m>,
2169                                                 <&dummy>,       <&dummy>,
2170
2171                                                 <&clk_32k_mux>, <&dummy>,
2172                                                 <&xin12m>,      <&hsicphy_480m>,
2173
2174                                                 <&dummy>,       <&dummy>,
2175                                                 <&dummy>,       <&dummy>,
2176
2177                                                 <&dummy>,       <&dummy>,
2178                                                 <&dummy>,       <&dummy>;
2179
2180                                         clock-output-names =
2181                                                 "hsic_usb_480m",        "clk_otgphy0",
2182                                                 "reserved",     "reserved",
2183
2184                                                 "g_clk_otg_adp",        "reserved",/* bit4: clk_otg_adp */
2185                                                 "hsicphy_12m",  "hsicphy_480m",
2186
2187                                                 "reserved",     "reserved",
2188                                                 "reserved",     "reserved",
2189
2190                                                 "reserved",     "reserved",
2191                                                 "reserved",     "reserved";
2192
2193                                         #clock-cells = <1>;
2194                                 };
2195
2196                                 clk_gates9: gate-clk@0224 {
2197                                         compatible = "rockchip,rk3188-gate-clk";
2198                                         reg = <0x0224 0x4>;
2199                                         clocks =
2200                                                 <&dummy>,       <&dummy>,
2201                                                 <&dummy>,       <&dummy>,
2202
2203                                                 <&dummy>,       <&dummy>,
2204                                                 <&dummy>,       <&dummy>,
2205
2206                                                 <&dummy>,       <&dummy>,
2207                                                 <&dummy>,       <&dummy>,
2208
2209                                                 <&dummy>,       <&dummy>,
2210                                                 <&dummy>,       <&dummy>;
2211
2212                                         clock-output-names =
2213                                                 "reserved",     "reserved",
2214                                                 "reserved",     "reserved",
2215
2216                                                 "reserved",     "reserved",
2217                                                 "reserved",     "reserved",
2218
2219                                                 "reserved",     "reserved",
2220                                                 "reserved",     "reserved",
2221
2222                                                 "reserved",     "reserved",
2223                                                 "reserved",     "reserved";
2224
2225                                         #clock-cells = <1>;
2226                                 };
2227
2228                                 clk_gates10: gate-clk@0228 {
2229                                         compatible = "rockchip,rk3188-gate-clk";
2230                                         reg = <0x0228 0x4>;
2231                                         clocks =
2232                                                 <&dummy>,       <&dummy>,
2233                                                 <&dummy>,       <&dummy>,
2234
2235                                                 <&dummy>,       <&dummy>,
2236                                                 <&dummy>,       <&dummy>,
2237
2238                                                 <&dummy>,       <&dummy>,
2239                                                 <&dummy>,       <&dummy>,
2240
2241                                                 <&dummy>,       <&dummy>,
2242                                                 <&dummy>,       <&dummy>;
2243
2244                                         clock-output-names =
2245                                                 "reserved",     "reserved",
2246                                                 "reserved",     "reserved",
2247
2248                                                 "reserved",     "reserved",
2249                                                 "reserved",     "reserved",
2250
2251                                                 "reserved",     "reserved",
2252                                                 "reserved",     "reserved",
2253
2254                                                 "reserved",     "reserved",
2255                                                 "reserved",     "reserved";
2256
2257                                         #clock-cells = <1>;
2258                                 };
2259
2260                                 clk_gates11: gate-clk@022c {
2261                                         compatible = "rockchip,rk3188-gate-clk";
2262                                         reg = <0x022c 0x4>;
2263                                         clocks =
2264                                                 <&dummy>,       <&dummy>,
2265                                                 <&dummy>,       <&dummy>,
2266
2267                                                 <&dummy>,       <&dummy>,
2268                                                 <&dummy>,       <&dummy>,
2269
2270                                                 <&dummy>,       <&dummy>,
2271                                                 <&dummy>,       <&dummy>,
2272
2273                                                 <&dummy>,       <&dummy>,
2274                                                 <&dummy>,       <&dummy>;
2275
2276                                         clock-output-names =
2277                                                 "reserved",     "reserved",
2278                                                 "reserved",     "reserved",
2279
2280                                                 "reserved",     "reserved",
2281                                                 "reserved",     "reserved",
2282
2283                                                 "reserved",     "reserved",
2284                                                 "reserved",     "reserved",
2285
2286                                                 "reserved",     "reserved",
2287                                                 "reserved",     "reserved";
2288
2289                                         #clock-cells = <1>;
2290                                 };
2291
2292                                 clk_gates12: gate-clk@0230 {
2293                                         compatible = "rockchip,rk3188-gate-clk";
2294                                         reg = <0x0230 0x4>;
2295                                         clocks =
2296                                                 <&pclk_bus>,    <&pclk_bus>,
2297                                                 <&pclk_bus>,    <&pclk_bus>,
2298
2299                                                 <&aclk_bus>,    <&aclk_bus>,
2300                                                 <&aclk_bus>,    <&hclk_bus>,
2301
2302                                                 <&hclk_bus>,    <&hclk_bus>,
2303                                                 <&hclk_bus>,    <&aclk_bus>,
2304
2305                                                 <&aclk_bus>,    <&dummy>,
2306                                                 <&dummy>,       <&dummy>;
2307
2308                                         clock-output-names =
2309                                                 "g_pclk_pwm0",  "g_p_mailbox",
2310                                                 "g_p_i2cpmu",   "g_p_i2caudio",
2311
2312                                                 "g_aclk_intmem",        "g_clk_intmem0",
2313                                                 "g_clk_intmem1",        "g_h_i2s_8ch",
2314
2315                                                 "g_h_i2s_2ch",  "g_hclk_rom",
2316                                                 "g_hclk_spdif", "g_aclk_dmac",
2317
2318                                                 "g_a_strc_sys", "reserved",/* bit13: pclk_ddrupctl */
2319                                                 "reserved",     "reserved";/* bit14: pclk_ddrphy */
2320
2321                                         #clock-cells = <1>;
2322                                 };
2323
2324                                 clk_gates13: gate-clk@0234 {
2325                                         compatible = "rockchip,rk3188-gate-clk";
2326                                         reg = <0x0234 0x4>;
2327                                         clocks =
2328                                                 <&pclk_bus>,    <&pclk_bus>,
2329                                                 <&dummy>,       <&hclk_bus>,
2330
2331                                                 <&hclk_bus>,    <&pclk_bus>,
2332                                                 <&pclk_bus>,    <&clkin_hsadc_tsp>,
2333
2334                                                 <&pclk_bus>,    <&aclk_bus>,
2335                                                 <&hclk_bus>,    <&dummy>,
2336
2337                                                 <&dummy>,       <&dummy>,
2338                                                 <&dummy>,       <&dummy>;
2339
2340                                         clock-output-names =
2341                                                 "g_p_efuse_1024",       "g_p_efuse_256",
2342                                                 "reserved",     "g_mclk_crypto",/* bit2: nclk_ddrupctl */
2343
2344                                                 "g_sclk_crypto",        "g_p_uartdbg",
2345                                                 "g_pclk_pwm1",  "clk_hsadc_tsp",
2346
2347                                                 "g_pclk_sim",   "g_aclk_gic400",
2348                                                 "g_hclk_tsp",   "reserved",
2349
2350                                                 "reserved",     "reserved",
2351                                                 "reserved",     "reserved";
2352
2353                                         #clock-cells = <1>;
2354                                 };
2355
2356                                 clk_gates14: gate-clk@0238 {
2357                                         compatible = "rockchip,rk3188-gate-clk";
2358                                         reg = <0x0238 0x4>;
2359                                         clocks =
2360                                                 <&dummy>,       <&dummy>,
2361                                                 <&dummy>,       <&dummy>,
2362
2363                                                 <&dummy>,       <&dummy>,
2364                                                 <&dummy>,       <&dummy>,
2365
2366                                                 <&dummy>,       <&dummy>,
2367                                                 <&dummy>,       <&dummy>,
2368
2369                                                 <&dummy>,       <&dummy>,
2370                                                 <&dummy>,       <&dummy>;
2371
2372                                         clock-output-names =
2373                                                 "reserved",     "reserved",
2374                                                 "reserved",     "reserved",
2375
2376                                                 "reserved",     "reserved",
2377                                                 "reserved",     "reserved",
2378
2379                                                 "reserved",     "reserved",
2380                                                 "reserved",     "reserved",
2381
2382                                                 "reserved",     "reserved",
2383                                                 "reserved",     "reserved";
2384
2385                                         #clock-cells = <1>;
2386                                 };
2387
2388                                 clk_gates15: gate-clk@023c {
2389                                         compatible = "rockchip,rk3188-gate-clk";
2390                                         reg = <0x023c 0x4>;
2391                                         clocks =
2392                                                 <&dummy>,       <&dummy>,
2393                                                 <&dummy>,       <&dummy>,
2394
2395                                                 <&dummy>,       <&dummy>,
2396                                                 <&dummy>,       <&dummy>,
2397
2398                                                 <&dummy>,       <&dummy>,
2399                                                 <&dummy>,       <&dummy>,
2400
2401                                                 <&dummy>,       <&dummy>,
2402                                                 <&dummy>,       <&dummy>;
2403
2404                                         clock-output-names =
2405                                                 "reserved",     "reserved",/* aclk_video hclk_video */
2406                                                 "reserved",     "reserved",
2407
2408                                                 "reserved",     "reserved",
2409                                                 "reserved",     "reserved",
2410
2411                                                 "reserved",     "reserved",
2412                                                 "reserved",     "reserved",
2413
2414                                                 "reserved",     "reserved",
2415                                                 "reserved",     "reserved";
2416
2417                                         #clock-cells = <1>;
2418                                 };
2419
2420                                 clk_gates16: gate-clk@0240 {
2421                                         compatible = "rockchip,rk3188-gate-clk";
2422                                         reg = <0x0240 0x4>;
2423                                         clocks =
2424                                                 <&clk_gates16 10>,      <&clk_gates16 8>,
2425                                                 <&clk_gates16 9>,       <&clk_gates16 8>,
2426
2427                                                 <&clk_gates16 9>,       <&clk_gates16 9>,
2428                                                 <&clk_gates16 8>,       <&clk_gates16 8>,
2429
2430                                                 <&hclk_vio>,    <&aclk_vio0>,
2431                                                 <&aclk_rga_pre>,        <&clk_gates16 9>,
2432
2433                                                 <&clk_gates16 8>,       <&pclkin_vip>,
2434                                                 <&clk_isp>,     <&dummy>;
2435
2436                                         clock-output-names =
2437                                                 "g_aclk_rga",   "g_hclk_rga",
2438                                                 "g_aclk_iep",   "g_hclk_iep",
2439
2440                                                 "g_aclk_vop_iep",       "g_aclk_vop",
2441                                                 "g_hclk_vop",   "h_vio_ahb_arbi",
2442
2443                                                 "g_hclk_vio_noc",       "g_aclk_vio0_noc",
2444                                                 "g_aclk_vio1_noc",      "g_aclk_vip",
2445
2446                                                 "g_hclk_vip",   "g_pclkin_vip",
2447                                                 "g_hclk_isp",   "reserved";
2448
2449                                         #clock-cells = <1>;
2450                                 };
2451
2452                                 clk_gates17: gate-clk@0244 {
2453                                         compatible = "rockchip,rk3188-gate-clk";
2454                                         reg = <0x0244 0x4>;
2455                                         clocks =
2456                                                 <&clk_isp>,     <&dummy>,
2457                                                 <&pclkin_isp>,  <&pclk_vio>,
2458
2459                                                 <&pclk_vio>,    <&dummy>,
2460                                                 <&pclk_vio>,    <&clk_gates16 8>,
2461
2462                                                 <&pclk_vio>,    <&pclk_vio>,
2463                                                 <&clk_gates16 10>,      <&pclk_vio>,
2464
2465                                                 <&clk_gates16 8>,       <&dummy>,
2466                                                 <&dummy>,       <&dummy>;
2467
2468                                         clock-output-names =
2469                                                 "g_aclk_isp",   "reserved",
2470                                                 "g_pclkin_isp", "g_p_mipi_dsi0",
2471
2472                                                 "g_p_mipi_csi", "reserved",
2473                                                 "g_p_hdmi_ctrl",        "g_hclk_vio_h2p",
2474
2475                                                 "g_pclk_vio_h2p",       "g_p_edp_ctrl",
2476                                                 "g_aclk_hdcp",  "g_pclk_hdcp",
2477
2478                                                 "g_h_hdcpmmu",  "reserved",
2479                                                 "reserved",     "reserved";
2480
2481                                         #clock-cells = <1>;
2482                                 };
2483
2484                                 clk_gates18: gate-clk@0248 {
2485                                         compatible = "rockchip,rk3188-gate-clk";
2486                                         reg = <0x0248 0x4>;
2487                                         clocks =
2488                                                 <&dummy>,       <&dummy>,
2489                                                 <&dummy>,       <&dummy>,
2490
2491                                                 <&dummy>,       <&dummy>,
2492                                                 <&dummy>,       <&dummy>,
2493
2494                                                 <&dummy>,       <&dummy>,
2495                                                 <&dummy>,       <&dummy>,
2496
2497                                                 <&dummy>,       <&dummy>,
2498                                                 <&dummy>,       <&dummy>;
2499
2500                                         clock-output-names =
2501                                                 "reserved",     "reserved",/* bit0-1: aclk_gpu_cfg aclk_gpu_mem */
2502                                                 "reserved",     "reserved",/* bit2: clk_gpu_core */
2503
2504                                                 "reserved",     "reserved",
2505                                                 "reserved",     "reserved",
2506
2507                                                 "reserved",     "reserved",
2508                                                 "reserved",     "reserved",
2509
2510                                                 "reserved",     "reserved",
2511                                                 "reserved",     "reserved";
2512
2513                                         #clock-cells = <1>;
2514                                 };
2515
2516                                 clk_gates19: gate-clk@024c {
2517                                         compatible = "rockchip,rk3188-gate-clk";
2518                                         reg = <0x024c 0x4>;
2519                                         clocks =
2520                                                 <&hclk_peri>,   <&pclk_peri>,
2521                                                 <&aclk_peri>,   <&aclk_peri>,
2522
2523                                                 <&pclk_peri>,   <&pclk_peri>,
2524                                                 <&pclk_peri>,   <&pclk_peri>,
2525
2526                                                 <&pclk_peri>,   <&pclk_peri>,
2527                                                 <&pclk_peri>,   <&pclk_peri>,
2528
2529                                                 <&pclk_peri>,   <&pclk_peri>,
2530                                                 <&pclk_peri>,   <&pclk_peri>;
2531
2532                                         clock-output-names =
2533                                                 "g_hp_axi_matrix",      "g_pp_axi_matrix",
2534                                                 "g_ap_axi_matrix",      "g_a_dmac_peri",
2535
2536                                                 "g_pclk_spi0",  "g_pclk_spi1",
2537                                                 "g_pclk_spi2",  "g_pclk_uart0",
2538
2539                                                 "g_pclk_uart1", "g_pclk_uart3",
2540                                                 "g_pclk_uart4", "g_pclk_i2c2",
2541
2542                                                 "g_pclk_i2c3",  "g_pclk_i2c4",
2543                                                 "g_pclk_i2c5",  "g_pclk_saradc";
2544
2545                                         #clock-cells = <1>;
2546                                 };
2547
2548                                 clk_gates20: gate-clk@0250 {
2549                                         compatible = "rockchip,rk3188-gate-clk";
2550                                         reg = <0x0250 0x4>;
2551                                         clocks =
2552                                                 <&pclk_peri>,   <&hclk_peri>,
2553                                                 <&hclk_peri>,   <&hclk_peri>,
2554
2555                                                 <&dummy>,       <&hclk_peri>,
2556                                                 <&hclk_peri>,   <&hclk_peri>,
2557
2558                                                 <&aclk_peri>,   <&hclk_peri>,
2559                                                 <&hclk_peri>,   <&hclk_peri>,
2560
2561                                                 <&dummy>,       <&aclk_peri>,
2562                                                 <&pclk_peri>,   <&aclk_peri>;
2563
2564                                         clock-output-names =
2565                                                 "g_pclk_tsadc", "g_hclk_otg0",
2566                                                 "g_h_pmu_otg0", "g_hclk_host0",
2567
2568                                                 "reserved",     "g_hclk_hsic",
2569                                                 "g_h_usb_peri", "g_h_p_ahb_arbi",
2570
2571                                                 "g_a_peri_niu", "g_h_emem_peri",
2572                                                 "g_h_mmc_peri", "g_hclk_nand0",
2573
2574                                                 "reserved",     "g_aclk_gmac",
2575                                                 "g_pclk_gmac",  "g_hclk_sfc";
2576
2577                                         #clock-cells = <1>;
2578                                 };
2579
2580                                 clk_gates21: gate-clk@0254 {
2581                                         compatible = "rockchip,rk3188-gate-clk";
2582                                         reg = <0x0254 0x4>;
2583                                         clocks =
2584                                                 <&hclk_peri>,   <&hclk_peri>,
2585                                                 <&hclk_peri>,   <&hclk_peri>,
2586
2587                                                 <&aclk_peri>,   <&dummy>,
2588                                                 <&dummy>,       <&dummy>,
2589
2590                                                 <&dummy>,       <&dummy>,
2591                                                 <&dummy>,       <&dummy>,
2592
2593                                                 <&dummy>,       <&dummy>,
2594                                                 <&dummy>,       <&dummy>;
2595
2596                                         clock-output-names =
2597                                                 "g_hclk_sdmmc", "g_hclk_sdio0",
2598                                                 "g_hclk_emmc",  "g_hclk_hsadc",
2599
2600                                                 "g_aclk_peri_mmu",      "reserved",
2601                                                 "reserved",     "reserved",
2602
2603                                                 "reserved",     "reserved",
2604                                                 "reserved",     "reserved",
2605
2606                                                 "reserved",     "reserved",
2607                                                 "reserved",     "reserved";
2608
2609                                         #clock-cells = <1>;
2610                                 };
2611
2612                                 clk_gates22: gate-clk@0258 {
2613                                         compatible = "rockchip,rk3188-gate-clk";
2614                                         reg = <0x0258 0x4>;
2615                                         clocks =
2616                                                 <&dummy>,       <&pclk_alive_pre>,
2617                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2618
2619                                                 <&dummy>,       <&dummy>,
2620                                                 <&dummy>,       <&dummy>,
2621
2622                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2623                                                 <&pclk_vio>,    <&pclk_vio>,
2624
2625                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2626                                                 <&dummy>,       <&dummy>;
2627
2628                                         clock-output-names =
2629                                                 "reserved",     "g_pclk_gpio1",
2630                                                 "g_pclk_gpio2", "g_pclk_gpio3",
2631
2632                                                 "reserved",     "reserved",
2633                                                 "reserved",     "reserved",
2634
2635                                                 "g_pclk_grf",   "g_p_alive_niu",
2636                                                 "g_pclk_dphytx0",       "g_pclk_dphyrx",
2637
2638                                                 "g_pclk_timer0",        "g_pclk_timer1",
2639                                                 "reserved",     "reserved";
2640
2641                                         #clock-cells = <1>;
2642                                 };
2643
2644                                 clk_gates23: gate-clk@025c {
2645                                         compatible = "rockchip,rk3188-gate-clk";
2646                                         reg = <0x025c 0x4>;
2647                                         clocks =
2648                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2649                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2650
2651                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2652                                                 <&dummy>,       <&dummy>,
2653
2654                                                 <&dummy>,       <&dummy>,
2655                                                 <&dummy>,       <&dummy>,
2656
2657                                                 <&dummy>,       <&dummy>,
2658                                                 <&dummy>,       <&dummy>;
2659
2660                                         clock-output-names =
2661                                                 "g_pclk_pmu",   "g_pclk_intmem1",
2662                                                 "g_pclk_pmu_noc",       "g_pclk_sgrf",
2663
2664                                                 "g_pclk_gpio0", "g_pclk_pmugrf",
2665                                                 "reserved",     "reserved",
2666
2667                                                 "reserved",     "reserved",
2668                                                 "reserved",     "reserved",
2669
2670                                                 "reserved",     "reserved",
2671                                                 "reserved",     "reserved";
2672
2673                                         #clock-cells = <1>;
2674                                 };
2675
2676                                 clk_gates24: gate-clk@0260 {
2677                                         compatible = "rockchip,rk3188-gate-clk";
2678                                         reg = <0x0260 0x4>;
2679                                         clocks =
2680                                                 <&xin24m>,      <&xin24m>,
2681                                                 <&xin24m>,      <&xin24m>,
2682
2683                                                 <&xin24m>,      <&xin24m>,
2684                                                 <&xin24m>,      <&xin24m>,
2685
2686                                                 <&xin24m>,      <&xin24m>,
2687                                                 <&xin24m>,      <&xin24m>,
2688
2689                                                 <&dummy>,       <&dummy>,
2690                                                 <&dummy>,       <&dummy>;
2691
2692                                         clock-output-names =
2693                                                 "g_clk_timer0", "g_clk_timer1",
2694                                                 "g_clk_timer2", "g_clk_timer3",
2695
2696                                                 "g_clk_timer4", "g_clk_timer5",
2697                                                 "g_clk_timer10",        "g_clk_timer11",
2698
2699                                                 "g_clk_timer12",        "g_clk_timer13",
2700                                                 "g_clk_timer14",        "g_clk_timer15",
2701
2702                                                 "reserved",     "reserved",
2703                                                 "reserved",     "reserved";
2704
2705                                         #clock-cells = <1>;
2706                                 };
2707                         };
2708                 };
2709
2710                 special_regs {
2711                         compatible = "rockchip,rk-clock-special-regs";
2712                         #address-cells = <2>;
2713                         #size-cells = <2>;
2714                         ranges;
2715
2716                         clk_32k_mux: clk_32k_mux {
2717                                 compatible = "rockchip,rk3188-mux-con";
2718                                 reg = <0x0 0xff738100 0x0 0x4>;
2719                                 rockchip,bits = <6 1>;
2720                                 clocks = <&xin32k>, <&clk_gates7 3>;
2721                                 clock-output-names = "clk_32k_mux";
2722                                 #clock-cells = <0>;
2723                                 #clock-init-cells = <1>;
2724                         };
2725                 };
2726         };
2727 };