arch/arm64/boot/dts/rk3368-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014-2015 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3368.h>
  15
  16 /{
  17         clocks {
  18                 compatible = "rockchip,rk-clocks";
  19                 rockchip,grf = <&grf>;
  20                 #address-cells = <2>;
  21                 #size-cells = <2>;
  22                 ranges;
  23
  24                 fixed_rate_cons {
  25                         compatible = "rockchip,rk-fixed-rate-cons";
  26
  27                         xin24m: xin24m {
  28                                 compatible = "rockchip,rk-fixed-clock";
  29                                 clock-output-names = "xin24m";
  30                                 clock-frequency = <24000000>;
  31                                 #clock-cells = <0>;
  32                         };
  33
  34                         xin12m: xin12m {
  35                                 compatible = "rockchip,rk-fixed-clock";
  36                                 clocks = <&xin24m>;
  37                                 clock-output-names = "xin12m";
  38                                 clock-frequency = <12000000>;
  39                                 #clock-cells = <0>;
  40                         };
  41
  42                         xin32k: xin32k {
  43                                 compatible = "rockchip,rk-fixed-clock";
  44                                 clock-output-names = "xin32k";
  45                                 clock-frequency = <32000>;
  46                                 #clock-cells = <0>;
  47                         };
  48
  49                         pvtm_clkout: pvtm_clkout {
  50                                 compatible = "rockchip,rk-fixed-clock";
  51                                 clock-output-names = "pvtm_clkout";
  52                                 clock-frequency = <32000>;
  53                                 #clock-cells = <0>;
  54                         };
  55
  56                         dummy: dummy {
  57                                 compatible = "rockchip,rk-fixed-clock";
  58                                 clock-output-names = "dummy";
  59                                 clock-frequency = <0>;
  60                                 #clock-cells = <0>;
  61                         };
  62
  63                         jtag_clkin: jtag_clkin {
  64                                 compatible = "rockchip,rk-fixed-clock";
  65                                 clock-output-names = "jtag_clkin";
  66                                 clock-frequency = <0>;
  67                                 #clock-cells = <0>;
  68                         };
  69
  70                         gmac_clkin: gmac_clkin {
  71                                 compatible = "rockchip,rk-fixed-clock";
  72                                 clock-output-names = "gmac_clkin";
  73                                 clock-frequency = <0>;
  74                                 #clock-cells = <0>;
  75                         };
  76
  77                         pclkin_isp: pclkin_isp {
  78                                 compatible = "rockchip,rk-fixed-clock";
  79                                 clock-output-names = "pclkin_isp";
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                         };
  83
  84                         pclkin_vip: pclkin_vip {
  85                                 compatible = "rockchip,rk-fixed-clock";
  86                                 clock-output-names = "pclkin_vip";
  87                                 clock-frequency = <0>;
  88                                 #clock-cells = <0>;
  89                         };
  90
  91                         clkin_hsadc_tsp: clkin_hsadc_tsp {
  92                                 compatible = "rockchip,rk-fixed-clock";
  93                                 clock-output-names = "clkin_hsadc_tsp";
  94                                 clock-frequency = <0>;
  95                                 #clock-cells = <0>;
  96                         };
  97
  98                         i2s_clkin: i2s_clkin {
  99                                 compatible = "rockchip,rk-fixed-clock";
 100                                 clock-output-names = "i2s_clkin";
 101                                 clock-frequency = <0>;
 102                                 #clock-cells = <0>;
 103                         };
 104                 };
 105
 106                 fixed_factor_cons {
 107                         compatible = "rockchip,rk-fixed-factor-cons";
 108
 109                         hclk_vepu: hclk_vepu {
 110                                 compatible = "rockchip,rk-fixed-factor-clock";
 111                                 clocks = <&aclk_vepu>;
 112                                 clock-output-names = "hclk_vepu";
 113                                 clock-div = <4>;
 114                                 clock-mult = <1>;
 115                                 #clock-cells = <0>;
 116                         };
 117
 118                         hclk_vdpu: hclk_vdpu {
 119                                 compatible = "rockchip,rk-fixed-factor-clock";
 120                                 clocks = <&aclk_vdpu>;
 121                                 clock-output-names = "hclk_vdpu";
 122                                 clock-div = <4>;
 123                                 clock-mult = <1>;
 124                                 #clock-cells = <0>;
 125                         };
 126
 127                         usbotg_480m_out: usbotg_480m_out {
 128                                 compatible = "rockchip,rk-fixed-factor-clock";
 129                                 clocks = <&clk_gates8 1>;
 130                                 clock-output-names = "usbotg_480m_out";
 131                                 clock-div = <1>;
 132                                 clock-mult = <20>;
 133                                 #clock-cells = <0>;
 134                         };
 135
 136                         pclkin_isp_inv: pclkin_isp_inv {
 137                                 compatible = "rockchip,rk-fixed-factor-clock";
 138                                 clocks = <&clk_gates17 2>;
 139                                 clock-output-names = "pclkin_isp_inv";
 140                                 clock-div = <1>;
 141                                 clock-mult = <1>;
 142                                 #clock-cells = <0>;
 143                         };
 144
 145                         pclkin_vip_inv: pclkin_vip_inv {
 146                                 compatible = "rockchip,rk-fixed-factor-clock";
 147                                 clocks = <&clk_gates16 13>;
 148                                 clock-output-names = "pclkin_vip_inv";
 149                                 clock-div = <1>;
 150                                 clock-mult = <1>;
 151                                 #clock-cells = <0>;
 152                         };
 153
 154                         pclk_vio: pclk_vio {
 155                                 compatible = "rockchip,rk-fixed-factor-clock";
 156                                 clocks = <&clk_gates16 8>;
 157                                 clock-output-names = "pclk_vio";
 158                                 clock-div = <1>;
 159                                 clock-mult = <1>;
 160                                 #clock-cells = <0>;
 161                         };
 162                 };
 163
 164                 pd_cons {
 165                         compatible = "rockchip,rk-pd-cons";
 166
 167                         pd_gpu_0: pd_gpu_0 {
 168                                 compatible = "rockchip,rk-pd-clock";
 169                                 clock-output-names = "pd_gpu_0";
 170                                 rockchip,pd-id = <CLK_PD_GPU_0>;
 171                                 #clock-cells = <0>;
 172                         };
 173
 174                         pd_gpu_1: pd_gpu_1 {
 175                                 compatible = "rockchip,rk-pd-clock";
 176                                 clocks = <&pd_gpu_0>;
 177                                 clock-output-names = "pd_gpu_1";
 178                                 rockchip,pd-id = <CLK_PD_GPU_1>;
 179                                 #clock-cells = <0>;
 180                         };
 181
 182                         pd_video: pd_video {
 183                                 compatible = "rockchip,rk-pd-clock";
 184                                 clock-output-names = "pd_video";
 185                                 rockchip,pd-id = <CLK_PD_VIDEO>;
 186                                 #clock-cells = <0>;
 187                         };
 188
 189                         pd_vio: pd_vio {
 190                                 compatible = "rockchip,rk-pd-clock";
 191                                 clock-output-names = "pd_vio";
 192                                 rockchip,pd-id = <CLK_PD_VIO>;
 193                                 #clock-cells = <0>;
 194                         };
 195
 196                         pd_hevc: pd_hevc {
 197                                 compatible = "rockchip,rk-pd-clock";
 198                                 clocks = <&pd_video>;
 199                                 clock-output-names = "pd_hevc";
 200                                 rockchip,pd-id = <CLK_PD_VIRT>;
 201                                 #clock-cells = <0>;
 202                         };
 203
 204                         pd_vop: pd_vop {
 205                                 compatible = "rockchip,rk-pd-clock";
 206                                 clocks = <&pd_vio>;
 207                                 clock-output-names = "pd_vop";
 208                                 rockchip,pd-id = <CLK_PD_VIRT>;
 209                                 #clock-cells = <0>;
 210                         };
 211
 212                         pd_isp: pd_isp {
 213                                 compatible = "rockchip,rk-pd-clock";
 214                                 clocks = <&pd_vio>;
 215                                 clock-output-names = "pd_isp";
 216                                 rockchip,pd-id = <CLK_PD_VIRT>;
 217                                 #clock-cells = <0>;
 218                         };
 219
 220                         pd_iep: pd_iep {
 221                                 compatible = "rockchip,rk-pd-clock";
 222                                 clocks = <&pd_vio>;
 223                                 clock-output-names = "pd_iep";
 224                                 rockchip,pd-id = <CLK_PD_VIRT>;
 225                                 #clock-cells = <0>;
 226                         };
 227
 228                         pd_rga: pd_rga {
 229                                 compatible = "rockchip,rk-pd-clock";
 230                                 clocks = <&pd_vio>;
 231                                 clock-output-names = "pd_rga";
 232                                 rockchip,pd-id = <CLK_PD_VIRT>;
 233                                 #clock-cells = <0>;
 234                         };
 235
 236                         pd_mipicsi: pd_mipicsi {
 237                                 compatible = "rockchip,rk-pd-clock";
 238                                 clocks = <&pd_vio>;
 239                                 clock-output-names = "pd_mipicsi";
 240                                 rockchip,pd-id = <CLK_PD_VIRT>;
 241                                 #clock-cells = <0>;
 242                         };
 243
 244                         pd_mipidsi: pd_mipidsi {
 245                                 compatible = "rockchip,rk-pd-clock";
 246                                 clocks = <&pd_vio>;
 247                                 clock-output-names = "pd_mipidsi";
 248                                 rockchip,pd-id = <CLK_PD_VIRT>;
 249                                 #clock-cells = <0>;
 250                         };
 251
 252                         pd_lvds: pd_lvds {
 253                                 compatible = "rockchip,rk-pd-clock";
 254                                 clocks = <&pd_vio>;
 255                                 clock-output-names = "pd_lvds";
 256                                 rockchip,pd-id = <CLK_PD_VIRT>;
 257                                 #clock-cells = <0>;
 258                         };
 259
 260                         pd_hdmi: pd_hdmi {
 261                                 compatible = "rockchip,rk-pd-clock";
 262                                 clocks = <&pd_vio>;
 263                                 clock-output-names = "pd_hdmi";
 264                                 rockchip,pd-id = <CLK_PD_VIRT>;
 265                                 #clock-cells = <0>;
 266                         };
 267
 268                         pd_edp: pd_edp {
 269                                 compatible = "rockchip,rk-pd-clock";
 270                                 clocks = <&pd_vio>;
 271                                 clock-output-names = "pd_edp";
 272                                 rockchip,pd-id = <CLK_PD_VIRT>;
 273                                 #clock-cells = <0>;
 274                         };
 275                 };
 276
 277                 clock_regs {
 278                         compatible = "rockchip,rk-clock-regs";
 279                         #address-cells = <1>;
 280                         #size-cells = <1>;
 281                         ranges = <0x0 0x0 0xff760000 0x1000>;
 282                         reg = <0x0 0xff760000 0x0 0x1000>;
 283
 284                         /* PLL control regs */
 285                         pll_cons {
 286                                 compatible = "rockchip,rk-pll-cons";
 287                                 #address-cells = <1>;
 288                                 #size-cells = <1>;
 289                                 ranges;
 290
 291                                 clk_apllb: pll-clk@0000 {
 292                                         compatible = "rockchip,rk3188-pll-clk";
 293                                         reg = <0x0000 0x10>;
 294                                         mode-reg = <0x000c 8>;
 295                                         status-reg = <0x0480 1>;
 296                                         clocks = <&xin24m>;
 297                                         clock-output-names = "clk_apllb";
 298                                         rockchip,pll-type = <CLK_PLL_3368_APLLB>;
 299                                         #clock-cells = <0>;
 300                                 };
 301
 302
 303                                 clk_aplll: pll-clk@0010 {
 304                                         compatible = "rockchip,rk3188-pll-clk";
 305                                         reg = <0x0010 0x10>;
 306                                         mode-reg = <0x001c 8>;
 307                                         status-reg = <0x0480 0>;
 308                                         clocks = <&xin24m>;
 309                                         clock-output-names = "clk_aplll";
 310                                         rockchip,pll-type = <CLK_PLL_3368_APLLL>;
 311                                         #clock-cells = <0>;
 312                                 };
 313
 314                                 clk_dpll: pll-clk@0020 {
 315                                         compatible = "rockchip,rk3188-pll-clk";
 316                                         reg = <0x0020 0x10>;
 317                                         mode-reg = <0x002c 8>;
 318                                         status-reg = <0x0480 2>;
 319                                         clocks = <&xin24m>;
 320                                         clock-output-names = "clk_dpll";
 321                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 322                                         #clock-cells = <0>;
 323                                 };
 324
 325
 326                                 clk_cpll: pll-clk@0030 {
 327                                         compatible = "rockchip,rk3188-pll-clk";
 328                                         reg = <0x0030 0x10>;
 329                                         mode-reg = <0x003c 8>;
 330                                         status-reg = <0x0480 3>;
 331                                         clocks = <&xin24m>;
 332                                         clock-output-names = "clk_cpll";
 333                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 334                                         #clock-cells = <0>;
 335                                         #clock-init-cells = <1>;
 336                                 };
 337
 338                                 clk_gpll: pll-clk@0040 {
 339                                         compatible = "rockchip,rk3188-pll-clk";
 340                                         reg = <0x0040 0x10>;
 341                                         mode-reg = <0x004c 8>;
 342                                         status-reg = <0x0480 4>;
 343                                         clocks = <&xin24m>;
 344                                         clock-output-names = "clk_gpll";
 345                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 346                                         #clock-cells = <0>;
 347                                         #clock-init-cells = <1>;
 348                                 };
 349
 350                                 clk_npll: pll-clk@0050 {
 351                                         compatible = "rockchip,rk3188-pll-clk";
 352                                         reg = <0x0050 0x10>;
 353                                         mode-reg = <0x005c 8>;
 354                                         status-reg = <0x0480 5>;
 355                                         clocks = <&xin24m>;
 356                                         clock-output-names = "clk_npll";
 357                                         rockchip,pll-type = <CLK_PLL_3368_LOW_JITTER>;
 358                                         #clock-cells = <0>;
 359                                         #clock-init-cells = <1>;
 360                                 };
 361                         };
 362
 363                         /* Select control regs */
 364                         clk_sel_cons {
 365                                 compatible = "rockchip,rk-sel-cons";
 366                                 #address-cells = <1>;
 367                                 #size-cells = <1>;
 368                                 ranges;
 369
 370                                 clk_sel_con0: sel-con@0100 {
 371                                         compatible = "rockchip,rk3188-selcon";
 372                                         reg = <0x0100 0x4>;
 373                                         #address-cells = <1>;
 374                                         #size-cells = <1>;
 375
 376                                         clk_core_b_div: clk_core_b_div {
 377                                                 compatible = "rockchip,rk3188-div-con";
 378                                                 rockchip,bits = <0 5>;
 379                                                 clocks = <&clk_core_b>;
 380                                                 clock-output-names = "clk_core_b";
 381                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 382                                                 #clock-cells = <0>;
 383                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 384                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 385                                                                         CLK_SET_RATE_NO_REPARENT)>;
 386                                         };
 387
 388                                         /* 6:5 reserved */
 389
 390                                         clk_core_b: clk_core_b_mux {
 391                                                 compatible = "rockchip,rk3188-mux-con";
 392                                                 rockchip,bits = <7 1>;
 393                                                 clocks = <&clk_apllb>, <&clk_gpll>;
 394                                                 clock-output-names = "clk_core_b";
 395                                                 #clock-cells = <0>;
 396                                                 #clock-init-cells = <1>;
 397                                         };
 398
 399                                         aclkm_core_b: aclkm_core_b_div {
 400                                                 compatible = "rockchip,rk3188-div-con";
 401                                                 rockchip,bits = <8 5>;
 402                                                 clocks = <&clk_core_b>;
 403                                                 clock-output-names = "aclkm_core_b";
 404                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 405                                                 #clock-cells = <0>;
 406                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 407                                         };
 408
 409                                         /* 15:13 reserved */
 410                                 };
 411
 412                                 clk_sel_con1: sel-con@0104 {
 413                                         compatible = "rockchip,rk3188-selcon";
 414                                         reg = <0x0104 0x4>;
 415                                         #address-cells = <1>;
 416                                         #size-cells = <1>;
 417
 418                                         atclk_core_b: atclk_core_b_div {
 419                                                 compatible = "rockchip,rk3188-div-con";
 420                                                 rockchip,bits = <0 5>;
 421                                                 clocks = <&clk_core_b>;
 422                                                 clock-output-names = "atclk_core_b";
 423                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 424                                                 #clock-cells = <0>;
 425                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 426                                         };
 427
 428                                         /* 7:5 reserved */
 429
 430                                         pclk_dbg_b: pclk_dbg_b_div {
 431                                                 compatible = "rockchip,rk3188-div-con";
 432                                                 rockchip,bits = <8 5>;
 433                                                 clocks = <&clk_core_b>;
 434                                                 clock-output-names = "pclk_dbg_b";
 435                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 436                                                 #clock-cells = <0>;
 437                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 438                                         };
 439                                 };
 440
 441                                 clk_sel_con2: sel-con@0108 {
 442                                         compatible = "rockchip,rk3188-selcon";
 443                                         reg = <0x0108 0x4>;
 444                                         #address-cells = <1>;
 445                                         #size-cells = <1>;
 446
 447                                         clk_core_l_div: clk_core_l_div {
 448                                                 compatible = "rockchip,rk3188-div-con";
 449                                                 rockchip,bits = <0 5>;
 450                                                 clocks = <&clk_core_l>;
 451                                                 clock-output-names = "clk_core_l";
 452                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 453                                                 #clock-cells = <0>;
 454                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 455                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 456                                                                         CLK_SET_RATE_NO_REPARENT)>;
 457                                         };
 458
 459                                         /* 6:5 reserved */
 460
 461                                         clk_core_l: clk_core_l_mux {
 462                                                 compatible = "rockchip,rk3188-mux-con";
 463                                                 rockchip,bits = <7 1>;
 464                                                 clocks = <&clk_aplll>, <&clk_gpll>;
 465                                                 clock-output-names = "clk_core_l";
 466                                                 #clock-cells = <0>;
 467                                                 #clock-init-cells = <1>;
 468                                         };
 469
 470                                         aclkm_core_l: aclkm_core_l_div {
 471                                                 compatible = "rockchip,rk3188-div-con";
 472                                                 rockchip,bits = <8 5>;
 473                                                 clocks = <&clk_core_l>;
 474                                                 clock-output-names = "aclkm_core_l";
 475                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 476                                                 #clock-cells = <0>;
 477                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 478                                         };
 479
 480                                         /* 15:13 reserved */
 481                                 };
 482
 483                                 clk_sel_con3: sel-con@010c {
 484                                         compatible = "rockchip,rk3188-selcon";
 485                                         reg = <0x010c 0x4>;
 486                                         #address-cells = <1>;
 487                                         #size-cells = <1>;
 488
 489                                         atclk_core_l: atclk_core_l_div {
 490                                                 compatible = "rockchip,rk3188-div-con";
 491                                                 rockchip,bits = <0 5>;
 492                                                 clocks = <&clk_core_l>;
 493                                                 clock-output-names = "atclk_core_l";
 494                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 495                                                 #clock-cells = <0>;
 496                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 497                                         };
 498
 499                                         /* 7:5 reserved */
 500
 501                                         pclk_dbg_l: pclk_dbg_l_div {
 502                                                 compatible = "rockchip,rk3188-div-con";
 503                                                 rockchip,bits = <8 5>;
 504                                                 clocks = <&clk_core_l>;
 505                                                 clock-output-names = "pclk_dbg_l";
 506                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 507                                                 #clock-cells = <0>;
 508                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 509                                         };
 510                                 };
 511
 512                                 clk_sel_con4: sel-con@0110 {
 513                                         compatible = "rockchip,rk3188-selcon";
 514                                         reg = <0x0110 0x4>;
 515                                         #address-cells = <1>;
 516                                         #size-cells = <1>;
 517
 518                                         clk_cs_div: clk_cs_div {
 519                                                 compatible = "rockchip,rk3188-div-con";
 520                                                 rockchip,bits = <0 5>;
 521                                                 clocks = <&clk_cs>;
 522                                                 clock-output-names = "clk_cs";
 523                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 524                                                 #clock-cells = <0>;
 525                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 526                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 527                                         };
 528
 529                                         /* 5 reserved */
 530
 531                                         clk_cs: clk_cs_mux {
 532                                                 compatible = "rockchip,rk3188-mux-con";
 533                                                 rockchip,bits = <6 2>;
 534                                                 clocks = <&clk_gates0 9>, <&clk_gates0 10>, <&clk_gates0 8>, <&dummy>;
 535                                                 clock-output-names = "clk_cs";
 536                                                 #clock-cells = <0>;
 537                                                 #clock-init-cells = <1>;
 538                                         };
 539
 540                                         clkin_trace: clkin_trace_div {
 541                                                 compatible = "rockchip,rk3188-div-con";
 542                                                 rockchip,bits = <8 5>;
 543                                                 clocks = <&clk_cs>;
 544                                                 clock-output-names = "clkin_trace";
 545                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 546                                                 #clock-cells = <0>;
 547                                                 #clock-init-cells = <1>;
 548                                         };
 549
 550                                 };
 551
 552                                 clk_sel_con5: sel-con@0114 {
 553                                         compatible = "rockchip,rk3188-selcon";
 554                                         reg = <0x0114 0x4>;
 555                                         #address-cells = <1>;
 556                                         #size-cells = <1>;
 557
 558                                         aclk_cci_div: aclk_cci_div {
 559                                                 compatible = "rockchip,rk3188-div-con";
 560                                                 rockchip,bits = <0 5>;
 561                                                 clocks = <&aclk_cci>;
 562                                                 clock-output-names = "aclk_cci";
 563                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 564                                                 #clock-cells = <0>;
 565                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 566                                         };
 567
 568                                         /* 5 reserved */
 569
 570                                         aclk_cci: aclk_cci_mux {
 571                                                 compatible = "rockchip,rk3188-mux-con";
 572                                                 rockchip,bits = <6 2>;
 573                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 574                                                 clock-output-names = "aclk_cci";
 575                                                 #clock-cells = <0>;
 576                                                 #clock-init-cells = <1>;
 577                                         };
 578                                 };
 579
 580                                 /* sel[7:6] reserved */
 581
 582                                 clk_sel_con8: sel-con@0120 {
 583                                         compatible = "rockchip,rk3188-selcon";
 584                                         reg = <0x0120 0x4>;
 585                                         #address-cells = <1>;
 586                                         #size-cells = <1>;
 587
 588                                         aclk_bus_div: aclk_bus_div {
 589                                                 compatible = "rockchip,rk3188-div-con";
 590                                                 rockchip,bits = <0 5>;
 591                                                 clocks = <&aclk_bus>;
 592                                                 clock-output-names = "aclk_bus";
 593                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 594                                                 #clock-cells = <0>;
 595                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 596                                         };
 597
 598                                         /* 6:5 reserved */
 599
 600                                         aclk_bus: aclk_bus_mux {
 601                                                 compatible = "rockchip,rk3188-mux-con";
 602                                                 rockchip,bits = <7 1>;
 603                                                 clocks = <&clk_gates1 11>, <&clk_gates1 10>;
 604                                                 clock-output-names = "aclk_bus";
 605                                                 #clock-cells = <0>;
 606                                                 #clock-init-cells = <1>;
 607                                         };
 608
 609                                         hclk_bus: hclk_bus_div {
 610                                                 compatible = "rockchip,rk3188-div-con";
 611                                                 rockchip,bits = <8 2>;
 612                                                 clocks = <&aclk_bus>;
 613                                                 clock-output-names = "hclk_bus";
 614                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 615                                                 #clock-cells = <0>;
 616                                                 #clock-init-cells = <1>;
 617                                         };
 618
 619                                         /* 11:10 reserved */
 620
 621                                         pclk_bus: pclk_bus_div {
 622                                                 compatible = "rockchip,rk3188-div-con";
 623                                                 rockchip,bits = <12 3>;
 624                                                 clocks = <&aclk_bus>;
 625                                                 clock-output-names = "pclk_bus";
 626                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 627                                                 #clock-cells = <0>;
 628                                                 #clock-init-cells = <1>;
 629                                         };
 630                                 };
 631
 632                                 clk_sel_con9: sel-con@0124 {
 633                                         compatible = "rockchip,rk3188-selcon";
 634                                         reg = <0x0124 0x4>;
 635                                         #address-cells = <1>;
 636                                         #size-cells = <1>;
 637
 638                                         aclk_peri_div: aclk_peri_div {
 639                                                 compatible = "rockchip,rk3188-div-con";
 640                                                 rockchip,bits = <0 5>;
 641                                                 clocks = <&aclk_peri>;
 642                                                 clock-output-names = "aclk_peri";
 643                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 644                                                 #clock-cells = <0>;
 645                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 646                                         };
 647
 648                                         /* 6:5 reserved */
 649
 650                                         aclk_peri: aclk_peri_mux {
 651                                                 compatible = "rockchip,rk3188-mux-con";
 652                                                 rockchip,bits = <7 1>;
 653                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 654                                                 clock-output-names = "aclk_peri";
 655                                                 #clock-cells = <0>;
 656                                                 #clock-init-cells = <1>;
 657                                         };
 658
 659                                         hclk_peri: hclk_peri_div {
 660                                                 compatible = "rockchip,rk3188-div-con";
 661                                                 rockchip,bits = <8 2>;
 662                                                 clocks = <&aclk_peri>;
 663                                                 clock-output-names = "hclk_peri";
 664                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 665                                                 rockchip,div-relations =
 666                                                                 <0x0 1
 667                                                                  0x1 2
 668                                                                  0x2 4>;
 669                                                 #clock-cells = <0>;
 670                                                 #clock-init-cells = <1>;
 671                                         };
 672
 673                                         /* 11:10 reserved */
 674
 675                                         pclk_peri: pclk_peri_div {
 676                                                 compatible = "rockchip,rk3188-div-con";
 677                                                 rockchip,bits = <12 2>;
 678                                                 clocks = <&aclk_peri>;
 679                                                 clock-output-names = "pclk_peri";
 680                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 681                                                 rockchip,div-relations =
 682                                                                 <0x0 1
 683                                                                  0x1 2
 684                                                                  0x2 4
 685                                                                  0x3 8>;
 686                                                 #clock-cells = <0>;
 687                                                 #clock-init-cells = <1>;
 688                                         };
 689                                 };
 690
 691                                 clk_sel_con10: sel-con@0128 {
 692                                         compatible = "rockchip,rk3188-selcon";
 693                                         reg = <0x0128 0x4>;
 694                                         #address-cells = <1>;
 695                                         #size-cells = <1>;
 696
 697                                         pclk_pmu_pre: pclk_pmu_pre_div {
 698                                                 compatible = "rockchip,rk3188-div-con";
 699                                                 rockchip,bits = <0 5>;
 700                                                 clocks = <&clk_gpll>;
 701                                                 clock-output-names = "pclk_pmu_pre";
 702                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 703                                                 #clock-cells = <0>;
 704                                                 #clock-init-cells = <1>;
 705                                         };
 706
 707                                         /* 7:5 reserved */
 708
 709                                         pclk_alive_pre: pclk_alive_pre_div {
 710                                                 compatible = "rockchip,rk3188-div-con";
 711                                                 rockchip,bits = <8 5>;
 712                                                 clocks = <&clk_gpll>;
 713                                                 clock-output-names = "pclk_alive_pre";
 714                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 715                                                 #clock-cells = <0>;
 716                                                 #clock-init-cells = <1>;
 717                                         };
 718
 719                                         /* 13 reserved */
 720
 721                                         clk_crypto: clk_crypto_div {
 722                                                 compatible = "rockchip,rk3188-div-con";
 723                                                 rockchip,bits = <14 2>;
 724                                                 clocks = <&aclk_bus>;
 725                                                 clock-output-names = "clk_crypto";
 726                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 727                                                 #clock-cells = <0>;
 728                                                 #clock-init-cells = <1>;
 729                                         };
 730                                 };
 731
 732                                 /* sel[11]: reserved */
 733
 734                                 clk_sel_con12: sel-con@0130 {
 735                                         compatible = "rockchip,rk3188-selcon";
 736                                         reg = <0x0130 0x4>;
 737                                         #address-cells = <1>;
 738                                         #size-cells = <1>;
 739
 740                                         fclk_mcu_div: fclk_mcu_div {
 741                                                 compatible = "rockchip,rk3188-div-con";
 742                                                 rockchip,bits = <0 5>;
 743                                                 clocks = <&fclk_mcu>;
 744                                                 clock-output-names = "fclk_mcu";
 745                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 746                                                 #clock-cells = <0>;
 747                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 748                                         };
 749
 750                                         /* 6:5 reserved */
 751
 752                                         fclk_mcu: fclk_mcu_mux {
 753                                                 compatible = "rockchip,rk3188-mux-con";
 754                                                 rockchip,bits = <7 1>;
 755                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 756                                                 clock-output-names = "fclk_mcu";
 757                                                 #clock-cells = <0>;
 758                                                 #clock-init-cells = <1>;
 759                                         };
 760
 761                                         stclk_mcu: stclk_mcu_div {
 762                                                 compatible = "rockchip,rk3188-div-con";
 763                                                 rockchip,bits = <8 3>;
 764                                                 clocks = <&fclk_mcu>;
 765                                                 clock-output-names = "stclk_mcu";
 766                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 767                                                 #clock-cells = <0>;
 768                                         };
 769                                 };
 770
 771                                 clk_sel_con13: sel-con@0134 {
 772                                         compatible = "rockchip,rk3188-selcon";
 773                                         reg = <0x0134 0x4>;
 774                                         #address-cells = <1>;
 775                                         #size-cells = <1>;
 776
 777                                         clk_ddr_div: clk_ddr_div {
 778                                                 compatible = "rockchip,rk3188-div-con";
 779                                                 rockchip,bits = <0 2>;
 780                                                 clocks = <&clk_ddr>;
 781                                                 clock-output-names = "clk_ddr";
 782                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 783                                                 #clock-cells = <0>;
 784                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 785                                                                         CLK_SET_RATE_NO_REPARENT)>;
 786                                                 rockchip,clkops-idx =
 787                                                         <CLKOPS_RATE_DDR_DIV4>;
 788                                         };
 789
 790                                         /* 3:2 reserved */
 791
 792                                         clk_ddr: clk_ddr_mux {
 793                                                 compatible = "rockchip,rk3188-mux-con";
 794                                                 rockchip,bits = <4 1>;
 795                                                 clocks = <&clk_dpll>, <&clk_gpll>;
 796                                                 clock-output-names = "clk_ddr";
 797                                                 #clock-cells = <0>;
 798                                         };
 799
 800                                         /* 7:5 reserved */
 801
 802                                         usbphy_480m: usbphy_480m_mux {
 803                                                 compatible = "rockchip,rk3188-mux-con";
 804                                                 rockchip,bits = <8 1>;
 805                                                 clocks = <&xin24m>, <&usbotg_480m_out>;
 806                                                 clock-output-names = "usbphy_480m";
 807                                                 #clock-cells = <0>;
 808                                                 rockchip,clkops-idx =
 809                                                         <CLKOPS_RATE_RK3288_USB480M>;
 810                                                 #clock-init-cells = <1>;
 811                                         };
 812                                 };
 813
 814                                 clk_sel_con14: sel-con@0138 {
 815                                         compatible = "rockchip,rk3188-selcon";
 816                                         reg = <0x0138 0x4>;
 817                                         #address-cells = <1>;
 818                                         #size-cells = <1>;
 819
 820                                         clk_gpu_core_div: clk_gpu_core_div {
 821                                                 compatible = "rockchip,rk3188-div-con";
 822                                                 rockchip,bits = <0 5>;
 823                                                 clocks = <&clk_gpu_core>;
 824                                                 clock-output-names = "clk_gpu";
 825                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 826                                                 #clock-cells = <0>;
 827                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 828                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
 829                                         };
 830
 831                                         /* 5 reserved */
 832
 833                                         clk_gpu_core: clk_gpu_core_mux {
 834                                                 compatible = "rockchip,rk3188-mux-con";
 835                                                 rockchip,bits = <6 2>;
 836                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 837                                                 clock-output-names = "clk_gpu";
 838                                                 #clock-cells = <0>;
 839                                                 #clock-init-cells = <1>;
 840                                         };
 841
 842                                         aclk_gpu_mem: aclk_gpu_mem_div {
 843                                                 compatible = "rockchip,rk3188-div-con";
 844                                                 rockchip,bits = <8 5>;
 845                                                 clocks = <&aclk_gpu>;
 846                                                 clock-output-names = "aclk_gpu_mem";
 847                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 848                                                 #clock-cells = <0>;
 849                                                 #clock-init-cells = <1>;
 850                                         };
 851
 852                                         /* 13 reserved */
 853
 854                                         aclk_gpu: aclk_gpu_mux {
 855                                                 compatible = "rockchip,rk3188-mux-con";
 856                                                 rockchip,bits = <14 1>;
 857                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 858                                                 clock-output-names = "aclk_gpu";
 859                                                 #clock-cells = <0>;
 860                                                 #clock-init-cells = <1>;
 861                                         };
 862                                 };
 863
 864                                 clk_sel_con15: sel-con@013c {
 865                                         compatible = "rockchip,rk3188-selcon";
 866                                         reg = <0x013c 0x4>;
 867                                         #address-cells = <1>;
 868                                         #size-cells = <1>;
 869
 870                                         aclk_vepu_div: aclk_vepu_div {
 871                                                 compatible = "rockchip,rk3188-div-con";
 872                                                 rockchip,bits = <0 5>;
 873                                                 clocks = <&aclk_vepu>;
 874                                                 clock-output-names = "aclk_vepu";
 875                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 876                                                 #clock-cells = <0>;
 877                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 878                                         };
 879
 880                                         /* 5 reserved */
 881
 882                                         aclk_vepu: aclk_vepu_mux {
 883                                                 compatible = "rockchip,rk3188-mux-con";
 884                                                 rockchip,bits = <6 2>;
 885                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 886                                                 clock-output-names = "aclk_vepu";
 887                                                 #clock-cells = <0>;
 888                                                 #clock-init-cells = <1>;
 889                                         };
 890
 891                                         aclk_vdpu_div: aclk_vdpu_div {
 892                                                 compatible = "rockchip,rk3188-div-con";
 893                                                 rockchip,bits = <8 5>;
 894                                                 clocks = <&aclk_vdpu>;
 895                                                 clock-output-names = "aclk_vdpu";
 896                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 897                                                 #clock-cells = <0>;
 898                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 899                                         };
 900
 901                                         /* 13 reserved */
 902
 903                                         aclk_vdpu: aclk_vdpu_mux {
 904                                                 compatible = "rockchip,rk3188-mux-con";
 905                                                 rockchip,bits = <14 2>;
 906                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 907                                                 clock-output-names = "aclk_vdpu";
 908                                                 #clock-cells = <0>;
 909                                                 #clock-init-cells = <1>;
 910                                         };
 911                                 };
 912
 913                                 clk_sel_con16: sel-con@0140 {
 914                                         compatible = "rockchip,rk3188-selcon";
 915                                         reg = <0x0140 0x4>;
 916                                         #address-cells = <1>;
 917                                         #size-cells = <1>;
 918
 919                                         aclk_gpu_cfg: aclk_gpu_cfg_div {
 920                                                 compatible = "rockchip,rk3188-div-con";
 921                                                 rockchip,bits = <8 5>;
 922                                                 clocks = <&aclk_gpu>;
 923                                                 clock-output-names = "aclk_gpu_cfg";
 924                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 925                                                 #clock-cells = <0>;
 926                                                 #clock-init-cells = <1>;
 927                                         };
 928                                 };
 929
 930                                 clk_sel_con17: sel-con@0144 {
 931                                         compatible = "rockchip,rk3188-selcon";
 932                                         reg = <0x0144 0x4>;
 933                                         #address-cells = <1>;
 934                                         #size-cells = <1>;
 935
 936                                         clk_hevc_cabac_div: clk_hevc_cabac_div {
 937                                                 compatible = "rockchip,rk3188-div-con";
 938                                                 rockchip,bits = <0 5>;
 939                                                 clocks = <&clk_hevc_cabac>;
 940                                                 clock-output-names = "clk_hevc_cabac";
 941                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 942                                                 #clock-cells = <0>;
 943                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 944                                         };
 945
 946                                         /* 5 reserved */
 947
 948                                         clk_hevc_cabac: clk_hevc_cabac_mux {
 949                                                 compatible = "rockchip,rk3188-mux-con";
 950                                                 rockchip,bits = <6 2>;
 951                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 952                                                 clock-output-names = "clk_hevc_cabac";
 953                                                 #clock-cells = <0>;
 954                                                 #clock-init-cells = <1>;
 955                                         };
 956
 957                                         clk_hevc_core_div: clk_hevc_core_div {
 958                                                 compatible = "rockchip,rk3188-div-con";
 959                                                 rockchip,bits = <8 5>;
 960                                                 clocks = <&clk_hevc_core>;
 961                                                 clock-output-names = "clk_hevc_core";
 962                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 963                                                 #clock-cells = <0>;
 964                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
 965                                         };
 966
 967                                         /* 13 reserved */
 968
 969                                         clk_hevc_core: clk_hevc_core_mux {
 970                                                 compatible = "rockchip,rk3188-mux-con";
 971                                                 rockchip,bits = <14 2>;
 972                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&usbphy_480m>;
 973                                                 clock-output-names = "clk_hevc_core";
 974                                                 #clock-cells = <0>;
 975                                                 #clock-init-cells = <1>;
 976                                         };
 977                                 };
 978
 979                                 clk_sel_con18: sel-con@0148 {
 980                                         compatible = "rockchip,rk3188-selcon";
 981                                         reg = <0x0148 0x4>;
 982                                         #address-cells = <1>;
 983                                         #size-cells = <1>;
 984
 985                                         clk_rga_div: clk_rga_div {
 986                                                 compatible = "rockchip,rk3188-div-con";
 987                                                 rockchip,bits = <0 5>;
 988                                                 clocks = <&clk_rga>;
 989                                                 clock-output-names = "clk_rga";
 990                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 991                                                 #clock-cells = <0>;
 992                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
 993                                         };
 994
 995                                         /* 5 reserved */
 996
 997                                         clk_rga: clk_rga_mux {
 998                                                 compatible = "rockchip,rk3188-mux-con";
 999                                                 rockchip,bits = <6 2>;
1000                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1001                                                 clock-output-names = "clk_rga";
1002                                                 #clock-cells = <0>;
1003                                                 #clock-init-cells = <1>;
1004                                         };
1005
1006                                         aclk_rga_div: aclk_rga_div {
1007                                                 compatible = "rockchip,rk3188-div-con";
1008                                                 rockchip,bits = <8 5>;
1009                                                 clocks = <&aclk_rga_pre>;
1010                                                 clock-output-names = "aclk_rga_pre";
1011                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1012                                                 #clock-cells = <0>;
1013                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1014                                         };
1015
1016                                         /* 13 reserved */
1017
1018                                         aclk_rga_pre: aclk_rga_mux {
1019                                                 compatible = "rockchip,rk3188-mux-con";
1020                                                 rockchip,bits = <14 2>;
1021                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1022                                                 clock-output-names = "aclk_rga_pre";
1023                                                 #clock-cells = <0>;
1024                                                 #clock-init-cells = <1>;
1025                                         };
1026                                 };
1027
1028                                 clk_sel_con19: sel-con@014c {
1029                                         compatible = "rockchip,rk3188-selcon";
1030                                         reg = <0x014c 0x4>;
1031                                         #address-cells = <1>;
1032                                         #size-cells = <1>;
1033
1034                                         aclk_vio0_div: aclk_vio0_div {
1035                                                 compatible = "rockchip,rk3188-div-con";
1036                                                 rockchip,bits = <0 5>;
1037                                                 clocks = <&aclk_vio0>;
1038                                                 clock-output-names = "aclk_vio0";
1039                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1040                                                 #clock-cells = <0>;
1041                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1042                                         };
1043
1044                                         /* 5 reserved */
1045
1046                                         aclk_vio0: aclk_vio0_mux {
1047                                                 compatible = "rockchip,rk3188-mux-con";
1048                                                 rockchip,bits = <6 2>;
1049                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1050                                                 clock-output-names = "aclk_vio0";
1051                                                 #clock-cells = <0>;
1052                                                 #clock-init-cells = <1>;
1053                                         };
1054                                 };
1055
1056                                 clk_sel_con20: sel-con@0150 {
1057                                         compatible = "rockchip,rk3188-selcon";
1058                                         reg = <0x0150 0x4>;
1059                                         #address-cells = <1>;
1060                                         #size-cells = <1>;
1061
1062                                         dclk_vop0_div: dclk_vop0_div {
1063                                                 compatible = "rockchip,rk3188-div-con";
1064                                                 rockchip,bits = <0 8>;
1065                                                 clocks = <&dclk_vop0>;
1066                                                 clock-output-names = "dclk_vop0";
1067                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1068                                                 #clock-cells = <0>;
1069                                                 rockchip,clkops-idx =
1070                                                         <CLKOPS_RATE_RK3368_DCLK_LCDC>;
1071                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1072
1073                                         };
1074
1075                                         dclk_vop0: dclk_vop0_mux {
1076                                                 compatible = "rockchip,rk3188-mux-con";
1077                                                 rockchip,bits = <8 2>;
1078                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&dummy>;
1079                                                 clock-output-names = "dclk_vop0";
1080                                                 #clock-cells = <0>;
1081                                                 #clock-init-cells = <1>;
1082                                         };
1083
1084                                         /* 15:10 reserved */
1085                                 };
1086
1087                                 clk_sel_con21: sel-con@0154 {
1088                                         compatible = "rockchip,rk3188-selcon";
1089                                         reg = <0x0154 0x4>;
1090                                         #address-cells = <1>;
1091                                         #size-cells = <1>;
1092
1093                                         hclk_vio: hclk_vio_div {
1094                                                 compatible = "rockchip,rk3188-div-con";
1095                                                 rockchip,bits = <0 5>;
1096                                                 clocks = <&aclk_vio0>;
1097                                                 clock-output-names = "hclk_vio";
1098                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1099                                                 #clock-cells = <0>;
1100                                                 #clock-init-cells = <1>;
1101                                         };
1102
1103                                         /* 5 reserved */
1104
1105                                         pclk_isp: pclk_isp_mux {
1106                                                 compatible = "rockchip,rk3188-mux-con";
1107                                                 rockchip,bits = <6 1>;
1108                                                 clocks = <&clk_gates17 2>, <&pclkin_isp_inv>;
1109                                                 clock-output-names = "pclk_isp";
1110                                                 #clock-cells = <0>;
1111                                         };
1112
1113                                         /* 7 reserved */
1114
1115                                         clk_vip_div: clk_vip_div {
1116                                                 compatible = "rockchip,rk3188-div-con";
1117                                                 rockchip,bits = <8 5>;
1118                                                 clocks = <&clk_vip>;
1119                                                 clock-output-names = "clk_vip";
1120                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1121                                                 #clock-cells = <0>;
1122                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1123                                         };
1124
1125                                         pclk_vip: pclk_vip_mux {
1126                                                 compatible = "rockchip,rk3188-mux-con";
1127                                                 rockchip,bits = <13 1>;
1128                                                 clocks = <&clk_gates16 13>, <&pclkin_vip_inv>;
1129                                                 clock-output-names = "pclk_vip";
1130                                                 #clock-cells = <0>;
1131                                         };
1132
1133                                         clk_vip: clk_vip_mux {
1134                                                 compatible = "rockchip,rk3188-mux-con";
1135                                                 rockchip,bits = <14 1>;
1136                                                 clocks = <&clk_vip_pll>, <&xin24m>;
1137                                                 clock-output-names = "clk_vip";
1138                                                 #clock-cells = <0>;
1139                                                 #clock-init-cells = <1>;
1140                                         };
1141
1142                                         clk_vip_pll: clk_vip_pll_mux {
1143                                                 compatible = "rockchip,rk3188-mux-con";
1144                                                 rockchip,bits = <15 1>;
1145                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1146                                                 clock-output-names = "clk_vip_pll";
1147                                                 #clock-cells = <0>;
1148                                                 #clock-init-cells = <1>;
1149                                         };
1150                                 };
1151
1152                                 clk_sel_con22: sel-con@0158 {
1153                                         compatible = "rockchip,rk3188-selcon";
1154                                         reg = <0x0158 0x4>;
1155                                         #address-cells = <1>;
1156                                         #size-cells = <1>;
1157
1158                                         clk_isp_div: clk_isp_div {
1159                                                 compatible = "rockchip,rk3188-div-con";
1160                                                 rockchip,bits = <0 6>;
1161                                                 clocks = <&clk_isp>;
1162                                                 clock-output-names = "clk_isp";
1163                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1164                                                 #clock-cells = <0>;
1165                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1166                                         };
1167
1168                                         clk_isp: clk_isp_mux {
1169                                                 compatible = "rockchip,rk3188-mux-con";
1170                                                 rockchip,bits = <6 2>;
1171                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1172                                                 clock-output-names = "clk_isp";
1173                                                 #clock-cells = <0>;
1174                                                 #clock-init-cells = <1>;
1175                                         };
1176                                 };
1177
1178                                 clk_sel_con23: sel-con@015c {
1179                                         compatible = "rockchip,rk3188-selcon";
1180                                         reg = <0x015c 0x4>;
1181                                         #address-cells = <1>;
1182                                         #size-cells = <1>;
1183
1184                                         clk_edp_div: clk_edp_div {
1185                                                 compatible = "rockchip,rk3188-div-con";
1186                                                 rockchip,bits = <0 6>;
1187                                                 clocks = <&clk_edp>;
1188                                                 clock-output-names = "clk_edp";
1189                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1190                                                 #clock-cells = <0>;
1191                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1192                                         };
1193
1194                                         clk_edp: clk_edp_mux {
1195                                                 compatible = "rockchip,rk3188-mux-con";
1196                                                 rockchip,bits = <6 2>;
1197                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1198                                                 clock-output-names = "clk_edp";
1199                                                 #clock-cells = <0>;
1200                                                 #clock-init-cells = <1>;
1201                                         };
1202
1203                                         clk_edp_24m: clk_edp_24m_mux {
1204                                                 compatible = "rockchip,rk3188-mux-con";
1205                                                 rockchip,bits = <8 1>;
1206                                                 clocks = <&xin24m>, <&dummy>;
1207                                                 clock-output-names = "clk_edp_24m";
1208                                                 #clock-cells = <0>;
1209                                         };
1210                                 };
1211
1212                                 /* sel[24]: reserved */
1213
1214                                 clk_sel_con25: sel-con@0164 {
1215                                         compatible = "rockchip,rk3188-selcon";
1216                                         reg = <0x0164 0x4>;
1217                                         #address-cells = <1>;
1218                                         #size-cells = <1>;
1219
1220                                         clk_tsadc: clk_tsadc_div {
1221                                                 compatible = "rockchip,rk3188-div-con";
1222                                                 rockchip,bits = <0 6>;
1223                                                 clocks = <&clk_32k_mux>;
1224                                                 clock-output-names = "clk_tsadc";
1225                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1226                                                 #clock-cells = <0>;
1227                                         };
1228
1229                                         /* 7:6 reserved */
1230
1231                                         clk_saradc: clk_saradc_div {
1232                                                 compatible = "rockchip,rk3188-div-con";
1233                                                 rockchip,bits = <8 8>;
1234                                                 clocks = <&xin24m>;
1235                                                 clock-output-names = "clk_saradc";
1236                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1237                                                 #clock-cells = <0>;
1238                                         };
1239                                 };
1240
1241                                 clk_sel_con26: sel-con@0168 {
1242                                         compatible = "rockchip,rk3188-selcon";
1243                                         reg = <0x0168 0x4>;
1244                                         #address-cells = <1>;
1245                                         #size-cells = <1>;
1246
1247                                         /* 7:0 reserved */
1248
1249                                         hsic_usb_480m: hsic_usb_480m_mux {
1250                                                 compatible = "rockchip,rk3188-mux-con";
1251                                                 rockchip,bits = <8 1>;
1252                                                 clocks = <&usbotg_480m_out>, <&dummy>;
1253                                                 clock-output-names = "hsic_usb_480m";
1254                                                 #clock-cells = <0>;
1255                                         };
1256
1257                                         /* 11:9 reserved */
1258
1259                                         hsicphy_480m: hsicphy_480m_mux {
1260                                                 compatible = "rockchip,rk3188-mux-con";
1261                                                 rockchip,bits = <12 2>;
1262                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&hsic_usb_480m>, <&hsic_usb_480m>;
1263                                                 clock-output-names = "hsicphy_480m";
1264                                                 #clock-cells = <0>;
1265                                         };
1266                                 };
1267
1268                                 clk_sel_con27: sel-con@016c {
1269                                         compatible = "rockchip,rk3188-selcon";
1270                                         reg = <0x016c 0x4>;
1271                                         #address-cells = <1>;
1272                                         #size-cells = <1>;
1273
1274                                         i2s_pll_div: i2s_pll_div {
1275                                                 compatible = "rockchip,rk3188-div-con";
1276                                                 rockchip,bits = <0 7>;
1277                                                 clocks = <&i2s_pll>;
1278                                                 clock-output-names = "i2s_pll";
1279                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1280                                                 #clock-cells = <0>;
1281                                                 rockchip,clkops-idx =
1282                                                         <CLKOPS_RATE_MUX_DIV>;
1283                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1284                                         };
1285
1286                                         /* 7 reserved */
1287
1288                                         clk_i2s: clk_i2s_mux {
1289                                                 compatible = "rockchip,rk3188-mux-con";
1290                                                 rockchip,bits = <8 2>;
1291                                                 clocks = <&i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
1292                                                 clock-output-names = "clk_i2s";
1293                                                 #clock-cells = <0>;
1294                                                 rockchip,clkops-idx =
1295                                                         <CLKOPS_RATE_RK3288_I2S>;
1296                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1297                                         };
1298
1299                                         /* 11:10 reserved */
1300
1301                                         i2s_pll: i2s_pll_mux {
1302                                                 compatible = "rockchip,rk3188-mux-con";
1303                                                 rockchip,bits = <12 1>;
1304                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1305                                                 clock-output-names = "i2s_pll";
1306                                                 #clock-cells = <0>;
1307                                                 #clock-init-cells = <1>;
1308                                         };
1309
1310                                         /* 14:13 reserved */
1311
1312                                         i2s_out: i2s_out_mux {
1313                                                 compatible = "rockchip,rk3188-mux-con";
1314                                                 rockchip,bits = <15 1>;
1315                                                 clocks = <&clk_i2s>, <&xin12m>;
1316                                                 clock-output-names = "i2s_out";
1317                                                 #clock-cells = <0>;
1318                                         };
1319                                 };
1320
1321                                 clk_sel_con28: sel-con@0170 {
1322                                         compatible = "rockchip,rk3188-selcon";
1323                                         reg = <0x0170 0x4>;
1324                                         #address-cells = <1>;
1325                                         #size-cells = <1>;
1326
1327                                         i2s_frac: i2s_frac {
1328                                                 compatible = "rockchip,rk3188-frac-con";
1329                                                 clocks = <&i2s_pll>;
1330                                                 clock-output-names = "i2s_frac";
1331                                                 /* numerator    denominator */
1332                                                 rockchip,bits = <0 32>;
1333                                                 rockchip,clkops-idx =
1334                                                         <CLKOPS_RATE_FRAC>;
1335                                                 #clock-cells = <0>;
1336                                         };
1337                                 };
1338
1339                                 /* sel[30:29] reserved */
1340
1341                                 clk_sel_con31: sel-con@017c {
1342                                         compatible = "rockchip,rk3188-selcon";
1343                                         reg = <0x017c 0x4>;
1344                                         #address-cells = <1>;
1345                                         #size-cells = <1>;
1346
1347
1348                                         spdif_8ch_pll_div: spdif_8ch_pll_div {
1349                                                 compatible = "rockchip,rk3188-div-con";
1350                                                 rockchip,bits = <0 7>;
1351                                                 clocks = <&spdif_8ch_pll>;
1352                                                 clock-output-names = "spdif_8ch_pll";
1353                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1354                                                 #clock-cells = <0>;
1355                                                 rockchip,clkops-idx =
1356                                                         <CLKOPS_RATE_MUX_DIV>;
1357                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1358                                         };
1359
1360                                         /* 7 reserved */
1361
1362                                         clk_spidf_8ch: clk_spidf_8ch_mux {
1363                                                 compatible = "rockchip,rk3188-mux-con";
1364                                                 rockchip,bits = <8 2>;
1365                                                 clocks = <&spdif_8ch_pll>, <&spdif_8ch_frac>, <&i2s_clkin>, <&xin12m>;
1366                                                 clock-output-names = "clk_spidf_8ch";
1367                                                 #clock-cells = <0>;
1368                                                 rockchip,clkops-idx =
1369                                                         <CLKOPS_RATE_RK3288_I2S>;
1370                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1371                                         };
1372
1373                                         /* 11:10 reserved */
1374
1375                                         spdif_8ch_pll: spdif_8ch_pll_mux {
1376                                                 compatible = "rockchip,rk3188-mux-con";
1377                                                 rockchip,bits = <12 1>;
1378                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1379                                                 clock-output-names = "spdif_8ch_pll";
1380                                                 #clock-cells = <0>;
1381                                                 #clock-init-cells = <1>;
1382                                         };
1383
1384                                         /* 15:13 reserved */
1385                                 };
1386
1387                                 clk_sel_con32: sel-con@0180 {
1388                                         compatible = "rockchip,rk3188-selcon";
1389                                         reg = <0x0180 0x4>;
1390                                         #address-cells = <1>;
1391                                         #size-cells = <1>;
1392
1393                                         spdif_8ch_frac: spdif_8ch_frac {
1394                                                 compatible = "rockchip,rk3188-frac-con";
1395                                                 clocks = <&spdif_8ch_pll>;
1396                                                 clock-output-names = "spdif_8ch_frac";
1397                                                 /* numerator    denominator */
1398                                                 rockchip,bits = <0 32>;
1399                                                 rockchip,clkops-idx =
1400                                                         <CLKOPS_RATE_FRAC>;
1401                                                 #clock-cells = <0>;
1402                                         };
1403                                 };
1404
1405                                 clk_sel_con33: sel-con@0184 {
1406                                         compatible = "rockchip,rk3188-selcon";
1407                                         reg = <0x0184 0x4>;
1408                                         #address-cells = <1>;
1409                                         #size-cells = <1>;
1410
1411                                         clk_uart0_pll_div: clk_uart0_pll_div {
1412                                                 compatible = "rockchip,rk3188-div-con";
1413                                                 rockchip,bits = <0 7>;
1414                                                 clocks = <&clk_uart0_pll>;
1415                                                 clock-output-names = "clk_uart0_pll";
1416                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1417                                                 #clock-cells = <0>;
1418                                                 rockchip,clkops-idx =
1419                                                         <CLKOPS_RATE_MUX_DIV>;
1420                                         };
1421
1422                                         /* 7: reserved */
1423
1424                                         clk_uart0: clk_uart0_mux {
1425                                                 compatible = "rockchip,rk3188-mux-con";
1426                                                 rockchip,bits = <8 2>;
1427                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&xin24m>;
1428                                                 clock-output-names = "clk_uart0";
1429                                                 #clock-cells = <0>;
1430                                                 rockchip,clkops-idx =
1431                                                         <CLKOPS_RATE_RK3288_I2S>;
1432                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1433                                         };
1434
1435                                         /* 11:10 reserved */
1436
1437                                         clk_uart0_pll: clk_uart0_pll_mux {
1438                                                 compatible = "rockchip,rk3188-mux-con";
1439                                                 rockchip,bits = <12 2>;
1440                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&usbphy_480m>;
1441                                                 clock-output-names = "clk_uart0_pll";
1442                                                 #clock-cells = <0>;
1443                                         };
1444                                 };
1445
1446                                 clk_sel_con34: sel-con@0188 {
1447                                         compatible = "rockchip,rk3188-selcon";
1448                                         reg = <0x0188 0x4>;
1449                                         #address-cells = <1>;
1450                                         #size-cells = <1>;
1451
1452                                         uart0_frac: uart0_frac {
1453                                                 compatible = "rockchip,rk3188-frac-con";
1454                                                 clocks = <&clk_uart0_pll>;
1455                                                 clock-output-names = "uart0_frac";
1456                                                 /* numerator    denominator */
1457                                                 rockchip,bits = <0 32>;
1458                                                 rockchip,clkops-idx =
1459                                                         <CLKOPS_RATE_FRAC>;
1460                                                 #clock-cells = <0>;
1461                                         };
1462                                 };
1463
1464                                 clk_sel_con35: sel-con@018c {
1465                                         compatible = "rockchip,rk3188-selcon";
1466                                         reg = <0x018c 0x4>;
1467                                         #address-cells = <1>;
1468                                         #size-cells = <1>;
1469
1470                                         uart1_div: uart1_div {
1471                                                 compatible = "rockchip,rk3188-div-con";
1472                                                 rockchip,bits = <0 7>;
1473                                                 clocks = <&clk_uart_pll>;
1474                                                 clock-output-names = "uart1_div";
1475                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1476                                                 #clock-cells = <0>;
1477                                         };
1478
1479                                         /* 7 reserved */
1480
1481                                         clk_uart1: clk_uart1_mux {
1482                                                 compatible = "rockchip,rk3188-mux-con";
1483                                                 rockchip,bits = <8 2>;
1484                                                 clocks = <&uart1_div>, <&uart1_frac>, <&xin24m>, <&xin24m>;
1485                                                 clock-output-names = "clk_uart1";
1486                                                 #clock-cells = <0>;
1487                                                 rockchip,clkops-idx =
1488                                                         <CLKOPS_RATE_RK3288_I2S>;
1489                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1490                                         };
1491
1492                                         /* 11:10 reserved */
1493
1494                                         clk_uart_pll: clk_uart_pll_mux {
1495                                                 compatible = "rockchip,rk3188-mux-con";
1496                                                 rockchip,bits = <12 1>;
1497                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1498                                                 clock-output-names = "clk_uart_pll";
1499                                                 #clock-cells = <0>;
1500                                                 #clock-init-cells = <1>;
1501                                         };
1502                                 };
1503
1504                                 clk_sel_con36: sel-con@0190 {
1505                                         compatible = "rockchip,rk3188-selcon";
1506                                         reg = <0x0190 0x4>;
1507                                         #address-cells = <1>;
1508                                         #size-cells = <1>;
1509
1510                                         uart1_frac: uart1_frac {
1511                                                 compatible = "rockchip,rk3188-frac-con";
1512                                                 clocks = <&uart1_div>;
1513                                                 clock-output-names = "uart1_frac";
1514                                                 /* numerator    denominator */
1515                                                 rockchip,bits = <0 32>;
1516                                                 rockchip,clkops-idx =
1517                                                         <CLKOPS_RATE_FRAC>;
1518                                                 #clock-cells = <0>;
1519                                         };
1520                                 };
1521
1522                                 clk_sel_con37: sel-con@0194 {
1523                                         compatible = "rockchip,rk3188-selcon";
1524                                         reg = <0x0194 0x4>;
1525                                         #address-cells = <1>;
1526                                         #size-cells = <1>;
1527
1528                                         uart2_div: uart2_div {
1529                                                 compatible = "rockchip,rk3188-div-con";
1530                                                 rockchip,bits = <0 7>;
1531                                                 clocks = <&clk_uart_pll>;
1532                                                 clock-output-names = "uart2_div";
1533                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1534                                                 #clock-cells = <0>;
1535                                         };
1536
1537                                         /* 7 reserved */
1538
1539                                         clk_uart2: clk_uart2_mux {
1540                                                 compatible = "rockchip,rk3188-mux-con";
1541                                                 rockchip,bits = <8 1>;
1542                                                 clocks = <&uart2_div>, <&xin24m>;
1543                                                 clock-output-names = "clk_uart2";
1544                                                 #clock-cells = <0>;
1545                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1546                                         };
1547                                 };
1548
1549                                 /* sel[38] reserved */
1550
1551                                 clk_sel_con39: sel-con@019c {
1552                                         compatible = "rockchip,rk3188-selcon";
1553                                         reg = <0x019c 0x4>;
1554                                         #address-cells = <1>;
1555                                         #size-cells = <1>;
1556
1557                                         uart3_div: uart3_div {
1558                                                 compatible = "rockchip,rk3188-div-con";
1559                                                 rockchip,bits = <0 7>;
1560                                                 clocks = <&clk_uart_pll>;
1561                                                 clock-output-names = "uart3_div";
1562                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1563                                                 #clock-cells = <0>;
1564                                         };
1565
1566                                         /* 7 reserved */
1567
1568                                         clk_uart3: clk_uart3_mux {
1569                                                 compatible = "rockchip,rk3188-mux-con";
1570                                                 rockchip,bits = <8 2>;
1571                                                 clocks = <&uart3_div>, <&uart3_frac>, <&xin24m>, <&xin24m>;
1572                                                 clock-output-names = "clk_uart3";
1573                                                 #clock-cells = <0>;
1574                                                 rockchip,clkops-idx =
1575                                                         <CLKOPS_RATE_RK3288_I2S>;
1576                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1577                                         };
1578                                 };
1579
1580                                 clk_sel_con40: sel-con@01a0 {
1581                                         compatible = "rockchip,rk3188-selcon";
1582                                         reg = <0x01a0 0x4>;
1583                                         #address-cells = <1>;
1584                                         #size-cells = <1>;
1585
1586                                         uart3_frac: uart3_frac {
1587                                                 compatible = "rockchip,rk3188-frac-con";
1588                                                 clocks = <&uart3_div>;
1589                                                 clock-output-names = "uart3_frac";
1590                                                 /* numerator    denominator */
1591                                                 rockchip,bits = <0 32>;
1592                                                 rockchip,clkops-idx =
1593                                                         <CLKOPS_RATE_FRAC>;
1594                                                 #clock-cells = <0>;
1595                                         };
1596                                 };
1597
1598                                 clk_sel_con41: sel-con@01a4 {
1599                                         compatible = "rockchip,rk3188-selcon";
1600                                         reg = <0x01a4 0x4>;
1601                                         #address-cells = <1>;
1602                                         #size-cells = <1>;
1603
1604                                         uart4_div: uart4_div {
1605                                                 compatible = "rockchip,rk3188-div-con";
1606                                                 rockchip,bits = <0 7>;
1607                                                 clocks = <&clk_uart_pll>;
1608                                                 clock-output-names = "uart4_div";
1609                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1610                                                 #clock-cells = <0>;
1611                                         };
1612
1613                                         /* 7 reserved */
1614
1615                                         clk_uart4: clk_uart4_mux {
1616                                                 compatible = "rockchip,rk3188-mux-con";
1617                                                 rockchip,bits = <8 2>;
1618                                                 clocks = <&uart4_div>, <&uart4_frac>, <&xin24m>, <&xin24m>;
1619                                                 clock-output-names = "clk_uart4";
1620                                                 #clock-cells = <0>;
1621                                                 rockchip,clkops-idx =
1622                                                         <CLKOPS_RATE_RK3288_I2S>;
1623                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1624                                         };
1625                                 };
1626
1627                                 clk_sel_con42: sel-con@01a8 {
1628                                         compatible = "rockchip,rk3188-selcon";
1629                                         reg = <0x01a8 0x4>;
1630                                         #address-cells = <1>;
1631                                         #size-cells = <1>;
1632
1633                                         uart4_frac: uart4_frac {
1634                                                 compatible = "rockchip,rk3188-frac-con";
1635                                                 clocks = <&uart4_div>;
1636                                                 clock-output-names = "uart4_frac";
1637                                                 /* numerator    denominator */
1638                                                 rockchip,bits = <0 32>;
1639                                                 rockchip,clkops-idx =
1640                                                         <CLKOPS_RATE_FRAC>;
1641                                                 #clock-cells = <0>;
1642                                         };
1643                                 };
1644
1645                                 clk_sel_con43: sel-con@01ac {
1646                                         compatible = "rockchip,rk3188-selcon";
1647                                         reg = <0x01ac 0x4>;
1648                                         #address-cells = <1>;
1649                                         #size-cells = <1>;
1650
1651                                         clk_mac_pll_div: clk_mac_pll_div {
1652                                                 compatible = "rockchip,rk3188-div-con";
1653                                                 rockchip,bits = <0 5>;
1654                                                 clocks = <&clk_mac_pll>;
1655                                                 clock-output-names = "clk_mac_pll";
1656                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1657                                                 #clock-cells = <0>;
1658                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1659                                         };
1660
1661                                         /* 5 reserved */
1662
1663                                         clk_mac_pll: clk_mac_pll_mux {
1664                                                 compatible = "rockchip,rk3188-mux-con";
1665                                                 rockchip,bits = <6 2>;
1666                                                 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>, <&clk_gpll>;
1667                                                 clock-output-names = "clk_mac_pll";
1668                                                 #clock-cells = <0>;
1669                                         };
1670
1671                                         clk_mac: clk_mac_mux {
1672                                                 compatible = "rockchip,rk3188-mux-con";
1673                                                 rockchip,bits = <8 1>;
1674                                                 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1675                                                 clock-output-names = "clk_mac";
1676                                                 #clock-cells = <0>;
1677                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1678                                                 #clock-init-cells = <1>;
1679                                         };
1680
1681                                         /* 11:9 reserved */
1682
1683                                         /* 12: test_clk: wifi_pll_sel */
1684
1685                                         /* 15:13 reserved */
1686                                 };
1687
1688                                 clk_sel_con44: sel-con@01b0 {
1689                                         compatible = "rockchip,rk3188-selcon";
1690                                         reg = <0x01b0 0x4>;
1691                                         #address-cells = <1>;
1692                                         #size-cells = <1>;
1693
1694                                         /* test_clk: wifi_frac */
1695                                 };
1696
1697                                 clk_sel_con45: sel-con@01b4 {
1698                                         compatible = "rockchip,rk3188-selcon";
1699                                         reg = <0x01b4 0x4>;
1700                                         #address-cells = <1>;
1701                                         #size-cells = <1>;
1702
1703                                         clk_spi0_div: clk_spi0_div {
1704                                                 compatible = "rockchip,rk3188-div-con";
1705                                                 rockchip,bits = <0 7>;
1706                                                 clocks = <&clk_spi0>;
1707                                                 clock-output-names = "clk_spi0";
1708                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1709                                                 #clock-cells = <0>;
1710                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1711                                         };
1712
1713                                         clk_spi0: clk_spi0_mux {
1714                                                 compatible = "rockchip,rk3188-mux-con";
1715                                                 rockchip,bits = <7 1>;
1716                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1717                                                 clock-output-names = "clk_spi0";
1718                                                 #clock-cells = <0>;
1719                                         };
1720
1721                                         clk_spi1_div: clk_spi1_div {
1722                                                 compatible = "rockchip,rk3188-div-con";
1723                                                 rockchip,bits = <8 7>;
1724                                                 clocks = <&clk_spi1>;
1725                                                 clock-output-names = "clk_spi1";
1726                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1727                                                 #clock-cells = <0>;
1728                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1729                                         };
1730
1731                                         clk_spi1: clk_spi1_mux {
1732                                                 compatible = "rockchip,rk3188-mux-con";
1733                                                 rockchip,bits = <15 1>;
1734                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1735                                                 clock-output-names = "clk_spi1";
1736                                                 #clock-cells = <0>;
1737                                         };
1738                                 };
1739
1740                                 clk_sel_con46: sel-con@01b8 {
1741                                         compatible = "rockchip,rk3188-selcon";
1742                                         reg = <0x01b8 0x4>;
1743                                         #address-cells = <1>;
1744                                         #size-cells = <1>;
1745
1746                                         clk_tsp_div: clk_tsp_div {
1747                                                 compatible = "rockchip,rk3188-div-con";
1748                                                 rockchip,bits = <0 5>;
1749                                                 clocks = <&clk_tsp>;
1750                                                 clock-output-names = "clk_tsp";
1751                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1752                                                 #clock-cells = <0>;
1753                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
1754                                         };
1755
1756                                         /* 5 reserved */
1757
1758                                         clk_tsp: clk_tsp_mux {
1759                                                 compatible = "rockchip,rk3188-mux-con";
1760                                                 rockchip,bits = <6 2>;
1761                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
1762                                                 clock-output-names = "clk_tsp";
1763                                                 #clock-cells = <0>;
1764                                         };
1765
1766                                         clk_spi2_div: clk_spi2_div {
1767                                                 compatible = "rockchip,rk3188-div-con";
1768                                                 rockchip,bits = <8 7>;
1769                                                 clocks = <&clk_spi2>;
1770                                                 clock-output-names = "clk_spi2";
1771                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1772                                                 #clock-cells = <0>;
1773                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1774                                         };
1775
1776                                         clk_spi2: clk_spi2_mux {
1777                                                 compatible = "rockchip,rk3188-mux-con";
1778                                                 rockchip,bits = <15 1>;
1779                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1780                                                 clock-output-names = "clk_spi2";
1781                                                 #clock-cells = <0>;
1782                                         };
1783                                 };
1784
1785                                 clk_sel_con47: sel-con@01bc {
1786                                         compatible = "rockchip,rk3188-selcon";
1787                                         reg = <0x01bc 0x4>;
1788                                         #address-cells = <1>;
1789                                         #size-cells = <1>;
1790
1791                                         clk_nandc0_div: clk_nandc0_div {
1792                                                 compatible = "rockchip,rk3188-div-con";
1793                                                 rockchip,bits = <0 5>;
1794                                                 clocks = <&clk_nandc0>;
1795                                                 clock-output-names = "clk_nandc0";
1796                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1797                                                 #clock-cells = <0>;
1798                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1799                                         };
1800
1801                                         /* 6:5 reserved */
1802
1803                                         clk_nandc0: clk_nandc0_mux {
1804                                                 compatible = "rockchip,rk3188-mux-con";
1805                                                 rockchip,bits = <7 1>;
1806                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1807                                                 clock-output-names = "clk_nandc0";
1808                                                 #clock-cells = <0>;
1809                                         };
1810
1811                                         /* 12:8 test_div */
1812
1813                                         /* 15:13 reserved */
1814                                 };
1815
1816                                 clk_sel_con48: sel-con@01c0 {
1817                                         compatible = "rockchip,rk3188-selcon";
1818                                         reg = <0x01c0 0x4>;
1819                                         #address-cells = <1>;
1820                                         #size-cells = <1>;
1821
1822                                         clk_sdio0_div: clk_sdio0_div {
1823                                                 compatible = "rockchip,rk3188-div-con";
1824                                                 rockchip,bits = <0 7>;
1825                                                 clocks = <&clk_sdio0>;
1826                                                 clock-output-names = "clk_sdio0";
1827                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1828                                                 #clock-cells = <0>;
1829                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1830                                         };
1831
1832                                         /* 7 reserved */
1833
1834                                         clk_sdio0: clk_sdio0_mux {
1835                                                 compatible = "rockchip,rk3188-mux-con";
1836                                                 rockchip,bits = <8 2>;
1837                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1838                                                 clock-output-names = "clk_sdio0";
1839                                                 #clock-cells = <0>;
1840                                         };
1841
1842                                         /* 15:10 reserved */
1843                                 };
1844
1845                                 /* sel[49] reserved */
1846
1847                                 clk_sel_con50: sel-con@01c8 {
1848                                         compatible = "rockchip,rk3188-selcon";
1849                                         reg = <0x01c8 0x4>;
1850                                         #address-cells = <1>;
1851                                         #size-cells = <1>;
1852
1853                                         clk_sdmmc0_div: clk_sdmmc0_div {
1854                                                 compatible = "rockchip,rk3188-div-con";
1855                                                 rockchip,bits = <0 7>;
1856                                                 clocks = <&clk_sdmmc0>;
1857                                                 clock-output-names = "clk_sdmmc0";
1858                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1859                                                 #clock-cells = <0>;
1860                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1861                                         };
1862
1863                                         /* 7 reserved */
1864
1865                                         clk_sdmmc0: clk_sdmmc0_mux {
1866                                                 compatible = "rockchip,rk3188-mux-con";
1867                                                 rockchip,bits = <8 2>;
1868                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1869                                                 clock-output-names = "clk_sdmmc0";
1870                                                 #clock-cells = <0>;
1871                                         };
1872
1873                                         /* 15:10 reserved */
1874                                 };
1875
1876                                 clk_sel_con51: sel-con@01cc {
1877                                         compatible = "rockchip,rk3188-selcon";
1878                                         reg = <0x01cc 0x4>;
1879                                         #address-cells = <1>;
1880                                         #size-cells = <1>;
1881
1882                                         clk_emmc_div: clk_emmc_div {
1883                                                 compatible = "rockchip,rk3188-div-con";
1884                                                 rockchip,bits = <0 7>;
1885                                                 clocks = <&clk_emmc>;
1886                                                 clock-output-names = "clk_emmc";
1887                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1888                                                 #clock-cells = <0>;
1889                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_EVENDIV>;
1890                                         };
1891
1892                                         /* 7 reserved */
1893
1894                                         clk_emmc: clk_emmc_mux {
1895                                                 compatible = "rockchip,rk3188-mux-con";
1896                                                 rockchip,bits = <8 2>;
1897                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&xin24m>;
1898                                                 clock-output-names = "clk_emmc";
1899                                                 #clock-cells = <0>;
1900                                         };
1901
1902                                         /* 15:10 reserved */
1903                                 };
1904
1905                                 clk_sel_con52: sel-con@01d0 {
1906                                         compatible = "rockchip,rk3188-selcon";
1907                                         reg = <0x01d0 0x4>;
1908                                         #address-cells = <1>;
1909                                         #size-cells = <1>;
1910
1911                                         clk_sfc_div: clk_sfc_div {
1912                                                 compatible = "rockchip,rk3188-div-con";
1913                                                 rockchip,bits = <0 5>;
1914                                                 clocks = <&clk_sfc>;
1915                                                 clock-output-names = "clk_sfc";
1916                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1917                                                 #clock-cells = <0>;
1918                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1919                                         };
1920
1921                                         /* 6:5 reserved */
1922
1923                                         clk_sfc: clk_sfc_mux {
1924                                                 compatible = "rockchip,rk3188-mux-con";
1925                                                 rockchip,bits = <7 1>;
1926                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1927                                                 clock-output-names = "clk_sfc";
1928                                                 #clock-cells = <0>;
1929                                         };
1930
1931                                         /* 15:8 reserved */
1932                                 };
1933
1934                                 clk_sel_con53: sel-con@01d4 {
1935                                         compatible = "rockchip,rk3188-selcon";
1936                                         reg = <0x01d4 0x4>;
1937                                         #address-cells = <1>;
1938                                         #size-cells = <1>;
1939
1940                                         i2s_2ch_pll_div: i2s_2ch_pll_div {
1941                                                 compatible = "rockchip,rk3188-div-con";
1942                                                 rockchip,bits = <0 7>;
1943                                                 clocks = <&i2s_2ch_pll>;
1944                                                 clock-output-names = "i2s_2ch_pll";
1945                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1946                                                 #clock-cells = <0>;
1947                                                 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1948                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1949                                         };
1950
1951                                         /* 7 reserved */
1952
1953                                         clk_i2s_2ch: clk_i2s_2ch_mux {
1954                                                 compatible = "rockchip,rk3188-mux-con";
1955                                                 rockchip,bits = <8 2>;
1956                                                 clocks = <&i2s_2ch_pll>, <&i2s_2ch_frac>, <&dummy>, <&xin12m>;
1957                                                 clock-output-names = "clk_i2s_2ch";
1958                                                 #clock-cells = <0>;
1959                                                 rockchip,clkops-idx =
1960                                                         <CLKOPS_RATE_RK3288_I2S>;
1961                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1962                                         };
1963
1964                                         /* 11:10 reserved */
1965
1966                                         i2s_2ch_pll: i2s_2ch_pll_mux {
1967                                                 compatible = "rockchip,rk3188-mux-con";
1968                                                 rockchip,bits = <12 1>;
1969                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1970                                                 clock-output-names = "i2s_2ch_pll";
1971                                                 #clock-cells = <0>;
1972                                                 #clock-init-cells = <1>;
1973                                         };
1974
1975                                 };
1976
1977                                 clk_sel_con54: sel-con@01d8 {
1978                                         compatible = "rockchip,rk3188-selcon";
1979                                         reg = <0x01d8 0x4>;
1980                                         #address-cells = <1>;
1981                                         #size-cells = <1>;
1982
1983                                         i2s_2ch_frac: i2s_2ch_frac {
1984                                                 compatible = "rockchip,rk3188-frac-con";
1985                                                 clocks = <&i2s_2ch_pll>;
1986                                                 clock-output-names = "i2s_2ch_frac";
1987                                                 /* numerator    denominator */
1988                                                 rockchip,bits = <0 32>;
1989                                                 rockchip,clkops-idx =
1990                                                         <CLKOPS_RATE_FRAC>;
1991                                                 #clock-cells = <0>;
1992                                         };
1993                                 };
1994
1995                                 clk_sel_con55: sel-con@01dc {
1996                                         compatible = "rockchip,rk3188-selcon";
1997                                         reg = <0x01dc 0x4>;
1998                                         #address-cells = <1>;
1999                                         #size-cells = <1>;
2000
2001                                         clk_hdcp_div: clk_hdcp_div {
2002                                                 compatible = "rockchip,rk3188-div-con";
2003                                                 rockchip,bits = <0 6>;
2004                                                 clocks = <&clk_hdcp>;
2005                                                 clock-output-names = "clk_hdcp";
2006                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2007                                                 #clock-cells = <0>;
2008                                                 rockchip,clkops-idx = <CLKOPS_RATE_RK3368_MUX_DIV_NPLL>;
2009                                         };
2010
2011                                         clk_hdcp: clk_hdcp_mux {
2012                                                 compatible = "rockchip,rk3188-mux-con";
2013                                                 rockchip,bits = <6 2>;
2014                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
2015                                                 clock-output-names = "clk_hdcp";
2016                                                 #clock-cells = <0>;
2017                                         };
2018                                 };
2019                         };
2020
2021                         /* Gate control regs */
2022                         clk_gate_cons {
2023                                 compatible = "rockchip,rk-gate-cons";
2024                                 #address-cells = <1>;
2025                                 #size-cells = <1>;
2026                                 ranges;
2027
2028                                 clk_gates0: gate-clk@0200 {
2029                                         compatible = "rockchip,rk3188-gate-clk";
2030                                         reg = <0x0200 0x4>;
2031                                         clocks =
2032                                                 <&dummy>,       <&dummy>,
2033                                                 <&dummy>,       <&dummy>,
2034
2035                                                 <&dummy>,       <&dummy>,
2036                                                 <&dummy>,       <&dummy>,
2037
2038                                                 <&clk_gpll>,    <&clk_apllb>,
2039                                                 <&clk_aplll>,   <&dummy>,
2040
2041                                                 <&aclk_cci>,    <&clkin_trace>,
2042                                                 <&dummy>,       <&dummy>;
2043
2044                                         clock-output-names =
2045                                                 "reserved",     "reserved",/* core_b_apll core_b_gpll */
2046                                                 "reserved",     "reserved",
2047
2048                                                 "reserved",     "reserved",/* core_l_apll core_l_gpll */
2049                                                 "reserved",     "reserved",
2050
2051                                                 "g_clk_cs_gpll",        "g_clk_cs_apllb",
2052                                                 "g_clk_cs_aplll",       "reserved",
2053
2054                                                 "aclk_cci",     "clkin_trace",
2055                                                 "reserved",     "reserved";
2056
2057                                         #clock-cells = <1>;
2058                                 };
2059
2060                                 clk_gates1: gate-clk@0204 {
2061                                         compatible = "rockchip,rk3188-gate-clk";
2062                                         reg = <0x0204 0x4>;
2063                                         clocks =
2064                                                 <&aclk_bus>,    <&hclk_bus>,
2065                                                 <&pclk_bus>,    <&fclk_mcu>,
2066
2067                                                 <&dummy>,       <&dummy>,
2068                                                 <&dummy>,       <&dummy>,
2069
2070                                                 <&dummy>,       <&dummy>,
2071                                                 <&clk_gpll>,    <&clk_cpll>,
2072
2073                                                 <&dummy>,       <&dummy>,
2074                                                 <&dummy>,       <&dummy>;
2075
2076                                         clock-output-names =
2077                                                 "aclk_bus",     "hclk_bus",
2078                                                 "pclk_bus",     "fclk_mcu",
2079
2080                                                 "reserved",     "reserved",
2081                                                 "reserved",     "reserved",
2082
2083                                                 "reserved",     "reserved",/* ddr_dpll  ddr_gpll */
2084                                                 "aclk_bus_gpll",        "aclk_bus_cpll",
2085
2086                                                 "reserved",     "reserved",
2087                                                 "reserved",     "reserved";
2088
2089                                         #clock-cells = <1>;
2090                                 };
2091
2092                                 clk_gates2: gate-clk@0208 {
2093                                         compatible = "rockchip,rk3188-gate-clk";
2094                                         reg = <0x0208 0x4>;
2095                                         clocks =
2096                                                 <&clk_uart0_pll>,       <&uart0_frac>,
2097                                                 <&uart1_div>,   <&uart1_frac>,
2098
2099                                                 <&uart2_div>,   <&dummy>,
2100                                                 <&uart3_div>,   <&uart3_frac>,
2101
2102                                                 <&uart4_div>,   <&uart4_frac>,
2103                                                 <&dummy>,       <&dummy>,
2104
2105                                                 <&dummy>,       <&dummy>,
2106                                                 <&dummy>,       <&dummy>;
2107
2108                                         clock-output-names =
2109                                                 "clk_uart0_pll",        "uart0_frac",
2110                                                 "uart1_div",    "uart1_frac",
2111
2112                                                 "uart2_div",    "reserved",
2113                                                 "uart3_div",    "uart3_frac",
2114
2115                                                 "uart4_div",    "uart4_frac",
2116                                                 "reserved",     "reserved",
2117
2118                                                 "reserved",     "reserved",
2119                                                 "reserved",     "reserved";
2120
2121                                         #clock-cells = <1>;
2122                                 };
2123
2124                                 clk_gates3: gate-clk@020c {
2125                                         compatible = "rockchip,rk3188-gate-clk";
2126                                         reg = <0x020c 0x4>;
2127                                         clocks =
2128                                                 <&aclk_peri>,   <&dummy>,
2129                                                 <&hclk_peri>,   <&pclk_peri>,
2130
2131                                                 <&clk_mac_pll>, <&clk_tsadc>,
2132                                                 <&clk_saradc>,  <&clk_spi0>,
2133
2134                                                 <&clk_spi1>,    <&clk_spi2>,
2135                                                 <&dummy>,       <&dummy>,
2136
2137                                                 <&dummy>,       <&dummy>,
2138                                                 <&dummy>,       <&dummy>;
2139
2140                                         clock-output-names =
2141                                                 "aclk_peri",    "reserved", /* bit1: aclk_peri */
2142                                                 "hclk_peri",    "pclk_peri",
2143
2144                                                 "clk_mac_pll",  "clk_tsadc",
2145                                                 "clk_saradc",   "clk_spi0",
2146
2147                                                 "clk_spi1",     "clk_spi2",
2148                                                 "reserved",     "reserved",
2149
2150                                                 "reserved",     "reserved",
2151                                                 "reserved",     "reserved";
2152
2153                                         #clock-cells = <1>;
2154                                 };
2155
2156                                 clk_gates4: gate-clk@0210 {
2157                                         compatible = "rockchip,rk3188-gate-clk";
2158                                         reg = <0x0210 0x4>;
2159                                         clocks =
2160                                                 <&aclk_vio0>,   <&dclk_vop0>,
2161                                                 <&xin24m>,      <&aclk_rga_pre>,
2162
2163                                                 <&clk_rga>,     <&clk_vip_pll>,
2164                                                 <&aclk_vepu>,   <&aclk_vdpu>,
2165
2166                                                 <&dummy>,       <&clk_isp>,
2167                                                 <&dummy>,       <&clk_gpu_core>,
2168
2169                                                 <&xin32k>,      <&xin24m>,
2170                                                 <&xin24m>,      <&dummy>;
2171
2172                                         clock-output-names =
2173                                                 "aclk_vio0",    "dclk_vop0",
2174                                                 "clk_vop0_pwm", "aclk_rga_pre",
2175
2176                                                 "clk_rga",      "clk_vip_pll",
2177                                                 "aclk_vepu",    "aclk_vdpu",
2178
2179                                                 "reserved",     "clk_isp", /* bit8: hclk_vpu */
2180                                                 "reserved",     "clk_gpu",
2181
2182                                                 "clk_hdmi_cec", "clk_hdmi_hdcp",
2183                                                 "clk_dsiphy_24m",       "reserved";
2184
2185                                         #clock-cells = <1>;
2186                                 };
2187
2188                                 clk_gates5: gate-clk@0214 {
2189                                         compatible = "rockchip,rk3188-gate-clk";
2190                                         reg = <0x0214 0x4>;
2191                                         clocks =
2192                                                 <&dummy>,       <&clk_hevc_cabac>,
2193                                                 <&clk_hevc_core>,       <&clk_edp>,
2194
2195                                                 <&clk_edp_24m>, <&clk_hdcp>,
2196                                                 <&dummy>,       <&dummy>,
2197
2198                                                 <&aclk_gpu_mem>,        <&aclk_gpu_cfg>,
2199                                                 <&dummy>,       <&dummy>,
2200
2201                                                 <&dummy>,       <&i2s_2ch_pll>,
2202                                                 <&i2s_2ch_frac>,        <&clk_i2s_2ch>;
2203
2204                                         clock-output-names =
2205                                                 "reserved",     "clk_hevc_cabac",
2206                                                 "clk_hevc_core",        "clk_edp",
2207
2208                                                 "clk_edp_24m",  "clk_hdcp",
2209                                                 "reserved",     "reserved",
2210
2211                                                 "aclk_gpu_mem", "aclk_gpu_cfg",
2212                                                 "reserved",     "reserved",
2213
2214                                                 "reserved",     "i2s_2ch_pll",
2215                                                 "i2s_2ch_frac", "clk_i2s_2ch";
2216
2217                                         #clock-cells = <1>;
2218                                 };
2219
2220                                 clk_gates6: gate-clk@0218 {
2221                                         compatible = "rockchip,rk3188-gate-clk";
2222                                         reg = <0x0218 0x4>;
2223                                         clocks =
2224                                                 <&i2s_out>,     <&i2s_pll>,
2225                                                 <&i2s_frac>,    <&clk_i2s>,
2226
2227                                                 <&spdif_8ch_pll>,       <&spdif_8ch_frac>,
2228                                                 <&clk_spidf_8ch>,       <&clk_sfc>,
2229
2230                                                 <&dummy>,       <&dummy>,
2231                                                 <&dummy>,       <&dummy>,
2232
2233                                                 <&clk_tsp>,     <&dummy>,
2234                                                 <&dummy>,       <&dummy>;
2235
2236                                         clock-output-names =
2237                                                 "i2s_out",      "i2s_pll",
2238                                                 "i2s_frac",     "clk_i2s",
2239
2240                                                 "spdif_8ch_pll",        "spdif_8ch_frac",
2241                                                 "clk_spidf_8ch",        "clk_sfc",
2242
2243                                                 "reserved",     "reserved",
2244                                                 "reserved",     "reserved",
2245
2246                                                 "clk_tsp",      "reserved",
2247                                                 "reserved",     "reserved";/* clk_ddrphy_gate   clk4x_ddrphy_gate */
2248
2249                                         #clock-cells = <1>;
2250                                 };
2251
2252                                 clk_gates7: gate-clk@021c {
2253                                         compatible = "rockchip,rk3188-gate-clk";
2254                                         reg = <0x021c 0x4>;
2255                                         clocks =
2256                                                 <&jtag_clkin>,  <&dummy>,
2257                                                 <&clk_crypto>,  <&xin24m>,
2258
2259                                                 <&dummy>,       <&dummy>,
2260                                                 <&clk_mac>,     <&clk_mac>,
2261
2262                                                 <&clk_nandc0>,  <&pclk_pmu_pre>,
2263                                                 <&xin24m>,      <&xin24m>,
2264
2265                                                 <&dummy>,       <&dummy>,
2266                                                 <&dummy>,       <&dummy>;
2267
2268                                         clock-output-names =
2269                                                 "clk_jtag",     "reserved",/* bit1: test_clk */
2270                                                 "clk_crypto",   "clk_pvtm_pmu",
2271
2272                                                 "clk_mac_rx",   "clk_mac_tx",
2273                                                 "clk_mac_ref",  "clk_mac_refout",
2274
2275                                                 "clk_nandc0",   "pclk_pmu_pre",
2276                                                 "clk_pvtm_core",        "clk_pvtm_gpu",
2277
2278                                                 "clk_sdmmc0",   "clk_sdio0",
2279                                                 "reserved",     "clk_emmc";
2280
2281                                         #clock-cells = <1>;
2282                                 };
2283
2284                                 clk_gates8: gate-clk@0220 {
2285                                         compatible = "rockchip,rk3188-gate-clk";
2286                                         reg = <0x0220 0x4>;
2287                                         clocks =
2288                                                 <&hsic_usb_480m>,       <&xin24m>,
2289                                                 <&dummy>,       <&dummy>,
2290
2291                                                 <&clk_32k_mux>, <&dummy>,
2292                                                 <&xin12m>,      <&hsicphy_480m>,
2293
2294                                                 <&dummy>,       <&dummy>,
2295                                                 <&dummy>,       <&dummy>,
2296
2297                                                 <&dummy>,       <&dummy>,
2298                                                 <&dummy>,       <&dummy>;
2299
2300                                         clock-output-names =
2301                                                 "hsic_usb_480m",        "clk_otgphy0",
2302                                                 "reserved",     "reserved",
2303
2304                                                 "g_clk_otg_adp",        "reserved",/* bit4: clk_otg_adp */
2305                                                 "hsicphy_12m",  "hsicphy_480m",
2306
2307                                                 "reserved",     "reserved",
2308                                                 "reserved",     "reserved",
2309
2310                                                 "reserved",     "reserved",
2311                                                 "reserved",     "reserved";
2312
2313                                         #clock-cells = <1>;
2314                                 };
2315
2316                                 clk_gates9: gate-clk@0224 {
2317                                         compatible = "rockchip,rk3188-gate-clk";
2318                                         reg = <0x0224 0x4>;
2319                                         clocks =
2320                                                 <&dummy>,       <&dummy>,
2321                                                 <&dummy>,       <&dummy>,
2322
2323                                                 <&dummy>,       <&dummy>,
2324                                                 <&dummy>,       <&dummy>,
2325
2326                                                 <&dummy>,       <&dummy>,
2327                                                 <&dummy>,       <&dummy>,
2328
2329                                                 <&dummy>,       <&dummy>,
2330                                                 <&dummy>,       <&dummy>;
2331
2332                                         clock-output-names =
2333                                                 "reserved",     "reserved",
2334                                                 "reserved",     "reserved",
2335
2336                                                 "reserved",     "reserved",
2337                                                 "reserved",     "reserved",
2338
2339                                                 "reserved",     "reserved",
2340                                                 "reserved",     "reserved",
2341
2342                                                 "reserved",     "reserved",
2343                                                 "reserved",     "reserved";
2344
2345                                         #clock-cells = <1>;
2346                                 };
2347
2348                                 clk_gates10: gate-clk@0228 {
2349                                         compatible = "rockchip,rk3188-gate-clk";
2350                                         reg = <0x0228 0x4>;
2351                                         clocks =
2352                                                 <&dummy>,       <&dummy>,
2353                                                 <&dummy>,       <&dummy>,
2354
2355                                                 <&dummy>,       <&dummy>,
2356                                                 <&dummy>,       <&dummy>,
2357
2358                                                 <&dummy>,       <&dummy>,
2359                                                 <&dummy>,       <&dummy>,
2360
2361                                                 <&dummy>,       <&dummy>,
2362                                                 <&dummy>,       <&dummy>;
2363
2364                                         clock-output-names =
2365                                                 "reserved",     "reserved",
2366                                                 "reserved",     "reserved",
2367
2368                                                 "reserved",     "reserved",
2369                                                 "reserved",     "reserved",
2370
2371                                                 "reserved",     "reserved",
2372                                                 "reserved",     "reserved",
2373
2374                                                 "reserved",     "reserved",
2375                                                 "reserved",     "reserved";
2376
2377                                         #clock-cells = <1>;
2378                                 };
2379
2380                                 clk_gates11: gate-clk@022c {
2381                                         compatible = "rockchip,rk3188-gate-clk";
2382                                         reg = <0x022c 0x4>;
2383                                         clocks =
2384                                                 <&dummy>,       <&dummy>,
2385                                                 <&dummy>,       <&dummy>,
2386
2387                                                 <&dummy>,       <&dummy>,
2388                                                 <&dummy>,       <&dummy>,
2389
2390                                                 <&dummy>,       <&dummy>,
2391                                                 <&dummy>,       <&dummy>,
2392
2393                                                 <&dummy>,       <&dummy>,
2394                                                 <&dummy>,       <&dummy>;
2395
2396                                         clock-output-names =
2397                                                 "reserved",     "reserved",
2398                                                 "reserved",     "reserved",
2399
2400                                                 "reserved",     "reserved",
2401                                                 "reserved",     "reserved",
2402
2403                                                 "reserved",     "reserved",
2404                                                 "reserved",     "reserved",
2405
2406                                                 "reserved",     "reserved",
2407                                                 "reserved",     "reserved";
2408
2409                                         #clock-cells = <1>;
2410                                 };
2411
2412                                 clk_gates12: gate-clk@0230 {
2413                                         compatible = "rockchip,rk3188-gate-clk";
2414                                         reg = <0x0230 0x4>;
2415                                         clocks =
2416                                                 <&pclk_bus>,    <&pclk_bus>,
2417                                                 <&pclk_bus>,    <&pclk_bus>,
2418
2419                                                 <&aclk_bus>,    <&aclk_bus>,
2420                                                 <&aclk_bus>,    <&hclk_bus>,
2421
2422                                                 <&hclk_bus>,    <&hclk_bus>,
2423                                                 <&hclk_bus>,    <&aclk_bus>,
2424
2425                                                 <&aclk_bus>,    <&dummy>,
2426                                                 <&dummy>,       <&dummy>;
2427
2428                                         clock-output-names =
2429                                                 "g_pclk_pwm0",  "g_p_mailbox",
2430                                                 "g_p_i2cpmu",   "g_p_i2caudio",
2431
2432                                                 "g_aclk_intmem",        "g_clk_intmem0",
2433                                                 "g_clk_intmem1",        "g_h_i2s_8ch",
2434
2435                                                 "g_h_i2s_2ch",  "g_hclk_rom",
2436                                                 "g_hclk_spdif", "g_aclk_dmac",
2437
2438                                                 "g_a_strc_sys", "reserved",/* bit13: pclk_ddrupctl */
2439                                                 "reserved",     "reserved";/* bit14: pclk_ddrphy */
2440
2441                                         #clock-cells = <1>;
2442                                 };
2443
2444                                 clk_gates13: gate-clk@0234 {
2445                                         compatible = "rockchip,rk3188-gate-clk";
2446                                         reg = <0x0234 0x4>;
2447                                         clocks =
2448                                                 <&pclk_bus>,    <&pclk_bus>,
2449                                                 <&dummy>,       <&hclk_bus>,
2450
2451                                                 <&hclk_bus>,    <&pclk_bus>,
2452                                                 <&pclk_bus>,    <&clkin_hsadc_tsp>,
2453
2454                                                 <&pclk_bus>,    <&aclk_bus>,
2455                                                 <&hclk_bus>,    <&dummy>,
2456
2457                                                 <&dummy>,       <&dummy>,
2458                                                 <&dummy>,       <&dummy>;
2459
2460                                         clock-output-names =
2461                                                 "g_p_efuse_1024",       "g_p_efuse_256",
2462                                                 "reserved",     "g_mclk_crypto",/* bit2: nclk_ddrupctl */
2463
2464                                                 "g_sclk_crypto",        "g_p_uartdbg",
2465                                                 "g_pclk_pwm1",  "clk_hsadc_tsp",
2466
2467                                                 "g_pclk_sim",   "g_aclk_gic400",
2468                                                 "g_hclk_tsp",   "reserved",
2469
2470                                                 "reserved",     "reserved",
2471                                                 "reserved",     "reserved";
2472
2473                                         #clock-cells = <1>;
2474                                 };
2475
2476                                 clk_gates14: gate-clk@0238 {
2477                                         compatible = "rockchip,rk3188-gate-clk";
2478                                         reg = <0x0238 0x4>;
2479                                         clocks =
2480                                                 <&dummy>,       <&dummy>,
2481                                                 <&dummy>,       <&dummy>,
2482
2483                                                 <&dummy>,       <&dummy>,
2484                                                 <&dummy>,       <&dummy>,
2485
2486                                                 <&dummy>,       <&dummy>,
2487                                                 <&dummy>,       <&dummy>,
2488
2489                                                 <&dummy>,       <&dummy>,
2490                                                 <&dummy>,       <&dummy>;
2491
2492                                         clock-output-names =
2493                                                 "reserved",     "reserved",
2494                                                 "reserved",     "reserved",
2495
2496                                                 "reserved",     "reserved",
2497                                                 "reserved",     "reserved",
2498
2499                                                 "reserved",     "reserved",
2500                                                 "reserved",     "reserved",
2501
2502                                                 "reserved",     "reserved",
2503                                                 "reserved",     "reserved";
2504
2505                                         #clock-cells = <1>;
2506                                 };
2507
2508                                 clk_gates15: gate-clk@023c {
2509                                         compatible = "rockchip,rk3188-gate-clk";
2510                                         reg = <0x023c 0x4>;
2511                                         clocks =
2512                                                 <&dummy>,       <&dummy>,
2513                                                 <&dummy>,       <&dummy>,
2514
2515                                                 <&dummy>,       <&dummy>,
2516                                                 <&dummy>,       <&dummy>,
2517
2518                                                 <&dummy>,       <&dummy>,
2519                                                 <&dummy>,       <&dummy>,
2520
2521                                                 <&dummy>,       <&dummy>,
2522                                                 <&dummy>,       <&dummy>;
2523
2524                                         clock-output-names =
2525                                                 "reserved",     "reserved",/* aclk_video hclk_video */
2526                                                 "reserved",     "reserved",
2527
2528                                                 "reserved",     "reserved",
2529                                                 "reserved",     "reserved",
2530
2531                                                 "reserved",     "reserved",
2532                                                 "reserved",     "reserved",
2533
2534                                                 "reserved",     "reserved",
2535                                                 "reserved",     "reserved";
2536
2537                                         #clock-cells = <1>;
2538                                 };
2539
2540                                 clk_gates16: gate-clk@0240 {
2541                                         compatible = "rockchip,rk3188-gate-clk";
2542                                         reg = <0x0240 0x4>;
2543                                         clocks =
2544                                                 <&clk_gates16 10>,      <&clk_gates16 8>,
2545                                                 <&clk_gates16 9>,       <&clk_gates16 8>,
2546
2547                                                 <&clk_gates16 9>,       <&clk_gates16 9>,
2548                                                 <&clk_gates16 8>,       <&clk_gates17 8>,
2549
2550                                                 <&clk_gates16 7>,       <&aclk_vio0>,
2551                                                 <&aclk_rga_pre>,        <&clk_gates16 9>,
2552
2553                                                 <&clk_gates16 8>,       <&pclkin_vip>,
2554                                                 <&clk_isp>,     <&dummy>;
2555
2556                                         clock-output-names =
2557                                                 "g_aclk_rga",   "g_hclk_rga",
2558                                                 "g_aclk_iep",   "g_hclk_iep",
2559
2560                                                 "g_aclk_vop_iep",       "g_aclk_vop",
2561                                                 "g_hclk_vop",   "h_vio_ahb_arbi",
2562
2563                                                 "g_hclk_vio_noc",       "g_aclk_vio0_noc",
2564                                                 "g_aclk_vio1_noc",      "g_aclk_vip",
2565
2566                                                 "g_hclk_vip",   "g_pclkin_vip",
2567                                                 "g_hclk_isp",   "reserved";
2568
2569                                         #clock-cells = <1>;
2570                                 };
2571
2572                                 clk_gates17: gate-clk@0244 {
2573                                         compatible = "rockchip,rk3188-gate-clk";
2574                                         reg = <0x0244 0x4>;
2575                                         clocks =
2576                                                 <&clk_isp>,     <&dummy>,
2577                                                 <&pclkin_isp>,  <&pclk_vio>,
2578
2579                                                 <&pclk_vio>,    <&dummy>,
2580                                                 <&pclk_vio>,    <&hclk_vio>,
2581
2582                                                 <&clk_gates17 7>,       <&pclk_vio>,
2583                                                 <&clk_gates16 10>,      <&pclk_vio>,
2584
2585                                                 <&clk_gates16 8>,       <&dummy>,
2586                                                 <&dummy>,       <&dummy>;
2587
2588                                         clock-output-names =
2589                                                 "g_aclk_isp",   "reserved",
2590                                                 "g_pclkin_isp", "g_p_mipi_dsi0",
2591
2592                                                 "g_p_mipi_csi", "reserved",
2593                                                 "g_p_hdmi_ctrl",        "g_hclk_vio_h2p",
2594
2595                                                 "g_pclk_vio_h2p",       "g_p_edp_ctrl",
2596                                                 "g_aclk_hdcp",  "g_pclk_hdcp",
2597
2598                                                 "g_h_hdcpmmu",  "reserved",
2599                                                 "reserved",     "reserved";
2600
2601                                         #clock-cells = <1>;
2602                                 };
2603
2604                                 clk_gates18: gate-clk@0248 {
2605                                         compatible = "rockchip,rk3188-gate-clk";
2606                                         reg = <0x0248 0x4>;
2607                                         clocks =
2608                                                 <&dummy>,       <&dummy>,
2609                                                 <&dummy>,       <&dummy>,
2610
2611                                                 <&dummy>,       <&dummy>,
2612                                                 <&dummy>,       <&dummy>,
2613
2614                                                 <&dummy>,       <&dummy>,
2615                                                 <&dummy>,       <&dummy>,
2616
2617                                                 <&dummy>,       <&dummy>,
2618                                                 <&dummy>,       <&dummy>;
2619
2620                                         clock-output-names =
2621                                                 "reserved",     "reserved",/* bit0-1: aclk_gpu_cfg aclk_gpu_mem */
2622                                                 "reserved",     "reserved",/* bit2: clk_gpu_core */
2623
2624                                                 "reserved",     "reserved",
2625                                                 "reserved",     "reserved",
2626
2627                                                 "reserved",     "reserved",
2628                                                 "reserved",     "reserved",
2629
2630                                                 "reserved",     "reserved",
2631                                                 "reserved",     "reserved";
2632
2633                                         #clock-cells = <1>;
2634                                 };
2635
2636                                 clk_gates19: gate-clk@024c {
2637                                         compatible = "rockchip,rk3188-gate-clk";
2638                                         reg = <0x024c 0x4>;
2639                                         clocks =
2640                                                 <&hclk_peri>,   <&pclk_peri>,
2641                                                 <&aclk_peri>,   <&aclk_peri>,
2642
2643                                                 <&pclk_peri>,   <&pclk_peri>,
2644                                                 <&pclk_peri>,   <&pclk_peri>,
2645
2646                                                 <&pclk_peri>,   <&pclk_peri>,
2647                                                 <&pclk_peri>,   <&pclk_peri>,
2648
2649                                                 <&pclk_peri>,   <&pclk_peri>,
2650                                                 <&pclk_peri>,   <&pclk_peri>;
2651
2652                                         clock-output-names =
2653                                                 "g_hp_axi_matrix",      "g_pp_axi_matrix",
2654                                                 "g_ap_axi_matrix",      "g_a_dmac_peri",
2655
2656                                                 "g_pclk_spi0",  "g_pclk_spi1",
2657                                                 "g_pclk_spi2",  "g_pclk_uart0",
2658
2659                                                 "g_pclk_uart1", "g_pclk_uart3",
2660                                                 "g_pclk_uart4", "g_pclk_i2c2",
2661
2662                                                 "g_pclk_i2c3",  "g_pclk_i2c4",
2663                                                 "g_pclk_i2c5",  "g_pclk_saradc";
2664
2665                                         #clock-cells = <1>;
2666                                 };
2667
2668                                 clk_gates20: gate-clk@0250 {
2669                                         compatible = "rockchip,rk3188-gate-clk";
2670                                         reg = <0x0250 0x4>;
2671                                         clocks =
2672                                                 <&pclk_peri>,   <&hclk_peri>,
2673                                                 <&hclk_peri>,   <&hclk_peri>,
2674
2675                                                 <&dummy>,       <&hclk_peri>,
2676                                                 <&hclk_peri>,   <&hclk_peri>,
2677
2678                                                 <&aclk_peri>,   <&hclk_peri>,
2679                                                 <&hclk_peri>,   <&hclk_peri>,
2680
2681                                                 <&dummy>,       <&aclk_peri>,
2682                                                 <&pclk_peri>,   <&aclk_peri>;
2683
2684                                         clock-output-names =
2685                                                 "g_pclk_tsadc", "g_hclk_otg0",
2686                                                 "g_h_pmu_otg0", "g_hclk_host0",
2687
2688                                                 "reserved",     "g_hclk_hsic",
2689                                                 "g_h_usb_peri", "g_h_p_ahb_arbi",
2690
2691                                                 "g_a_peri_niu", "g_h_emem_peri",
2692                                                 "g_h_mmc_peri", "g_hclk_nand0",
2693
2694                                                 "reserved",     "g_aclk_gmac",
2695                                                 "g_pclk_gmac",  "g_hclk_sfc";
2696
2697                                         #clock-cells = <1>;
2698                                 };
2699
2700                                 clk_gates21: gate-clk@0254 {
2701                                         compatible = "rockchip,rk3188-gate-clk";
2702                                         reg = <0x0254 0x4>;
2703                                         clocks =
2704                                                 <&hclk_peri>,   <&hclk_peri>,
2705                                                 <&hclk_peri>,   <&hclk_peri>,
2706
2707                                                 <&aclk_peri>,   <&dummy>,
2708                                                 <&dummy>,       <&dummy>,
2709
2710                                                 <&dummy>,       <&dummy>,
2711                                                 <&dummy>,       <&dummy>,
2712
2713                                                 <&dummy>,       <&dummy>,
2714                                                 <&dummy>,       <&dummy>;
2715
2716                                         clock-output-names =
2717                                                 "g_hclk_sdmmc", "g_hclk_sdio0",
2718                                                 "g_hclk_emmc",  "g_hclk_hsadc",
2719
2720                                                 "g_aclk_peri_mmu",      "reserved",
2721                                                 "reserved",     "reserved",
2722
2723                                                 "reserved",     "reserved",
2724                                                 "reserved",     "reserved",
2725
2726                                                 "reserved",     "reserved",
2727                                                 "reserved",     "reserved";
2728
2729                                         #clock-cells = <1>;
2730                                 };
2731
2732                                 clk_gates22: gate-clk@0258 {
2733                                         compatible = "rockchip,rk3188-gate-clk";
2734                                         reg = <0x0258 0x4>;
2735                                         clocks =
2736                                                 <&dummy>,       <&pclk_alive_pre>,
2737                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2738
2739                                                 <&dummy>,       <&dummy>,
2740                                                 <&dummy>,       <&dummy>,
2741
2742                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2743                                                 <&pclk_vio>,    <&pclk_vio>,
2744
2745                                                 <&pclk_alive_pre>,      <&pclk_alive_pre>,
2746                                                 <&dummy>,       <&dummy>;
2747
2748                                         clock-output-names =
2749                                                 "reserved",     "g_pclk_gpio1",
2750                                                 "g_pclk_gpio2", "g_pclk_gpio3",
2751
2752                                                 "reserved",     "reserved",
2753                                                 "reserved",     "reserved",
2754
2755                                                 "g_pclk_grf",   "g_p_alive_niu",
2756                                                 "g_pclk_dphytx0",       "g_pclk_dphyrx",
2757
2758                                                 "g_pclk_timer0",        "g_pclk_timer1",
2759                                                 "reserved",     "reserved";
2760
2761                                         #clock-cells = <1>;
2762                                 };
2763
2764                                 clk_gates23: gate-clk@025c {
2765                                         compatible = "rockchip,rk3188-gate-clk";
2766                                         reg = <0x025c 0x4>;
2767                                         clocks =
2768                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2769                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2770
2771                                                 <&pclk_pmu_pre>,        <&pclk_pmu_pre>,
2772                                                 <&dummy>,       <&dummy>,
2773
2774                                                 <&dummy>,       <&dummy>,
2775                                                 <&dummy>,       <&dummy>,
2776
2777                                                 <&dummy>,       <&dummy>,
2778                                                 <&dummy>,       <&dummy>;
2779
2780                                         clock-output-names =
2781                                                 "g_pclk_pmu",   "g_pclk_intmem1",
2782                                                 "g_pclk_pmu_noc",       "g_pclk_sgrf",
2783
2784                                                 "g_pclk_gpio0", "g_pclk_pmugrf",
2785                                                 "reserved",     "reserved",
2786
2787                                                 "reserved",     "reserved",
2788                                                 "reserved",     "reserved",
2789
2790                                                 "reserved",     "reserved",
2791                                                 "reserved",     "reserved";
2792
2793                                         #clock-cells = <1>;
2794                                 };
2795
2796                                 clk_gates24: gate-clk@0260 {
2797                                         compatible = "rockchip,rk3188-gate-clk";
2798                                         reg = <0x0260 0x4>;
2799                                         clocks =
2800                                                 <&xin24m>,      <&xin24m>,
2801                                                 <&xin24m>,      <&xin24m>,
2802
2803                                                 <&xin24m>,      <&xin24m>,
2804                                                 <&xin24m>,      <&xin24m>,
2805
2806                                                 <&xin24m>,      <&xin24m>,
2807                                                 <&xin24m>,      <&xin24m>,
2808
2809                                                 <&dummy>,       <&dummy>,
2810                                                 <&dummy>,       <&dummy>;
2811
2812                                         clock-output-names =
2813                                                 "g_clk_timer0", "g_clk_timer1",
2814                                                 "g_clk_timer2", "g_clk_timer3",
2815
2816                                                 "g_clk_timer4", "g_clk_timer5",
2817                                                 "g_clk_timer10",        "g_clk_timer11",
2818
2819                                                 "g_clk_timer12",        "g_clk_timer13",
2820                                                 "g_clk_timer14",        "g_clk_timer15",
2821
2822                                                 "reserved",     "reserved",
2823                                                 "reserved",     "reserved";
2824
2825                                         #clock-cells = <1>;
2826                                 };
2827                         };
2828                 };
2829
2830                 special_regs {
2831                         compatible = "rockchip,rk-clock-special-regs";
2832                         #address-cells = <2>;
2833                         #size-cells = <2>;
2834                         ranges;
2835
2836                         clk_32k_mux: clk_32k_mux {
2837                                 compatible = "rockchip,rk3188-mux-con";
2838                                 reg = <0x0 0xff738100 0x0 0x4>;
2839                                 rockchip,bits = <6 1>;
2840                                 clocks = <&xin32k>, <&pvtm_clkout>;
2841                                 clock-output-names = "clk_32k_mux";
2842                                 #clock-cells = <0>;
2843                                 #clock-init-cells = <1>;
2844                         };
2845                 };
2846         };
2847 };