arch/arm64/boot/dts/juno.dts

   1 /*
   2  * ARM Ltd. Juno Plaform
   3  *
   4  * Fast Models FVP v2 support
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         model = "Juno";
  13         compatible = "arm,juno", "arm,vexpress";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &soc_uart0;
  20         };
  21
  22         cpus {
  23                 #address-cells = <2>;
  24                 #size-cells = <0>;
  25
  26                 cpu@100 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a53","arm,armv8";
  29                         reg = <0x0 0x100>;
  30                         enable-method = "psci";
  31                 };
  32
  33                 cpu@101 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53","arm,armv8";
  36                         reg = <0x0 0x101>;
  37                         enable-method = "psci";
  38                 };
  39
  40                 cpu@102 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53","arm,armv8";
  43                         reg = <0x0 0x102>;
  44                         enable-method = "psci";
  45                 };
  46
  47                 cpu@103 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53","arm,armv8";
  50                         reg = <0x0 0x103>;
  51                         enable-method = "psci";
  52                 };
  53
  54                 cpu@0 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a57","arm,armv8";
  57                         reg = <0x0 0x0>;
  58                         enable-method = "psci";
  59                 };
  60
  61                 cpu@1 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a57","arm,armv8";
  64                         reg = <0x0 0x1>;
  65                         enable-method = "psci";
  66                 };
  67         };
  68
  69         memory@80000000 {
  70                 device_type = "memory";
  71                 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
  72                       <0x00000008 0x80000000 0x1 0x80000000>;
  73         };
  74
  75         /* memory@14000000 {
  76                 device_type = "memory";
  77                 reg = <0x00000000 0x14000000 0x0 0x02000000>;
  78         }; */
  79
  80         gic: interrupt-controller@2c001000 {
  81                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  82                 #interrupt-cells = <3>;
  83                 #address-cells = <0>;
  84                 interrupt-controller;
  85                 reg = <0x0 0x2c010000 0 0x1000>,
  86                       <0x0 0x2c02f000 0 0x1000>,
  87                       <0x0 0x2c04f000 0 0x2000>,
  88                       <0x0 0x2c06f000 0 0x2000>;
  89                 interrupts = <GIC_PPI 9 0xf04>;
  90         };
  91
  92         msi0: msi@2c1c0000 {
  93                 compatible = "arm,gic-msi";
  94                 reg = <0x0 0x2c1c0000 0 0x10000
  95                        0x0 0x2c1d0000 0 0x10000
  96                        0x0 0x2c1e0000 0 0x10000
  97                        0x0 0x2c1f0000 0 0x10000>;
  98         };
  99
 100         timer {
 101                 compatible = "arm,armv8-timer";
 102                 interrupts = <GIC_PPI 13 0xff01>,
 103                              <GIC_PPI 14 0xff01>,
 104                              <GIC_PPI 11 0xff01>,
 105                              <GIC_PPI 10 0xff01>;
 106         };
 107
 108         pmu {
 109                 compatible = "arm,armv8-pmuv3";
 110                 interrupts = <GIC_SPI 60 4>,
 111                              <GIC_SPI 61 4>,
 112                              <GIC_SPI 62 4>,
 113                              <GIC_SPI 63 4>;
 114         };
 115
 116         psci {
 117                 compatible = "arm,psci";
 118                 method = "smc";
 119                 cpu_suspend = <0xC4000001>;
 120                 cpu_off = <0x84000002>;
 121                 cpu_on = <0xC4000003>;
 122                 migrate = <0xC4000005>;
 123         };
 124
 125         pci0: pci@30000000 {
 126                 compatible = "arm,pcie-xr3";
 127                 device_type = "pci";
 128                 reg = <0 0x7ff30000 0 0x1000
 129                        0 0x7ff20000 0 0x10000
 130                        0 0x40000000 0 0x10000000>;
 131                 bus-range = <0 255>;
 132                 #address-cells = <3>;
 133                 #size-cells = <2>;
 134                 ranges = <0x01000000 0x0 0x00000000 0x00 0x5ff00000 0x0 0x00100000
 135                           0x02000000 0x0 0x00000000 0x40 0x00000000 0x0 0x80000000
 136                           0x42000000 0x0 0x80000000 0x40 0x80000000 0x0 0x80000000>;
 137                 #interrupt-cells = <1>;
 138                 interrupt-map-mask = <0 0 0 7>;
 139                 interrupt-map = <0 0 0 1 &gic 0 136 4
 140                                  0 0 0 2 &gic 0 137 4
 141                                  0 0 0 3 &gic 0 138 4
 142                                  0 0 0 4 &gic 0 139 4>;
 143         };
 144
 145         scpi: scpi@2b1f0000 {
 146                 compatible = "arm,scpi-mhu";
 147                 reg = <0x0 0x2b1f0000 0x0 0x10000>,   /* MHU registers */
 148                       <0x0 0x2e000000 0x0 0x10000>;   /* Payload area */
 149                 interrupts = <0 36 4>,   /* low priority interrupt */
 150                              <0 35 4>,   /* high priority interrupt */
 151                              <0 37 4>;   /* secure channel interrupt */
 152                 #clock-cells = <1>;
 153                 clock-output-names = "a57", "a53", "gpu", "hdlcd0", "hdlcd1";
 154         };
 155
 156         hdlcd0_osc: scpi_osc@3 {
 157                 compatible = "arm,scpi-osc";
 158                 #clock-cells = <0>;
 159                 clocks = <&scpi 3>;
 160                 frequency-range = <23000000 210000000>;
 161                 clock-output-names = "pxlclk0";
 162         };
 163
 164         hdlcd1_osc: scpi_osc@4 {
 165                 compatible = "arm,scpi-osc";
 166                 #clock-cells = <0>;
 167                 clocks = <&scpi 4>;
 168                 frequency-range = <23000000 210000000>;
 169                 clock-output-names = "pxlclk1";
 170         };
 171
 172         soc_uartclk: refclk72738khz {
 173                 compatible = "fixed-clock";
 174                 #clock-cells = <0>;
 175                 clock-frequency = <7273800>;
 176                 clock-output-names = "juno:uartclk";
 177         };
 178
 179         soc_refclk24mhz: clk24mhz {
 180                 compatible = "fixed-clock";
 181                 #clock-cells = <0>;
 182                 clock-frequency = <24000000>;
 183                 clock-output-names = "juno:clk24mhz";
 184         };
 185
 186         mb_eth25mhz: clk25mhz {
 187                 compatible = "fixed-clock";
 188                 #clock-cells = <0>;
 189                 clock-frequency = <25000000>;
 190                 clock-output-names = "ethclk25mhz";
 191         };
 192
 193         soc_usb48mhz: clk48mhz {
 194                 compatible = "fixed-clock";
 195                 #clock-cells = <0>;
 196                 clock-frequency = <48000000>;
 197                 clock-output-names = "clk48mhz";
 198         };
 199
 200         soc_smc50mhz: clk50mhz {
 201                 compatible = "fixed-clock";
 202                 #clock-cells = <0>;
 203                 clock-frequency = <50000000>;
 204                 clock-output-names = "smc_clk";
 205         };
 206
 207         soc_refclk100mhz: refclk100mhz {
 208                 compatible = "fixed-clock";
 209                 #clock-cells = <0>;
 210                 clock-frequency = <100000000>;
 211                 clock-output-names = "apb_pclk";
 212         };
 213
 214         soc_faxiclk: refclk533mhz {
 215                 compatible = "fixed-clock";
 216                 #clock-cells = <0>;
 217                 clock-frequency = <533000000>;
 218                 clock-output-names = "faxi_clk";
 219         };
 220
 221         soc_fixed_3v3: fixedregulator@0 {
 222                 compatible = "regulator-fixed";
 223                 regulator-name = "3V3";
 224                 regulator-min-microvolt = <3300000>;
 225                 regulator-max-microvolt = <3300000>;
 226                 regulator-always-on;
 227         };
 228
 229         memory-controller@7ffd0000 {
 230                 compatible = "arm,pl354", "arm,primecell";
 231                 reg = <0 0x7ffd0000 0 0x1000>;
 232                 interrupts = <0 86 4>,
 233                              <0 87 4>;
 234                 clocks = <&soc_smc50mhz>;
 235                 clock-names = "apb_pclk";
 236                 chip5-memwidth = <16>;
 237         };
 238
 239         dma0: dma@0x7ff00000 {
 240                 compatible = "arm,pl330", "arm,primecell";
 241                 reg = <0x0 0x7ff00000 0 0x1000>;
 242                 interrupts = <0 95 4>,
 243                              <0 88 4>,
 244                              <0 89 4>,
 245                              <0 90 4>,
 246                              <0 91 4>,
 247                              <0 108 4>,
 248                              <0 109 4>,
 249                              <0 110 4>,
 250                              <0 111 4>;
 251                 #dma-cells = <1>;
 252                 #dma-channels = <8>;
 253                 #dma-requests = <32>;
 254                 clocks = <&soc_faxiclk>;
 255                 clock-names = "apb_pclk";
 256         };
 257
 258         soc_uart0: uart@7ff80000 {
 259                 compatible = "arm,pl011", "arm,primecell";
 260                 reg = <0x0 0x7ff80000 0x0 0x1000>;
 261                 interrupts = <0 83 4>;
 262                 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
 263                 clock-names = "uartclk", "apb_pclk";
 264                 dmas = <&dma0 1
 265                         &dma0 2>;
 266                 dma-names = "rx", "tx";
 267         };
 268
 269         /* this UART is reserved for secure software.
 270         soc_uart1: uart@7ff70000 {
 271                 compatible = "arm,pl011", "arm,primecell";
 272                 reg = <0x0 0x7ff70000 0x0 0x1000>;
 273                 interrupts = <0 84 4>;
 274                 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
 275                 clock-names = "uartclk", "apb_pclk";
 276         }; */
 277
 278         ulpi_phy: phy@0 {
 279                 compatible = "phy-ulpi-generic";
 280                 reg = <0x0 0x94 0x0 0x4>;
 281                 phy-id = <0>;
 282         };
 283
 284         ehci@7ffc0000 {
 285                 compatible = "snps,ehci-h20ahb";
 286                 /* compatible = "arm,h20ahb-ehci"; */
 287                 reg = <0x0 0x7ffc0000 0x0 0x10000>;
 288                 interrupts = <0 117 4>;
 289                 clocks = <&soc_usb48mhz>;
 290                 clock-names = "otg";
 291                 phys = <&ulpi_phy>;
 292         };
 293
 294         ohci@0x7ffb0000 {
 295                 compatible = "generic-ohci";
 296                 reg = <0x0 0x7ffb0000 0x0 0x10000>;
 297                 interrupts = <0 116 4>;
 298                 clocks = <&soc_usb48mhz>;
 299                 clock-names = "otg";
 300         };
 301
 302         i2c@0x7ffa0000 {
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 compatible = "snps,designware-i2c";
 306                 reg = <0x0 0x7ffa0000 0x0 0x1000>;
 307                 interrupts = <0 104 4>;
 308                 clock-frequency = <400000>;
 309                 i2c-sda-hold-time-ns = <500>;
 310                 clocks = <&soc_smc50mhz>;
 311
 312                 dvi0: dvi-transmitter@70 {
 313                         compatible = "nxp,tda998x";
 314                         reg = <0x70>;
 315                 };
 316
 317                 dvi1: dvi-transmitter@71 {
 318                         compatible = "nxp,tda998x";
 319                         reg = <0x71>;
 320                 };
 321         };
 322
 323         /* mmci@1c050000 {
 324                 compatible = "arm,pl180", "arm,primecell";
 325                 reg = <0x0 0x1c050000 0x0 0x1000>;
 326                 interrupts = <0 73 4>,
 327                              <0 74 4>;
 328                 max-frequency = <12000000>;
 329                 vmmc-supply = <&soc_fixed_3v3>;
 330                 clocks = <&soc_refclk24mhz>, <&soc_refclk100mhz>;
 331                 clock-names = "mclk", "apb_pclk";
 332         }; */
 333
 334         hdlcd@7ff60000 {
 335                 compatible = "arm,hdlcd";
 336                 reg = <0 0x7ff60000 0 0x1000>;
 337                 interrupts = <0 85 4>;
 338                 clocks = <&hdlcd0_osc>;
 339                 clock-names = "pxlclk";
 340                 i2c-slave = <&dvi0>;
 341
 342                 /* display-timings {
 343                         native-mode = <&timing0>;
 344                         timing0: timing@0 {
 345                                 /* 1024 x 768 framebufer, standard VGA timings * /
 346                                 clock-frequency = <65000>;
 347                                 hactive = <1024>;
 348                                 vactive = <768>;
 349                                 hfront-porch = <24>;
 350                                 hback-porch = <160>;
 351                                 hsync-len = <136>;
 352                                 vfront-porch = <3>;
 353                                 vback-porch = <29>;
 354                                 vsync-len = <6>;
 355                         };
 356                 }; */
 357         };
 358
 359         hdlcd@7ff50000 {
 360                 compatible = "arm,hdlcd";
 361                 reg = <0 0x7ff50000 0 0x1000>;
 362                 interrupts = <0 93 4>;
 363                 clocks = <&hdlcd1_osc>;
 364                 clock-names = "pxlclk";
 365                 i2c-slave = <&dvi1>;
 366
 367                 display-timings {
 368                         native-mode = <&timing1>;
 369                         timing1: timing@1 {
 370                                 /* 1024 x 768 framebufer, standard VGA timings */
 371                                 clock-frequency = <65000>;
 372                                 hactive = <1024>;
 373                                 vactive = <768>;
 374                                 hfront-porch = <24>;
 375                                 hback-porch = <160>;
 376                                 hsync-len = <136>;
 377                                 vfront-porch = <3>;
 378                                 vback-porch = <29>;
 379                                 vsync-len = <6>;
 380                         };
 381                 };
 382         };
 383
 384         smb {
 385                 compatible = "simple-bus";
 386                 #address-cells = <2>;
 387                 #size-cells = <1>;
 388                 ranges = <0 0 0 0x08000000 0x04000000>,
 389                          <1 0 0 0x14000000 0x04000000>,
 390                          <2 0 0 0x18000000 0x04000000>,
 391                          <3 0 0 0x1c000000 0x04000000>,
 392                          <4 0 0 0x0c000000 0x04000000>,
 393                          <5 0 0 0x10000000 0x04000000>;
 394
 395                 #interrupt-cells = <1>;
 396                 interrupt-map-mask = <0 0 15>;
 397                 interrupt-map = <0 0  0 &gic 0  68 4>,
 398                                 <0 0  1 &gic 0  69 4>,
 399                                 <0 0  2 &gic 0  70 4>,
 400                                 <0 0  3 &gic 0 160 4>,
 401                                 <0 0  4 &gic 0 161 4>,
 402                                 <0 0  5 &gic 0 162 4>,
 403                                 <0 0  6 &gic 0 163 4>,
 404                                 <0 0  7 &gic 0 164 4>,
 405                                 <0 0  8 &gic 0 165 4>,
 406                                 <0 0  9 &gic 0 166 4>,
 407                                 <0 0 10 &gic 0 167 4>,
 408                                 <0 0 11 &gic 0 168 4>,
 409                                 <0 0 12 &gic 0 169 4>;
 410
 411                 motherboard {
 412                         model = "V2M-Juno";
 413                         arm,hbi = <0x252>;
 414                         arm,vexpress,site = <0>;
 415                         arm,v2m-memory-map = "rs1";
 416                         compatible = "arm,vexpress,v2p-p1", "simple-bus";
 417                         #address-cells = <2>;  /* SMB chipselect number and offset */
 418                         #size-cells = <1>;
 419                         #interrupt-cells = <1>;
 420                         ranges;
 421
 422                         usb@5,00000000 {
 423                                 compatible = "nxp,usb-isp1763";
 424                                 reg = <5 0x00000000 0x20000>;
 425                                 bus-width = <16>;
 426                                 interrupts = <4>;
 427                         };
 428
 429                         ethernet@2,00000000 {
 430                                 compatible = "smsc,lan9118", "smsc,lan9115";
 431                                 reg = <2 0x00000000 0x10000>;
 432                                 interrupts = <3>;
 433                                 phy-mode = "mii";
 434                                 reg-io-width = <4>;
 435                                 smsc,irq-active-high;
 436                                 smsc,irq-push-pull;
 437                                 clocks = <&mb_eth25mhz>;
 438                                 vdd33a-supply = <&soc_fixed_3v3>; /* change this */
 439                                 vddvario-supply = <&soc_fixed_3v3>; /* and this */
 440                         };
 441
 442                         iofpga@3,00000000 {
 443                                 compatible = "arm,amba-bus", "simple-bus";
 444                                 #address-cells = <1>;
 445                                 #size-cells = <1>;
 446                                 ranges = <0 3 0 0x200000>;
 447
 448                                 kmi@060000 {
 449                                         compatible = "arm,pl050", "arm,primecell";
 450                                         reg = <0x060000 0x1000>;
 451                                         interrupts = <8>;
 452                                         clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
 453                                         clock-names = "KMIREFCLK", "apb_pclk";
 454                                 };
 455
 456                                 kmi@070000 {
 457                                         compatible = "arm,pl050", "arm,primecell";
 458                                         reg = <0x070000 0x1000>;
 459                                         interrupts = <8>;
 460                                         clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
 461                                         clock-names = "KMIREFCLK", "apb_pclk";
 462                                 };
 463
 464                                 wdt@0f0000 {
 465                                         compatible = "arm,sp805", "arm,primecell";
 466                                         reg = <0x0f0000 0x10000>;
 467                                         interrupts = <7>;
 468                                         clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
 469                                         clock-names = "wdogclk", "apb_pclk";
 470                                 };
 471
 472                                 v2m_timer01: timer@110000 {
 473                                         compatible = "arm,sp804", "arm,primecell";
 474                                         reg = <0x110000 0x10000>;
 475                                         interrupts = <9>;
 476                                         clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
 477                                         clock-names = "timclken1", "apb_pclk";
 478                                 };
 479
 480                                 v2m_timer23: timer@120000 {
 481                                         compatible = "arm,sp804", "arm,primecell";
 482                                         reg = <0x120000 0x10000>;
 483                                         interrupts = <9>;
 484                                         clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
 485                                         clock-names = "timclken1", "apb_pclk";
 486                                 };
 487
 488                                 rtc@170000 {
 489                                         compatible = "arm,pl031", "arm,primecell";
 490                                         reg = <0x170000 0x10000>;
 491                                         interrupts = <0>;
 492                                         clocks = <&soc_smc50mhz>;
 493                                         clock-names = "apb_pclk";
 494                                 };
 495                         };
 496                 };
 497         };
 498 };